Positive and negative voltage sampling circuit of battery management system

Abstract

The application discloses a positive and negative voltage sampling circuit of a battery management system. The application comprises a P-pole switch array, an N-pole switch array, four sampling capacitors, a sampling resistor and two common-mode switches. The P-pole switch array and the N-pole switch array are of the same structure and each comprises 16 switches. The input end of the switch array is connected to the two ends of the sampling resistor, the output end is connected to the sampling capacitor, and the sampling capacitor is connected to one end of the common-mode switch, which is the output end of the sampling circuit, and the other end of the common-mode switch is connected to the back common-mode voltage. The application transfers the leakage current of the switch caused by the negative voltage to the non-main sampling path, without affecting the main sampling path. The application alternately uses the positive sampling process and the negative sampling process to realize the chopping sampling function, and reduces the influence of capacitor mismatch on the sampling accuracy. The application reduces the cost of the battery management system and improves the current sampling accuracy.

Description

Technical Field

[0001] This invention belongs to the field of voltage detection in electronic technology, and specifically relates to a high-precision positive and negative voltage sampling circuit used in a battery management system. Background Technology

[0002] A Battery Management System (BMS) is designed for the intelligent management and maintenance of individual battery cells, preventing overcharging and over-discharging, extending battery life, and monitoring battery status. Charge / discharge current detection is a fundamental function of a BMS. Typically, a sampling resistor is connected in series in the current path to convert the current value into a voltage value for sampling. Depending on the connection position of the sampling resistor, current detection can be categorized into two methods: high-side detection and low-side detection. In high-side detection, the sampling resistor is connected in series with the positive terminal of the battery. In low-side detection, the sampling resistor is connected in series with the negative terminal of the battery. High-side detection requires a high-voltage-resistant circuit, resulting in complex and costly circuitry. Low-side detection generates a positive voltage across the sampling resistor during battery discharge and a negative voltage (lower than the negative terminal voltage) during battery charging. To sample the negative voltage, an amplifier is typically used to raise and amplify the potential, as illustrated in patents CN202122280836 and CN202211588798.

[0003] Switched capacitors can be used for voltage sampling, but when the sampling voltage is negative, there is a negative potential across the sampling switch, causing the switch to not completely disconnect, and leakage current affects the accuracy of the sampling voltage. To reduce leakage current under negative voltage, a deep N-well process can be used in CMOS technology, placing the CMOS switch in a deep N-well, and then using a negative bias voltage to keep the body voltage of the CMOS switch below 0V. However, this increases the cost of the CMOS process and requires circuitry to generate the negative bias body voltage of the CMOS switch. Summary of the Invention

[0004] The purpose of this invention is to provide a high-precision positive and negative voltage sampling circuit that is unaffected by leakage current when leakage occurs due to negative voltage. This circuit can eliminate the impact of negative voltage leakage on sampling accuracy, and it does not require deep N-well technology or a potential boost amplifier.

[0005] This invention includes:

[0006] The system consists of a P-type switch array, an N-type switch array, four sampling capacitors, one sampling resistor, and two common-mode switches.

[0007] The P-type switch array and the N-type switch array have the same structure, both including 16 switches. All switches are NMOS switches. The source of the NMOS switch is one end of the switch, the drain is the other end of the switch, and the gate is the control terminal of the switch.

[0008] The specific structure of the switch array is as follows:

[0009] One end of the first, second, third, and fourth switches is connected as the positive input terminal of the switch array, and one end of the fifth, sixth, seventh, and eighth switches is connected as the negative input terminal of the switch array.

[0010] One end of the ninth and tenth switches is connected to the other end of the first switch; one end of the eleventh and twelfth switches is connected to the other end of the sixth switch; the other ends of the second, fifth, tenth, and twelfth switches are connected; the other ends of the ninth and eleventh switches are connected as the positive output terminal of the switch array.

[0011] One end of the thirteenth and fourteenth switches is connected to the other end of the third switch; one end of the fifteenth and sixteenth switches is connected to the other end of the eighth switch; the other ends of the fourth, seventh, fourteenth, and sixteenth switches are connected; the other ends of the thirteenth and fifteenth switches are connected, serving as the negative output terminals of the switch array.

[0012] The positive input terminals of the P-type switch array and the N-type switch array are connected to one end of the sampling resistor, serving as the positive input terminals of the sampling circuit. The negative input terminals of the P-type switch array and the N-type switch array are connected to the other end of the sampling resistor, serving as the negative input terminals of the sampling circuit.

[0013] The positive output terminal of the P-type switch array is connected to one end of the first sampling capacitor, and the negative output terminal is connected to one end of the second sampling capacitor. The other ends of the first and second sampling capacitors are connected to one end of the first common-mode switch, serving as the positive output terminal of the sampling circuit. The positive output terminal of the N-type switch array is connected to one end of the third sampling capacitor, and the negative output terminal is connected to one end of the fourth sampling capacitor. The other ends of the third and fourth sampling capacitors are connected to one end of the second common-mode switch, serving as the negative output terminal of the sampling circuit. The other ends of the first and second common-mode switches are connected to the common-mode voltage Vcm.

[0014] This invention, without adding additional CMOS deep N-well technology, transfers leakage current caused by negative voltage to a non-main sampling path through leakage current transfer, without affecting the main sampling path. This invention does not require an amplifier; only a switch is needed to achieve accurate negative voltage sampling. It can alternately use positive and negative sampling processes to achieve chopping sampling, reducing the impact of capacitor mismatch on sampling accuracy. The circuit implementation is low-cost, highly adaptable to various processes, reduces the cost of the battery management system, and improves the accuracy of current sampling. Attached Figure Description

[0015] Figure 1 This is a circuit diagram of the present invention;

[0016] Figure 2This is a schematic diagram of a positive sampling operation;

[0017] Figure 3 This is a diagram illustrating positive and negative shift operations;

[0018] Figure 4 This is a schematic diagram of a positive sampling operation. Detailed Implementation

[0019] The present invention will be further described below with reference to embodiments.

[0020] The positive and negative voltage sampling circuit of the battery management system, such as Figure 1 As shown, it includes: a P-pole switch array, an N-pole switch array, four sampling capacitors, one sampling resistor, and two common-mode switches.

[0021] P-pole switch arrays and N-pole switch arrays have the same structure. Figure 1 The dashed box in the middle contains 16 switches, all of which are NMOS switches. The source of the NMOS switch is one end of the switch, the drain is the other end of the switch, and the gate is the control terminal of the switch.

[0022] Taking a P-pole switch array as an example, the specific structure is as follows:

[0023] One end of the first switch P1, the second switch P2, the third switch P3 and the fourth switch P4 are connected as the positive input terminal of the switch array, and one end of the fifth switch P5, the sixth switch P6, the seventh switch P7 and the eighth switch P8 are connected as the negative input terminal of the switch array.

[0024] One end of the ninth switch P9 and the tenth switch P10 is connected to the other end of the first switch P1. One end of the eleventh switch P11 and the twelfth switch P12 is connected to the other end of the sixth switch P6. The other ends of the second switch P2, the fifth switch P5, the tenth switch P10 and the twelfth switch P12 are connected. The other ends of the ninth switch P9 and the eleventh switch P11 are connected as the positive output terminal of the switch array.

[0025] One end of the thirteenth switch P13 and the fourteenth switch P14 are connected to the other end of the third switch P3. One end of the fifteenth switch P15 and the sixteenth switch P16 are connected to the other end of the eighth switch P8. The other ends of the fourth switch P4, the seventh switch P7, the fourteenth switch P14 and the sixteenth switch P16 are connected. The other ends of the thirteenth switch P13 and the fifteenth switch P15 are connected, serving as the negative output terminal of the switch array.

[0026] like Figure 1 The switch number at the same position in the N-pole switch array is the same as that in the P-pole switch array.

[0027] The positive input terminals of the P-type and N-type switch arrays are connected to one end of the sampling resistor R, serving as the positive input terminal P of the sampling circuit. The negative input terminals of the P-type and N-type switch arrays are connected to the other end of the sampling resistor R, serving as the negative input terminal N of the sampling circuit. The positive input terminal P of the sampling circuit is connected to the negative terminal of the battery, and the positive terminal of the battery is connected to the positive terminal of the charger. The negative input terminal N of the sampling circuit is connected to the negative terminal of the charger.

[0028] The positive output terminal of the P-type switch array is connected to one end of the first sampling capacitor C1, and the negative output terminal is connected to one end of the second sampling capacitor C2. The other ends of the first sampling capacitor C1 and the second sampling capacitor C2 are connected to one end of the first common-mode switch S1, serving as the positive output terminal Po of the sampling circuit. The positive output terminal of the N-type switch array is connected to one end of the third sampling capacitor C3, and the negative output terminal is connected to one end of the fourth sampling capacitor C4. The other ends of the third sampling capacitor C3 and the fourth sampling capacitor C4 are connected to one end of the second common-mode switch S2, serving as the negative output terminal No of the sampling circuit. The other ends of the first common-mode switch S1 and the second common-mode switch S2 are connected to the common-mode voltage Vcm.

[0029] The sampling process is divided into positive sampling and negative sampling. Alternating between positive and negative sampling achieves chopping sampling, reducing the impact of capacitor mismatch on sampling accuracy. Since the circuit does not generate negative voltage during battery discharge, there is no accuracy loss due to leakage. The following explanation uses a charging scenario where negative voltage occurs. Taking a sampling resistor of 100 milliohms and a charging current of 2 amps as an example, the 2 amps of current flow from the positive terminal of the charger through the battery to point P, then to point N, and finally back to the negative terminal of the charger. When the common-mode voltage Vcm = 2.5V, we can obtain Vp = 0V and Vn = -200mV.

[0030] The positive sampling process consists of two consecutive operations: a positive sampling operation and a positive shift operation.

[0031] like Figure 2As shown, the positive sampling operation specifically involves closing the fifth switch P5, sixth switch P6, seventh switch P7, eighth switch P8, tenth switch P10, eleventh switch P11, fourteenth switch P14, and fifteenth switch P15 in the P-pole switch array; the first switch N1, second switch N2, third switch N3, fourth switch N4, ninth switch N9, twelfth switch N12, thirteenth switch N13, and sixteenth switch N16 in the N-pole switch array; and the first common-mode switch S1 and the second common-mode switch S2. All other switches are open. The voltage at one end of the first sampling capacitor C1 and the second sampling capacitor C2 is the N-point voltage Vn, and the voltage at the other end is the common-mode voltage Vcm. The voltage at one end of the third sampling capacitor C3 and the fourth sampling capacitor C4 is the P-point voltage Vp, and the voltage at the other end is the common-mode voltage Vcm. The voltages at the ends of switches P9, P13, N11, and N15 are equal, resulting in no leakage current and not affecting the voltage at the connection points of C1, C2, C3, and C4 with the output terminals of the switch array.

[0032] like Figure 3 As shown, the positive shift operation specifically involves: simultaneously disconnecting all switches, and then closing the following switches in the P-pole switch array: the first switch P1, the second switch P2, the seventh switch P7, the eighth switch P8, the ninth switch P9, the twelfth switch P12, the fourteenth switch P14, and the fifteenth switch P15; and the first switch N1, the second switch N2, the seventh switch N7, the eighth switch N8, the ninth switch N9, the twelfth switch N12, the fourteenth switch N14, and the fifteenth switch N15. The voltage at one end of the first sampling capacitor C1 and the third sampling capacitor C3 is the voltage at point P, Vp; the voltage at one end of the second sampling capacitor C2 and the fourth sampling capacitor C4 is the voltage at point N, Vn. According to the law of charge conservation, the voltage Vn at the positive output terminal Po of the sampling circuit... Po =Vcm + (Vp - Vn) / 2, the voltage V at the negative output terminal No of the sampling circuit. No =Vcm-(Vp-Vn) / 2, V Po -V No =Vp-Vn, realizing positive voltage sampling and level shifting. The voltages across switches P11, P13, N11 and N13 are equal, no leakage current is generated, and it does not affect the voltage at the connection points of C1, C2, C3 and C4 with the output terminals of the switch array.

[0033] The negative sampling process consists of two consecutive operations: a negative sampling operation and a negative shift operation.

[0034] like Figure 4As shown, the negative sampling operation specifically involves closing the following switches in the P-pole switch array: the first switch P1, the second switch P2, the third switch P3, the fourth switch P4, the ninth switch P9, the twelfth switch P12, the thirteenth switch P13, and the sixteenth switch P16; the fifth switch N5, the sixth switch N6, the seventh switch N7, the eighth switch N8, the tenth switch N10, the eleventh switch N11, the fourteenth switch N14, and the fifteenth switch N15; and the first common-mode switch S1 and the second common-mode switch S2. All other switches are open. The voltage at one end of the first sampling capacitor C1 and the second sampling capacitor C2 is the voltage at point P (Vp), and the voltage at the other end is the common-mode voltage (Vcm). The voltage at one end of the third sampling capacitor C3 and the fourth sampling capacitor C4 is the voltage at point N (Vn), and the voltage at the other end is the common-mode voltage (Vcm). The voltages at the ends of switches P11, P15, N9, and N13 are equal, resulting in no leakage current and not affecting the voltage at the connection points of C1, C2, C3, and C4 with the output terminals of the switch array.

[0035] The negative shift operation is the same as the positive shift operation: simultaneously open all switches, then close the following switches in the P-pole switch array: the first switch P1, the second switch P2, the seventh switch P7, the eighth switch P8, the ninth switch P9, the twelfth switch P12, the fourteenth switch P14, and the fifteenth switch P15; and the first switch N1, the second switch N2, the seventh switch N7, the eighth switch N8, the ninth switch N9, the twelfth switch N12, the fourteenth switch N14, and the fifteenth switch N15. The voltage at one end of the first sampling capacitor C1 and the third sampling capacitor C3 is the voltage at point P, Vp; the voltage at one end of the second sampling capacitor C2 and the fourth sampling capacitor C4 is the voltage at point N, Vn. By the law of conservation of charge, the voltage Vn at the positive output terminal Po of the sampling circuit... Po =Vcm-(Vp-Vn) / 2, the voltage V at the negative output terminal No of the sampling circuit. No =Vcm + (Vp - Vn) / 2, V Po -V No =-(Vp-Vn), realizing negative voltage sampling and level shifting. The voltages across switches P11, P13, N11 and N13 are equal, no leakage current is generated, and it does not affect the voltage at the connection points of C1, C2, C3 and C4 with the output terminals of the switch array.

[0036] This invention, without adding additional CMOS deep N-well technology, transfers leakage current so that leakage current caused by negative voltage does not affect the main sampling path. This invention does not require an amplifier; only a switch is needed to achieve accurate negative voltage sampling. It can alternate between positive and negative sampling processes to achieve chopping sampling, reducing the impact of capacitor mismatch on sampling accuracy. The circuit implementation is low-cost, highly adaptable to various processes, reduces the cost of the battery management system, and improves the accuracy of current sampling.

[0037] It should be understood that the above examples are merely illustrative of the present invention and not limitations thereof. Any invention that does not exceed the essential spirit and scope of the present invention falls within the protection scope of the present invention.

Claims

1. A positive and negative voltage sampling circuit for a battery management system, characterized in that, include: P-type switch array, N-type switch array, four sampling capacitors, one sampling resistor and two common-mode switches; The P-pole switch array and the N-pole switch array have the same structure, both including 16 switches. The specific structure of the switch array is as follows: One end of the first, second, third, and fourth switches is connected as the positive input terminal of the switch array, and one end of the fifth, sixth, seventh, and eighth switches is connected as the negative input terminal of the switch array. One end of the ninth and tenth switches is connected to the other end of the first switch; one end of the eleventh and twelfth switches is connected to the other end of the sixth switch; the other ends of the second, fifth, tenth, and twelfth switches are connected; the other ends of the ninth and eleventh switches are connected as the positive output terminal of the switch array. One end of the thirteenth and fourteenth switches is connected to the other end of the third switch; one end of the fifteenth and sixteenth switches is connected to the other end of the eighth switch; the other ends of the fourth, seventh, fourteenth, and sixteenth switches are connected; the other ends of the thirteenth and fifteenth switches are connected, serving as the negative output terminals of the switch array. The positive input terminals of the P-pole switch array and the N-pole switch array are connected to one end of the sampling resistor, serving as the positive input terminals of the sampling circuit. The negative input terminals of the P-pole switch array and the N-pole switch array are connected to the other end of the sampling resistor, serving as the negative input terminals of the sampling circuit. The positive output terminal of the P-type switch array is connected to one end of the first sampling capacitor, and the negative output terminal is connected to one end of the second sampling capacitor. The other ends of the first and second sampling capacitors are connected to one end of the first common-mode switch, serving as the positive output terminal of the sampling circuit. The positive output terminal of the N-type switch array is connected to one end of the third sampling capacitor, and the negative output terminal is connected to one end of the fourth sampling capacitor. The other ends of the third and fourth sampling capacitors are connected to one end of the second common-mode switch, serving as the negative output terminal of the sampling circuit. The other ends of the first and second common-mode switches are connected to the common-mode voltage Vcm. All switches are NMOS switches. The source of an NMOS switch is one end of the switch, the drain is the other end of the switch, and the gate is the control terminal of the switch.

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