A Multi-channel Data Low-latency DDR Off-chip Memory Access Method Based on FPGA

Abstract

The present invention discloses a method for low-latency off-chip DDR memory access of multiple channels of data based on FPGA, comprising the following steps: S1. When the write signal is valid, select the write address and the read address according to the address slice rotation scheduling method; S2. Perform cross-clock domain processing on the data through a handshake-type asynchronous FIFO, and splice the data so that the bit width meets the DDR maximum cache standard; S3. Write the data of each channel into the DDR address space selected by the address scheduling through write arbitration; S4. When the read signal is valid, update the read address to the read address selected by the address scheduling; S5. Read the data from the read address selected by the address scheduling through read arbitration; S6. Perform cross-clock domain processing on the data through a handshake-type asynchronous FIFO, and decompose the cached data into data that meets the bit width of the data receiving end. This method realizes coordinated DDR memory access of multiple channels of data through arbitration, avoids competition caused by read-write conflicts, and thus improves the memory access efficiency.

Description

Technical Field

[0001] The present invention belongs to the field of FPGA data storage, and particularly relates to a method for low-latency DDR off-chip memory access of multiplexed data based on FPGA. Background Art

[0002] With the advent of the big data era, the need for data storage is getting higher and higher. DDR (Double Data Rate) storage technology is one of the most widely used technologies at present. The characteristics of DDR memory are high speed, high bandwidth, low power consumption, etc. And FPGA (Field Programmable Gate Array) is a programmable logic device that can be programmed according to different application requirements to achieve different functions, with the advantages of high speed, low power consumption, low latency, etc.

[0003] In practical applications, DDR is usually used in FPGA for off-chip data caching; however, when multiplexed data needs to be cached, the speed and efficiency of DDR memory will become a problem; because when multiple channels are involved, the clock frequencies of each channel may be different from each other, which makes it very difficult to ensure correct and fast caching of data.

[0004] In addition, when using DDR to perform read and write operations on the same address, read-write conflicts will occur, resulting in unpredictable changes in the data at the conflict address. Although such problems can be avoided through read-write priority control, the data anomalies caused by read-write conflicts cannot be completely solved; when considering the clock frequency of the data source, the clock frequency of the data readout end, and the DDR cache clock frequency, it is necessary to reduce data transmission delay and avoid competition caused by read-write conflicts. Summary of the Invention

[0005] In view of the deficiencies of the prior art, the present invention proposes a method for low-latency DDR off-chip memory access of multiplexed data based on FPGA, which selects the buffer areas of each path of data through the address slice rotation scheduling method to prevent read-write conflicts, realizes data cross-clock domain transmission and matches different data bit widths through a handshake-type asynchronous FIFO, and further improves data transmission efficiency; realizes multiplexed data collaborative memory access to DDR through arbitration, avoids competition caused by read-write conflicts, and thus improves memory access efficiency.

[0006] In order to solve the above technical problems, the technical solution of the present invention is as follows:

[0007] A method for low-latency DDR off-chip memory access of multiplexed data based on FPGA, comprising the following steps:

[0008] S1. When the write signal is valid, select the write address and the read address according to the address slice rotation scheduling method;

[0009] S2. Perform cross-clock domain processing on the data through a handshake-type asynchronous FIFO, and splice the data so that the bit width meets the DDR maximum cache standard;

[0010] S3. Write the data of each channel into the DDR address space selected by the address scheduling through write arbitration;

[0011] S4. When the read signal is valid, update the read address to the read address selected by the address scheduling;

[0012] S5. Read the data from the read address selected by the address scheduling through read arbitration;

[0013] S6. Perform cross-clock domain processing on the data through a handshake-type asynchronous FIFO, and decompose the cached data into data that meets the bit width of the data receiving end.

[0014] Preferably, the step S1 includes the following sub-steps:

[0015] S1-1. Save the state of the write signal of the data source through a two-stage register structure. The first-stage register saves the current state, and the second-stage register saves the previous state. When the states saved by the two-stage registers are different and the current state saved by the first-stage register is valid, output a single-cycle write request signal;

[0016] S1-2. Transmit the write enable signal to the handshake-type asynchronous FIFO;

[0017] S1-3. Set multiple address slices for each path of data. Select the starting address for writing data through the address slice rotation scheduling method, and select the starting address of the data written in the previous round as the read address;

[0018] Preferably, the specific process of the address slice rotation scheduling method is as follows:

[0019] Divide the DDR address space into cache spaces for multiple channels. Each channel's cache space is divided into multiple buffer areas, numbered 1, 2, 3... address slices. When each channel transmits data, different address slices are allocated, and the buffer areas are selected in turn according to a preset rule for read and write operations;

[0020] The specific preset rule is: when the allocated address slice is full or a write cycle is completed, if the data writing is not completed, the next address slice is automatically allocated. At this time, the read address is the starting address of the address slice of the data written in the previous round. After the last address slice is allocated, the next address slice starts to be selected from the first address slice to ensure that only one thread can perform read and write operations on the buffer area of the address slice.

[0021] Preferably, the step S2 includes the following sub-steps:

[0022] After the handshake-type asynchronous FIFO receives the write request signal, the state of the write FIFO state machine changes, and a handshake signal is generated to wait for the DDR response;

[0023] S2-2. The FIFO internally checks whether there are idle storage units to store data; if so, when the write enable is valid, the FIFO first splices the channel data that does not conform to the DDR data width into the cache data with the maximum DDR data width, and then transfers the spliced data from the write clock domain to the storage clock domain and stores it at the position pointed to by the write pointer;

[0024] S2-3. When the amount of data cached in the FIFO reaches the set threshold, a write request signal is generated to the write arbitration module to obtain the access right to the bus;

[0025] S2-4. When receiving the write data request signal of the DDR, read the data from the buffer area of the FIFO;

[0026] S2-5. When receiving the write completion signal of the write arbitration module, stop generating the write request, output the write address plus the length of the data written this time, and change the write data count value to the count value after adding the number of data written this time;

[0027] S2-6. When the write data count value is greater than the write data length, stop the current round of data transmission and wait for the next round of data transmission.

[0028] Preferably, the step S3 includes the following sub-steps:

[0029] S3-1. After the write arbitration module receives the write requests from each data source, it starts the write preparation for each channel in a polling manner;

[0030] Specifically, the write arbitration module checks each channel in turn and sends a specific write request to one of the channels in the available state. If the request is successfully processed, it means that the channel has completed a write operation; otherwise, it will try to send a request to the next channel in the available state until all channels have been checked;

[0031] S3-2. When receiving the write completion signal of the DDR, transfer the write data, write address, and data length to the AXI4 transfer bridge according to the priority of each channel;

[0032] S3-3. The AXI4 transfer bridge converts the write protocol into the AXI4 protocol and calls the DDR control module to cache the write data into the corresponding buffer area of the DDR.

[0033] Preferably, the step S5 includes the following sub-steps:

[0034] S5-1, the read arbitration module receives the read request signal from the data receiving end and starts preparing to read the data through polling;

[0035] Specifically, the read arbitration module checks each channel in turn and sends a specific read request to one of the available channels. If the request is successfully processed, it means that the channel has completed a read operation; otherwise, it will try to send a request to the next available channel until all channels have been checked.

[0036] S5-2, after receiving the read completion signal from the DDR control module converted by the AXI4 transfer bridge, output the read address, read data length and read enable signal selected by the address slice round-robin scheduling method to the AXI4 transfer bridge according to the priority of the data receiving end;

[0037] S5-3, the AXI4 transfer bridge converts the read protocol into the AXI4 protocol and controls the DDR control module to read data from the corresponding address space.

[0038] Preferably, step S6 includes the following sub-steps:

[0039] S6-1, after the handshake asynchronous FIFO receives the read request signal, the state of the read FIFO state machine changes, and a handshake signal is generated, waiting for the DDR response;

[0040] S6-2, the FIFO internally checks whether there are free storage cells to store data; if so, when receiving a read valid signal, the FIFO first decomposes the buffered data of the DDR maximum data bit width into received data that conforms to the data bit width of the data receiving end, and then transfers the decomposed data from the write clock domain to the storage clock domain and stores it at the location pointed by the write pointer;

[0041] S6-3: When the amount of data cached in the FIFO is less than the set threshold, a read request signal is generated to the read arbitration module to obtain access to the bus;

[0042] S6-4, when receiving the read enable signal from the data receiving end, reading the data from the buffer area of FIFO;

[0043] S6-5, when receiving the read completion signal from the read arbitration module, stop generating read requests, output the read address plus the length of the data read this time, and change the read data count value to the count value plus the amount of data read this time;

[0044] S6-6. When the read data count value is greater than the read data length, stop the current round of data reading and wait for the next round of data reading.

[0045] The present invention has the following characteristics and beneficial effects:

[0046] The multi-channel data low-latency DDR off-chip memory access method based on FPGA of the present invention enables multi-channel data to be cached in DDR and read out in real time, while reducing data transmission latency, increasing channel rate, and avoiding read-write conflicts.

[0047] The present invention applies the address slice round-robin scheduling method, which is suitable for high-speed memory access, has the characteristics of real-time and high bandwidth, reasonably allocates the capacity of DDR, and reduces the cost of multi-channel data caching; at the same time, it applies a handshake-type asynchronous FIFO to implement cross-clock domain processing of data, avoid data transmission errors, and match the data bit width, greatly reducing the latency in the data transmission process and being suitable for data transmission in various clock domains. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0049] Figure 1 It is a flowchart of a multi-channel data low-latency DDR off-chip memory access method based on FPGA according to an embodiment of the present invention.

[0050] Figure 2 It is a structural block diagram of a multi-channel data low-latency DDR off-chip memory access method based on FPGA according to an embodiment of the present invention.

[0051] Figure 3 It is a DDR data read-write address transformation diagram of a multi-channel data low-latency DDR off-chip memory access method based on FPGA according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0052] It should be noted that, without conflict, the embodiments in the present invention and the features in the embodiments can be combined with each other.

[0053] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "lateral", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the present invention. In addition, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first", "second", etc. may explicitly or implicitly include one or more of such features. In the description of the present invention, unless otherwise specified, the meaning of "a plurality" is two or more.

[0054] In the description of the present invention, it should be noted that unless otherwise clearly specified and limited, the terms "installation", "connection", and "coupling" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood through specific situations.

[0055] The present invention provides a method for low-latency DDR off-chip memory access of multiplex data based on FPGA, as Figures 1-3 shown, including the following steps:

[0056] S1. When the write signal is valid, select the write address and read address according to the address slice rotation scheduling method;

[0057] The step S1 includes the following sub-steps:

[0058] S1-1. Save the state of the write signal of the data source through a two-stage register structure. The first-stage register saves the current state, and the second-stage register saves the previous state. When the states saved in the two-stage registers are different and the current state saved in the first-stage register is valid, output a single-cycle write request signal;

[0059] S1-2. Transmit the write enable signal to the handshake-type asynchronous FIFO;

[0060] S1-3. Set multiple address slices for each path of data, select the starting address of the data to be written through the address slice rotation scheduling method, and select the starting address of the data written in the previous round as the read address;

[0061] Specifically, the specific process of the address slice rotation scheduling method is as follows:

[0062] Divide the address space of the DDR into cache spaces of multiple channels. The cache space of each channel is divided into multiple buffer areas, numbered 1, 2, 3... address slices. When data is transmitted for each channel, different address slices are allocated, and the buffer areas are selected in turn according to a preset rule for read and write operations;

[0063] Among them, the specific preset rule is: when the allocated address slice is full or a write cycle is completed, if the data writing is not completed, the next address slice is automatically allocated. At this time, the read address is the starting address of the address slice where the data was written in the previous round. After the last address slice is allocated, the next address slice is selected starting from the first address slice, ensuring that only one thread can perform read and write operations on the buffer area of the address slice.

[0064] S2. Perform cross-clock domain processing on the data through a handshake-type asynchronous FIFO, and splice the data so that the bit width meets the DDR maximum cache standard;

[0065] The step S2 includes the following sub-steps:

[0066] S2-1. After the handshake-type asynchronous FIFO receives the write request signal, the state of the write FIFO state machine changes, and a handshake signal is generated, waiting for the DDR response;

[0067] S2-2. Check whether there are idle storage units in the FIFO to store data; if so, when the write enable is valid, the FIFO first splices the channel data that does not meet the DDR data bit width into cache data with the DDR maximum data bit width, and then transfers the spliced data from the write clock domain to the storage clock domain and stores it at the position pointed to by the write pointer;

[0068] S2-3. When the amount of data cached in the FIFO reaches the set threshold, a write request signal is generated to the write arbitration module to obtain the access right to the bus;

[0069] S2-4. When receiving the write data request signal of the DDR, read the data from the buffer area of the FIFO;

[0070] S2-5. When receiving the write completion signal of the write arbitration module, stop generating the write request, output the write address plus the length of the data written this time, and change the write data count value to the count value after adding the number of data written this time;

[0071] S2-6. When the write data count value is greater than the write data length, stop the current round of data transmission and wait for the next round of data transmission.

[0072] S3. Write the data of each channel into the DDR address space selected by the write arbitration address scheduling;

[0073] Step S3 includes the following sub-steps:

[0074] S3-1. After the write arbitration module receives the write requests from each data source, it starts the write preparation for each channel in a polling manner;

[0075] Specifically, the write arbitration module checks each channel in turn and sends a specific write request to one of the channels in the available state. If the request is successfully processed, it means that the channel has completed a write operation; otherwise, it will try to send a request to the next available channel until all channels have been checked;

[0076] S3-2. When the write completion signal of the DDR is received, the write data, write address, and data length are transmitted to the AXI4 transfer bridge according to the priorities of each channel;

[0077] S3-3. The AXI4 transfer bridge converts the write protocol to the AXI4 protocol and calls the DDR control module to cache the write data into the corresponding buffer area of the DDR.

[0078] S4. When the read signal is valid, update the read address to the read address selected by the address scheduling;

[0079] S5. Read data from the read address selected by the address scheduling through read arbitration;

[0080] The said step S5 includes the following sub-steps:

[0081] S5-1. The read arbitration module receives the read request signal from the data receiving end and starts the read preparation for the data in a polling manner;

[0082] Specifically, the read arbitration module checks each channel in turn and sends a specific read request to one of the channels in the available state. If the request is successfully processed, it means that the channel has completed a read operation; otherwise, it will try to send a request to the next available channel until all channels have been checked;

[0083] S5-2. When the read completion signal of the DDR control module converted by the AXI4 transfer bridge is received, according to the different priorities of the data receiving end, output the read address, read data length, and read enable signal selected by the address slice round-robin scheduling method to the AXI4 transfer bridge;

[0084] S5-3. The AXI4 transfer bridge converts the read protocol to the AXI4 protocol and controls the DDR control module to read data from the corresponding address space.

[0085] S6. Perform cross-clock domain processing on the data through a handshake-type asynchronous FIFO and decompose the cached data into data that conforms to the bit width of the data receiving end;

[0086] Step S6 includes the following sub-steps:

[0087] S6-1: After the handshake-type asynchronous FIFO receives the read request signal, the state of the read FIFO state machine changes, and a handshake signal is generated to wait for the DDR response;

[0088] S6-2: The FIFO internally checks whether there are idle storage units to store data; if so, when the read valid signal is received, the FIFO first decomposes the cached data with the maximum data width of the DDR into received data that conforms to the data width of the data receiving end, and then transfers the decomposed data from the write clock domain to the storage clock domain and stores it at the position pointed to by the write pointer;

[0089] S6-3: When the amount of cached data in the FIFO is less than the set threshold, a read request signal is generated to the read arbitration module to obtain the access right to the bus;

[0090] S6-4: When the read enable signal of the data receiving end is received, data is read from the buffer area of the FIFO;

[0091] S6-5: When the read completion signal of the read arbitration module is received, the generation of the read request is stopped, the read address plus the length of the data read this time is output, and the read data count value is changed to the count value after adding the number of data read this time;

[0092] S6-6: When the read data count value is greater than the read data length, the reading of the current round of data is stopped, and waiting for the next round of data reading.

[0093] The above has described the embodiments of the present invention in detail in conjunction with the accompanying drawings, but the present invention is not limited to the described embodiments. For those skilled in the art, without departing from the principle and spirit of the present invention, various changes, modifications, substitutions, and variations to these embodiments including components still fall within the protection scope of the present invention.

Claims

1. A method for low-latency DDR off-chip memory access of multiple channels of data based on FPGA, characterized in that, It includes the following steps: S1. When the write signal is valid, select the write address and read address according to the address slice round-robin scheduling method; The S1 includes the following sub-steps: S1-1. Save the state of the write signal of the data source through a two-stage register structure. The first-stage register saves the current state, and the second-stage register saves the previous state. When the states saved in the two-stage registers are different and the current state saved in the first-stage register is valid, output a single-cycle write request signal; S1-2. Transmit the write enable signal to the FIFO; S1-3. Set multiple address slices for each path of data. Select the starting address of the data to be written through the address slice round-robin scheduling method, and select the starting address of the data written in the previous round as the read address; The address slice round-robin scheduling method is: divide the address space of the DDR into cache spaces of multiple channels, and divide the cache space of each channel into multiple buffer areas numbered 1, 2, 3... address slices. When each channel transmits data, allocate different address slices and select buffer areas to perform read and write operations in turn according to a preset rule; The preset rule for alternately selecting buffer areas to perform read and write operations is: when the allocated address slice is full or a write cycle is completed, if the data writing is not completed, automatically allocate the next address slice. At this time, the read address is the starting address of the address slice of the data written in the previous round. After the last address slice is allocated, the next address slice starts to be selected from the first address slice to ensure that only one thread can perform read and write operations on the buffer area of the address slice; S2. Perform cross-clock domain processing on the data through the FIFO, and splice the data so that the bit width meets the DDR maximum cache standard; S3. Write the data of each channel into the DDR address space selected by the address scheduling through write arbitration; S4. When the read signal is valid, update the read address to the read address selected by the address scheduling; S5. Read the data from the read address selected by the address scheduling through read arbitration; S6. Perform cross-clock domain processing on the data through the FIFO, and decompose the cached data into data that meets the bit width of the data receiving end.

2. The method for low-latency DDR off-chip memory access of multiplexed data based on FPGA according to claim 1, wherein The step S3 includes the following sub-steps: S3-1. After the write arbitration module receives the write requests of each data source, start the write preparation of each channel in a polling manner; S3-2. When receiving the write completion signal of the DDR, transmit the written data, write address and data length to the AXI4 transfer bridge according to the priorities of each channel; S3-3. The AXI4 transfer bridge converts the write protocol into the AXI4 protocol, and calls the DDR control module to cache the written data into the corresponding buffer area of the DDR.

3. The method for low-latency DDR off-chip memory access of multiplexed data based on FPGA according to claim 1, wherein The step S5 includes the following sub-steps: S5-1. After the read arbitration module receives the read request signal from the data receiving end, start the read preparation of the data in a polling manner; S5-2. When receiving the read completion signal of the DDR control module converted by the AXI4 transfer bridge, output the read address, read data length and read enable signal selected by the address slice round-robin scheduling method to the AXI4 transfer bridge according to the different priorities of the data receiving end; S5-3. The AXI4 transfer bridge converts the read protocol into the AXI4 protocol, and controls the DDR control module to read the data from the corresponding address space.

4. The method for low-latency DDR off-chip memory access of multiplexed data based on FPGA according to claim 1, wherein Step S2 includes the following sub-steps: S2-1. After the FIFO receives the write request signal, the state of the write FIFO state machine changes, and a handshake signal is generated to wait for the DDR response; S2-2. The FIFO internally checks whether there are idle storage units to store data; if so, when the write enable is valid, the FIFO first splices the channel data that does not conform to the DDR data width into buffer data with the maximum DDR data width, and then transfers the spliced data from the write clock domain to the storage clock domain and stores it at the position pointed to by the write pointer; S2-3. When the amount of data buffered in the FIFO reaches the set threshold, a write request signal is generated to the write arbitration module to obtain the access right to the bus; S2-4. When the DDR write data request signal is received, data is read from the buffer area of the FIFO; S2-5. When the write completion signal from the write arbitration module is received, the generation of the write request is stopped, the write address plus the length of the data written this time is output, and the write data count value is changed to the count value after adding the number of data written this time; S2-6. When the write data count value is greater than the write data length, this round of data transmission is stopped and waiting for the next round of data transmission.

5. The method for low-latency off-chip memory access of multiplexed data based on FPGA according to claim 1, wherein Step S6 includes the following sub-steps: S6-1. After the FIFO receives the read request signal, the state of the read FIFO state machine changes, and a handshake signal is generated to wait for the DDR response; S6-2. The FIFO internally checks whether there are idle storage units to store data; if so, when the read valid signal is received, the FIFO first decomposes the buffer data with the maximum DDR data width into received data that conforms to the data width of the data receiving end, and then transfers the decomposed data from the write clock domain to the storage clock domain and stores it at the position pointed to by the write pointer; S6-3. When the amount of data buffered in the FIFO is less than the set threshold, a read request signal is generated to the read arbitration module to obtain the access right to the bus; S6-4. When the read enable signal of the data receiving end is received, data is read from the buffer area of the FIFO; S6-5. When the read completion signal from the read arbitration module is received, the generation of the read request is stopped, the read address plus the length of the data read this time is output, and the read data count value is changed to the count value after adding the number of data read this time; S6-6. When the read data count value is greater than the read data length, this round of data reading is stopped and waiting for the next round of data reading.

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