Computational graph simplification method and apparatus for ai chips, device, and medium

Abstract

The application discloses a calculation graph simplification method and device applied to an AI chip, equipment and a medium. The method comprises the following steps: acquiring a main calculation graph corresponding to an algorithm model and a sub-calculation graph to be searched; acquiring AI chip information matched with the main calculation graph, and establishing a main structure and a sub-structure matched with the main calculation graph and the sub-calculation graph respectively according to the AI chip information; matching and identifying the sub-structure and the main structure, acquiring a matching position when the sub-structure is matched in the main structure, and folding the main structure according to the AI chip information and the matching position to acquire a simplified main structure. After the main structure and the sub-structure corresponding to the main calculation graph and the sub-calculation graph are acquired, the abstracted calculation graph is used for sub-structure searching, matching and folding, and different hardware architectures are supported, so that the complexity of the calculation graph is simplified, and the cost of analysis and research is reduced.

Description

Technical Field

[0001] The embodiments of the present invention relate to artificial intelligence chip technology, and more particularly to a method, apparatus, device and medium for simplifying computational graphs for AI chips. Background Technology

[0002] Currently, in the optimization of computational graphs for neural network models in artificial intelligence (AI) chips, the market and research focus are gradually shifting towards the optimization of substructures, thus increasing the demand for substructure analysis.

[0003] However, the existing methods for generating different computation graph representations based on different hardware and software architectures cannot intuitively, conveniently, and uniformly search and match substructures, analyze the main computation graph based on hardware characteristics, or flexibly fold and simplify the main computation graph, leading to an increase in the cost of current computation graph optimization analysis and research. Summary of the Invention

[0004] This invention provides a method, apparatus, device, and medium for simplifying computational graphs applied to AI chips.

[0005] In a first aspect, embodiments of the present invention provide a method for simplifying computation graphs applied to AI chips, comprising: obtaining a main computation graph corresponding to an algorithm model and a sub-computation graph to be searched, wherein the main computation graph and the sub-computation graph respectively contain nodes and node descriptions of the algorithm model;

[0006] Obtain AI chip information that is compatible with the main computation graph, and establish a main structure and a substructure that are respectively matched with the main computation graph and the sub-computation graph based on the AI ​​chip information;

[0007] The substructure is matched and identified with the main structure. When the substructure is found to be matched in the main structure, the matching position is obtained. The main structure is folded according to the AI ​​chip information and the matching position to obtain a simplified main structure.

[0008] Secondly, embodiments of the present invention provide a computational graph simplification device for AI chips, comprising:

[0009] The computation graph acquisition module is used to acquire the main computation graph corresponding to the algorithm model and the sub-computation graph to be searched, wherein the main computation graph and the sub-computation graph respectively contain the nodes and node descriptions of the algorithm model;

[0010] The structure acquisition module is used to acquire AI chip information that is compatible with the main computation graph, and to determine the main structure and sub-structure that are respectively matched with the main computation graph and the sub-computation graph based on the AI ​​chip information.

[0011] The matching and folding module is used to match and identify the substructure with the main structure. When it is determined that the substructure is matched in the main structure, the matching position is obtained. The main structure is folded according to the AI ​​chip information and the matching position to obtain a simplified main structure.

[0012] Thirdly, embodiments of the present invention provide a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the method described above.

[0013] Fourthly, embodiments of the present invention provide a storage medium for computer-executable instructions, on which a computer program is stored, which, when executed by a processor, implements the method described above.

[0014] This application embodiment obtains the main structure and substructure corresponding to the main computation graph and sub-computation graph respectively, and then uses the abstracted computation graph to perform substructure search, matching and folding. It also supports different hardware architectures, thereby simplifying the complexity of the computation graph and reducing the cost of analysis and research. Attached Figure Description

[0015] Figure 1 This is a flowchart of a computation graph simplification method for AI chips provided in Embodiment 1 of the present invention;

[0016] Figure 2 This is a flowchart of the computation graph simplification method for AI chips provided in Embodiment 2 of the present invention;

[0017] Figure 3 This is a schematic diagram of the computation graph simplification device for AI chips provided in Embodiment 3 of the present invention;

[0018] Figure 4 This is a schematic diagram of the structure of a computer device provided in Embodiment 4 of the present invention. Detailed Implementation

[0019] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0020] Example 1

[0021] Figure 1 This is a flowchart of a computation graph simplification method for AI chips provided in Embodiment 1 of the present invention. This embodiment is applicable to the simplification of computation graphs. The method can be executed by a computation graph simplification device for AI chips, which can be implemented in software and / or hardware. The computation graph simplification method for AI chips includes:

[0022] Step S101: Obtain the main computation graph corresponding to the algorithm model and the sub-computation graph to be searched.

[0023] Specifically, the algorithm model can be a neural network model or a Bayesian model; this implementation does not limit the specific type of algorithm model. Furthermore, the main computation graph corresponding to the algorithm model can be generated using any deep learning framework, and the main computation graph generated by any deep learning framework can include the nodes and node descriptions of the algorithm model. The obtained main computation graph can be in the form of an intermediate representation, for example: %22 = "gather"(%arg60, %19){dimension_numbers = collapsed_slice_dims = dense} <0> :tensor<1xi64>,index_vector_dim=1:i64,offset_dims=dense <1> :tensor<1xi64>,start_index_map=dense <0> The code snippet `{}` defines a tensor named `<1x1xi64>`, with indices_are_sorted = `fal se`, name = "gather.278", op_id = 7:i64, slice_size = dense<[1,1024]>:tensor<2xi64>, tensor_split = dense<[4,1]>:tensor<1x2xi32>, unique_name = "common20_gather"`. Here, `gather` is the name of the node, and the content within the curly braces `{}` is the node description. This implementation is merely illustrative and does not specify the exact number of nodes in the main computation graph or the content of the node descriptions.

[0024] The sub-computation graph can be a computation graph with a classic known structure, or a computation graph selected by the user with strong universality. The sub-computation graph will also include nodes and node descriptions of the algorithm model. However, the number of nodes in the sub-computation graph is usually no more than the number of nodes in the main computation graph. Its specific form is roughly the same as the form of the main computation graph described above. In this embodiment, there is no limitation on the number of nodes or the specific form of the sub-computation graph.

[0025] Step S102: Obtain AI chip information that is compatible with the main computation graph, and establish a main structure and a substructure that are compatible with the main computation graph and the sub-computation graph respectively based on the AI ​​chip information.

[0026] Optionally, obtain AI chip information that is compatible with the main computation graph, and establish main structures and substructures that match the main computation graph and sub-computation graph respectively based on the AI ​​chip information, including:

[0027] The node descriptions in the main computation graph are identified to obtain AI chip information that is compatible with the main computation graph. The node descriptions include node type and node name. Based on the AI ​​chip information, the main computation graph and the sub-computation graph are traversed backward to establish the main structure and the sub-structure. The main structure and the sub-structure contain the nodes, node descriptions and node dependencies of the algorithm model, respectively.

[0028] In this embodiment, after obtaining the main computation graph, the node descriptions in the main computation graph are identified. Since the node descriptions include node names and node types, and different AI chip information supports different node types, given that the node types in the main computation graph are known, the main computation graph information adapted to the AI ​​chip information can be obtained based on the correspondence between node types and AI chip information. The AI ​​chip information may include the AI ​​chip type, underlying hardware operator information based on the AI ​​chip, or hardware parameter information, etc. This embodiment does not limit the specific content contained in the AI ​​chip information. Furthermore, after obtaining the AI ​​chip information, the main computation graph and sub-computation graphs can be traversed backwards according to the AI ​​chip type to establish the main structure and sub-structures.

[0029] It should be noted that, in this embodiment, when obtaining the main structure corresponding to the main computation graph, the main computation graph is traversed backward according to a determined traversal method to obtain node dependencies, and an initial main structure is constructed based on the nodes, node descriptions, and node dependencies. At this point, the obtained initial main structure may contain redundant information. Therefore, non-computational nodes and node descriptions of a specified form can be deleted from the initial main structure according to specified rules, and node evaluation calculations are performed based on AI chip information to obtain the final main structure. Of course, this embodiment only illustrates the method of obtaining the main structure; the method of obtaining substructures is largely the same, and will not be elaborated upon in this embodiment.

[0030] Step S103: Match and identify the substructure with the main structure. When it is determined that a substructure is matched in the main structure, obtain the matching position. Based on the AI ​​chip information and the matching position, fold the main structure to obtain a simplified main structure.

[0031] Optionally, the substructure is matched and identified with the main structure, including: traversing backwards from the main structure to find a target node that is the same as the last node of the substructure; obtaining the attribute information of the target node and the attribute information of the last node, wherein the attribute information includes associated parent nodes; when it is determined that the associated parent node contained in the attribute information of the target node is exactly the same as or overlaps with the associated parent node contained in the attribute information of the last node, then traversing backwards from the target node in sequence; determining whether there is a node in the main structure that is the same as the remaining nodes in the substructure and also has the same attribute information; if so, it is determined that a substructure is matched in the main structure; otherwise, no substructure is matched in the main structure.

[0032] Specifically, when the nodes contained in the main structure are: ABCDEFGHICDE FG HI CDEFGH IC DEFGH IA DIA, and the nodes contained in the substructure are GHI, the system searches backwards from the main structure for a target node that is identical to the last node I in the substructure. When the target node I in the second-to-last position in the main structure is obtained, since the main structure and the substructure each contain description information for each node, and the description information is the attribute information of the node, and the attribute information contains the associated parent node, it is determined whether the associated parent node of the target node I in the main structure is completely identical or duplicated with the last node I in the substructure. Completely identical is determined by exact matching, that is, if the number and type of associated parent nodes contained in both are the same, then the two nodes are determined to be matched. Duplicate is determined by coarse matching, that is, if the associated parent node of the last node I in the substructure is a subset of the associated parent node of the target node I in the main structure, then the two nodes are determined to be matched. Of course, users can choose between exact matching and coarse matching according to the actual situation of simplified matching, and this embodiment does not limit them.

[0033] When it is determined that the target node I in the main structure matches the last node I in the substructure, the target node D in the third-to-last position of the main structure is sequentially searched for its identity with the next node H in the substructure. Clearly, they are not the same, so there is no need to compare the associated parent nodes. Then, the process restarts from the second-to-last position in the main structure, traversing backwards until a new target node I is found in the fifth-to-last position. The matching comparison is then performed again in the same manner. When it is determined that the nodes GHI in the fifth, sixth, and seventh-to-last positions of the main structure are the same as the associated parent nodes of each node in the substructure GHI, a substructure is found to be matched in the main structure, and the position of node GHI in the main structure is marked as the first matching position. When multiple substructures are matched in multiple positions in the main structure, multiple matching positions can be obtained. This embodiment does not limit the number of matching positions obtained in the main structure.

[0034] Optionally, the main structure is folded according to the AI ​​chip information and the matching position to obtain a simplified main structure, including: folding the substructures at the matching position to obtain a folded main structure; obtaining the hardware parameter information of the AI ​​chip information, determining the hardware resource information of each node in the folded main structure according to the hardware parameter information, wherein the hardware resource information includes storage space usage and runtime evaluation information; and adding the hardware resource information of each node to the folded main structure to obtain the simplified main structure.

[0035] Specifically, in this embodiment, after determining multiple matching positions through matching, the substructures at the matching positions are folded to obtain a folded main structure. For example, after obtaining the first matching position in the main structure, the node GHI at the matching position can be represented by a node O, thereby realizing the folding of the main structure. Simultaneously, hardware parameter information of the AI ​​chip is obtained, and the hardware resource information of each node in the folded main structure is determined based on this information. This hardware resource information includes storage space usage and runtime evaluation information. The hardware resource information of each node is then added to the folded main structure to obtain a simplified main structure. Therefore, this embodiment simplifies the computation graph while retaining hardware parameter information, further facilitating user analysis and optimization based on the simplified main structure.

[0036] It should be noted that the algorithm complexity used in the above matching and folding method is calculated as follows: Assume there is a graph G(V,E) consisting of a vertex set V:{v1,v2,v3,......} and an edge set E:{e1,e2,e3,.......}, where the edge ei connected to any fixed vertex vi belongs to E':{e'1,e'2,e'3,.......}. Therefore, there are graphs T and S belonging to G, where T is the main graph and S is the subgraph. To precisely match the subgraph S in T, we have: the complexity of traversing the vertices of the main graph is O(V), the consistency of nodes between the main graph and the subgraph is O(E'+E'log2E'), and the time complexity after vectorizing the node determination is O(E'log2E'). Therefore, the current algorithm complexity is O(VE'log2E'). Of course, this embodiment is only an example and does not limit the specific calculation method of the algorithm complexity during matching and folding.

[0037] Optionally, when the number of substructures is determined to be multiple, after folding the main structure according to the AI ​​chip information and matching position to obtain a simplified main structure, the following steps are also included:

[0038] When it is determined that there is an association between multiple substructures in the main structure, the substructure at the matching position is represented by a specified node using a non-cloning method to obtain the updated main structure; the nodes associated with the substructure at the matching position in the remaining substructures to be matched are replaced with specified nodes to obtain the updated remaining substructures to be matched; the updated remaining substructures to be matched are matched and identified with the updated main structure to obtain a new matching position, and the remaining substructures to be matched at the new matching position are folded to simplify the simplified main structure.

[0039] Specifically, when there are multiple substructures, for example, the main structure contains nodes as follows: ABCDEFGHICDEFGHICDEFG H IC DEFGH IA DIA, the first substructure contains node GHI, and the second substructure contains node EF. When GHI is matched at the first matching position in the main structure, and GHI is replaced with O, if the parent node of E is H, directly replacing it will prevent a precise match in the second substructure since GHI has already been replaced with O. In this case, EF can be adjusted to E(parent node -> H -> modified to O)F, which adaptively modifies the nodes related to H in the second substructure. This method can be called the non-cloning method. While using the non-cloning method may increase memory pressure due to the avoidance of redundant calculations of H, it will not increase the computation time of the H node. When both the main structure and the second substructure are updated, the updated second substructure can be matched and identified with the updated main structure to obtain a new matching position. The substructure at the new matching position is then folded to optimize the simplified main structure obtained by matching and folding the first substructure, thereby further reducing the complexity of the computation graph. The method of folding the second substructure is roughly the same as that of folding the first substructure, and will not be described in detail in this embodiment.

[0040] Optionally, when the number of substructures is determined to be multiple, after folding the main structure according to the AI ​​chip information and the matching position to obtain a simplified main structure, the method further includes: when it is determined that there is an association between multiple substructures in the main structure, using a cloning method to combine the substructure at the matching position with a specified node and the associated node in the other substructures to be matched to obtain an updated main structure; directly matching and identifying the other substructures to be matched with the updated main structure to obtain a new matching position, and folding the other substructures to be matched at the new matching position to simplify the simplified main structure.

[0041] Specifically, when the number of substructures is determined to be multiple, for example, the main structure contains nodes as follows: ABCDEFGHICDEFGHICDEFG H IC DEFGH IA DIA, the first substructure contains node GHI, and the second substructure contains node EF. When GHI is matched at the first matching position in the main structure, if GHI is replaced with O, and if the parent node of E is H, direct replacement would prevent accurate matching of the second substructure since GHI has already been replaced with O. In this case, GHI matched at the first matching position can be replaced with H'O, where H' is a clone of H. The second substructure can then remain unchanged as E(parent node -> H)F. This method can be called cloning. While cloning may reduce memory pressure by repeatedly calculating the H node, it increases the computation time for the H node. If the main structure is updated but the second substructure remains unchanged, the second substructure can continue to be matched and identified with the updated main structure to obtain a new matching position. The substructure at the new matching position is then folded to optimize the simplified main structure obtained by matching and folding the first substructure, further reducing the complexity of the computation graph. The method of folding the second substructure is largely the same as that of folding the first substructure, and will not be described in detail in this embodiment. Of course, this method is only used as an example of cloning and non-cloning methods, and does not limit the specific configuration method used. Users can select the appropriate method based on their actual matching and folding needs.

[0042] This application obtains the main structure and substructure corresponding to the main computation graph and sub-computation graph respectively, and then uses the abstracted computation graph to search, match and fold the substructure. It also supports different hardware architectures, thereby simplifying the complexity of the computation graph and reducing the cost of analysis and research.

[0043] Example 2

[0044] Figure 2 This is a flowchart of a computational graph simplification method for AI chips provided in Embodiment 2 of the present invention. Based on the above embodiments, after folding the main structure according to AI chip information and matching positions to obtain a simplified main structure, the method further includes: detecting the simplified main structure, and issuing an alarm when the simplified main structure is found to be abnormal based on the detection results. Figure 2 As shown, the method includes:

[0045] Step S201: Obtain the main computation graph corresponding to the algorithm model and the sub-computation graph to be searched.

[0046] Step S202: Obtain AI chip information that is compatible with the main computation graph, and establish main structures and substructures that match the main computation graph and subcomputation graph respectively based on the AI ​​chip information.

[0047] Optionally, obtain AI chip information that is compatible with the main computation graph, and establish main structures and substructures that match the main computation graph and sub-computation graph respectively based on the AI ​​chip information, including:

[0048] The node descriptions in the main computation graph are identified to obtain AI chip information that is compatible with the main computation graph. The node descriptions include node type and node name. Based on the AI ​​chip information, the main computation graph and the sub-computation graph are traversed backward to establish the main structure and the sub-structure. The main structure and the sub-structure contain the nodes, node descriptions and node dependencies of the algorithm model, respectively.

[0049] Step S203: Match and identify the substructure with the main structure. When it is determined that a substructure is matched in the main structure, obtain the matching position. Based on the AI ​​chip information and the matching position, fold the main structure to obtain a simplified main structure.

[0050] Optionally, the substructure is matched and identified with the main structure, including: traversing backwards from the main structure to find a target node that is the same as the last node of the substructure; obtaining the attribute information of the target node and the attribute information of the last node, wherein the attribute information includes associated parent nodes; when it is determined that the associated parent node contained in the attribute information of the target node is exactly the same as or overlaps with the associated parent node contained in the attribute information of the last node, then traversing backwards from the target node in sequence; determining whether there is a node in the main structure that is the same as the remaining nodes in the substructure and also has the same attribute information; if so, it is determined that a substructure is matched in the main structure; otherwise, no substructure is matched in the main structure.

[0051] Step S204: The simplified main structure is tested by the calculation diagram simplification self-test system, and an alarm is triggered when the simplified main structure is found to be abnormal based on the test results.

[0052] Specifically, after obtaining the simplified main structure, this implementation method performs a check on it, specifically checking for changes in the number of nodes. If the number of nodes decreases or remains unchanged, it indicates that the simplified main structure is normal; a decrease in the number of nodes indicates that a substructure has been matched within the main structure, while a unchanged number of nodes indicates that no substructure has been matched within the main structure. However, if the number of nodes in the simplified main structure increases, it indicates that the simplified main structure is abnormal, because an increase in the number of nodes is impossible during normal matching and folding. The reason for this situation may be an error in the algorithm matching or folding.

[0053] In particular, when the simplified main structure is abnormal, an alarm message will be generated and an alarm will be triggered to prompt the developers to check the software in a timely manner to restore normal processing operations, thereby further ensuring the accuracy of the simplified calculation graph.

[0054] This application obtains the main structure and substructure corresponding to the main computation graph and sub-computation graph respectively, and then uses the abstracted computation graph to search, match and fold the substructure. It also supports different hardware architectures, thereby simplifying the complexity of the computation graph and reducing the cost of analysis and research.

[0055] Example 3

[0056] Figure 3 This is a schematic diagram of a computational graph simplification device for AI chips provided in Embodiment 3 of the present invention. This device can execute the computational graph simplification methods for AI chips involved in the above embodiments. This device can be implemented in software and / or hardware, such as... Figure 4 As shown, the computational graph simplification device applied to AI chips specifically includes: a computational graph acquisition module 310, a structure acquisition module 320, and a matching and folding module 330.

[0057] The computation graph acquisition module 310 is used to acquire the main computation graph corresponding to the algorithm model and the sub-computation graph to be searched, wherein the main computation graph and the sub-computation graph contain the nodes and node descriptions of the algorithm model, respectively.

[0058] The structure acquisition module 320 is used to acquire AI chip information that is compatible with the main computation graph, and to establish a main structure and a substructure that are respectively matched with the main computation graph and the sub-computation graph based on the AI ​​chip information.

[0059] The matching and folding module 330 is used to match and identify the substructure with the main structure. When it is determined that a substructure is matched in the main structure, the matching position is obtained. Based on the AI ​​chip information and the matching position, the main structure is folded to obtain a simplified main structure.

[0060] Optionally, a structure acquisition module is used to identify the node descriptions in the main computation graph and obtain AI chip information that is compatible with the main computation graph. The node descriptions include node type and node name.

[0061] Based on the AI ​​chip information, backward traversal calculations are performed on the main computation graph and the sub-computation graph respectively to establish the main structure and the sub-structure. The main structure and the sub-structure respectively contain the nodes of the algorithm model, node descriptions and node dependencies.

[0062] Optionally, the matching module includes a main structure simplification submodule, which is used to fold the substructures at the matching positions to obtain the folded main structure;

[0063] Obtain hardware parameter information of AI chip information, and determine hardware resource information of each node in the folded main structure based on hardware parameter information. The hardware resource information includes storage space usage and runtime evaluation information.

[0064] Add the hardware resource information of each node to the collapsed main structure to obtain the simplified main structure.

[0065] Optionally, the matching module includes a matching submodule, which is used to traverse backwards from the main structure to find the target node that is the same as the last node of the substructure;

[0066] Obtain the attribute information of the target node and the attribute information of the last node, where the attribute information includes the associated parent node;

[0067] When it is determined that the associated parent node contained in the attribute information of the target node is exactly the same as or overlaps with the associated parent node contained in the attribute information of the last node, the main structure is traversed in reverse order from the target node.

[0068] Determine if there exists a node in the main structure that is identical to the remaining nodes in the substructure and has the same attribute information. If it exists, then the substructure is matched in the main structure; otherwise, the substructure is not matched in the main structure.

[0069] Optionally, the device also includes a non-cloning matching optimization module, which is used to represent the substructure at the matching position with a specified node in a non-cloning manner when it is determined that there is an association between multiple substructures in the main structure, so as to obtain the updated main structure.

[0070] Replace the nodes associated with the matching substructure in the remaining substructures with the specified nodes to obtain the updated remaining substructures to be matched.

[0071] The updated substructures to be matched are matched with the updated main structure to obtain new matching positions. The remaining substructures to be matched at the new matching positions are then folded to simplify the simplified main structure.

[0072] Optionally, the device also includes a clone matching optimization module, which, when it is determined that there is an association between multiple substructures in the main structure, uses a cloning method to combine the substructure at the matching position with a specified node and the associated node in the other substructures to be matched to obtain an updated main structure.

[0073] The remaining substructures to be matched are directly matched and identified with the updated main structure to obtain new matching positions. The remaining substructures to be matched at the new matching positions are then folded to simplify the simplified main structure.

[0074] Optionally, the device also includes a detection module for detecting the simplified main structure;

[0075] An alarm will be triggered when the simplified main structure is found to be abnormal based on the test results.

[0076] Example 4

[0077] Figure 4 This is a schematic diagram of the structure of a computer device provided in Embodiment Six of the present invention, as shown below. Figure 4 As shown, the computer device includes a processor 610, a memory 620, an input device 630, and an output device 640; the number of processors 610 in the computer device can be one or more. Figure 4 Taking a processor 610 as an example; the processor 610, memory 620, input device 630, and output device 640 in a computer device can be connected via a bus or other means. Figure 4 Taking the example of a connection between China and Israel via a bus.

[0078] The memory 620, as a computer-readable storage medium, can be used to store software programs, computer-executable programs, and modules, such as the program instructions / modules corresponding to the computational graph simplification method applied to AI chips in this embodiment of the invention (e.g., the recurrent neural network acquisition module 410, quantization scale calculation module 420, quantization parameter calculation module 430, and post-training quantization network generation module 440 in the parameter quantization device of the recurrent neural network), and the program instructions / modules corresponding to the computational graph simplification method applied to AI chips in this embodiment of the invention (e.g., the input data sequence acquisition module 510, quantization input sequence input module 520, and network calculation module 530 in the inference device of the quantization network). The processor 610 executes various functional applications and data processing of the computer device by running the software programs, instructions, and modules stored in the memory 620, thereby realizing the above-mentioned computational graph simplification method applied to AI chips.

[0079] Computational graph simplification methods applied to AI chips include:

[0080] Obtain the main computation graph corresponding to the algorithm model and the sub-computation graph to be searched. The main computation graph and the sub-computation graph contain the nodes and node descriptions of the algorithm model, respectively.

[0081] Obtain AI chip information that is compatible with the main computation graph, and determine the main structure and substructure that match the main computation graph and sub-computation graph respectively based on the AI ​​chip information;

[0082] The substructure is matched and identified with the main structure. When a substructure is found to be matched in the main structure, the matching position is obtained. Based on the AI ​​chip information and the matching position, the main structure is folded to obtain a simplified main structure.

[0083] The memory 620 may primarily include a program storage area and a data storage area. The program storage area may store the operating system and at least one application program required for a given function; the data storage area may store data created based on terminal usage. Furthermore, the memory 620 may include high-speed random access memory and non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some instances, the memory 620 may further include memory remotely located relative to the processor 610, which can be connected to the computer device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0084] Input device 630 can be used to receive input digital or character information, and to generate key signal inputs related to user settings and function control of the computer device. Output device 640 may include display devices such as a display screen.

[0085] Example 5

[0086] Embodiment 5 of the present invention also provides a storage medium containing computer-executable instructions, which, when executed by a computer processor, are used to execute a computation graph simplification method applied to an AI chip;

[0087] Obtain the main computation graph corresponding to the algorithm model and the sub-computation graph to be searched. The main computation graph and the sub-computation graph contain the nodes and node descriptions of the algorithm model, respectively.

[0088] Obtain AI chip information that is compatible with the main computation graph, and determine the main structure and substructure that match the main computation graph and sub-computation graph respectively based on the AI ​​chip information;

[0089] The substructure is matched and identified with the main structure. When a substructure is found to be matched in the main structure, the matching position is obtained. Based on the AI ​​chip information and the matching position, the main structure is folded to obtain a simplified main structure.

[0090] Of course, the computer-executable instructions provided in the embodiments of the present invention are not limited to the above-described method operations, but can also perform related operations in the computation graph simplification method for AI chips provided in any embodiment of the present invention.

[0091] Based on the above description of the implementation methods, those skilled in the art can clearly understand that the present invention can be implemented using software and necessary general-purpose hardware, and of course, it can also be implemented using hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as a computer floppy disk, read-only memory (ROM), random access memory (RAM), flash memory, hard disk, or optical disk, etc., including several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods of the various embodiments of the present invention.

[0092] It is worth noting that the various units and modules included in the above embodiments are only divided according to functional logic, but are not limited to the above division, as long as the corresponding functions can be achieved; in addition, the specific names of each functional unit are only for easy differentiation and are not used to limit the scope of protection of the present invention.

[0093] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A method for simplifying a computational graph applied to an AI chip, the method comprising: The method comprises the following steps: obtaining a main computation graph corresponding to an algorithm model and a sub-computation graph to be searched, wherein the main computation graph and the sub-computation graph respectively contain nodes and node descriptions of the algorithm model; obtaining AI chip information adapted to the main computation graph, and establishing a main structure and a sub-structure matched with the main computation graph and the sub-computation graph respectively according to the AI chip information; matching and identifying the sub-structure and the main structure, obtaining a matching position when it is determined that the sub-structure is matched in the main structure, and folding the main structure according to the AI chip information and the matching position to obtain a simplified main structure; the step of obtaining AI chip information adapted to the main computation graph and establishing a main structure and a sub-structure matched with the main computation graph and the sub-computation graph respectively according to the AI chip information comprises: identifying node descriptions in the main computation graph to obtain AI chip information adapted to the main computation graph, wherein the node descriptions include node types and node names; performing backward traversal calculation on the main computation graph and the sub-computation graph respectively according to the AI chip information to establish the main structure and the sub-structure, wherein the main structure and the sub-structure respectively contain nodes, node descriptions and node dependency relationships of the algorithm model.

2. The method of claim 1, wherein, the step of folding the main structure according to the AI chip information and the matching position to obtain a simplified main structure comprises: folding the sub-structure at the matching position to obtain a folded main structure; obtaining hardware parameter information of the AI chip information, and determining hardware resource information of each node in the folded main structure according to the hardware parameter information, wherein the hardware resource information includes storage space usage and running time evaluation information; adding the hardware resource information of each node to the folded main structure to obtain the simplified main structure.

3. The method of claim 1, wherein, the step of matching and identifying the sub-structure and the main structure comprises: finding a target node same as a last node of the sub-structure from the main structure by reverse traversal; obtaining attribute information of the target node and attribute information of the last node, wherein the attribute information contains associated parent nodes; when it is determined that the associated parent nodes contained in the attribute information of the target node are completely same as or overlap with the associated parent nodes contained in the attribute information of the last node, the main structure is sequentially traversed from the target node by reverse traversal; determining whether there is a node same as and having same attribute information as a remaining node in the sub-structure in the main structure, if there is, it is determined that the sub-structure is matched in the main structure, otherwise, the sub-structure is not matched in the main structure.

4. The method of claim 1, wherein, when it is determined that the number of the sub-structures is multiple, after the step of folding the main structure according to the AI chip information and the matching position to obtain a simplified main structure, the method further comprises: When it is determined that there is a correlation relationship between the plurality of sub-structures in the main structure, the sub-structure at the matching position is represented by a specified node in a non-cloning manner to obtain an updated main structure; The nodes in the remaining to-be-matched sub-structures that are correlated to the sub-structure at the matching position are replaced by the specified node to obtain updated remaining to-be-matched sub-structures; The updated remaining to-be-matched sub-structures are matched with the updated main structure to obtain a new matching position, and the remaining to-be-matched sub-structure at the new matching position is folded to fold and simplify the simplified main structure.

5. The method of claim 1, wherein, After the AI chip information and the matching position are used to fold the main structure to obtain a simplified main structure, the method further includes: When it is determined that there is a correlation relationship between the plurality of sub-structures in the main structure, the sub-structure at the matching position is represented by a specified node and a correlated node in the remaining to-be-matched sub-structure in a cloning manner to obtain an updated main structure; The remaining to-be-matched sub-structures are directly matched with the updated main structure to obtain a new matching position, and the remaining to-be-matched sub-structure at the new matching position is folded to fold and simplify the simplified main structure.

6. The method according to any one of claims 1 to 5, characterized in that, After the AI chip information and the matching position are used to fold the main structure to obtain a simplified main structure, the method further includes: The simplified main structure is detected; When it is determined that the simplified main structure is abnormal according to a detection result, an alarm is given.

7. A computing graph simplification apparatus applied to an AI chip, characterized in that, The method includes: A computation graph obtaining module is configured to obtain a main computation graph corresponding to an algorithm model and a to-be-searched sub-computation graph, where the main computation graph and the sub-computation graph respectively include nodes and node descriptions of the algorithm model; A structure obtaining module is configured to obtain AI chip information adapted to the main computation graph, and establish a main structure and a sub-structure matched with the main computation graph and the sub-computation graph respectively according to the AI chip information; A matching and folding module is configured to match the sub-structure with the main structure, obtain a matching position when it is determined that the sub-structure is matched in the main structure, fold the main structure according to the AI chip information and the matching position to obtain a simplified main structure; The structure obtaining module is configured to identify node descriptions in the main computation graph, and obtain AI chip information adapted to the main computation graph, where the node descriptions include node types and node names; The main computation graph and the sub-computation graph are respectively calculated backward according to the AI chip information, and the main structure and the sub-structure are established, where the main structure and the sub-structure respectively include nodes, node descriptions, and node dependency relationships of the algorithm model.

8. A computer device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, The processor implements the method of any one of claims 1-6 when executing the program.

9. A storage medium of computer executable instructions, on which a computer program is stored, characterized in that, The program, when executed by the processor, implements the method of any one of claims 1-6.

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