Simulation platform providing method, simulation method and device of memory computing integrated system

Abstract

The present disclosure provides a simulation platform providing method, a simulation method and a device of a memory-compute integrated system. The memory-compute integrated system includes at least one processing unit. The simulation platform providing method of the memory-compute integrated system includes: providing a model library including a plurality of modules implemented using a hardware description language, wherein the plurality of modules include a first module, the first module is used to simulate the processing unit, the processing unit includes a memristor array and a peripheral circuit for the memristor array, and the processing unit is configured to perform a memory-compute integrated operation. The provided simulation platform and simulation method have better flexibility.

Description

Technical Field

[0001] The embodiments of this disclosure relate to in-memory computing systems, and more specifically, to a method, simulation method, and apparatus for providing a simulation platform for an in-memory computing system. Background Technology

[0002] Neural networks have made significant progress in various artificial intelligence fields such as image classification, object detection, and speech recognition, bringing about a revolution in information intelligence for human society. Meanwhile, the development of neural network applications is inseparable from the performance improvement of neural network accelerator chips. Traditional neural network accelerator chips are limited by the design of separating storage and computing units in the von Neumann architecture, resulting in a bottleneck in memory bandwidth. In-memory computing systems based on memristors (such as resistive random access memory, phase-change memory, resistive random access memory, and magnetoresistive random access memory) utilize physical laws such as Ohm's law and Kirchhoff's current law to perform simulation calculations within the memory array, integrating storage and computing units. This avoids large amounts of data transfer and significantly reduces the demand for storage bandwidth.

[0003] Neural network acceleration chips based on in-memory computing systems have proven to have a significant advantage in energy efficiency compared to traditional computing chips. Future research should focus on larger array sizes, greater versatility, and more comprehensive system functions. However, the lack of effective system simulation tools makes the design and optimization of large-scale in-memory computing systems extremely challenging. Summary of the Invention

[0004] At least one embodiment of this disclosure provides a method for providing a simulation platform for an in-memory computing system, the in-memory computing system including at least one processing unit, the method comprising: providing a model library including a plurality of modules implemented using a hardware description language, wherein the plurality of modules includes a first module for simulating the processing unit, the processing unit including the memristor array and peripheral circuitry for the memristor array, and the processing unit configured to perform in-memory computing operations.

[0005] For example, in a method provided in at least one embodiment of this disclosure, the in-memory computing system includes at least one computing block, the computing block includes at least one processing unit, and the computing block is configured to assign computing tasks to the included processing units for execution. The plurality of modules further includes a second module, the second module being used to simulate the computing block.

[0006] The method provided in at least one embodiment of this disclosure further includes: implementing the modules in the model library using a transaction-level modeling approach, wherein the communication function and the computing function are modeled separately for the object modules being modeled.

[0007] For example, in the method provided in at least one embodiment of this disclosure, at least one module in the model library includes at least one process block, and the at least one process block is provided with a sensitivity table to represent the activation conditions of the process corresponding to the process block.

[0008] For example, in the method provided in at least one embodiment of this disclosure, the hardware description language is System C, the modules in the model library are provided via SC_MODULE, and the at least one process block corresponds to an SC-METHOD process or an SC_THREAD process.

[0009] For example, in a method provided in at least one embodiment of this disclosure, the at least one process block includes a first process block configured to be triggered and activated based on a clock edge and inherited from the SC_THREAD process.

[0010] For example, in at least one embodiment of the method provided in this disclosure, the modules in the model library include a clock terminal, a reset terminal, and input and output ports.

[0011] The clock terminal and the reset terminal are used to input clock signals and reset signals, respectively, to drive and reset the process blocks in the corresponding modules. The input and output ports are used to input the data to be processed and output the processed data.

[0012] At least one embodiment of this disclosure also provides a simulation method for an in-memory computing system. The simulation method includes: obtaining first configuration information for a simulation model to be simulated for the in-memory computing system, wherein the in-memory computing system includes at least one processing unit; selecting a required module from a model library including multiple modules implemented using a hardware description language, wherein the multiple modules include at least one first module, the first module being used to simulate the processing unit; and constructing the simulation model based on the first configuration information and the selected required module, wherein the processing unit includes the memristor array and peripheral circuitry for the memristor array, and the processing unit is configured to perform in-memory computing operations.

[0013] For example, in the simulation method provided in at least one embodiment of this disclosure, the in-memory computing system includes at least one computing block, the computing block includes at least one processing unit, and the computing block is configured to assign computing tasks to the included processing unit for execution. The plurality of modules further includes a second module, the second module being used to simulate the computing block.

[0014] For example, in the simulation method provided in at least one embodiment of this disclosure, the modules in the model library adopt a transaction-level modeling approach and model the communication function and computing function of the object module being modeled respectively.

[0015] For example, in the simulation method provided in at least one embodiment of this disclosure, at least one module in the model library includes at least one process block, and the at least one process block is provided with a sensitivity table to represent the activation conditions of the process corresponding to the process block.

[0016] For example, in the simulation method provided in at least one embodiment of this disclosure, the hardware description language is SystemC, the modules in the model library are provided through SC_MODULE, and the at least one process block corresponds to an SC-METHOD process or an SC_THREAD process.

[0017] For example, in the simulation method provided in at least one embodiment of this disclosure, the at least one process block includes a first process block, which is configured to be triggered and activated based on a clock edge and inherits from the SC_THREAD process.

[0018] For example, at least one embodiment of the simulation method provided by this disclosure further includes: obtaining second configuration information based on a neural network model to be configured into the simulation model; configuring the simulation model using the second configuration information; and inputting test data into the simulation model so that the simulation model processes the test data to obtain the performance index of the first model in the in-memory computing system.

[0019] For example, in the simulation method provided in at least one embodiment of this disclosure, obtaining second configuration information based on a neural network model to be configured into the simulation model includes: compiling the neural network model using a memory-based compiler to obtain a neural network configuration as the second configuration information.

[0020] At least one embodiment of this disclosure also provides a simulation apparatus, the simulation apparatus comprising: at least one processor; and a memory storing executable instructions, wherein the executable instructions, when executed by the at least one processor, perform the simulation method according to at least one embodiment of this disclosure. Attached Figure Description

[0021] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0022] Figure 1 This is a schematic diagram of the architecture of an in-memory computing system.

[0023] Figure 2 This is a schematic diagram of a memristor array.

[0024] Figure 3A flowchart illustrating a method for providing a simulation platform for an in-memory computing system, provided for at least one embodiment of this disclosure;

[0025] Figure 4 for Figure 3 A schematic diagram of the simulation platform provided by the method described;

[0026] Figure 5 for Figure 4 A schematic diagram illustrating examples of modules in the model library of the simulation platform shown;

[0027] Figure 6 for Figure 4 This diagram illustrates an example of interaction between modules in the model library of the simulation platform.

[0028] Figure 7 A flowchart illustrating a simulation method for an in-memory computing system, provided for at least one embodiment of this disclosure;

[0029] Figure 8 A flowchart illustrating a simulation method for another in-memory computing system provided for at least one embodiment of this disclosure;

[0030] Figure 9 for Figure 7 or Figure 8 A schematic diagram of the simulation method described above;

[0031] Figure 10 This is a schematic block diagram of a simulation device provided for at least one embodiment of the present disclosure. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0033] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0034] Memristors are a new type of information processing device with in-memory computing capabilities. They can perform computations on stored data in situ, eliminating the significant overhead of data transfer. Furthermore, memristors can perform operations directly in the analog domain (for example, multiplication based on Ohm's law and addition based on Kirchhoff's current law), thus enabling matrix-vector multiplication in one step without the overhead of analog-to-digital conversion.

[0035] As a two-terminal device, memristors have adjustable and non-volatile resistance, making them widely used in in-memory computing. According to Kirchhoff's current law and Ohm's law, an array of memristors can be used to perform multiply-accumulate calculations in parallel, with both storage and computation occurring within the individual devices of the memristor array. Therefore, based on this computing architecture suitable for memristor arrays, in-memory computing systems that do not require extensive data transfer can be implemented.

[0036] When in-memory computing systems are used to implement computing chips that are larger than traditional computing chip arrays (e.g., neural network accelerator chips), a simulation tool capable of simulating in-memory computing systems is needed to facilitate their design and optimization. However, currently, there is a lack of effective simulation tools for in-memory computing systems, which makes the design and optimization of large-scale in-memory computing systems very difficult.

[0037] On the one hand, the lack of efficient and accurate hardware architecture simulation models suitable for in-memory computing systems makes the evaluation of design indicators and the determination of architecture parameters particularly time-consuming; on the other hand, the lack of accurate hardware models in the software toolchain designed for in-memory computing systems has led to a situation where software and hardware are developed separately for in-memory computing systems, making it difficult to optimize software and hardware in a coordinated manner.

[0038] Furthermore, traditional architecture simulators (such as GEM5) cannot analyze the computing architecture of in-memory computing systems, and therefore cannot be used to model or simulate them. Existing simulation models designed for in-memory computing systems are either macro-circuit level, lacking flexibility at the algorithm and architecture levels, or simple evaluation models that ignore communication behavior, resulting in limited simulation accuracy.

[0039] As mentioned earlier, there are currently no mature design methods for large-scale in-memory computing systems, and there is still considerable room for design exploration in terms of accuracy, throughput, area, and power consumption. However, the lack of fast and effective simulation tools and performance evaluation models for in-memory computing systems makes system design and optimization for these systems extremely difficult.

[0040] To address at least one of the aforementioned problems, at least one embodiment of this disclosure provides a method for providing a simulation platform for an in-memory computing system, the in-memory computing system including at least one processing unit. The method for providing a simulation platform for an in-memory computing system includes: providing a model library including multiple modules implemented using a hardware description language, wherein the multiple modules include a first module, the first module being used to simulate the processing unit, the processing unit including a memristor array and peripheral circuitry for the memristor array, and the processing unit being configured to perform in-memory computing operations.

[0041] The method for providing a simulation platform for an in-memory computing system according to at least one embodiment of the present disclosure uses a hardware description language to build a model library including multiple modules. These modules can be used to simulate the basic processing units of an in-memory computing system, thereby allowing users to build an in-memory computing system for simulation using these modules and other modules (such as clocks) in a software or hardware-software integrated manner.

[0042] On the one hand, the memristor array size corresponding to the basic processing unit simulated by the modules included in the model library provided by the simulation platform can be set by parameters, including but not limited to the number of rows and columns of the memristor array, and the physical parameters of the memristors. This makes the simulation model of the in-memory computing system designed using this simulation platform more flexible in terms of algorithm and architecture.

[0043] On the other hand, the simulation platform uses a hardware description language to simulate the in-memory computing system, which makes it easy to perform hardware and software co-simulation of the in-memory computing system, thereby enabling hardware and software co-optimization of the in-memory computing system.

[0044] In some aspects, the method for providing a simulation platform for in-memory computing systems according to at least one embodiment of this disclosure can use a unified model structure to build an in-memory computing model library. This allows designers or users of in-memory computing systems to easily customize and / or extend the target in-memory computing architecture to meet the needs of different applications.

[0045] In some aspects, the method for providing a simulation platform for an in-memory computing system according to at least one embodiment of this disclosure can model modules in the model library of the simulation platform using a transaction-level modeling approach. For example, the transaction-level modeling approach can model the communication and computational functions of the modules being modeled separately. On the one hand, since the modeling considers not only the computational functions of the modules but also the communication functions between the modules, the simulation accuracy of the simulation model is higher; on the other hand, by modeling the communication and computational functions of the modules separately, the provided simulation platform can enable the in-memory computing system to have a faster simulation speed.

[0046] At least one embodiment of this disclosure also provides a simulation method for an in-memory computing system, comprising: obtaining first configuration information of a simulation model to be simulated for the in-memory computing system, wherein the in-memory computing system includes at least one processing unit; selecting a required module from a model library including multiple modules implemented using a hardware description language, wherein the multiple modules include at least one first module, the first module being used to simulate the processing unit; and constructing a simulation model based on the first configuration information and the selected required module, wherein the processing unit includes a memristor array and peripheral circuitry for the memristor array, and the processing unit is configured to perform in-memory computing operations.

[0047] At least one embodiment of this disclosure also provides a simulation apparatus, including: at least one processor, and a memory storing executable instructions, wherein the executable instructions, when executed by the at least one processor, are used to perform the simulation method provided by at least one embodiment of this disclosure. For example, the executable instructions are stored in the memory as program segments or program modules.

[0048] The simulation method and simulation apparatus for in-memory computing systems provided by at least one embodiment of this disclosure can correspondingly have some or all of the beneficial effects described above for the simulation platform provided by at least one embodiment of this disclosure.

[0049] Furthermore, by utilizing the simulation platform or simulation apparatus according to at least one embodiment of the present disclosure, a high-level model at the time approximation level can be established, which can have a greater improvement in simulation speed (e.g., a speed improvement of 100 times or more) compared to the previous Verilog RTL model.

[0050] The embodiments and examples of this disclosure will now be described in detail with reference to the accompanying drawings.

[0051] like Figure 1 As shown, for example, the architecture of a typical in-memory computing system can include multiple layers, such as the overall chip layer, the compute block layer, and the basic processing unit layer (PE).

[0052] The top layer of an in-memory computing system is defined as the chip layer. An in-memory computing system can include one or more in-memory computing chips (memristor banks), each of which acts as a coprocessor in a computer system, communicating with the host-side main processor (e.g., CPU) and memory (DRAM) via global interfaces and global controllers to perform operations such as transmitting operation instructions and data, for example, implementing the initial input and weight deployment of a neural network. Furthermore, in some implementations, the chip layer can also include global buffers. For example, depending on the network size, deep neural networks typically consist of multiple cascaded network layers; therefore, multiple submodules are needed at the chip layer to handle the computation of each cascaded network layer. The computation of network layers includes various computational operations such as matrix-vector multiplication, activation function operations, and pooling operations. These network layers can be coupled with each other, and their computations are parallel. To achieve this spatially parallel and data-dependent computational operation, the chip layer can include one or more compute tiles interconnected using a network-on-chip (NoC) or bus.

[0053] Computation tiles are the second layer of an in-memory computing system. A single computation tile can support the computation of a single network layer or work in conjunction with multiple other computation tiles to support the computation of a single network layer. Memristor arrays are limited by physical constraints and cannot be designed to be too large. Therefore, when processing network layers with a large number of parameters, the layer can be divided into multiple memristor arrays for computation. The partial sums of these memristor arrays are then accumulated using an addition tree to obtain the complete computation result. Furthermore, computation tiles may also include adders, local buffers, etc.

[0054] Here, the memristor array that performs multiply-accumulate operations, along with its associated peripheral circuitry, is defined as the basic processing unit (PE). Other neural network operators besides multiply-accumulate can be computed (activated, pooled) using dedicated digital circuit units. The PE is the third layer of the in-memory computing system, and the memristor array is its computational core. Under the control of the PE controller, digital signals from other computing modules are converted into analog voltage inputs via a digital-to-analog converter (DAC). These analog voltages are then applied to the memristor array, and the output current, obtained according to Ohm's law and Kirchhoff's laws, represents the analog multiply-accumulate calculation result. The analog calculation result is converted back into a digital signal by a multiplexer (MUX) and an analog-to-digital converter (ADC) and then transmitted to other computing modules. Furthermore, the PE may also include, for example, an input register (iReg), line buffers, shifters, and adders.

[0055] By using a memristor array as the computing component, the in-memory computing system can achieve in-memory computing functionality based on the above hierarchical structure.

[0056] like Figure 2 As shown, as an important component of in-memory computing systems, memristor arrays can include multiple memristors arranged in an array, such as multiple memristors 1511. For example, according to Kirchhoff's laws, the output current of the memristor array can be obtained from the following formula:

[0057]

[0058] Where i = 1, ..., M, j = 1, ..., n, and n and M are both integers greater than 1.

[0059] In the above formula, v i This represents the voltage excitation input to neuron node i in the input layer, i j G represents the output current of neuron node j in the next layer. i,j This represents the conductance matrix of the memristor array.

[0060] For example, a memristor has a threshold voltage. When the amplitude of the operating voltage input across the memristor is less than the threshold voltage, the conductance of the memristor will not change. In this case, the conductance of the memristor can be calculated by inputting a voltage less than the threshold voltage; the conductance of the memristor can be changed by inputting a voltage greater than the threshold voltage. For example, each memristor can be implemented as a 1T1R (i.e., one switching element and one memristor) or 2T2R (i.e., two switching elements and two memristors) structure, and the embodiments of this disclosure are not limited thereto.

[0061] like Figure 3As shown, at least one embodiment of this disclosure provides a method 300 for providing a simulation platform for an in-memory computing system, including step S301:

[0062] Step S301: Provide a model library including multiple modules implemented using a hardware description language, wherein the multiple modules include a first module, which is used to simulate a processing unit.

[0063] The processing unit is, for example, the basic processing unit (PE) of the in-memory computing system described above. For instance, the basic processing unit (PE) may include a memristor array and peripheral circuitry for the memristor array, and the processing unit is configured to perform in-memory computing operations. For example, the first module is used to simulate the functions of the processing unit; for example, the function corresponding to the first module may include parameters for setting the dimensions of the corresponding memristor array, such as the number of rows and columns of the memristor array.

[0064] The simulation platform of this disclosure includes a model library that can be used by users when modeling on a computer. It can provide a first module for simulating a basic processing unit with a configurable array size of memristor array. By calling or instantiating one or more of the first modules, an in-memory computing system can be constructed. Furthermore, by combining multiple first modules, a memristor array with a large number of memristors can be realized, thereby overcoming the inflexibility of macro-circuit-level simulation platforms in terms of architecture and algorithms.

[0065] In this way, users of the simulation platform can configure and / or adjust the number of first modules and the size of the memristor array simulated by each first module according to design needs.

[0066] On the other hand, using hardware description languages ​​to implement modules in the model library can also enable the simulation platform to provide simulation models for hardware and software co-simulation, thereby enabling more accurate modeling of in-memory computing systems and the establishment of higher-precision simulation models.

[0067] Furthermore, because a unified model library is used to provide the first module of the basic processing unit for simulating in-memory computing systems, users of the simulation platform can easily customize and extend the target in-memory computing system architecture.

[0068] In one implementation, the model library provided in method 300 may further include a second module for simulating computation blocks in an in-memory computing system. Each computation block includes at least one processing unit, and the computation block is configured to assign computational tasks to the included processing units for execution. For example, the second module is used to simulate the functionality of the computation block; for instance, the function corresponding to the second module may include parameters for setting the number of corresponding processing units (PEs).

[0069] In one implementation, a method for providing a simulation platform for an in-memory computing system provided in at least one embodiment of this disclosure may further include step S302:

[0070] Step S302: Implement the modules in the model library using a transaction-level modeling approach, wherein the communication function and the computing function are modeled separately for the object modules being modeled.

[0071] By adopting a transaction-level modeling approach, the provided simulation platform enables users to create simulation models with faster simulation speeds, thereby facilitating rapid iteration of in-memory computing chip architecture design.

[0072] The following will combine Figure 4 and Figure 5 Provide a detailed description of the provided simulation platform.

[0073] like Figure 4 As shown, Figure 3 The simulation platform 400 provided by the method described includes a model library 401 comprising one or more first modules M1. Optionally, the simulation platform may also include one or more second modules M2. For example, during instantiation, each second module M2 may include one or more first modules, can input configuration parameters and calculation parameters to the first modules, and receive the output results of the first modules after performing calculations using these parameters.

[0074] In one implementation, Figure 4 The modules in the model library can include at least one process block, and each process block has a sensitivity table, which is used to represent the activation conditions of the process corresponding to the process block.

[0075] For example, modules in a model library can include some basic elements: clock input, reset input, input and output ports, and process blocks. The clock input and reset input are used to input clock signals and reset signals, respectively, to drive and reset the processes in the module. The input and output ports are used to receive input and output results, respectively, and the process blocks are used to implement the module's own functions.

[0076] In at least one embodiment, the hardware description language used by the simulation platform is System C, and the modules in the model library are implemented using SC_MODULE in System C.

[0077] like Figure 5 As shown, Figure 4The modules in the model library are implemented using SC_MODULE. SC_MODULE includes process blocks that can be at least one of a method process (SC_METHOD), a thread process (SC_THREAD), or a clock-controlled thread process (SC_CTHREAD). The method process (SC_METHOD) can configure the module's functionality based on a configured sensitivity table, and it executes once to configure or reconfigure the module's functionality whenever an event in the sensitivity table is notified. The thread process (SC_THREAD) can execute the process's functionality based on the sensitivity table. The clock-controlled thread process (SC_CTHREAD), which inherits from the thread process, can execute the corresponding function based on the rising or falling edge of the clock. This edge-triggered behavior more closely resembles hardware behavior.

[0078] As described above, the simulation platform provided by the method according to at least one embodiment of the present disclosure can implement the modules in the model library using a transaction-level modeling approach. By using the transaction-level modeling approach, the communication function and the computing function of the object module being modeled can be modeled separately. The communication model is responsible for the transmission of transactions, and the computing model is responsible for the processing of transactions.

[0079] like Figure 6 As shown, for example, in a well-constructed in-memory computing system, the initiator and the target communicate via a channel, while transaction processing occurs within the initiator and the target, implemented by a module (SC_MODULE). Here, the initiator and the target can be any possible module within the in-memory computing system, as long as one initiates communication and the other receives it.

[0080] At least one embodiment of this disclosure also provides a simulation method for an in-memory computing system. For example... Figure 7 As shown, the simulation method 700 for an in-memory computing system provided in at least one embodiment of this disclosure includes the following steps:

[0081] Step S701: Obtain first configuration information of the simulation model to be simulated for the in-memory computing system, wherein the in-memory computing system includes at least one processing unit, wherein the processing unit includes a memristor array and peripheral circuitry for the memristor array, and the processing unit is configured to perform in-memory computing operations.

[0082] Step S702: Select the required module from a model library that includes multiple modules implemented using a hardware description language, wherein the multiple modules include at least one first module, the first module being used to simulate the processing unit;

[0083] Step S703: Based on the first configuration information and the selected required modules, construct the simulation model.

[0084] According to the method 700 described above, a user can use a simulation platform designed according to the method provided in at least one embodiment of this disclosure (e.g., refer to...). Figure 4-6 The simulation platform described above is used to design an in-memory computing system, such as configuring or adjusting the parameters of the in-memory computing system. The first configuration information in the above method 700 is, for example, configuration information related to the hardware corresponding to the designed in-memory computing system, such as, but not limited to, the number of computing blocks, the number of PEs (or the number of PEs in each computing block), the size of the memristor array in the PE, the bus width, the cache size, the structure type of the memristor (e.g., but not limited to, 2T2R structure), etc.

[0085] The model library, modules, etc. described in the above method 700 can be found in the above description of the model library and model. To avoid redundancy, they will not be repeated here.

[0086] In one implementation, method 700 may further include the following steps to obtain: Figure 8 Method 800:

[0087] Step S704: Obtain second configuration information based on the neural network model to be configured into the simulation model;

[0088] Step S705: Configure the simulation model using the second configuration information; and

[0089] Step S706: Input the test data into the simulation model so that the simulation model can process the test data to obtain the performance index of the first model in the in-memory computing system.

[0090] In one implementation, the second configuration information described in method 800 may include the network configuration of the neural network model to be configured into the simulation model. For example, this second configuration information can be obtained by compiling the neural network model using an in-memory compiler, such as the number of layers in the neural network model, the size of each layer, the type of loss function, etc. For example, for a CNN neural network, this configuration information includes the number of input channels, the size (length, width, and height) of the input layer, the number of output channels, the size of the convolutional kernel, etc.

[0091] In one implementation, the test data in method 800 may include simulation files such as pre-trained neural network weight parameters and test datasets. By configuring the simulation model of the designed in-memory computing system using the neural network configuration information, the configured simulation model can be used for, for example, inference or training. This allows for testing using test data, yielding performance metrics of the neural network algorithm corresponding to the neural network model under the designed in-memory computing system architecture, such as throughput, resource utilization, and data flow waveforms.

[0092] By using method 800, users can analyze data flow and hardware resource usage (e.g., bandwidth, storage) for a designed in-memory computing system and generate corresponding simulation results, for example, for evaluation.

[0093] The following will refer to Figure 9 A schematic diagram illustrating a simulation method according to at least one embodiment of the present disclosure is provided. Figure 9 As shown, users can utilize model libraries (e.g., references) Figure 3-6 The model library contains basic modules (e.g., a first module for implementing processing units, a second module for implementing computation blocks, etc.) and a simulation model of the in-memory computing system is built according to system specifications (e.g., configuration information related to the hardware corresponding to the designed in-memory computing system). In this in-memory computing system, for example, the main processor and memory on the host side can also be simulated by writing or calling corresponding modules using a hardware programming language. Furthermore, users can provide neural network models to the in-memory computing compiler for compilation. The resulting neural network configuration is then used as input to the in-memory computing simulation model to configure it.

[0094] Users can input test data into simulation models for inference to simulate the performance metrics of the neural network model under the architecture of the built in-memory computing system. The user-input test data can include simulation files such as pre-trained neural network weights and test datasets. These simulation files, along with the network configuration, can be used as input to the simulation model to obtain various performance metrics of the neural network algorithm under the designed in-memory computing system architecture (e.g., throughput, utilization, data flow waveforms, etc.).

[0095] At least one embodiment of this disclosure also provides a simulation device. For example... Figure 10 As shown, the simulation apparatus 1000 includes at least one processor and a memory. The memory stores executable instructions, which, when executed by the processor, can implement or carry out the simulation method according to at least one embodiment of this disclosure, or provide the simulation platform as described above.

[0096] It should be noted that, for clarity and brevity, this disclosure does not show all the constituent units of the simulation device 1000. To achieve the necessary functions of the simulation device 1000, those skilled in the art can provide and set other constituent units (not shown) according to specific needs, and this disclosure does not limit this.

[0097] For the technical effects of the simulation device 1000 in different embodiments, please refer to the technical effects of the simulation platform or simulation method provided in the embodiments of this disclosure, which will not be repeated here.

[0098] The above descriptions are merely some exemplary embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the appended claims and their equivalents.

Claims

1. A method for providing a simulation platform for an in-memory computing system, the in-memory computing system including at least one processing unit, the method comprising: A model library is provided comprising multiple modules implemented using a hardware description language. The multiple modules include a first module for simulating the processing unit, which includes a memristor array and peripheral circuitry for the memristor array, and is configured to perform in-memory computing operations. The in-memory computing system is constructed by calling and instantiating one or more first modules with configurable array sizes, the configurable array size being set based on parameters of a function corresponding to the first module. The in-memory computing system includes at least one computing block, which includes at least one of the processing units, and is configured to distribute computational tasks to the included processing units for execution. The multiple modules also include a second module for simulating the computing block, where a single computing block or multiple computing blocks are used to support a single network layer. The function corresponding to the second module includes parameters for setting the number of corresponding processing units. The modules in the model library are implemented using a transaction-level modeling approach, wherein the communication and computing functions of the object modules being modeled are modeled separately.

2. The method according to claim 1, wherein, At least one module in the model library includes at least one process block. The at least one process block is equipped with a sensitivity table to represent the activation conditions of the process corresponding to the process block.

3. The method according to claim 2, wherein, The hardware description language is System C, the modules in the model library are provided through SC_MODULE, and the at least one process block corresponds to the SC-METHOD process or the SC_THREAD process.

4. The method according to claim 3, wherein, The at least one process block includes a first process block, which is configured to be triggered and activated based on a clock edge and inherits from the SC_THREAD process.

5. The method according to claim 2, wherein, The modules in the model library include clock terminals, reset terminals, input and output ports. The clock terminal and the reset terminal are used to input clock signals and reset signals, respectively, to drive and reset the process blocks in the corresponding modules. The input and output ports are used to input the data to be processed and to output the processed data.

6. A simulation method for an in-memory computing system, comprising: Obtain first configuration information for the simulation model to be simulated for the in-memory computing system, wherein the in-memory computing system includes at least one processing unit; Select the required module from a model library comprising multiple modules implemented using a hardware description language, wherein the multiple modules include at least one first module for simulating the processing unit; Based on the first configuration information and the selected required modules, the simulation model is constructed. The processing unit includes a memristor array and peripheral circuitry for the memristor array. The processing unit is configured to perform in-memory computing operations. The in-memory computing system is constructed by calling and instantiating one or more first modules with configurable array sizes, where the configurable array size is set based on parameters of the function corresponding to the first module. The in-memory computing system includes at least one computing block, which includes at least one of the processing units. The computing block is configured to distribute computing tasks to the included processing units for execution. The multiple modules also include a second module, which simulates the computing block. A single computing block or multiple computing blocks are used to support a single network layer. The function corresponding to the second module includes parameters for setting the number of corresponding processing units. The modules in the model library employ transaction-level modeling and model the communication and computing functions of the modeled object modules respectively.

7. The method according to claim 6, wherein, At least one module in the model library includes at least one process block. The at least one process block is provided with a sensitivity table, which is used to represent the activation conditions of the process corresponding to the process block.

8. The method according to claim 7, wherein, The hardware description language is System C, the modules in the model library are provided through SC_MODULE, and the at least one process block corresponds to at least one of the SC-METHOD process, the SC_THREAD process, or the SC_CTHREAD process which is inherited from the SC_THREAD process.

9. The method according to claim 6, further comprising: Obtain second configuration information based on the neural network model to be configured into the simulation model; Configure the simulation model using the second configuration information; as well as The test data is input into the simulation model, and the simulation model processes the test data to obtain the performance indicators of the first model in the in-memory computing system.

10. The method according to claim 9, wherein, Obtaining second configuration information based on the neural network model to be configured into the simulation model includes: The neural network model is compiled using an in-memory compiler to obtain the neural network configuration, which serves as the second configuration information.

11. A simulation device, comprising: At least one processor, The memory stores executable instructions. When the executable instructions are executed by the at least one processor, they perform the simulation method according to any one of claims 6-10.

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