LED chip and manufacturing method thereof

Abstract

The embodiment of the present application discloses an LED chip and a manufacturing method thereof. In the LED chip, the mirror structure and the P electrode at least partially overlap in the direction perpendicular to the plane where the transparent substrate is located, and the passivation layer between the mirror structure and the P electrode is an insulating layer. Therefore, the P electrode, the passivation layer and the mirror structure can form a sandwich structure of the flat plate type parasitic capacitance. In addition, the P electrode and the N electrode have a junction capacitance, and the mirror structure is electrically connected with the N electrode. Therefore, the capacitance between the P electrode and the mirror structure and the junction capacitance between the P electrode and the N electrode are connected in parallel, the overall capacitance of the LED chip is increased, and the ability of the LED chip to resist ESD static breakdown is improved.

Description

Technical Field

[0001] This application relates to the field of LED technology, and in particular to an LED chip and its manufacturing method. Background Technology

[0002] With the introduction of technologies such as CSP (Chip Scale Package), LED packaging is constantly progressing towards smaller size, higher power density, and better heat dissipation. Among them, flip-chip Mini LED chips with transparent substrates have become an important development direction for LED chips due to their advantages of no bonding wires during packaging, high light emission efficiency, small package size, and high reliability.

[0003] However, as flip-chip LEDs evolve into Mini LEDs and Micro LEDs, the size of LED chips continues to shrink, and the junction capacitance of LED chips also decreases significantly. This makes small-sized LED chips more susceptible to ESD (electrostatic discharge) breakdown. Therefore, how to increase the junction capacitance of LED chips within a limited chip area and reduce the probability of ESD breakdown has become a research hotspot for those skilled in the art. Summary of the Invention

[0004] To address the aforementioned technical problems, embodiments of this application provide an LED chip and its manufacturing method, which increases the junction capacitance of the LED chip within a limited chip area, thereby reducing the probability of the LED chip being electrostatically broken down.

[0005] To address the above problems, the embodiments of this application provide the following technical solutions:

[0006] An LED chip, comprising:

[0007] Transparent substrate;

[0008] An epitaxial structure located on the first side of the transparent substrate, the epitaxial structure comprising a stacked P-type window layer, a P-type confinement layer, a multiple quantum well active layer, an N-type confinement layer, an N-type current spreading layer and an N-type ohmic contact layer, wherein the N-type ohmic contact layer is located in a portion of the surface region of the N-type current spreading layer;

[0009] A mirror structure located on the side of the epitaxial structure away from the substrate, the mirror structure covering the N-type ohmic contact layer and the N-type current spreading layer, and electrically connected to the N-type ohmic contact layer;

[0010] The first through-hole extends through the mirror structure and a portion of the epitaxial structure into the P-type window layer.

[0011] The P-electrode ohmic contact layer is located at the bottom of the first through-hole;

[0012] A passivation layer covering the surface of the reflector structure and the sidewall of the first through hole, the passivation layer also having a through hole that exposes part of the surface of the reflector structure;

[0013] The P electrode is electrically connected to the P electrode ohmic contact layer through the first through hole, and the N electrode is electrically connected to the N-type ohmic contact layer through the through hole;

[0014] In the direction perpendicular to the plane of the transparent substrate, the P electrode at least partially overlaps with the mirror structure.

[0015] Optionally, the passivation layer is a High-K insulating layer.

[0016] Optionally, the P-electrode ohmic contact layer extends along a first direction, the N-type ohmic contact layer extends along the first direction, and the P-electrode ohmic contact layer and the N-type ohmic contact layer are disposed opposite each other in a second direction. The first direction and the second direction are parallel to the plane where the transparent substrate is located, and the first direction and the second direction are perpendicular to each other.

[0017] Optionally, the reflector structure includes:

[0018] An ODR dielectric film layer located on the surface of the N-type current spreading layer, wherein the ODR dielectric film layer is an insulating dielectric film;

[0019] And an ODR metal reflective layer covering the N-type ohmic contact layer and the ODR dielectric film layer.

[0020] Optionally, the projection of the ODR metal reflective layer onto the plane of the transparent substrate is smaller than the projection of the epitaxial structure onto the plane of the transparent substrate.

[0021] Optionally, the projection of the P-electrode ohmic contact layer onto the plane of the transparent substrate does not overlap with the projections of the four corners of the LED chip onto the plane of the transparent substrate.

[0022] A method for manufacturing an LED chip, the method comprising:

[0023] An epitaxial structure is formed on a transparent substrate. The epitaxial structure includes a stacked P-type window layer, a P-type confinement layer, a multiple quantum well active layer, an N-type confinement layer, an N-type current spreading layer, and an N-type ohmic contact layer. The N-type ohmic contact layer is located in a portion of the surface region of the N-type current spreading layer.

[0024] A partial structure is formed that penetrates the epitaxial structure and extends into the first through-hole in the P-type window layer, and a P-electrode ohmic contact layer is formed at the bottom of the first through-hole.

[0025] A mirror structure is formed on the side of the epitaxial structure away from the substrate. The mirror structure covers the N-type ohmic contact layer and the N-type current spreading layer, and is electrically connected to the N-type ohmic contact layer.

[0026] A passivation layer is formed covering the surface of the reflector structure and the sidewall of the first through hole. The passivation layer also has a through hole, which exposes part of the surface of the reflector structure.

[0027] A P electrode and an N electrode are formed, wherein the P electrode is electrically connected to the P electrode ohmic contact layer through the first through hole, and the N electrode is electrically connected to the N-type ohmic contact layer through the through hole;

[0028] In the direction perpendicular to the plane of the transparent substrate, the P electrode at least partially overlaps with the mirror structure.

[0029] Optionally, a mirror structure is formed on the side of the epitaxial structure away from the substrate. The mirror structure covers the N-type ohmic contact layer and the N-type current spreading layer, and is electrically connected to the N-type ohmic contact layer, including:

[0030] An ODR dielectric film layer is formed on the side of the N-type ohmic contact layer away from the N-type current spreading layer;

[0031] Through holes are formed in the ODR dielectric film layer, and the through holes expose the N-type ohmic contact layer, that is, the ODR dielectric film layer and the N-type ohmic contact layer form a complementary pattern;

[0032] A third photoresist layer is formed on the surface of the ODR dielectric film layer;

[0033] The third photoresist layer is exposed and developed to define the ODR metal reflective layer region, which includes the region where the N-type ohmic contact layer is located.

[0034] An ODR metal reflective layer is formed in the ODR metal reflective layer region;

[0035] Remove the third photoresist layer.

[0036] Optionally, the method further includes annealing the ODR metal reflective layer.

[0037] Optionally, the ODR dielectric film layer and the N-type ohmic contact layer share the same photoresist layer.

[0038] Compared with existing technologies, the above technical solution has the following advantages:

[0039] In the technical solution provided in this application embodiment, in the direction perpendicular to the plane where the transparent substrate is located, the reflector structure and the P electrode at least partially overlap, and the passivation layer between the reflector structure and the P electrode is an insulating layer. Therefore, the P electrode, the passivation layer and the reflector structure can form a sandwich structure with a planar parasitic capacitance. Since there is a junction capacitance between the P electrode and the N electrode, and the reflector structure is electrically connected to the N electrode, the capacitance formed between the P electrode and the reflector structure and the junction capacitance formed between the P electrode and the N electrode are connected in parallel, increasing the overall capacitance of the LED chip, thereby improving the LED chip's ability to resist ESD electrostatic breakdown.

[0040] Furthermore, in a direction perpendicular to the plane of the transparent substrate, the mirror structure at least partially overlaps with the P electrode, that is, the mirror structure extends below at least a portion of the P electrode area, which can enhance the reflection of light at the bottom of the LED chip, so that the light emitted by the MQW multi-quantum-well active layer is emitted from the transparent substrate side as much as possible. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1 This is a schematic diagram of the structure of an LED chip provided in one embodiment of this application;

[0043] Figure 2 This is a top view of an LED chip provided in one embodiment of this application;

[0044] Figure 3 A top view of an LED chip provided in another embodiment of this application;

[0045] Figure 4 A top view showing the two corners of an LED chip being etched.

[0046] Figure 5 A top view of an LED chip provided in yet another embodiment of this application;

[0047] Figure 6 This is a flowchart illustrating a method for manufacturing an LED chip according to one embodiment of this application. Detailed Implementation

[0048] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0049] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0050] Secondly, this application provides a detailed description in conjunction with schematic diagrams. When detailing the embodiments of this application, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not adhering to the usual scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of this application. In addition, actual fabrication should include three-dimensional spatial dimensions of length, width, and depth.

[0051] As described in the background section, how to increase the junction capacitance of LED chips within a limited chip area and reduce the probability of LED chips being electrostatically broken down has become a research hotspot for those skilled in the art.

[0052] In view of this, embodiments of this application provide an LED chip and a method for manufacturing the same, to increase the junction capacitance of the LED chip within a limited chip area and reduce the probability of the LED chip being electrostatically broken down. Optionally, the LED chip is a MiniLED chip, but this application does not limit it and the choice depends on the specific circumstances.

[0053] Specifically, such as Figure 1 As shown, the LED chip provided in this application embodiment includes:

[0054] Transparent substrate 10;

[0055] The epitaxial structure 20 located on the first side of the transparent substrate 10 includes a stacked P-type window layer 21, a P-type confinement layer 22, a multi-quantum-well active layer 23, an N-type confinement layer 24, an N-type current spreading layer 25, and an N-type ohmic contact layer 26, wherein the N-type ohmic contact layer 26 is located in a portion of the surface of the N-type current spreading layer 25.

[0056] A mirror structure 30 is located on the side of the epitaxial structure 20 away from the transparent substrate 10. The mirror structure 30 covers the N-type ohmic contact layer 26 and the N-type current spreading layer 25, and is electrically connected to the N-type ohmic contact layer 26.

[0057] The first through-hole extends through a portion of the structure in the mirror structure 30 and the epitaxial structure 20, and into the P-type window layer 21.

[0058] The P-electrode ohmic contact layer 40 is located at the bottom of the first through hole;

[0059] A passivation layer 50 covers the surface of the mirror structure 30 and the sidewall of the first through hole. The passivation layer 50 also has a through hole that exposes part of the surface of the mirror structure 30.

[0060] P electrode 61, which is electrically connected to the P electrode ohmic contact layer 40 through the first through hole, and N electrode 62, which is electrically connected to the N-type ohmic contact layer through the through hole;

[0061] In the direction perpendicular to the plane of the transparent substrate, the P electrode at least partially overlaps with the mirror structure.

[0062] Specifically, in one embodiment of this application, the epitaxial structure is an AlGaInP-based epitaxial structure, the P-type window layer is a P-type GaP window layer, the multi-quantum well active layer is an MQW multi-quantum well active layer, and the N-type ohmic contact layer is an n-GaAs ohmic contact layer. However, this application does not limit the specific implementation of these provisions and the choice depends on the specific circumstances.

[0063] In the LED chip provided in this application embodiment, the reflector structure and the P electrode at least partially overlap in the direction perpendicular to the plane of the transparent substrate, and the passivation layer between the reflector structure and the P electrode is an insulating layer. Therefore, the P electrode, the passivation layer, and the reflector structure can form a sandwich structure with a planar parasitic capacitance. Since there is a junction capacitance between the P electrode and the N electrode, and the reflector structure is electrically connected to the N electrode, the capacitance formed between the P electrode and the reflector structure and the junction capacitance formed between the P electrode and the N electrode are connected in parallel, increasing the overall capacitance of the LED chip, thereby improving the LED chip's resistance to ESD electrostatic breakdown.

[0064] Furthermore, in a direction perpendicular to the plane of the transparent substrate, the mirror structure at least partially overlaps with the P electrode, that is, the mirror structure extends below at least a portion of the P electrode area, which can enhance the reflection of light at the bottom of the LED chip, so that the light emitted by the MQW multi-quantum-well active layer is emitted from the transparent substrate side as much as possible.

[0065] Optionally, in one embodiment of this application, the passivation layer is a High-K insulating layer. According to the formula for calculating a planar capacitor, C=εS / (4πkd), using a High-K insulating material to fabricate the passivation layer can further increase the planar capacitor and further improve the LED chip's resistance to ESD electrostatic discharge. However, this application does not limit this choice; it depends on the specific circumstances.

[0066] Based on any of the above embodiments, in one embodiment of this application, the epitaxial structure and the transparent substrate have a bonding layer. Optionally, the bonding layer is a transparent oxide bonding layer, but this application does not limit it and it depends on the specific situation.

[0067] Optionally, based on the above embodiments, in one embodiment of this application, the surface of the P-type window layer is a roughened surface to enhance the adhesion between the epitaxial structure and the bonding layer. However, this application does not limit this and it depends on the specific circumstances.

[0068] Specifically, in one embodiment of this application, the following continues... Figure 1 As shown, the reflector structure includes:

[0069] The ODR dielectric film layer 31 is located on the surface of the N-type current spreading layer 25. The ODR dielectric film layer 31 is an insulating dielectric film. Optionally, the ODR dielectric film layer is an insulating dielectric film, specifically a MgF2 layer, and the formation process is a deposition process.

[0070] And an ODR metal reflective layer 32 covering the N-type ohmic contact layer 26 and the ODR dielectric film layer 31. Optionally, the ODR metal reflective layer includes stacked AuGeNi layers, Au layers, Pt layers and Au layers, and the ODR metal reflective layer is formed by vapor deposition.

[0071] It should be noted that, in this embodiment, the ODR metal reflective layer serves two purposes: firstly, it reflects light emitted from the MQW multi-quantum-well active layer that is directed toward the N-type current extension layer back to the transparent substrate; secondly, it forms an ohmic contact with the N-type ohmic contact layer to create a conductive channel.

[0072] Based on any of the above embodiments, in one embodiment of this application, such as Figure 2 As shown, the P-electrode ohmic contact layer 40 extends along the first direction X, and the N-type ohmic contact layer 26 extends along the first direction X. The P-electrode ohmic contact layer 40 and the N-type ohmic contact layer 26 are arranged opposite each other in the second direction Y, which is beneficial for optimizing current injection and uniform current spread. The first direction X and the second direction Y are parallel to the plane of the transparent substrate, and the first direction X and the second direction Y are perpendicular. Figure 3 As shown, the P electrode 61 is electrically connected to the P electrode ohmic contact layer 40 through the P electrode through hole 611, and the N electrode 62 is electrically connected to the N-type ohmic contact layer 26 through the N electrode through hole 621.

[0073] Based on any of the above embodiments, in one embodiment of this application, such as Figure 2 and Figure 3 As shown, the P-electrode ohmic contact layer 40 is located in the non-edge region of the epitaxial structure. That is, during the fabrication of the P-electrode ohmic contact layer, when etching the epitaxial structure to expose the P-type window layer, the four corners of the epitaxial structure must be avoided to ensure that the four corners of the final LED chip are at the same height, thus preventing tilting during die bonding. For ease of understanding, as a comparison, Figure 4 An example is given where two corners of an LED chip are etched. This method results in uneven heights at the four corners of the LED chip, making it more prone to tilting.

[0074] Optionally, in one embodiment of this application, the projection of the P-electrode ohmic contact layer onto the plane of the transparent substrate does not overlap with the projections of the four corners of the LED chip onto the plane of the transparent substrate.

[0075] Based on any of the above embodiments, in one embodiment of this application, such as Figure 5 As shown, the projection of the ODR metal reflective layer 32 onto the plane of the transparent substrate is smaller than the projection of the epitaxial structure onto the plane of the transparent substrate. That is, the ODR metal reflective layer is slightly smaller than the epitaxial structure to prevent the ODR metal reflective layer from covering the sidewall of the epitaxial structure and causing leakage abnormality.

[0076] It should be noted that in this embodiment, both the P electrode and the N electrode are partially located on the surface of the passivation layer, that is, the surface of the P electrode away from the passivation layer is flush with the surface of the N electrode away from the passivation layer, thereby solving the LED tilting problem.

[0077] Furthermore, this application also provides a method for manufacturing the LED chip provided in any of the above embodiments, specifically, as follows: Figure 6 As shown, the method for manufacturing an LED chip provided in this application includes:

[0078] S1: An epitaxial structure is formed on a transparent substrate. The epitaxial structure includes a stacked P-type window layer, a P-type confinement layer, a multi-quantum-well active layer, an N-type confinement layer, an N-type current spreading layer, and an N-type ohmic contact layer. The N-type ohmic contact layer is located in a portion of the surface of the N-type current spreading layer.

[0079] Optionally, in this embodiment, the LED chip is a flip-chip LED chip, and forming an epitaxial structure on a transparent substrate includes:

[0080] S11: An epitaxial wafer is grown on a first substrate. The epitaxial wafer includes a stacked buffer layer, an etching stop layer, an N-type ohmic contact layer, an N-type current spreading layer, an N-type confinement layer, an MQW multiple quantum well active layer, a P-type confinement layer, and a P-type window layer. Optionally, the first substrate is a GaAs substrate, and the epitaxial wafer includes a stacked GaAs buffer layer, a GaInP etching stop layer, an N-type GaAs ohmic contact layer, an N-type current spreading layer, an N-type confinement layer, an MQW multiple quantum well active layer, a P-type confinement layer, and a P-type GaP window layer.

[0081] S12: Roughen the epitaxial wafer on the side away from the first substrate and remove surface particles, that is, roughen the P-type GaP window layer on the side away from the first substrate and remove surface particles to obtain a submicron roughened morphology, thereby enhancing the adhesion between the epitaxial wafer and the subsequently formed bonding layer.

[0082] S13: A bonding layer is formed on the side of the epitaxial wafer away from the first substrate, and the bonding layer on the side away from the epitaxial wafer is polished. That is, a bonding layer is formed on the surface of the P-type window layer away from the first substrate, and the bonding layer on the side away from the epitaxial wafer is polished, so that the surface of the bonding layer on the side away from the epitaxial wafer has nanoscale flatness. Optionally, the bonding layer is a transparent bonding layer. Specifically, the bonding layer is a SiO2 layer or an Al2O3 layer, and its formation process is a deposition process.

[0083] S14: The bonding layer is bonded to the second substrate. Specifically, a transparent bonding material can be used. The side of the bonding layer away from the epitaxial structure is bonded to the second substrate. Optionally, the second substrate is a transparent sapphire substrate, and the transparent bonding material is a transparent oxide.

[0084] S15: Remove the buffer layer and etch stop layer in the first substrate and the epitaxial wafer to expose the n-type ohmic contact layer, forming a transparent substrate and an epitaxial structure located on the surface of the transparent substrate. The epitaxial structure includes a stacked P-type window layer, a P-type confinement layer, a multi-quantum well active layer, an N-type confinement layer, an N-type current spreading layer, and an N-type ohmic contact layer.

[0085] S2: Form a partial structure that penetrates the epitaxial structure, extends into the first through-hole in the P-type window layer, and form a P-electrode ohmic contact layer at the bottom of the first through-hole.

[0086] Optionally, forming a first via extending through a portion of the epitaxial structure into the P-type window layer includes: etching a first region of the epitaxial structure from the side of the N-type ohmic contact layer away from the N-type current extension layer to expose a portion of the surface of the P-type window layer, thereby forming the first via.

[0087] Specifically, in one embodiment of this application, etching is performed on a first region of the epitaxial structure from the side of the N-type ohmic contact layer away from the N-type current extension layer to expose a portion of the surface area of ​​the P-type window layer, including:

[0088] A first photoresist layer is formed on the surface of the N-type ohmic contact layer on the side away from the N-type current spreading layer;

[0089] The first photoresist layer is exposed and developed to expose the first region of the epitaxial structure, which is the region where a P-type electrode is to be formed.

[0090] Using a dry etching process, with the first photoresist pattern as a mask, the N-type ohmic contact layer, N-type current spreading layer, N-type confinement layer, MQW multi-quantum well active layer and P-type confinement layer are etched until a portion of the surface area of ​​the P-type window layer is exposed to form a first via.

[0091] Remove the first photoresist pattern.

[0092] Specifically, in one embodiment of this application, forming a P-electrode ohmic contact layer at the bottom of the first through-hole includes:

[0093] A second photoresist layer is formed on the surface of the N-type ohmic contact layer away from the N-type current spreading layer;

[0094] The second photoresist layer is exposed and developed to form a photoresist pattern, which exposes the bottom of the first via and covers the sidewall of the first via.

[0095] A metal contact layer is formed on the surface of the photoresist pattern, and the metal contact layer also covers the bottom of the first through hole. Optionally, the metal contact layer is formed by vapor deposition, but this application does not limit it and it depends on the specific situation.

[0096] Remove the portion of the photoresist pattern and the metal contact layer located on the surface of the photoresist pattern, and form a P-electrode ohmic contact layer at the bottom of the first via. Optionally, in one embodiment of this application, a lift-off process is used to remove the portion of the photoresist pattern and the metal contact layer located on the surface of the photoresist pattern.

[0097] Based on the above embodiments, in one embodiment of this application, the formation of a P-electrode ohmic contact layer at the bottom of the first through-hole further includes:

[0098] The P-electrode ohmic contact layer is annealed to improve the ohmic contact performance between the P-electrode ohmic contact layer and the P-type window layer.

[0099] Specifically, in one embodiment of this application, the P-electrode ohmic contact layer includes at least one of an AuBe layer, an AuZn layer, and an Au layer.

[0100] Optionally, in one embodiment of this application, the following continues... Figure 2 As shown, the P-electrode ohmic contact layer 40 extends along the first direction X, the N-type ohmic contact layer 26 extends along the first direction X, and the P-electrode ohmic contact layer 40 and the N-type ohmic contact layer 26 are arranged opposite to each other in the second direction Y, which is beneficial for optimizing current injection and uniform current spread. The first direction X and the second direction Y are parallel to the plane where the transparent substrate is located, and the first direction X and the second direction Y are perpendicular to each other.

[0101] Based on any of the above embodiments, in one embodiment of this application, the following continues... Figure 2 and Figure 3 As shown, the P-electrode ohmic contact layer is located in the non-edge region of the epitaxial structure. That is, during the fabrication of the P-electrode ohmic contact layer, when etching the epitaxial structure to expose the P-type window layer, the four corners of the epitaxial structure must be avoided so that the four corners of the final LED chip are at the same height, which can prevent tilting during die bonding.

[0102] S3: A mirror structure is formed on the side of the epitaxial structure away from the substrate, that is, a mirror structure is formed on the side of the N-type ohmic contact layer away from the N-type current spreading layer. The mirror structure covers the N-type ohmic contact layer and the N-type current spreading layer, and is electrically connected to the N-type ohmic contact layer.

[0103] Specifically, in one embodiment of this application, forming a reflective structure on the side of the N-type ohmic contact layer away from the N-type current spreading layer includes:

[0104] An ODR dielectric film layer is formed on the side of the N-type ohmic contact layer away from the N-type current spreading layer. Optionally, the ODR dielectric film layer is an insulating dielectric film, specifically a MgF2 layer, and the formation process is a deposition process.

[0105] Through holes are formed in the ODR dielectric film layer, and the through holes expose the N-type ohmic contact layer, that is, the ODR dielectric film layer and the N-type ohmic contact layer form a complementary pattern;

[0106] A third photoresist layer is formed on the surface of the ODR dielectric film layer;

[0107] The third photoresist layer is exposed and developed to define the ODR metal reflective layer region, which includes the region where the N-type ohmic contact layer is located.

[0108] An ODR metal reflective layer is formed in the ODR metal reflective layer region;

[0109] Remove the third photoresist layer.

[0110] It should be noted that, in the above embodiments, the ODR metal reflective layer in the ODR metal reflective layer region can be formed by etching process or by stripping process. This application does not limit this, and it depends on the specific circumstances.

[0111] It should also be noted that, in this embodiment, the ODR metal reflective layer serves two purposes: firstly, it reflects a portion of the light emitted by the MQW multi-quantum-well active layer that is directed toward the N-type current extension layer back to the transparent substrate; secondly, it forms an ohmic contact with the N-type ohmic contact layer to create a conductive channel.

[0112] Optionally, based on the above embodiments, in one embodiment of this application, the method further includes: annealing the ODR metal reflective layer to enhance the ohmic contact performance between the ODR metal reflective layer and the N-type ohmic contact layer, as well as the adhesion between the ODR metal reflective layer and the ODR dielectric film layer.

[0113] Specifically, in one embodiment of this application, the ODR metal reflective layer includes stacked AuGeNi layers, Au layers, Pt layers and Au layers, and the ODR metal reflective layer is formed by vapor deposition, but this application does not limit it and it depends on the specific situation.

[0114] It should be noted that in the above embodiments, when forming the ODR dielectric film layer, the photoresist layer can be formed separately or it can share the same photoresist layer with the N-type ohmic contact layer. Optionally, the ODR dielectric film layer and the N-type ohmic contact layer share the same photoresist layer. That is, when forming the N-type ohmic contact layer in the epitaxial wafer, a metal layer is first formed without etching. After the P-electrode ohmic contact layer is formed, a photoresist layer is formed on the surface of the metal layer used to form the N-type ohmic contact layer. The photoresist layer is exposed and developed. Then, using the developed photoresist layer as a mask, the metal layer used to form the N-type ohmic contact layer is etched to form the N-type ohmic contact layer. At this time, the photoresist layer is not removed, but the ODR dielectric film layer is formed directly. Then, the developed photoresist layer and the ODR dielectric film layer portion on its surface are removed using a stripping process to complete the fabrication of the ODR dielectric film layer and the N-type ohmic contact layer. In this embodiment, since the N-type ohmic contact layer and the ODR dielectric film layer share the same photoresist pattern, the through-holes in the ODR dielectric film layer are naturally aligned with the N-type ohmic contact layer, and the ODR dielectric film layer and the N-type ohmic contact layer form complementary patterns.

[0115] Optionally, in one embodiment of this application, the following continues... Figure 5 As shown, the projection of the ODR metal reflective layer 32 onto the plane of the transparent substrate is smaller than the projection of the epitaxial structure onto the plane of the transparent substrate. That is, the ODR metal reflective layer is slightly smaller than the epitaxial structure to prevent the ODR metal reflective layer from covering the sidewall of the epitaxial structure and causing leakage abnormality.

[0116] S4: Form a passivation layer covering the surface of the reflector structure and the sidewall of the first through hole, the passivation layer also having a through hole that exposes part of the surface of the reflector structure.

[0117] Specifically, in one embodiment of this application, a passivation layer is formed covering the surface of the reflector structure and the sidewall of the first through hole. The passivation layer also has a through hole, which exposes a portion of the surface of the reflector structure, including:

[0118] S41: A passivation layer is formed on the side of the reflector structure away from the N-type current extension layer. Optionally, the passivation layer is an insulating layer, specifically a high-k material such as Al2O3, SiN, Ti2O3, or SiON. The formation process can be a deposition process, but this application does not limit it and it depends on the specific circumstances.

[0119] S42: Etch the passivation layer to form P-electrode vias and N-electrode vias, wherein the P-electrode vias penetrate the passivation layer and extend to the surface of the P-electrode ohmic contact layer, exposing a portion of the surface of the P-electrode ohmic contact layer, and the N-electrode vias penetrate the passivation layer and extend to the surface of the mirror structure, exposing a portion of the surface of the mirror structure.

[0120] S5: Forming a P electrode and an N electrode, wherein the P electrode is electrically connected to the P electrode ohmic contact layer through the first through-hole, and the N electrode is electrically connected to the N-type ohmic contact layer through the through-hole. It should be noted that, in this embodiment, the first through-hole includes the P electrode through-hole, the P electrode fills the P electrode through-hole, is electrically connected to the P electrode ohmic contact layer, and covers a portion of the passivation layer surface, forming a good conductive channel; the N electrode fills the N electrode through-hole, is electrically connected to the mirror structure, forming a good conductive channel, and extends to cover a portion of the passivation layer surface, and the P electrode and the N electrode are insulated.

[0121] Specifically, in one embodiment of this application, forming the P electrode and N electrode includes: forming a fourth photoresist layer on the surface of the passivation layer; exposing and developing the fourth photoresist layer to expose the N electrode via, the P electrode via, and a portion of the surface of the passivation layer; depositing a metal electrode layer, the metal electrode layer further filling the P electrode via and the N electrode via; and removing the developed fourth photoresist layer and the portion of the metal electrode layer located on its surface using a stripping process to obtain the P electrode and N electrode.

[0122] It should be noted that, in this embodiment, in the direction perpendicular to the plane of the transparent substrate, the portion of the reflector structure and the P electrode located on the surface of the passivation layer at least partially overlap, and the passivation layer between the reflector structure and the P electrode is an insulating layer. Therefore, the P electrode, the passivation layer, and the reflector structure can form a sandwich structure with a planar parasitic capacitance. Furthermore, because there is a junction capacitance between the P electrode and the N electrode, and the reflector structure is electrically connected to the N electrode, the capacitance formed between the P electrode and the reflector structure and the junction capacitance formed between the P electrode and the N electrode are connected in parallel, increasing the overall capacitance of the LED chip and thus improving the LED chip's resistance to ESD electrostatic discharge. According to the planar capacitance calculation formula C=εS / (4πkd), using High-K insulating material to make the passivation layer can further increase the planar capacitance and further improve the LED chip's resistance to ESD electrostatic discharge.

[0123] Furthermore, in a direction perpendicular to the plane of the transparent substrate, the mirror structure at least partially overlaps with the P electrode, that is, the mirror structure extends below at least a portion of the P electrode area, which can enhance the reflection of light at the bottom of the LED chip, so that the light emitted by the MQW multi-quantum-well active layer is emitted from the transparent substrate side as much as possible.

[0124] It should also be noted that in this embodiment, both the P electrode and the N electrode are partially located on the surface of the passivation layer, that is, the surface of the P electrode away from the passivation layer is flush with the surface of the N electrode away from the passivation layer, thereby solving the problem of LED tilt.

[0125] Based on any of the above embodiments, in one embodiment of this application, the method further includes:

[0126] A transparent substrate is thinned to obtain an LED chip structure, the LED chip structure comprising at least one LED chip.

[0127] It should be noted that if the LED chip structure includes multiple LED chips, the method further includes: cutting and splitting the LED chip structure to obtain multiple independent LED chips.

[0128] The LED chip and its manufacturing method provided in the embodiments of this application

[0129] The various parts of this manual are described in a combination of parallel and progressive methods. Each part focuses on the differences between the other parts, and the same or similar parts can be referred to each other.

[0130] The features described above regarding the disclosed embodiments can be substituted or combined with each other to enable those skilled in the art to implement or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An LED chip, characterized in that, include: Transparent substrate; An epitaxial structure located on the first side of the transparent substrate, the epitaxial structure comprising a stacked P-type window layer, a P-type confinement layer, a multiple quantum well active layer, an N-type confinement layer, an N-type current spreading layer and an N-type ohmic contact layer, wherein the N-type ohmic contact layer is located in a portion of the surface region of the N-type current spreading layer; A mirror structure located on the side of the epitaxial structure away from the substrate, the mirror structure covering the N-type ohmic contact layer and the N-type current spreading layer, and electrically connected to the N-type ohmic contact layer; The first through-hole extends through the mirror structure and a portion of the epitaxial structure into the P-type window layer. The P-electrode ohmic contact layer is located at the bottom of the first through-hole; A passivation layer covering the surface of the reflector structure and the sidewall of the first through hole, the passivation layer also having a through hole that exposes part of the surface of the reflector structure; The P electrode is electrically connected to the P electrode ohmic contact layer through the first through hole, and the N electrode is electrically connected to the N-type ohmic contact layer through the through hole; In the direction perpendicular to the plane of the transparent substrate, the P electrode at least partially overlaps with the mirror structure.

2. The LED chip according to claim 1, characterized in that, The passivation layer is a High-K insulating layer.

3. The LED chip according to claim 1, characterized in that, The P-electrode ohmic contact layer extends along a first direction, the N-type ohmic contact layer extends along the first direction, the P-electrode ohmic contact layer and the N-type ohmic contact layer are disposed opposite each other in a second direction, the first direction and the second direction are parallel to the plane of the transparent substrate, and the first direction and the second direction are perpendicular to each other.

4. The LED chip according to claim 1, characterized in that, The reflector structure includes: An ODR dielectric film layer located on the surface of the N-type current spreading layer, wherein the ODR dielectric film layer is an insulating dielectric film; And an ODR metal reflective layer covering the N-type ohmic contact layer and the ODR dielectric film layer.

5. The LED chip according to claim 4, characterized in that, The projection of the ODR metal reflective layer onto the plane of the transparent substrate is smaller than the projection of the epitaxial structure onto the plane of the transparent substrate.

6. The LED chip according to claim 1, characterized in that, The projection of the P-electrode ohmic contact layer onto the plane of the transparent substrate does not overlap with the projections of the four corners of the LED chip onto the plane of the transparent substrate.

7. A method for manufacturing an LED chip, characterized in that, The method includes: An epitaxial structure is formed on a transparent substrate. The epitaxial structure includes a stacked P-type window layer, a P-type confinement layer, a multiple quantum well active layer, an N-type confinement layer, an N-type current spreading layer, and an N-type ohmic contact layer. The N-type ohmic contact layer is located in a portion of the surface region of the N-type current spreading layer. A partial structure is formed that penetrates the epitaxial structure and extends into the first through-hole in the P-type window layer, and a P-electrode ohmic contact layer is formed at the bottom of the first through-hole. A mirror structure is formed on the side of the epitaxial structure away from the substrate. The mirror structure covers the N-type ohmic contact layer and the N-type current spreading layer, and is electrically connected to the N-type ohmic contact layer. A passivation layer is formed covering the surface of the reflector structure and the sidewall of the first through hole. The passivation layer also has a through hole, which exposes part of the surface of the reflector structure. A P electrode and an N electrode are formed, wherein the P electrode is electrically connected to the P electrode ohmic contact layer through the first through hole, and the N electrode is electrically connected to the N-type ohmic contact layer through the through hole; In the direction perpendicular to the plane of the transparent substrate, the P electrode at least partially overlaps with the mirror structure.

8. The manufacturing method according to claim 7, characterized in that, A mirror structure is formed on the side of the epitaxial structure away from the substrate. The mirror structure covers the N-type ohmic contact layer and the N-type current spreading layer, and is electrically connected to the N-type ohmic contact layer, including: An ODR dielectric film layer is formed on the side of the N-type ohmic contact layer away from the N-type current spreading layer; Through holes are formed in the ODR dielectric film layer, and the through holes expose the N-type ohmic contact layer, that is, the ODR dielectric film layer and the N-type ohmic contact layer form a complementary pattern; A third photoresist layer is formed on the surface of the ODR dielectric film layer; The third photoresist layer is exposed and developed to define the ODR metal reflective layer region, which includes the region where the N-type ohmic contact layer is located. An ODR metal reflective layer is formed in the ODR metal reflective layer region; Remove the third photoresist layer.

9. The manufacturing method according to claim 8, characterized in that, The method further includes annealing the ODR metal reflective layer.

10. The manufacturing method according to claim 8, characterized in that, The ODR dielectric film layer and the N-type ohmic contact layer share the same photoresist layer.

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