Chip structure and method for manufacturing the same

Abstract

The application discloses a chip structure and a preparation method thereof. The chip structure comprises a substrate, a first semiconductor layer, a second semiconductor layer and an active layer. The active layer is located between the first semiconductor layer and the second semiconductor layer. The first semiconductor layer, the active layer and the second semiconductor layer are sequentially grown on the substrate. A conductive layer one forms ohmic contact with the second semiconductor layer. A reflective layer forms electrical connection with the conductive layer one. A conductive layer two forms electrical connection with the reflective layer. The conductive layer two comprises a multilayer metal structure. The application adjusts the composition of the insulating layer one, changes the etching rate of different levels of the insulating layer one, and thus obtains a better etching guide angle. The application can effectively improve the internal stress of the chip device, reduce the sharp tip discharge phenomenon, improve the stability of the chip device, and increase the reflection of the optical film and improve the light efficiency of the chip device by adjusting the composition of the insulating layer one and changing the refractive index of different levels of the insulating layer one.

Description

Technical Field

[0001] This invention relates to the field of chip technology, specifically a chip structure and its fabrication method. Background Technology

[0002] A chip is a miniaturized form of circuit (mainly including semiconductor devices, but also passive components). Using certain processes, transistors, resistors, capacitors, inductors, and other components required for a circuit, along with interconnecting wiring, are fabricated on one or several small pieces of semiconductor wafers or dielectric substrates. These are then packaged in a casing to form a miniature structure with the required circuit function. All components are structurally integrated into a single unit, representing a significant step forward in the miniaturization, low power consumption, intelligence, and high reliability of electronic components.

[0003] The existing film layers in chips mainly include ohmic contact layers, reflective layers, current conduction layers, and insulating layers. The conditions of the formation process of these film layers and the mutual influence between the film layers will affect the photoelectric performance of the chip device. Therefore, studying the film layers is an important way to optimize the photoelectric performance of the chip device. The insulating layer with different compositions affects the propagation path of the optical film and also affects the stress release inside the chip device. Summary of the Invention

[0004] The purpose of this invention is to provide a chip structure and its fabrication method to solve the problems mentioned in the background art.

[0005] To achieve the above objectives, the present invention provides the following technical solution:

[0006] A chip structure, comprising:

[0007] The substrate comprises a first semiconductor layer, a second semiconductor layer, and an active layer, wherein the active layer is located between the first semiconductor layer and the second semiconductor layer, and the first semiconductor layer, the active layer, and the second semiconductor layer are sequentially grown on the substrate.

[0008] A recess that penetrates the second semiconductor layer and the active layer and extends into the interior of the first semiconductor layer;

[0009] A conductive layer that forms an ohmic contact with the second semiconductor layer;

[0010] A reflective layer is electrically connected to the conductive layer, and the reflective layer comprises a multilayer structure;

[0011] A second conductive layer is electrically connected to the reflective layer, and the second conductive layer comprises a multilayer metal structure;

[0012] A conductive layer three is electrically connected to the second conductive layer and fills the depression; the third conductive layer comprises a multilayer metal structure.

[0013] The pads that form an electrical connection with the third conductive layer contain a multi-layer metal structure, and the first conductive layer, the reflective layer, the second conductive layer, the third conductive layer, and the pads together form the first electrical connection layer.

[0014] The surface of the second semiconductor layer and part of the conductive layer are covered with an insulating layer. The silicon content of the insulating layer near the conductive layer is higher than that near the second semiconductor layer.

[0015] As a further aspect of the present invention: the insulating layer and the edge of the reflective layer have two etched chamfers θ1 and θ2, where θ1 < θ2, and 8° ≤ θ1 < 50°, θ2 ≥ 50°.

[0016] As a further aspect of the present invention: the surface of the insulating layer one and one side of the first electrical connection layer are covered with an insulating layer two.

[0017] As a further aspect of the present invention: a conductive layer three is mostly covered on the surface of the second insulating layer and forms an electrical connection with the first semiconductor layer. The conductive layer three includes a multilayer structure, and the conductive layer three and the pads together form a second electrical connection layer.

[0018] As a further embodiment of the present invention: the surface of the conductive layer three is covered with an insulating layer three, and the insulating layer three isolates the direct conduction between the first electrical connection layer and the second electrical connection layer.

[0019] A method for fabricating a chip structure includes the following steps:

[0020] Step 1: Sequentially grow a first semiconductor layer, an active layer, and a second semiconductor layer on the substrate;

[0021] Step 2: Form a recess that penetrates the second semiconductor layer and the active layer and extends into the interior of the first semiconductor layer;

[0022] Step 3: Form an ohmic contact conductive layer 1 on the surface of the second semiconductor layer;

[0023] Step 4: Form an insulating layer 1 covering the surface of the second semiconductor layer and the conductive layer 1, and form etched guide angles θ1 and θ2 by etching.

[0024] Step 5: Form an electrically connected reflective layer on a portion of the surface of the insulating layer and the surface of the first conductive layer, and form an electrically connected second conductive layer on the surface of the reflective layer;

[0025] Step 6: Form insulating layer 2 covering the surface of insulating layer 1, conductive layer 2, and the recessed sidewalls;

[0026] Step 7: Form the second insulating layer and the third conductive layer to fill the depressions;

[0027] Step 8: Form an insulating layer 3 covering the surface of conductive layer 3, etch part of the surface of insulating layer 3, and form pads. The pads are electrically connected to conductive layer 3.

[0028] Step 9: Conductive layer 1 is electrically connected to the reflective layer, the reflective layer is electrically connected to conductive layer 2, conductive layer 2 is electrically connected to conductive layer 3, and conductive layer 3 is electrically connected to the pad. Conductive layer 1, reflective layer, conductive layer 2, conductive layer 3, and pad together form the first electrical connection layer. The recess, conductive layer 3, and pad together form the second electrical connection layer. Insulating layer 3 isolates the direct conduction between the first and second electrical connection layers. The chip device fabrication is now complete.

[0029] Compared with the prior art, the beneficial effects of the present invention are:

[0030] 1. By adjusting the composition of the insulating layer, the etching rate of different layers of the insulating layer can be changed, thereby obtaining a better etching chamfer. This can effectively improve the internal stress of the chip device, reduce the phenomenon of tip discharge, and improve the stability of the chip device.

[0031] 2. By adjusting the composition of the insulating layer, the refractive index of different layers of the insulating layer is changed, thereby increasing the reflection of the optical film and improving the optical efficiency of the chip device. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of the chip structure.

[0033] Figure 2 This is a magnified schematic diagram of the internal structure of the chip.

[0034] Figure 3 This is a schematic diagram of the internal structure between insulating layer one and insulating layer two in the chip structure and its fabrication method.

[0035] In the figure: 1-First semiconductor layer, 2-Second semiconductor layer, 3-Active layer, 4-Second insulating layer, 5-First conductive layer, 6-Reflective layer, 7-Second conductive layer, 8-First insulating layer, 9-Third conductive layer, 10-Third insulating layer, 11-Pad, 12-Substrate. Detailed Implementation

[0036] Various exemplary embodiments, features, and aspects of this application will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0037] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0038] Furthermore, to better illustrate this application, numerous specific details are provided in the following detailed embodiments. Those skilled in the art should understand that this application can be implemented even without certain specific details. In some instances, methods, means, and elements well-known to those skilled in the art have not been described in detail in order to highlight the main points of this application.

[0039] Example 1

[0040] Please see Figure 1-3 A chip structure includes: a substrate 12, a first semiconductor layer 1, a second semiconductor layer 2, and an active layer 3. The active layer 3 is located between the first semiconductor layer 1 and the second semiconductor layer 2. The first semiconductor layer 1, the active layer 3, and the second semiconductor layer 2 are sequentially grown on the substrate 12. A conductive layer 5, which penetrates the second semiconductor layer 2 and the active layer 3 and extends into a recess inside the first semiconductor layer 1, forms an ohmic contact with the second semiconductor layer 2. A reflective layer 6, which is electrically connected to the conductive layer 5, is also formed. The reflective layer 6 comprises a multilayer structure. Layer 2 7, conductive layer 2 7 includes a multi-layer metal structure, conductive layer 3 9 forms an electrical connection with conductive layer 2 7 and fills the depression, conductive layer 3 9 includes a multi-layer metal structure, pad 11 forms an electrical connection with conductive layer 3 9, pad 11 includes a multi-layer metal structure, and conductive layer 1 5, reflective layer 6, conductive layer 2 7, conductive layer 3 9 and pad 11 together form a first electrical connection layer, the surface of part of the second semiconductor layer 2 and part of the surface of conductive layer 1 5 are covered with insulating layer 1 8, the silicon content of insulating layer 1 8 on the side near conductive layer 2 7 is higher than the silicon content on the side near the second semiconductor layer 2.

[0041] Preferably, in this embodiment, the edge connection between the insulating layer 8 and the reflective layer 6 has two etched chamfers θ1 and θ2, where θ1 < θ2, and 8° ≤ θ1 < 50°, and θ2 ≥ 50°.

[0042] Preferably, in this embodiment, the surface of the insulating layer 1 8 and one side of the first electrical connection layer are covered by an insulating layer 2 4, and a conductive layer 3 9 is mostly covered on the surface of the insulating layer 2 4 and forms an electrical connection with the first semiconductor layer 1. The conductive layer 3 9 includes a multilayer structure, and the conductive layer 3 9 and the pad 11 together form the second electrical connection layer. In this embodiment, the surface of the conductive layer 3 9 is covered by an insulating layer 3 10, and the insulating layer 3 10 isolates the direct conduction between the first electrical connection layer and the second electrical connection layer.

[0043] It should be specifically explained that by adjusting the structure of the insulating layer 8, the silicon content of the surface layer is higher than that of the bottom layer, thereby making the etching rate of the surface layer faster than that of the bottom layer. The etching guide angle is reduced from θ2 to θ1, where 8°≤θ1<50° and θ2≥50°. As the etching guide angle decreases, the generation of internal stress can be reduced.

[0044] Furthermore, the straighter the etching guide angle of the insulating layer 8, the straighter the etching guide angle of the directly connected metal layer is. The surface charge density at the tip is relatively large, and the electric field strength near the tip is relatively strong, which makes it easy to generate discharge phenomena and accelerate metal migration. As the etching guide angle of the insulating layer 8 becomes smaller, the etching guide angle of the directly connected metal layer also tends to be flatter, which can effectively improve the abnormal discharge at the tip, thereby reducing metal migration and stabilizing the chip device.

[0045] Furthermore, the different component contents of the insulating layer 8 also result in differences in refractive index between different layers. As the silicon content increases, the refractive index also decreases. When the silicon content of the surface layer is higher than that of the bottom layer, the refractive index of the surface layer is lower than that of the bottom layer. When light travels from a high refractive index to a low refractive index, the total internal reflection inside the chip device is increased, thereby improving the optical efficiency of the chip device.

[0046] Example 2

[0047] Please see Figure 1-3 A chip structure includes: a substrate 12, a first semiconductor layer 1, a second semiconductor layer 2, and an active layer 3. The active layer 3 is located between the first semiconductor layer 1 and the second semiconductor layer 2. The first semiconductor layer 1, the active layer 3, and the second semiconductor layer 2 are sequentially grown on the substrate 12. A conductive layer 5, which penetrates the second semiconductor layer 2 and the active layer 3 and extends into a recess inside the first semiconductor layer 1, forms an ohmic contact with the second semiconductor layer 2. A reflective layer 6, which is electrically connected to the conductive layer 5, is also formed. The reflective layer 6 comprises a multilayer structure. Layer 2 7, conductive layer 2 7 includes a multi-layer metal structure, conductive layer 3 9 forms an electrical connection with conductive layer 2 7 and fills the depression, conductive layer 3 9 includes a multi-layer metal structure, pad 11 forms an electrical connection with conductive layer 3 9, pad 11 includes a multi-layer metal structure, and conductive layer 1 5, reflective layer 6, conductive layer 2 7, conductive layer 3 9 and pad 11 together form a first electrical connection layer, the surface of part of the second semiconductor layer 2 and part of the surface of conductive layer 1 5 are covered with insulating layer 1 8, the silicon content of insulating layer 1 8 on the side near conductive layer 2 7 is higher than the silicon content on the side near the second semiconductor layer 2.

[0048] Preferably, in this embodiment, the edge connection between the insulating layer 8 and the reflective layer 6 has two etched chamfers θ1 and θ2, where θ1 < θ2, and 8° ≤ θ1 < 50°, and θ2 ≥ 50°.

[0049] Preferably, in this embodiment, the surface of the insulating layer 1 8 and one side of the first electrical connection layer are covered by an insulating layer 2 4, and a conductive layer 3 9 is mostly covered on the surface of the insulating layer 2 4 and forms an electrical connection with the first semiconductor layer 1. The conductive layer 3 9 includes a multilayer structure, and the conductive layer 3 9 and the pad 11 together form the second electrical connection layer. In this embodiment, the surface of the conductive layer 3 9 is covered by an insulating layer 3 10, and the insulating layer 3 10 isolates the direct conduction between the first electrical connection layer and the second electrical connection layer.

[0050] Preferably, in this embodiment, it further includes: a method for fabricating a chip structure, comprising the following steps:

[0051] Step 1: Grow the first semiconductor layer 1, the active layer 3, and the second semiconductor layer 2 sequentially on the substrate 12;

[0052] Step 2: Form a recess that penetrates the second semiconductor layer 2 and the active layer 3 and extends into the interior of the first semiconductor layer 1;

[0053] Step 3: Form an ohmic contact conductive layer 5 on the surface of the second semiconductor layer 2;

[0054] Step 4: Form an insulating layer 8 covering the surface of the second semiconductor layer 2 and the conductive layer 5, and form etched guide angles θ1 and θ2 by etching.

[0055] Step 5: Form an electrically connected reflective layer 6 on the surface of insulating layer 8 and conductive layer 5, and form an electrically connected conductive layer 7 on the surface of reflective layer 6;

[0056] Step 6: Form insulating layer 2 4 covering the surface of insulating layer 1 8, conductive layer 2 7, and recessed sidewalls;

[0057] Step 7: Form the covering insulating layer 2 4 and the filling conductive layer 3 9;

[0058] Step 8: Form an insulating layer 3 10 covering the surface of conductive layer 3 9, etch a portion of the surface of insulating layer 3 10, and form pads 11. The pads are electrically connected to conductive layer 3 9.

[0059] Step 9: Conductive layer 1 5 is electrically connected to reflective layer 6, reflective layer 6 is electrically connected to conductive layer 2 7, conductive layer 2 7 is electrically connected to conductive layer 3 9, and conductive layer 3 9 is electrically connected to pad 11. Conductive layer 1 5, reflective layer 6, conductive layer 2 7, conductive layer 3 9, and pad 11 together form the first electrical connection layer. The recess, conductive layer 3 9, and pad 11 together form the second electrical connection layer. Insulating layer 3 10 isolates the direct conduction between the first and second electrical connection layers. The chip device fabrication is complete.

[0060] It should be specifically noted that: by adjusting the composition of insulating layer 8, the present invention changes the etching rate of different layers of insulating layer 8, thereby obtaining a better etching chamfer angle, which can effectively improve the internal stress of the chip device, reduce the phenomenon of tip discharge, and improve the stability of the chip device. Furthermore, by adjusting the composition of insulating layer 8, the refractive index of different layers of insulating layer 8 is changed, thereby increasing the reflection of the optical film and improving the light efficiency of the chip device.

[0061] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, it is intended that all variations falling within the meaning and scope of equivalents of the claims be included within the present invention.

[0062] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A chip structure, characterized in that, include: The substrate (12), the first semiconductor layer (1), the second semiconductor layer (2) and the active layer (3) are located between the first semiconductor layer (1) and the second semiconductor layer (2), and the first semiconductor layer (1), the active layer (3) and the second semiconductor layer (2) are grown sequentially on the substrate (12). A recess that penetrates the second semiconductor layer (2) and the active layer (3) and extends into the interior of the first semiconductor layer (1); A conductive layer (5) that forms an ohmic contact with the second semiconductor layer (2); A reflective layer (6) is electrically connected to the conductive layer (5), and the reflective layer (6) comprises a multilayer structure; A conductive layer 2 (7) is electrically connected to the reflective layer (6), and the conductive layer 2 (7) comprises a multilayer metal structure; A conductive layer three (9) is electrically connected to the conductive layer two (7) and fills the depression, the conductive layer three (9) comprising a multilayer metal structure; The pad (11) forms an electrical connection with the conductive layer three (9). The pad (11) contains a multi-layer metal structure, and the conductive layer one (5), the reflective layer (6), the conductive layer two (7), the conductive layer three (9) and the pad (11) together form the first electrical connection layer. The surface of the second semiconductor layer (2) and the surface of the conductive layer (5) are covered with an insulating layer (8). The silicon content of the insulating layer (8) near the conductive layer (7) is higher than that near the second semiconductor layer (2).

2. The chip structure according to claim 1, characterized in that, The edge connection between the insulating layer (8) and the reflective layer (6) has two etched guide angles θ1 and θ2, where θ1 < θ2, and 8° ≤ θ1 < 50°, θ2 ≥ 50°.

3. The chip structure according to claim 1, characterized in that, The surface of the first insulating layer (8) and one side of the first electrical connection layer are covered with the second insulating layer (4).

4. The chip structure according to claim 3, characterized in that, The conductive layer three (9) covers most of the surface of the insulating layer two (4) and forms an electrical connection with the first semiconductor layer (1). The conductive layer three (9) contains a multilayer structure. The conductive layer three (9) and the pad (11) together form the second electrical connection layer.

5. The chip structure according to claim 4, characterized in that, The surface of the conductive layer three (9) is covered with an insulating layer three (10), which isolates the direct conduction between the first electrical connection layer and the second electrical connection layer.

6. A method for fabricating a chip structure according to claims 1-5, characterized in that, Includes the following steps: Step 1: Grow a first semiconductor layer (1), an active layer (3), and a second semiconductor layer (2) sequentially on a substrate (12); Step 2: Form a recess that penetrates the second semiconductor layer (2) and the active layer (3) and extends into the interior of the first semiconductor layer (1); Step 3: Form an ohmic contact conductive layer 1 (5) on the surface of the second semiconductor layer (2); Step 4: Form an insulating layer (8) covering the surface of the second semiconductor layer (2) and the conductive layer (5), and form etched guide angles θ1 and θ2 by etching. Step 5: An electrically connected reflective layer (6) is formed on the surface of insulating layer 1 (8) and conductive layer 1 (5), and an electrically connected conductive layer 2 (7) is formed on the surface of reflective layer (6); Step 6: Form insulating layer 2 (4) covering the surface of insulating layer 1 (8), conductive layer 2 (7) and recessed sidewalls; Step 7: Form the second insulating layer (4) and the third conductive layer (9) that fills the depression; Step 8: Form an insulating layer 3 (10) covering the surface of conductive layer 3 (9), etch part of the surface of insulating layer 3 (10), and form pads (11). The pads are electrically connected to conductive layer 3 (9). Step 9: Conductive layer 1 (5) is electrically connected to reflective layer (6), reflective layer (6) is electrically connected to conductive layer 2 (7), conductive layer 2 (7) is electrically connected to conductive layer 3 (9), conductive layer 3 (9) is electrically connected to pad (11). The first electrical connection layer is formed by conductive layer 1 (5), reflective layer (6), conductive layer 2 (7), conductive layer 3 (9) and pad (11). The recess, conductive layer 3 (9) and pad (11) form the second electrical connection layer. Insulating layer 3 (10) isolates the direct conduction between the first electrical connection layer and the second electrical connection layer. The chip device fabrication is completed.

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