Phase-locked loop circuit and clock generator

Abstract

The present application relates to a phase-locked loop circuit and a clock generator. The phase-locked loop circuit includes a phase frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator and a feedback divider which are sequentially connected in series to form a negative feedback loop, as well as a lock detection circuit, a digitally controlled current source and a damping correction circuit; the digitally controlled current source is used to divide the output current of the voltage-controlled oscillator by the frequency division coefficient to obtain the output current of the digitally controlled current source, and output it to the charge pump as the pump current of the charge pump; the lock detection circuit is used to detect the internal nodes of the phase frequency detector to determine whether the phase-locked loop circuit is locked, and output an indication signal to the damping correction circuit according to the detection result; the damping correction circuit is used to output a digital control signal to the loop filter when it is determined that the phase-locked loop circuit is not locked according to the indication signal, so as to control the resistance value of the zero compensation resistor in the loop filter to be inversely proportional to the input reference frequency of the phase-locked loop circuit. The phase-locked loop circuit has high stability and good response performance.

Description

Technical Field

[0001] The present application relates to the field of circuit technology, and in particular to a phase-locked loop circuit and a clock generator. Background Art

[0002] The structure of the clock generator is a phase locked loop (PLL) that can set different frequency multiplication factors. Clock generators that can configure different output frequencies are widely used in various electronic systems. For many electronic systems, the stability and response speed of the phase locked loop need to meet certain requirements.

[0003] However, the phase-locked loop in the related art has poor stability and response performance. Summary of the invention

[0004] Based on this, it is necessary to provide a phase-locked loop circuit and a clock generator with high stability and good response performance to address the above technical problems.

[0005] In a first aspect, the present application provides a phase-locked loop circuit. The phase-locked loop circuit includes a phase frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, and a feedback divider which are sequentially connected in series to form a negative feedback loop, and the phase-locked loop circuit also includes a lock detection circuit, a digitally controlled current source, and a damping correction circuit;

[0006] The digitally controlled current source is connected to the voltage-controlled oscillator and the charge pump, and is used to divide the output current of the voltage-controlled oscillator by the frequency division coefficient to obtain the output current of the digitally controlled current source, and output the output current of the digitally controlled current source to the charge pump as the pump current of the charge pump;

[0007] The lock detection circuit is connected to the phase frequency detector and the damping correction circuit, and is used to detect the internal nodes of the phase frequency detector to determine whether the phase locked loop circuit is locked, and output an indication signal to the damping correction circuit according to the detection result;

[0008] The damping correction circuit is also connected to the loop filter, and is used to output a digital control signal to the loop filter when it is determined that the phase-locked loop circuit is not locked according to the indication signal, so as to control the resistance value of the zero-point compensation resistor in the loop filter to be inversely proportional to the input reference frequency of the phase-locked loop circuit according to the digital control signal.

[0009] In one of the embodiments, the damping correction circuit is further used to keep the output digital control signal unchanged when it is determined that the phase-locked loop circuit is locked according to the indication signal.

[0010] In one embodiment, the damping correction circuit is used to detect the magnitude of the input reference frequency according to the RC network, so as to convert the magnitude of the input reference frequency into the digital control signal.

[0011] In one embodiment, the lock detection circuit is used to determine that the phase-locked loop circuit is locked when it is detected that the phase difference of the internal node is lower than a preset threshold, and to determine that the phase-locked loop circuit is not locked when it is detected that the phase difference of the internal node is not lower than the preset threshold.

[0012] In one embodiment, the phase-locked loop circuit also includes a start-up circuit, which is connected to the feedback divider and the voltage-controlled oscillator; the input signal of the start-up circuit is the divided clock signal output by the feedback divider; the start-up circuit is used to drive the voltage-controlled oscillator to start oscillation when it is detected that the feedback divider does not output the divided clock signal, so as to enable the phase-locked loop to operate normally.

[0013] In one embodiment, the startup circuit is specifically used to output a logic control signal when it is detected that the feedback divider does not output the divided clock signal, so as to control the voltage of the voltage-controlled oscillator to a preset voltage value through the logic control signal, wherein the preset voltage value corresponds to the startup current of the voltage-controlled oscillator.

[0014] In one embodiment, the digitally controlled current source includes N current division circuits, N+1 first switches, a first NMOS tube and a second NMOS tube; the drain of the first NMOS tube is connected to the current output end, the gate of the first NMOS tube is connected to the current input end, and the source of the first NMOS tube is grounded; the gate and drain of the second NMOS tube are connected to the current input end, and the source of the second NMOS tube is connected to one end of the first first switch; the kth current division circuit among the N current division circuits includes NMOS tubes MNk1, MNk2 and MNk3 and PMOS tubes MPk1 and MPk2, the drain of MNk1 The MNk1 is connected to the gate of the MPk1, the drain of the MPk1 and the gate of the MPk2, and the source of the MNk1 is grounded; the source of the MPk1 is connected to a power supply; the source of the MPk2 is connected to a power supply, the drain of the MPk2 is connected to the drain of the MNk2, the gate of the MNk2 and the gate of the MNk3; the drain of the MNk3 is connected to the current input terminal, and the source of the MNk3 is connected to one end of the k+1th switch; if k is equal to 1, the gate of the MNk1 is connected to the gate of the second NMOS tube; if k is not equal to 1, the gate of the MNk1 is connected to the gate of MN(k-1)3; the other end of each of the first switches is grounded.

[0015] In one embodiment, the loop filter includes m series-connected adjustable circuits, a first capacitor, and a second capacitor; wherein each of the adjustable circuits includes a compensation resistor and a second switch connected in parallel, and the resistance value of each compensation resistor is respectively 2 times of the unit compensation resistor. Ltimes, L=0,1,2...,m-1, m is the number of control signal bits input to the loop filter, and m is a positive integer greater than or equal to 1; one end of the first adjustable circuit of the m series-connected adjustable circuits is grounded, and the other end is connected to one end of the second adjustable circuit; one end of the m-th adjustable circuit of the m series-connected adjustable circuits is connected to one end of the (m-1)-th adjustable circuit, and the other end is connected to one end of the first capacitor; the other end of the first capacitor is connected to one end of the second capacitor, and the other end of the second capacitor is grounded.

[0016] In one embodiment, the damping correction circuit obtains the digital control signal based on successive approximation logic.

[0017] In one embodiment, the damping correction circuit includes w first D flip-flops, w delay units, w AND gates, a third switch, w capacitor circuits, a comparator, w second D flip-flops, w third D flip-flops and an integrating resistor; wherein the AND gate is a three-input AND gate circuit, the capacitor circuit includes a fourth switch and a fifth capacitor, one end of the fourth switch is connected to one end of the fifth capacitor; the input signal of the CK end of each of the first D flip-flops is the input reference frequency; for the sth first D flip-flop among the w first D flip-flops, if s is equal to 1, the Q end of the sth first D flip-flop is connected to the D end of the last first D flip-flop; if s is not equal to 1, the Q end of the sth first D flip-flop is connected to the D end of the s-1th first D flip-flop; the Qb end of each of the first D flip-flops is respectively connected to the input end of each of the delay units; each of the delay units The output end of the element is respectively connected to the first input end of each AND gate; the second input end of each AND gate is connected in parallel and connected to the third switch; the third input end of each AND gate is respectively connected to the Q end of each second D flip-flop; the output end of each AND gate is respectively connected to the other end of the fourth switch in each capacitor circuit; one end of the third switch is connected to the non-inverting end of the comparator, and the other end is connected to the power supply; the other end of the fifth capacitor in each capacitor circuit is connected in parallel and connected to the non-inverting end of the comparator; one end of the integrating resistor is connected to the non-inverting end of the comparator, and the other end is grounded; the inverting end of the comparator is connected to the power supply, and the output end of the comparator is connected to the D end of each second D flip-flop; the Q end of each second D flip-flop is respectively connected to the D end of each third D flip-flop; the CK end of each third D flip-flop inputs a sampling signal; the Q end of each third D flip-flop outputs the digital control signal.

[0018] In one embodiment, the startup circuit includes a first inverter, a second inverter, a first PMOS tube, a second PMOS tube, a third capacitor, a fourth capacitor, a constant current source and a trigger; the input signal of the first inverter is the divided clock signal, and the input end of the second inverter is connected to the output end of the first inverter; the source of the first PMOS tube is grounded, the gate of the first PMOS tube is connected to the output end of the second inverter, and the drain of the first PMOS tube is connected to one end of the third capacitor and the source of the second PMOS tube; the gate of the second PMOS tube is connected to the output end of the first inverter, and the drain of the second PMOS tube is connected to one end of the fourth capacitor, the input end of the constant current source and the input end of the trigger; the other end of the third capacitor, the other end of the fourth capacitor and the output end of the constant current source are grounded; the output signal of the trigger is the logic control signal.

[0019] In a second aspect, the present application further provides a clock generator, which includes a phase-locked loop circuit as described in any one of the first aspects above.

[0020] The phase-locked loop circuit and clock generator are as follows: the phase-locked loop circuit includes a phase frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator and a feedback divider which are connected in series in sequence to form a negative feedback loop; the phase-locked loop circuit also includes a lock detection circuit, a digitally controlled current source and a damping correction circuit; the digitally controlled current source is connected to the voltage-controlled oscillator and the charge pump, and is used to divide the output current of the voltage-controlled oscillator by the frequency division coefficient to obtain the output current of the digitally controlled current source, and output the output current of the digitally controlled current source to the charge pump as the pump current of the charge pump; the lock detection circuit is connected to the phase frequency detector and the damping correction circuit, and is used to detect the internal nodes of the phase frequency detector to determine whether the phase-locked loop circuit is locked, and output an indication signal to the damping correction circuit according to the detection result; the damping correction circuit is also connected to the loop filter, and is used to output a digital control signal to the loop filter when it is determined that the phase-locked loop circuit is not locked according to the indication signal, so as to control the resistance value of the zero compensation resistor in the loop filter to be inversely proportional to the input reference frequency of the phase-locked loop circuit according to the digital control signal. Since the digitally controlled current source can divide the output current of the voltage-controlled oscillator by the frequency division coefficient, the output current of the digitally controlled current source is obtained and input to the charge pump as the pump current of the charge pump, and the pump current is related to the loop bandwidth, the loop bandwidth of the phase-locked loop circuit can be proportional to the input reference frequency of the phase-locked loop, thereby improving the system response rate. In addition, the resistance value of the zero-point compensation resistor in the loop filter is inversely proportional to the input reference frequency of the phase-locked loop circuit by outputting a digital control signal through the damping correction circuit, so that the damping coefficient of the loop is kept at a constant value, which is independent of the input reference frequency, thereby ensuring the stability of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0022] Figure 1 A conventional charge pump phase-locked loop structure according to an embodiment;

[0023] Figure 2 A phase-locked loop circuit structure according to an embodiment;

[0024] Figure 3 A phase-locked loop circuit structure according to another embodiment;

[0025] Figure 4 A digitally controlled current source structure according to an embodiment;

[0026] Figure 5 A conventional current division circuit structure according to an embodiment;

[0027] Figure 6 A loop filter structure according to an embodiment;

[0028] Figure 7 A damping correction circuit structure of an embodiment;

[0029] Figure 8 A signal waveform diagram of an embodiment;

[0030] Fig. 9 The figure is a startup circuit structure of an embodiment.

[0031] Description of reference numerals:

[0032] 201, frequency detector and phase detector; 202, charge pump; 203, loop filter;

[0033] 204, voltage controlled oscillator; 205, feedback frequency divider; 206, lock detection circuit;

[0034] 207. Digitally controlled current source; 208. Damping correction circuit; 209. Starting circuit;

[0035] M B , the first NMOS tube; S k , the first switch; M N0 , the second NMOS tube;

[0036] C 1 , the first capacitor; C 2 , the second capacitor; R C, unit compensation resistance;

[0037] DFFk, the kth first D flip-flop; DL0, a delay unit;

[0038] AND, AND gate; R 0 , integrating resistor; SW-RT, the third switch;

[0039] CMP, comparator; DFFS1, second D flip-flop;

[0040] DFFS2, the third D flip-flop; INV1, the first inverter;

[0041] INV2, the second inverter; SW1, the first PMOS tube;

[0042] SW2, the second PMOS tube; C A , a third capacitor;

[0043] C B , the fourth capacitor; IDN, constant current source; SCHM, trigger. DETAILED DESCRIPTION

[0044] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0046] It is understood that the terms "first", "second", etc. used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, without departing from the scope of this application, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor.

[0047] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if the connected circuits, modules, units, etc. have electrical signals or data transmission between each other.

[0048] It can be understood that “at least one” means one or more, “plurality” means two or more, and “at least a portion of an element” means a part or all of an element.

[0049] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, the term "and / or" used in this specification includes any and all combinations of the relevant listed items.

[0050] First of all, before specifically introducing the technical solution of the embodiments of the present application, the technical background or technical evolution context on which the embodiments of the present application are based is introduced.

[0051] Currently, clock generators that can be configured with different output frequencies are widely used in various electronic systems. A widely used clock generator structure is a frequency-multiplied phase-locked loop (PLL) that can set different frequency multiplication factors. For traditional phase-locked loops, setting different frequency multiplication factors will cause changes in the bandwidth and jitter characteristics of the phase-locked loop, and in severe cases will cause oscillation. For many digital systems, the desired frequency-multiplied phase-locked loop needs to meet the requirements that the loop bandwidth and jitter characteristics are insensitive to the process, power supply voltage, temperature and frequency multiplication factor, and can adapt to the widest possible output frequency range and input frequency range. This requires that the bandwidth of the phase-locked loop can adapt to the input reference frequency, generally less than one-tenth of the input reference frequency and automatically follow the input reference frequency; the phase margin or damping coefficient, an important indicator of the loop stability of the phase-locked loop, is independent of the loop bandwidth.

[0052] like Figure 1 As shown in FIG. 1 , the charge pump phase-locked loop in the conventional technology is composed of a phase frequency detector (PFD), a charge pump (CP), a loop filter (LP), a voltage controlled oscillator (VCO), and a feedback divider (FD). REF It is the input reference clock of the phase-locked loop, which is generally of low frequency and is generated by a crystal oscillator circuit; F VCO It is the output clock of the phase-locked loop, which is generally of high frequency, and F VCO With F REF There is a multiple relationship between them, and the multiple N = F VCO / F REF , a phase-locked loop with N as an integer is an integer-division phase-locked loop, where N refers to the division coefficient of the feedback divider.

[0053] The phase-locked loop is a phase negative feedback system. Assume that the low-pass filter of the charge pump phase-locked loop is a first-order RC (R1 and C 1 ) structure, the charge pump phase-locked loop is a second-order type II loop, and its closed-loop transfer function can be expressed as:

[0054]

[0055] Among them, I P is the pump current of the charge pump in the charge pump phase-locked loop, generally generated by the bias circuit; K VCO is the gain of the voltage-controlled oscillator VCO; N is the frequency division coefficient of the feedback divider; C 1 and R 1 is the parameter of the first-order passive low-pass filter. Voltage controlled oscillator gain K VCO The unit is rad / sV, I P is the charge pump current. According to the above closed-loop transfer function, the loop bandwidth ω can be obtained n And the damping coefficient ζ is:

[0056]

[0057]

[0058] Generally speaking, the loop bandwidth of the phase-locked loop is n That is, the closed-loop -3dB bandwidth or the open-loop 0dB bandwidth characterizes the response speed of the phase-locked loop. From the perspective of locking, the bandwidth of the phase-locked loop should be as large as possible, because the output signal can quickly respond to changes in the input reference signal. However, on the one hand, an excessively large bandwidth will cause the high-frequency phase noise of the input reference frequency to be injected into the output signal spectrum with a large component. On the other hand, the phase-locked loop is essentially a non-continuous time system, and the current analysis is based on the continuous time model. When the loop bandwidth is close to the input reference frequency, the continuous time approximation fails and the loop stability is reduced. Therefore, the loop bandwidth is generally required to be less than one-tenth of the input reference frequency. The damping coefficient characterizes the stability of the closed-loop negative feedback system. When the damping coefficient is less than 0, the system is in a negative damping state and is unstable; when the damping coefficient is between 0 and 1, the system is in an underdamped state, and the step response is a damped oscillation; when the damping coefficient is greater than 1, the system is in an overdamped state and the system is stable, but an excessively large damping coefficient will result in a slow response, which is manifested as a longer locking time for the phase-locked loop. The damping coefficient of an ideal phase-locked loop is generally set to 1.

[0059] For different input reference frequencies and output frequencies, if the PLL's I P , K VCO , C 1 , R 1If the parameters remain unchanged and only N can change, the loop bandwidth needs to meet the minimum standard, that is, the maximum loop bandwidth must be lower than one tenth of the lowest configurable input reference frequency at this time. That is, at the configurable lowest input reference frequency, N needs to be set to the minimum allowed value (Equation (2) shows that the smaller N, the larger the bandwidth), at which time the output frequency is the lowest and the loop bandwidth is closest to the input reference frequency (the loop bandwidth is the largest). Assuming that a suitable loop bandwidth is set at the lowest input reference frequency and the smallest N (less than one tenth of the input reference frequency at this time), gradually increasing N means gradually increasing the output frequency. At this time, the loop bandwidth gradually decreases, but the input reference frequency remains unchanged, the response capability of the phase-locked loop deteriorates, and the phase noise contribution of the voltage-controlled oscillator in the low-frequency part of the output signal increases. If, under the current setting, N remains unchanged and the input reference frequency is gradually increased, the loop bandwidth remains unchanged. At this time, the ratio between the input reference frequency and the loop bandwidth increases, and the suppression capability of the input reference phase noise and the voltage-controlled oscillator phase noise remains unchanged, but the loop bandwidth can be set larger to ensure linear approximation and obtain higher noise suppression capability. Equation (3) shows that if the loop bandwidth remains unchanged and the low-pass filter parameters remain unchanged, the damping coefficient remains unchanged; if the loop bandwidth changes under different configurations, the damping coefficient also changes, resulting in changes in the dynamic characteristics of the system, which is undesirable.

[0060] In short, from the perspective of stability, the damping coefficient needs to be kept constant near 1, regardless of the input and output frequencies and the feedback coefficient N; from the perspective of system response, the loop bandwidth needs to be as large as possible but cannot exceed one tenth of the input reference frequency. Therefore, if the above goals need to be met, the phase-locked loop needs to meet the following requirements: loop bandwidth ω n Automatically follows the input reference frequency and maintains a fixed ratio, damping factor and loop bandwidth ω n The bandwidth of the charge pump phase-locked loop commonly used in traditional technology is determined by circuit parameters and has nothing to do with the input reference frequency, so it cannot automatically follow the input reference frequency.

[0061] In view of this, according to the above objectives, the embodiments of the present application provide a phase-locked loop circuit with adaptive bandwidth, which can keep the loop bandwidth automatically following the input reference frequency, and use an automatic adjustment loop to ensure that the damping coefficient is independent of the loop bandwidth. In addition, it should be noted that the applicant has made a lot of creative efforts from determining the above technical problems to the technical solutions introduced in the following embodiments.

[0062] In one embodiment, Figure 2As shown, a phase-locked loop circuit provided by an embodiment of the present application is shown. The phase-locked loop circuit includes a phase frequency detector 201, a charge pump 202, a loop filter 203, a voltage-controlled oscillator 204 and a feedback divider 205, which are sequentially connected in series to form a negative feedback loop, as well as a lock detection circuit 206, a digitally controlled current source 207 and a damping correction circuit 208. Among them, the digitally controlled current source 207 is connected to the voltage-controlled oscillator 204 and the charge pump 202, and is used to divide the output current of the voltage-controlled oscillator 204 by the frequency division coefficient to obtain the output current of the digitally controlled current source 207, and output the output current of the digitally controlled current source 207 to the charge pump 202 as the pump current of the charge pump 202. The lock detection circuit 206 is connected to the phase frequency detector 201 and the damping correction circuit 208, and is used to detect the internal nodes of the phase frequency detector 201 to determine whether the phase-locked loop circuit is locked, and output an indication signal to the damping correction circuit 208 according to the detection result. The damping correction circuit 208 is also connected to the loop filter 203, and is used to output a digital control signal to the loop filter 203 when it is determined according to the indication signal that the phase-locked loop circuit is not locked, so as to control the resistance value of the zero-point compensation resistor in the loop filter 203 to be inversely proportional to the input reference frequency of the phase-locked loop circuit according to the digital control signal.

[0063] Specifically, Figure 2 Medium, F REF is the input reference frequency of the phase-locked loop circuit; F DIV is the output frequency of the feedback divider 205; UP and DN are the switch drive signals of the PMOS current source and the NMOS current source in the charge pump 202; V CP is the output voltage of the charge pump 202; V C V CP The filtered voltage controls the output frequency of the voltage controlled oscillator 204; F VCO is the output frequency of the voltage-controlled oscillator 204 , and may also be the output frequency of the phase-locked loop circuit; EN_DFA is the indication signal output by the lock detection circuit 206 .

[0064] To facilitate understanding, before specifically describing the phase-locked loop circuit provided in the embodiment of the present application, it is first theoretically explained that the phase-locked loop circuit provided in the embodiment of the present application can keep the loop bandwidth automatically following the input reference frequency, and at the same time, automatically adjust the loop to ensure that the damping coefficient is independent of the loop bandwidth, thereby ensuring the stability and responsiveness of the phase-locked loop circuit.

[0065] Continue to refer to the loop bandwidth ω given by equation 2 and equation 3 above n and the damping coefficient ζ. Further, for the voltage-controlled oscillator 204 with a ring oscillation structure, generally, its output frequency F VCO With its bias current I VCO The following relationship is satisfied:

[0066] I VCO =βF VCO 2 (4)

[0067] β is the coefficient.

[0068] Assuming the division factor of the feedback divider is N, the PLL output frequency F VCO With the input reference frequency F REF Between VCO =N*F REF Therefore, formula (4) can be rewritten as:

[0069] I VCO =βN 2 F REF 2 (5)

[0070] Directly use the current of equation (4) after passing through a fixed mirror ratio P current mirror as the charge pump current I P Substituting into equation (2), the bandwidth ω n Although proportional to F REF , but there is still a frequency division factor N in the expression, which will result in: even if the input reference frequency remains unchanged, the PLL output frequency F is modified VCO , that is, modifying the division factor N will cause the loop bandwidth to change.

[0071] Based on this, if there is a digitally controlled current source circuit that can convert I VCO The current after mirroring according to the mirror ratio P is divided by the frequency division coefficient N, and the obtained current is used as the pump current of the charge pump. Then the charge pump current is:

[0072]

[0073] Furthermore, substituting the above formula (5) into formula (2), the loop bandwidth is obtained as follows:

[0074]

[0075] Where k is the simplified coefficient.

[0076] Equation 7 above shows that: for a PLL using the above digitally controlled current source circuit, if the capacitor C 1 and the voltage controlled oscillator gain K VCO If the loop bandwidth is proportional to the input reference frequency and has nothing to do with the output frequency and the frequency division factor, then the damping coefficient ζ can be obtained by substituting equation 7 into equation 3:

[0077]

[0078] In PLL, the capacitor C 1 If R 1 If the capacitance C is also fixed, the damping coefficient is proportional to the input reference frequency, which is undesirable because the damping coefficient characterizes the stability of the loop and is generally best kept near 1. 1 The only variable is the resistance R. 1 , if there is a resistor whose resistance is inversely proportional to the input reference frequency, substituting it into formula 8, we can get the damping coefficient and input reference frequency F REF Adjusting other parameters can ensure that the damping coefficient is constant at 1, which is independent of the input reference frequency.

[0079] In the phase-locked loop circuit provided by the embodiment of the present application, based on the above principle, the digitally controlled current source extracts current from the voltage-controlled oscillator and divides it by the frequency division coefficient as the pump current of the charge pump, so that the loop bandwidth that automatically follows the input reference frequency can be obtained to achieve the best loop dynamic performance. In addition, the lock detection circuit detects whether the loop is stable, and its output indication signal serves as an enable signal for the damping correction circuit. Before the loop is locked, the damping correction circuit dynamically outputs correction data; after the loop is locked, the output data of the damping correction circuit is latched unchanged. The damping correction circuit outputs a digital control signal as a trimming signal for the zero-point compensation resistor in the filter, thereby automatically adjusting the damping coefficient to be independent of the loop bandwidth and keeping the damping coefficient at a constant value. In addition, the stability and responsiveness of the phase-locked loop circuit can be made higher.

[0080] The various parts of the phase-locked loop circuit are described below.

[0081] First, the working process of the negative feedback loop of the phase-locked loop circuit is described. Specifically, the frequency detector 201 detects the input reference frequency F REF and the output frequency F of the feedback divider 205 DIV Phase detection is performed and two drive signals UP and DN are output. UP and DN control the current switch in the charge pump 202 respectively. REF With F DIV If there is a phase misalignment, UP and DN are driven to change the output voltage V of the charge pump 202. CP Furthermore, V CP After filtering the high frequency noise through the loop filter 203, the control voltage V is output C . Control voltage V C Control the output frequency of the voltage controlled oscillator 204, so that after the feedback divider 205 divides the frequency, the F DIV The phase gradually changes with F REF The logic of the negative feedback loop is: if F DIV Advanced F REF , then V CAdjust the voltage controlled oscillator 204 to reduce its output frequency, that is, F DIV The frequency is reduced, thus delaying F DIV phase, thereby reducing F DIV With F REF Phase difference, after multiple cycles of adjustment F DIV With F REF The phase difference reaches the minimum and the loop is locked; if F DIV Falling behind REF , then V C Adjust the voltage controlled oscillator 204 to increase its output frequency, that is, F DIV The frequency increases, thus advancing F DIV phase, thereby reducing F DIV With F REF Phase difference, after multiple cycles of adjustment F DIV With F REF The phase difference is minimized and the loop is locked.

[0082] The lock detection circuit 206 , the digitally controlled current source 207 and the damping correction circuit 208 will be described below.

[0083] The input of the digitally controlled current source 207 is the output current of the voltage controlled oscillator 204. Specifically, the working current I VCO The mirrored current is mirrored by the current mirror and input into the digitally controlled current source 207 according to a set ratio.

[0084] The digitally controlled current source 207 divides the output current of the voltage controlled oscillator 204 by a fixed decimal number N to obtain the output current of the digitally controlled current source 207, and the output current of the digitally controlled current source 207 is input to the charge pump 202 as a pump current. The fixed decimal number N is also the division ratio of the feedback divider 205.

[0085] The lock detection circuit 206 is connected to the phase frequency detector 201 and the damping correction circuit 208. The lock detection circuit 206 is used to detect the internal nodes of the phase frequency detector 201, so as to identify whether the phase locked loop has been locked. The lock detection circuit 206 outputs an indication signal to the damping coefficient correction circuit, and the indication signal can indicate whether the phase locked loop circuit is locked.

[0086] The input of the damping coefficient correction circuit is the input reference frequency of the phase-locked loop circuit and the indication signal output by the lock detection circuit 206. The function of the damping correction circuit 208 is to detect the magnitude of the input reference frequency, thereby generating a corresponding digital control signal and inputting it into the loop filter 203 to control the magnitude of the zero-point compensation resistor in the loop filter 203, so that the resistance value of the zero-point compensation resistor in the control loop filter 203 is inversely proportional to the input reference frequency of the phase-locked loop circuit, thereby achieving the damping coefficient being independent of the input reference frequency.

[0087] The phase-locked loop circuit and clock generator are as follows: the phase-locked loop circuit includes a phase frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator and a feedback divider which are connected in series in sequence to form a negative feedback loop; the phase-locked loop circuit also includes a lock detection circuit, a digitally controlled current source and a damping correction circuit; the digitally controlled current source is connected to the voltage-controlled oscillator and the charge pump, and is used to divide the output current of the voltage-controlled oscillator by the frequency division coefficient to obtain the output current of the digitally controlled current source, and output the output current of the digitally controlled current source to the charge pump as the pump current of the charge pump; the lock detection circuit is connected to the phase frequency detector and the damping correction circuit, and is used to detect the internal nodes of the phase frequency detector to determine whether the phase-locked loop circuit is locked, and output an indication signal to the damping correction circuit according to the detection result; the damping correction circuit is also connected to the loop filter, and is used to output a digital control signal to the loop filter when it is determined that the phase-locked loop circuit is not locked according to the indication signal, so as to control the resistance value of the zero compensation resistor in the loop filter to be inversely proportional to the input reference frequency of the phase-locked loop circuit according to the digital control signal. Since the digitally controlled current source can divide the output current of the voltage-controlled oscillator by the frequency division coefficient, the output current of the digitally controlled current source is obtained and input to the charge pump as the pump current of the charge pump, and the pump current is related to the loop bandwidth, so that the loop bandwidth of the phase-locked loop circuit can be proportional to the input reference frequency of the phase-locked loop, and the loop bandwidth can adapt to the input reference frequency, which can not only ensure the stability of the loop but also keep the dynamic characteristics of the loop unchanged, thereby improving the system response rate. In addition, the resistance value of the zero-point compensation resistor in the control loop filter is inversely proportional to the input reference frequency of the phase-locked loop circuit by outputting a digital control signal through the damping correction circuit, so that the damping coefficient of the loop is kept at a constant value, which is independent of the input reference frequency, thereby ensuring the stability of the system. At the same time, the phase-locked loop circuit also avoids the disadvantage of the traditional charge pump phase-locked loop having strict requirements on the input reference frequency range, so it can also be widely used in on-chip SoC (system-on-chip) as a universal frequency synthesizer.

[0088] In one embodiment, the damping correction circuit 208 is further configured to keep the output digital control signal unchanged when it is determined that the phase-locked loop circuit is locked according to the indication signal.

[0089] In the embodiment of the present application, when the phase-locked loop circuit is not locked, the damping correction circuit 208 is in working state. When the phase-locked loop circuit is locked, the damping coefficient correction circuit is in a locked state, and at this time, the signal outputted by it is locked to the previous value, thereby avoiding noise interference to the loop filter.

[0090] In one embodiment, the damping correction circuit 208 is used to detect the magnitude of the input reference frequency according to the RC network, so as to convert the magnitude of the input reference frequency into a digital control signal.

[0091] As mentioned above, the damping correction circuit 208 needs to generate a digital control signal and input it into the loop filter 203, so as to control the size of the zero compensation resistor in the loop filter 203. In the embodiment of the present application, optionally, the damping correction circuit 208 can use an RC network to detect the size of the input reference frequency. Then, based on the size of the detected input reference frequency, it is converted into a corresponding multi-bit digital control signal, and the digital control signal is input into the loop filter 203, so as to control the size of the zero compensation resistor in the loop filter 203.

[0092] In one embodiment, the lock detection circuit 206 is used to determine that the phase-locked loop circuit is locked when the phase difference of the internal node is detected to be lower than a preset threshold, and to determine that the phase-locked loop circuit is not locked when the phase difference of the internal node is detected to be not lower than the preset threshold.

[0093] Specifically, when a PLL is not locked, there is a phase difference between the reference clock and the clock divided by the feedback divider 205, and the phase difference can be identified by using an XOR gate. The principle of the XOR gate is that the same is 0, and different is 1. If there is a phase difference, the result of the XOR within a clock cycle is a pulse of 1. This pulse is converted into a DC voltage, and the value of this DC voltage can be judged to determine the degree of phase alignment. When the PLL is completely locked, the pulse of 1 is very narrow, and the converted DC value is very low. Therefore, by setting a threshold, it can be used to detect whether the PLL is locked.

[0094] Based on this, in an optional embodiment of the present application, the method in which the lock detection circuit 206 detects the internal nodes of the frequency detector 201 to determine whether the phase-locked loop circuit is locked can be: the lock detection circuit 206 detects whether the normalized phase difference of the internal nodes is lower than a preset threshold value, and if it is lower than the preset threshold value, it indicates that the loop is locked. Otherwise, the loop is not locked. The phase difference can be a normalized phase difference.

[0095] In the embodiment of the present application, considering that there is no independent reference current source in the phase-locked loop circuit of the charge pump 202, the circuit may enter a degenerate state after initial startup, so a startup circuit 209 may be provided in the phase-locked loop circuit to ensure the normal operation of the loop. The startup circuit 209 is described below.

[0096] In one embodiment, Figure 3 As shown, the phase-locked loop circuit also includes a start-up circuit 209, which is connected to the feedback divider 205 and the voltage-controlled oscillator 204; the input signal of the start-up circuit 209 is the divided clock signal output by the feedback divider 205; the start-up circuit 209 is used to drive the voltage-controlled oscillator 204 to start oscillating when it is detected that the feedback divider 205 does not output the divided clock signal, so as to enable the phase-locked loop to operate normally.

[0097] Specifically, the input signal of the start-up circuit 209 is the divided clock signal output by the feedback divider 205 , and the output signal of the start-up circuit 209 is used to drive the control voltage of the voltage-controlled oscillator 204 .

[0098] The function of the start-up circuit 209 is to drive the driving voltage of the voltage-controlled oscillator 204 when it is detected that the feedback divider 205 has no clock output, so that the voltage-controlled oscillator 204 starts to oscillate quickly, so that the digitally controlled current source 207 receives the input current and outputs a certain current to allow the charge pump 202 to work normally, thereby establishing the loop operating point.

[0099] Optionally, when the loop operating point is established, the startup circuit 209 receives a valid output clock of the feedback divider 205 and the startup circuit 209 is automatically turned off.

[0100] In an optional embodiment of the present application, the start-up circuit 209 is specifically used to output a logic control signal when it is detected that the feedback divider 205 does not output the divided clock signal, so as to control the voltage of the voltage-controlled oscillator 204 to a preset voltage value through the logic control signal, wherein the preset voltage value corresponds to the start-up current of the voltage-controlled oscillator 204.

[0101] Specifically, when the startup circuit 209 detects that there is no frequency-divided clock signal, it can output a logic control signal 0. By connecting a resistor in series, the control voltage of the voltage-controlled oscillator 204 is directly pulled to a value at which the voltage-controlled oscillator 204 can obtain current, that is, pulled to a preset voltage value. The preset voltage value can be determined according to actual conditions, and can make the voltage-controlled oscillator 204 generate a startup current and start based on the startup current.

[0102] The above describes the principle of the phase-locked loop circuit provided in the embodiment of the present application, as well as the connection relationship and working process of the various components. The following is an illustrative description of an implementable structure of the digitally controlled current source 207, the loop filter 203, the damping correction circuit 208 and the starting circuit 209 provided in the embodiment of the present application.

[0103] In one embodiment, Figure 4 As shown, a structural schematic diagram of a digitally controlled current source provided by an embodiment of the present application is shown. The digitally controlled current source 207 includes N current division circuits, N+1 first switches, a first NMOS tube and a second NMOS tube; the drain of the first NMOS tube is connected to the current output terminal, the gate of the first NMOS tube is connected to the current input terminal, and the source of the first NMOS tube is grounded; the gate and drain of the second NMOS tube are connected to the current input terminal, and the source of the second NMOS tube is connected to one end of the first first switch; the kth current division circuit among the N current division circuits includes NMOS tubes MNk1, MNk2 and MNk3 and PMOS tubes MPk1 and MPk2, the drain of MNk1 is connected to the gate of MPk1, the drain of MPk1 and the gate of MPk2, and the source of MNk1 is grounded;

[0104] The source of MPk1 is connected to the power supply; the source of MPk2 is connected to the power supply, the drain of MPk2 is connected to the drain of MNk2, the gate of MNk2 and the gate of MNk3; the drain of MNk3 is connected to the current input terminal, and the source of MNk3 is connected to one end of the k+1th switch; if k is equal to 1, the gate of MNk1 is connected to the gate of the second NMOS tube; if k is not equal to 1, the gate of MNk1 is connected to the gate of MN(k-1)3; the other end of each first switch is grounded.

[0105] Specifically, based on the above analysis, it can be seen that the output current of the voltage-controlled oscillator 204 needs to be divided by a coefficient N, so the system needs a current division circuit as the digitally controlled current source 207. Figure 5 The current dividing circuit in the conventional technology shown, I in is the current input terminal, which comes from the voltage controlled oscillator 204, I out It is the current output terminal and is input into the charge pump. The two currents satisfy the following functional relationship:

[0106]

[0107] Among them, the total control signal of the current division circuit is DIV <n-1:0>, logic 1 indicates that the switch is on, logic 0 indicates that the switch is off, and S k The switches correspond one to one. k (k=0,1,2,3......n-1) represents the corresponding switch device. W / L is the width-to-length ratio of the unit device.

[0108] The disadvantage of the conventional current division circuit is that the size of the current mirror tubes is doubled. Therefore, if the number of switch devices n in the current division circuit is relatively large, the size of the current mirror tube corresponding to the last switch device is very different from that of the first switch device, resulting in a large circuit area. In order to solve this problem, the embodiment of the present application proposes a Figure 4 The new small-size current division circuit shown is applied to the digitally controlled current source 207 to achieve a better area saving effect.

[0109] refer to Figure 4 As shown, the first NMOS tube is an output current mirror NMOS tube M B , its drain is connected to the current output terminal I out , the source is grounded, and the gate is connected to the current input terminal I in . S k (k=0,1,2,3......n-1) represents the first switch, where S 0 For the first switch, S 1 For the second first switch, S ,k is the k+1th first switch.

[0110] The second NMOS tube is Figure 4 M N0 , whose gate and drain are connected to the current input terminal I in , the source is connected to the first switch S 0 And, the first switch S 0 The other end is grounded.

[0111] Define k = 1, 2, 3…n-1, then M Nk1 , M Nk2 ,M Nk3 , M Pk1 ,M Pk2 A current division circuit (also known as a current division circuit) is formed, which is called the kth current division circuit. Nk1 Connect M of the k-1th current division by 2 circuit N(k-1)3 of the gate.

[0112] For k = 1, M N11 Connect M N0 The gate of the kth current divide-by-2 circuit, M Nk1 The source is grounded and the drain is connected to M Pk1 The gate and drain of M Pk2 The gate. M Pk1 The source is connected to the power supply V DD . M Pk2 The source is connected to the power supply V DD , the drain is connected to M Nk2 and gate and drain and M Nk3 The gate of Nk2 The source of M is grounded; Nk3 The source of the switch S k One end of the drain is connected to I in ; Switch S k The other end is grounded.

[0113] Figure 4 In the digitally controlled current source 207 provided in the embodiment of the present application, the size of all NMOS is W / L. Figure 5 The number of NMOS is 3 times, but Figure 5 The total area of ​​the NMOS is 2 n WL, and Figure 4 The total area of ​​NMOS in the circuit is 3WL, so if n is greater than 3, a better area saving effect can be achieved. P(k-1)2 With M P(k-1)1 The size ratio is 2, so M P(k-1)2 The current is M P(k-1)1 Twice the current, or M N(k-1)3 The current is M N(k-1)1 Twice the current, where k=0,1,2......n-1.

[0114] The digitally controlled current source proposed in the embodiment of the present application adopts a new cascade current division circuit to realize that the output current is the decimal number corresponding to the input current divided by the frequency division coefficient. Compared with the traditional current division circuit, its area and complexity are greatly reduced.

[0115] It can be understood that the above-mentioned digitally controlled current source can also adopt other forms, not limited to the forms mentioned in the above embodiments, as long as it can achieve the functions achieved by the digitally controlled current source in the embodiments of the present application.

[0116] In one embodiment, Figure 6 , which shows a schematic diagram of the structure of a loop filter provided by an embodiment of the present application. The loop filter 203 includes m series-connected adjustable circuits, a first capacitor, and a second capacitor; wherein each adjustable circuit includes a compensation resistor and a second switch connected in parallel, and the resistance of each compensation resistor is respectively 2 times the unit compensation resistor. L times, L=0,1,2...,m-1, m is the number of control signal bits input to the loop filter 203, and m is a positive integer greater than or equal to 1; one end of the first adjustable circuit among the m series-connected adjustable circuits is grounded, and the other end is connected to one end of the second adjustable circuit; one end of the m-th adjustable circuit among the m series-connected adjustable circuits is connected to one end of the (m-1)-th adjustable circuit, and the other end is connected to one end of the first capacitor; the other end of the first capacitor is connected to one end of the second capacitor, and the other end of the second capacitor is grounded.

[0117] The loop filter 203 is a second-order loop filter 203 with an adjustable resistance structure. Figure 6 As shown, C 1 is the first capacitor, C 2 is the second capacitor. The first adjustable circuit includes a parallel compensation resistor R C and the second switch S 0 The mth adjustable circuit includes a parallel compensation resistor 2 m-1 R C and the second switch S m-1 ; Other adjustable circuits are similar and will not be described in detail.

[0118] Specifically, a single R C Characterizes the unit compensation resistance. S k (k=0,1,2......m-1) represents the corresponding switch device. The total control signal is RT <m-1:0>Logic 1 indicates that the switch is on, and logic 0 indicates that the switch is off. k The switches correspond one to one. The resistance value in the equivalent series circuit is:

[0119]

[0120] m is a positive integer greater than or equal to 1, representing an input m-bit digital control signal.

[0121] The first capacitor C 1 The upper end is the output terminal V of the charge pump 202 CP Or the input terminal V of the voltage controlled oscillator 204 C , its lower plate is connected to 2 m-1 R C The upper end and S m-1 If m = 1, then the first resistor R C The lower end and the first switch S 1 The lower end is grounded; if m is greater than 1, then the m-1th resistor 2 m-1 R C The lower end and the m-1th switch S m-1 The lower end of is connected in parallel to the m-2th resistor 2 m-2 R C The upper end and the m-2th switch S m-2 The upper end of.

[0122] It can be understood that the above-mentioned loop filter can also adopt other forms, not limited to the forms mentioned in the above embodiments, as long as it can achieve the functions that can be achieved by the loop filter in the embodiments of the present application.

[0123] In one embodiment, the damping correction circuit 208 derives the digital control signal based on successive approximation logic.

[0124] That is, in the embodiment of the present application, the damping correction circuit 208 can implement successive approximation logic, thereby automatically adjusting the compensation resistance of the loop filter 203 to achieve that the damping coefficient is independent of the loop bandwidth.

[0125] Please refer to Figure 7 , showing a schematic diagram of the structure of a realizable damping correction circuit provided by an embodiment of the present application. The damping correction circuit 208 includes w first D flip-flops, w delay units, w AND gates, a third switch, w capacitor circuits, a comparator, w second D flip-flops, w third D flip-flops and an integrating resistor; wherein the AND gate is a three-input AND gate circuit, the capacitor circuit includes a fourth switch and a fifth capacitor, and one end of the fourth switch is connected to one end of the fifth capacitor; the input signal at the CK end of each first D flip-flop is the input reference frequency; for the sth first D flip-flop among the w first D flip-flops, if s is equal to 1, the Q end of the sth first D flip-flop is connected to the D end of the last first D flip-flop; if s is not equal to 1, the Q end of the sth first D flip-flop is connected to the D end of the s-1th first D flip-flop; the Qb end of each first D flip-flop is connected to the input end of each delay unit respectively; each delay The output end of the unit is respectively connected to the first input end of each AND gate; the second input end of each AND gate is connected in parallel and connected to the third switch; the third input end of each AND gate is respectively connected to the Q end of each second D flip-flop; the output end of each AND gate is respectively connected to the other end of the fourth switch in each capacitor circuit; one end of the third switch is connected to the non-inverting end of the comparator, and the other end is connected to the power supply; the other end of the fifth capacitor in each capacitor circuit is connected in parallel and connected to the non-inverting end of the comparator; one end of the integrating resistor is connected to the non-inverting end of the comparator, and the other end is grounded; the inverting end of the comparator is connected to the power supply, and the output end of the comparator is connected to the D end of each second D flip-flop; the Q end of each second D flip-flop is respectively connected to the D end of each third D flip-flop; the CK end of each third D flip-flop is input as a sampling signal; the Q end of each third D flip-flop outputs a digital control signal.

[0126] The input of the damping correction circuit 208 is the input reference frequency F of the PLL. REF The output of the damping correction circuit 208 is an m-bit binary signal RT <m-1:0>, which is the digital control signal.

[0127] DFF0 to DFF(m-1) are w first D flip-flops, generating a uniform sequence signal DIN <m-1:0>For specific waveforms, please refer to Figure 8 The Q end of each DFFk is connected to the D end of DFFk-1, and the Q end of DFF0 is connected to the D end of DFFm-1, forming a ring counter. The Qb end of DFFk is DIN <k>。

[0128] FROM <m-1:0>Input to w delay units DL0 respectively <m-1:0>, w delay units DL0 <m-1:0>Output signal DO <m-1:0>Input to w three-input AND gates respectively <m-1:0>Specifically, after passing through w delay units DL0 and F REF The inverted signal F REFB And feedback signal FB <m-1:0>Perform AND operation. There are w three-input AND gates in total, and the output control signal is SW <m-1:0>, which respectively control the switched capacitor array C 0 ~2 m-1 C 0 The corresponding switches SW <m-1:0>, logic 0 means the switch is on. 0 is the integrating resistor. 0 to 2 m-1 C 0 and SW <0> To SW <m-1>w capacitor circuits are formed. Specifically, the fourth switch in the first capacitor circuit is SW <0> , the fifth capacitor is C 0 ; The fourth switch in the wth capacitor circuit is SW <m-1>, the fifth capacitor is 2 m-1 C 0 The third switch is SW-RT, F REFB Control SW_RT.

[0129] CMP is a comparator, DFFS1 and DSFFS2 are D flip-flops with asynchronous set 1 function. Among them, the in-phase terminal of a single comparator CMP is connected to VP, and the inverting terminal is connected to V DD / 2, the output signal CPO is connected to w second D flip-flops DFFS1 <m-1:0>The D input terminal.

[0130] Among them, one DFFS1 is a second D flip-flop, and there are w DFFS1 in the damping correction circuit 208; one DFFS2 is a third D flip-flop, and there are w DFFS2 in the damping correction circuit 208. The CK terminal of each third D flip-flop DFFS2 is connected to the sampling signal SAMP, and the Q terminal outputs the digital control signal RT <m-1:0>.

[0131] The Sb input of DFFS1 is 0, and the Q input is 1. The specific waveform is as follows Figure 8 shown.

[0132] Damping correction circuit 208 outputs binary data RT <m-1:0>Converted to decimal:

[0133]

[0134] After RT <m-1:0>The value of the resistance of the loop filter 203 after data adjustment is:

[0135]

[0136] Substituting equation 12 into equation 8, we can obtain:

[0137]

[0138] It can be seen that the damping coefficient is related to F REF Not relevant.

[0139] It can be understood that the above-mentioned damping correction circuit can also adopt other forms, not limited to the forms mentioned in the above embodiments, as long as it can achieve the functions that can be achieved by the damping correction circuit in the embodiments of the present application.

[0140] It should be noted that, in order to make the circuit diagram clearer, the figure does not fully show the specific connection lines between multiple DL0s and multiple ANDs and other components, and each DL0 uses an overlapping DL0 as a schematic, and each AND uses an overlapping AND as a schematic.

[0141] The initialization-enabled damping correction circuit provided in the embodiment of the present application samples the input reference frequency and converts it into a corresponding digital control signal, which controls the zero-point compensation resistor in the loop filter, thereby automatically adjusting the size of the zero-point compensation resistor when the bandwidth automatically follows the change of the input reference frequency to keep the damping coefficient basically unchanged.

[0142] In one embodiment, Fig. 9 As shown, a schematic diagram of the structure of a startup circuit provided by an embodiment of the present application is shown. The startup circuit 209 includes a first inverter, a second inverter, a first PMOS tube, a second PMOS tube, a third capacitor, a fourth capacitor, a constant current source and a trigger; the input signal of the first inverter is a frequency-divided clock signal, and the input end of the second inverter is connected to the output end of the first inverter; the source of the first PMOS tube is grounded, the gate of the first PMOS tube is connected to the output end of the second inverter, and the drain of the first PMOS tube is connected to one end of the third capacitor and the source of the second PMOS tube; the gate of the second PMOS tube is connected to the output end of the first inverter, and the drain of the second PMOS tube is connected to one end of the fourth capacitor, the input end of the constant current source and the input end of the trigger; the other end of the third capacitor, the other end of the fourth capacitor and the output end of the constant current source are grounded; the output signal of the trigger is a logic control signal.

[0143] Specifically, the startup circuit 209 is a clock detection circuit, wherein the input of the first inverter INV1 is the output clock CLK_DIV of the feedback divider 205, and the output is signal A. The input of the second inverter INV2 is signal A, and the output is signal B.

[0144] The source of the first PMOS switch tube SW1 is connected to the power supply V DD , the gate is connected to signal B, the drain is connected to signal N 1 (That is, with the third capacitor C A The source of the second PMOS switch SW2 is connected to the signal N 1 The gate is connected to the signal A (that is, connected to the output end of the first inverter), and the drain is connected to the signal N 2 (That is, with the fourth capacitor C B The third capacitor C A The upper plate is connected to the signal N 1 , the lower plate is grounded; the fourth capacitor C B The upper plate is connected to the signal N 2 , the lower plate is grounded; the current direction of the constant current source IDN is from N 2 flows to ground; the input of the trigger SCHM is signal N 2 , the output is OUT. Optionally, the trigger can be a Schmitt trigger.

[0145] The reverse clocks A and B drive the PMOS switches SW1 and SW2 respectively. DD is the power supply voltage, I DN is the current sink to ground, N 1 and N 2 is the circuit node, and OUT is the output signal.

[0146] If there is no clock at CLKDIV, that is, CLKDIV is 1 or 0, A and B remain static. If A=1, B=0, then N 2 With node N 1 Even if C 2 There is an initial charge on 2 The node voltage is eventually pulled down to 0 by IDN, OUT = 0; if A = 0, B = 1, N 2 With N 1 short circuit, so C A With C B The capacitors share charge and have equal voltages, but SW1 is open, so no charge is injected into C A and C B Because of the role of IDN, N 2 or N 1 The node voltage is eventually pulled down to 0, OUT = 0. If there is a clock signal in CLKDIV, A and B will flip alternately, and C A Transfer the charge from the power supply to C B On, raising the node N 2 voltage, if its average injected current is greater than IDN, then N 2 Finally, it is pulled close to the power supply voltage, OUT = 1. The above circuit detects whether the input CLKDIV exists, but there is a minimum allowable input frequency. Because the average injection current is proportional to the frequency of CLKDIV, the current must be greater than IDN. Below the minimum allowable input frequency, the circuit cannot work properly.

[0147] It can be understood that the above-mentioned starting circuit can also adopt other forms, not limited to the forms mentioned in the above embodiments, as long as it can achieve the functions that can be achieved by the starting circuit in the embodiments of the present application.

[0148] In one embodiment, the present application further provides a clock generator, which includes a phase-locked loop circuit as described in any of the above embodiments.

[0149] The above phase-locked loop circuit can be applied to a clock generator, and the clock generator can be applied to various electronic systems, which is not specifically limited here.

[0150] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic description of the above terms does not necessarily refer to the same embodiment or example.

[0151] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0152] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims. < / k>

Claims

1. A phase-locked loop circuit, characterized in that: The phase-locked loop circuit comprises a phase frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator and a feedback frequency divider which are sequentially connected in series to form a negative feedback loop, and the phase-locked loop circuit also comprises a lock detection circuit, a digitally controlled current source and a damping correction circuit; The digitally controlled current source is connected to the voltage-controlled oscillator and the charge pump, and is used to divide the output current of the voltage-controlled oscillator by a frequency division coefficient to obtain the output current of the digitally controlled current source, and output the output current of the digitally controlled current source to the charge pump as a pump current of the charge pump; The lock detection circuit is connected to the phase frequency detector and the damping correction circuit, and is used to detect the internal nodes of the phase frequency detector to determine whether the phase locked loop circuit is locked, and output an indication signal to the damping correction circuit according to the detection result; The damping correction circuit is also connected to the loop filter, and is used to output a digital control signal to the loop filter when it is determined according to the indication signal that the phase-locked loop circuit is not locked, so as to control the resistance value of the zero-point compensation resistor in the loop filter to be inversely proportional to the input reference frequency of the phase-locked loop circuit according to the digital control signal.

2. The phase-locked loop circuit according to claim 1, characterized in that: The damping correction circuit is also used to keep the output digital control signal unchanged when it is determined that the phase-locked loop circuit is locked according to the indication signal.

3. The phase-locked loop circuit according to claim 1, characterized in that: The damping correction circuit is used to detect the magnitude of the input reference frequency according to the RC network, so as to convert the magnitude of the input reference frequency into the digital control signal.

4. The phase-locked loop circuit according to claim 1, characterized in that: The lock detection circuit is used to determine that the phase-locked loop circuit is locked when it is detected that the phase difference of the internal node is lower than a preset threshold, and to determine that the phase-locked loop circuit is not locked when it is detected that the phase difference of the internal node is not lower than the preset threshold.

5. The phase-locked loop circuit according to claim 1, characterized in that: The phase-locked loop circuit further comprises a start-up circuit, which is connected to the feedback frequency divider and the voltage-controlled oscillator; an input signal of the start-up circuit is a frequency-divided clock signal output by the feedback frequency divider; The startup circuit is used to drive the voltage-controlled oscillator to start oscillating when it is detected that the feedback frequency divider does not output the divided clock signal, so as to enable the phase-locked loop to operate normally.

6. The phase-locked loop circuit according to claim 5, characterized in that: The startup circuit is specifically used to output a logic control signal when it is detected that the feedback divider does not output the divided clock signal, so as to control the voltage of the voltage-controlled oscillator to a preset voltage value through the logic control signal, wherein the preset voltage value corresponds to the startup current of the voltage-controlled oscillator.

7. The phase-locked loop circuit according to any one of claims 1 to 6, characterized in that: The digitally controlled current source comprises N current division circuits, N+1 first switches, a first NMOS tube and a second NMOS tube; The drain of the first NMOS tube is connected to the current output terminal, the gate of the first NMOS tube is connected to the current input terminal, and the source of the first NMOS tube is grounded; The gate and drain of the second NMOS tube are connected to the current input terminal, and the source of the second NMOS tube is connected to one end of the first first switch; The kth current division circuit among the N current division circuits comprises NMOS tubes MNk1, MNk2 and MNk3 and PMOS tubes MPk1 and MPk2, the drain of MNk1 is connected to the gate of MPk1, the drain of MPk1 and the gate of MPk2, and the source of MNk1 is grounded; The source level of MPk1 is connected to a power source; The source of MPk2 is connected to a power source, the drain of MPk2 is connected to the drain of MNk2, the gate of MNk2 and the gate of MNk3; the drain of MNk3 is connected to the current input terminal, and the source of MNk3 is connected to one end of the k+1th switch; If k is equal to 1, the gate of the MNk1 is connected to the gate of the second NMOS transistor; if k is not equal to 1, the gate of the MNk1 is connected to the gate of MN(k-1)3; The other end of each of the first switches is grounded.

8. The phase-locked loop circuit according to any one of claims 1 to 6, characterized in that: The loop filter comprises m series-connected adjustable circuits, a first capacitor and a second capacitor; wherein each of the adjustable circuits comprises a compensation resistor and a second switch connected in parallel, and the resistance value of each of the compensation resistors is respectively 2 times the unit compensation resistor. L times, L = 0, 1, 2 ..., m-1, m is the number of control signal bits input to the loop filter, and m is a positive integer greater than or equal to 1; One end of the first adjustable circuit of the m series-connected adjustable circuits is grounded, and the other end is connected to one end of the second adjustable circuit; One end of the m-th adjustable circuit among the m series-connected adjustable circuits is connected to one end of the m-1-th adjustable circuit, and the other end is connected to one end of the first capacitor; The other end of the first capacitor is connected to one end of the second capacitor, and the other end of the second capacitor is grounded.

9. The phase-locked loop circuit according to any one of claims 1 to 6, characterized in that: The damping correction circuit obtains the digital control signal based on successive approximation logic.

10. The phase-locked loop circuit according to claim 9, characterized in that: The damping correction circuit includes w first D flip-flops, w delay units, w AND gates, a third switch, w capacitor circuits, a comparator, w second D flip-flops, w third D flip-flops and an integrating resistor; wherein the AND gate is a three-input AND gate circuit, the capacitor circuit includes a fourth switch and a fifth capacitor, and one end of the fourth switch is connected to one end of the fifth capacitor; The input signal of the CK terminal of each of the first D flip-flops is the input reference frequency; For the sth first D flip-flop among the w first D flip-flops, if s is equal to 1, the Q end of the sth first D flip-flop is connected to the D end of the last first D flip-flop; if s is not equal to 1, the Q end of the sth first D flip-flop is connected to the D end of the s-1th first D flip-flop; The Qb terminal of each of the first D flip-flops is connected to the input terminal of each of the delay units respectively; the output terminal of each of the delay units is connected to the first input terminal of each of the AND gates respectively; The second input end of each AND gate is connected in parallel and connected to the third switch; the third input end of each AND gate is respectively connected to the Q end of each second D flip-flop; the output end of each AND gate is respectively connected to the other end of the fourth switch in each capacitor circuit; One end of the third switch is connected to the non-inverting end of the comparator, and the other end is connected to the power supply; The other end of the fifth capacitor in each of the capacitor circuits is connected in parallel and connected to the non-inverting end of the comparator; One end of the integrating resistor is connected to the non-inverting end of the comparator, and the other end is grounded; the inverting end of the comparator is connected to a power supply, and the output end of the comparator is connected to the D end of each of the second D flip-flops; The Q end of each of the second D flip-flops is connected to the D end of each of the third D flip-flops respectively; the CK end of each of the third D flip-flops inputs a sampling signal; and the Q end of each of the third D flip-flops outputs the digital control signal.

11. The phase-locked loop circuit according to claim 6, characterized in that: The startup circuit includes a first inverter, a second inverter, a first PMOS tube, a second PMOS tube, a third capacitor, a fourth capacitor, a constant current source and a trigger; The input signal of the first inverter is the divided clock signal, and the input terminal of the second inverter is connected to the output terminal of the first inverter; The source of the first PMOS tube is grounded, the gate of the first PMOS tube is connected to the output end of the second inverter, and the drain of the first PMOS tube is connected to one end of the third capacitor and the source of the second PMOS tube; The gate of the second PMOS tube is connected to the output end of the first inverter, and the drain of the second PMOS tube is connected to one end of the fourth capacitor, the input end of the constant current source and the input end of the trigger; The other end of the third capacitor, the other end of the fourth capacitor and the output end of the constant current source are grounded; The output signal of the trigger is the logic control signal.

12. A clock generator, characterized in that: The clock generator comprises a phase-locked loop circuit as claimed in any one of claims 1 to 11.

Images