A fully digital single-carrier symbol timing synchronization method under arbitrary oversampling ratio

Abstract

A method for all-digital single-carrier symbol timing synchronization under arbitrary oversampling ratios belongs to the field of communication signal processing. The received signal sampling points are transformed into the frequency domain through DFT; the signal is matched filtered by point-by-point multiplication in the frequency domain; the symbol timing deviation of the signal is estimated using the Godard method, and the estimation result drives a numerically controlled oscillator after passing through a loop filter; the sliding of the sampling point and the frequency domain compensation of the timing deviation are determined by the phase accumulation and overflow of the numerically controlled oscillator, the frequency domain aliasing area and the length of the IDFT are calculated according to the oversampling ratio, and the signal sampling points are converted to the time domain through the IDFT to obtain the recovered symbols, thereby realizing all-digital single-carrier symbol timing synchronization under arbitrary oversampling ratios and adapting to arbitrary oversampling ratios. The present invention is applicable to the field of communication signal processing and is used to expand the scope of application of single-carrier systems.

Description

Technical Field

[0001] The present invention relates to a full-digital symbol timing synchronization method for a single-carrier signal, and in particular to a full-digital single-carrier symbol timing synchronization method under an arbitrary oversampling ratio, and belongs to the field of communication signal processing. Background Art

[0002] Single-carrier communication is the most important transmission mode in communication systems. Signals such as MPSK, MAPSK, and QAM are widely used in single-carrier systems. In high-speed, high-bandwidth applications, modulation schemes such as MPSK, MAPSK, and QAM are widely used in broadband single-carrier systems due to their simple mapping / demapping methods, good power efficiency, and strong adaptability to carrier frequency offset and phase noise.

[0003] Unlike the corresponding orthogonal frequency division multiplexing (OFDM) system, although the single-carrier system has a stronger tolerance for carrier frequency deviation and phase noise, its symbol timing synchronization accuracy requirements are also much greater than those of the OFDM system. Especially in the case of high-order modulation such as 16 / 64QAM, a small symbol timing deviation can lead to a significant deterioration in the bit error rate. In addition, in large bandwidth scenarios, due to the performance limitations of existing analog-to-digital conversion (A / D) and digital-to-analog conversion (D / A) devices, for broadband signals up to several GHz or even tens of GHz, only a zero-IF receiver architecture can be used. This allows for complete acquisition of analog signals at a lower oversampling rate. However, the corresponding oversampling rate cannot be guaranteed to be an integer multiple of the symbol rate, rendering many classic symbol timing synchronization methods ineffective.

[0004] Commonly used, high-performance single-carrier symbol timing deviation estimation methods include the Godard algorithm, the Gardner algorithm, and the O&M algorithm. Corresponding compensation methods include Farrow interpolation based on Lagrange interpolation, triangular interpolation, and frequency-domain compensation followed by time-domain decimation. These compensation methods require an oversampling ratio of 2x or higher and therefore cannot function properly in low-oversampling systems using a zero-IF architecture. Summary of the Invention

[0005] In response to the problem of limited applicability of oversampling rates in existing single-carrier systems, the main purpose of the present invention is to provide a fully digital single-carrier symbol timing synchronization method under arbitrary oversampling ratios, using discrete Fourier transform (DFT) to convert the signal to the frequency domain, perform symbol timing deviation estimation in the frequency domain and compensate using frequency domain phase characteristics, then utilize the length arbitrariness of DFT and the frequency domain pre-aliasing method to implement the extraction process in the frequency domain, and finally use the inverse discrete Fourier transform (IDFT) to convert the frequency domain signal to the time domain to complete symbol timing synchronization. The present invention can avoid the complex interpolation processing of traditional methods and can adapt to any rational number oversampling relationship, and is particularly suitable under low oversampling rates. The fully digital architecture is easy to implement in FPGA, can be completely decoupled from the front-end RF module, and can adapt to any form of receiver architecture with any oversampling ratio, which can expand the scope of application of single-carrier systems.

[0006] The purpose of the present invention is achieved through the following technical solutions:

[0007] The present invention discloses a method for all-digital single-carrier symbol timing synchronization under arbitrary oversampling ratio. For the received signal sampling points, DFT transformation is performed on them to the frequency domain, and matched filtering processing is performed on the signal by point-by-point multiplication in the frequency domain; after matched filtering, the Godard method is used to estimate the symbol timing deviation of the signal; the estimation result drives a numerically controlled oscillator (NCO) after passing through a loop filter; the sliding of the sampling point and the frequency domain compensation of the timing deviation are determined by the phase accumulation and overflow of the NCO, the frequency domain aliasing area and the length of the IDFT are calculated according to the oversampling ratio, and the signal sampling points are converted to the time domain through the IDFT to obtain the recovered symbols. Since the lengths of the DFT and IDFT are arbitrarily set, they can adapt to any multiple of the oversampling ratio. All operations are performed in the digital signal domain, so it is possible to achieve all-digital single-carrier symbol timing synchronization under arbitrary oversampling ratios, expanding the scope of application of single-carrier systems.

[0008] The present invention discloses a full-digital single-carrier symbol timing synchronization method under arbitrary oversampling ratio, comprising the following steps:

[0009] Step 1: The received signal is sampled by an analog-to-digital converter (ADC) and quadrature-converted to zero frequency, generating a quadrature zero-frequency signal. The ADC oversampling ratio is N / M times the symbol rate, where N>M. The data is stored in memory. The data in the memory is subsequently batch-output based on the output bias control signal to select the sampled data.

[0010] Step 2: Perform DFT transformation on the received signal, with the transformation length being an integer multiple of N, that is, N×L, where L is a positive integer, to obtain the corresponding frequency domain signal. The length of the memory output data in step 1 is N×L.

[0011] The frequency domain signal obtained after the N×L point DFT transform is X(k), k=0,1,…,NL-1, and the roll-off factor of the transmitter shaping filter is α, then the effective signal is

[0012]

[0013] In the frequency domain, the effective signal is processed by matched filtering. The matched filter is in the form of convolution in the time domain and point-by-point multiplication in the frequency domain. The frequency domain expression of the matched filter is G(k), which is the same as X s The filtered frequency domain signal is obtained by point-by-point multiplication of (k)

[0014] Y(k)=X s (k)G(k)

[0015] Where k = 0, 1,…, NL-1.

[0016] Step 3: Perform timing deviation compensation on the frequency domain signal Y(k) after matched filtering in step 2. The timing deviation to be compensated is

[0017] Using the frequency domain point-by-point multiplication method, the corrected frequency domain signal is

[0018]

[0019] Step 4: Correct the frequency domain signal after timing deviation in step 3 Perform timing deviation estimation.

[0020] Step 4.1: First Perform a circular shift and get

[0021]

[0022] Here||·|| NL Indicates the cyclic shift of the NL point.

[0023] Step 4.2: and Multiply the conjugate of point by point to get

[0024]

[0025] Here, all components of Z(k) include timing synchronization deviation values.

[0026] Step 4.3: To maximize the signal-to-noise ratio, sum all components of Z(k) and take their phase to obtain the symbol timing deviation estimate

[0027]

[0028] In the formula To find the complex phase, we have The value range of is [-π, π).

[0029] Step 4.4: For the convenience of subsequent processing, Perform normalization and obtain

[0030]

[0031] here The value range of is [-0.5, 0.5), which represents the relative value of the symbol timing deviation estimate to the duration of one symbol.

[0032] Step 5: The normalized symbol timing deviation obtained in step 4 is The signal is sent to a second-order loop filter, which can reduce the impact of noise in symbol timing deviation estimation.

[0033] Step 6: The loop output drives the NCO and determines whether the NCO overflows positively, negatively, or not. Based on the overflow and overflow direction, the offset of the front-end memory output data is determined. The NCO residual is used as a timing synchronization offset compensation.

[0034] Step 6.1: The loop filtering result is Then the cumulative value of NCO is

[0035]

[0036] Step 6.2: After completing one accumulation, the current NCO value is judged, and its threshold is

[0037]

[0038] Step 6.3: Memory offset control index O(i) satisfies

[0039]

[0040] The value of O(i) determines whether the corresponding data block is advanced by one additional sampling point, i.e., O(i) = -1, or delayed by one additional sampling point, i.e., O(i) = 1, when data is retrieved from the memory next time, or whether no additional offset processing is performed, i.e., O(i) = 0.

[0041] Step 6.4: After calculating O(i), update the overflow of NCO:

[0042]

[0043] Then we get the overflow updated NCO(i), which will be used as Compensation is performed in step 3.

[0044] Step 7: Transform the signal from step 3 Perform frequency domain aliasing processing. The length of the signal S(n) after aliasing is NL, and the length of the signal S(n) after aliasing is ML. The aliasing process satisfies

[0045]

[0046] Step 8: Perform IDFT of length ML on S(n):

[0047] s(n)=IDFT(S(n)) ML

[0048] s(n) is the final recovered symbol.

[0049] Step 9: Return to step 1 and, based on O(i) obtained in step 6, control the position of the memory output data for the (i+1)th time. Repeat the loop to continuously recover the symbol. Because N and M can be arbitrarily selected in this process, the above steps can adapt to signals with any oversampling ratio, expanding the applicability of single-carrier systems.

[0050] Beneficial effects:

[0051] 1. This invention discloses a fully digital single-carrier symbol timing synchronization method at any oversampling ratio. The method performs a DFT transform on the input signal to the frequency domain, performs matched filtering, timing offset compensation, timing offset estimation, and frequency domain aliasing extraction in the frequency domain, and converts the frequency domain signal to the time domain via an IDFT to achieve frequency domain timing synchronization. During this process, the accumulated overflow value of the NCO is used to precisely control the read and write offsets of the front-end memory cache data, enabling accurate tracking of signals with sampling clock deviations.

[0052] 2. The present invention discloses a fully digital single-carrier symbol timing synchronization method under arbitrary oversampling ratio, which uses the Godard method to estimate symbol timing deviation in the frequency domain at arbitrary oversampling ratio, greatly improving the adaptability of symbol synchronization and expanding the scope of application of single-carrier systems.

[0053] 3. This invention discloses a fully digital single-carrier symbol timing synchronization method at any oversampling ratio. During the DFT and IDFT processing performed on the memory output, this method essentially performs parallel signal processing, allowing for arbitrary parallelism. This method can operate even when the logic device processing clock is limited and the symbol rate is excessive, achieving symbol synchronization at ultra-high speeds.

[0054] 4. This invention discloses a fully digital single-carrier symbol timing synchronization method for arbitrary oversampling ratios. By configuring DFT and IDFT operations of varying lengths and combining them with frequency-domain aliasing, it can replace the decimation process used in traditional time-domain methods. This method is particularly effective at non-integer oversampling, where traditional time-domain decimation requires polyphase filtering.

[0055] 5. The present invention discloses a fully digital single-carrier symbol timing synchronization method under arbitrary oversampling ratio. Since all processing is performed in the frequency domain, the frequency domain equalization widely used in high-speed communications can be directly applied in this method without the need for additional DFT and IDFT processing, which can greatly reduce resource consumption from the overall system. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] Figure 1 This is a structural block diagram of a fully digital single-carrier symbol timing synchronization method at an arbitrary oversampling ratio disclosed in this embodiment;

[0057] Figure 2 The embodiment of the present invention discloses a 256QAM modulation mode with a 1.25 times oversampling rate, a roll-off factor of 0.125, and a signal-to-noise ratio of E b / N0 is 31dB, and the sampling clock deviation is 1×10 -4 The power spectrum of the signal received when

[0058] Figure 3 The loop filter structure disclosed in the embodiment of the present invention;

[0059] Figure 4 The embodiment of the present invention discloses a 256QAM modulation mode with a 1.25 times oversampling rate, a roll-off factor of 0.125, and a signal-to-noise ratio E b / N0 is 31dB, and the sampling clock deviation is 1×10 -4 When , the constellation diagram before and after symbol synchronization,

[0060] Figure (a) shows the constellation diagram before synchronization, and Figure (b) shows the constellation diagram after synchronization.

[0061] Figure 5 The embodiment of the present invention discloses a 256QAM modulation mode with a 1.25 times oversampling rate, a roll-off factor of 0.125, and a sampling clock deviation of 1×10 -4 , different E b / N0 and compared with the theoretical value.

[0062] Figure 6 The present invention discloses a flow chart of a method for all-digital single-carrier symbol timing synchronization under arbitrary oversampling ratio. DETAILED DESCRIPTION

[0063] The present invention will be described in detail below with reference to the accompanying drawings and embodiments. The technical problems solved by the technical solution of the present invention and the beneficial effects thereof are also described. It should be noted that the described embodiments are only intended to facilitate understanding of the present invention and do not serve to limit the present invention in any way.

[0064] The present embodiment discloses a method for all-digital single-carrier symbol timing synchronization under arbitrary oversampling ratio, based on the structure of the method for all-digital single-carrier symbol timing synchronization under arbitrary oversampling ratio disclosed in the present embodiment. The structural block diagram is as follows: Figure 1 As shown, it includes a RAM cache module, an NL point DFT module, a matched filter module, a symbol timing deviation compensation module, a symbol timing deviation estimation module, a loop filter, an NCO, a RAM offset control module, a frequency domain aliasing module and an ML point IDFT module. After the ADC performs zero intermediate frequency sampling, an oversampled signal is obtained, and the ADC sampling signal is sent to the RAM cache module to cache the data; the RAM cache module checks the internal cached data, and when a DFT processing length is met, the data is output to the DFT module; the DFT module performs discrete Fourier transform on the received time domain signal to obtain the same number of frequency domain signals, which are sent to the matched filter module; the matched filter module multiplies the frequency domain signal according to the corresponding matched filter coefficient to obtain the filtered signal, and sends it to the symbol timing deviation compensation module; the symbol timing deviation compensation module receives the timing deviation output from the NCO module and performs frequency domain compensation on the frequency domain signal, and outputs the signal to the symbol timing deviation estimation module and the frequency domain aliasing module; the symbol timing deviation estimation module performs timing deviation estimation on the corrected frequency domain signal, and sends the estimation result to the loop filter; the loop filter performs second-order Jaffe filtering on the estimation result , and sends the filtering result to the NCO module; the NCO receives the filtering result of the loop filter, performs NCO accumulation, and determines the overflow after accumulation, and sends the forward overflow / reverse overflow / no overflow result to the RAM offset control module, and at the same time sends the residual value after the accumulated overflow as the timing deviation correction input to the symbol timing deviation compensation module; the RAM offset control module receives the NCO overflow result, and according to the result, performs offset control on the output address of the RAM cache module to complete the closed loop of the entire processing loop; the frequency domain signal output by the symbol timing deviation compensation module is also output to the frequency domain aliasing module, which performs aliasing extraction on the frequency domain signal according to the oversampling ratio relationship and the roll-off factor of the modulation signal, and performs frequency domain extraction equivalently, and sends the shorter frequency domain data after extraction to the IDFT module; the IDFT module performs IDFT transformation on the frequency domain signal from the frequency domain aliasing module, and finally obtains the restored time domain symbol to complete the entire processing process.

[0065] In this implementation, the 256QAM modulation mode is used, the oversampling ratio is 1.25 (i.e., 5 / 4), the roll-off factor is 0.125, and the sampling clock deviation of the received signal is 1×10 -4 , whose spectrum is Figure 2 As shown in the figure, based on the oversampling factor of 1.2, the number of DFT single processing points is determined to be 160, and the corresponding IDFT processing points is 128. After determining the number of processing points, the specific steps are as follows.

[0066] S1: The RAM module caches data and records the initial read address ADDR_rd. As data enters, the write address ADDR_wr is updated one by one. The offset signal input by the RAM offset control module is Offset_index (a value range of 0 and ±1). When the cache contains enough data for one DFT process (160 samples, corresponding to ADDR_wr = ADDR_rd + 160 + Offset_index), the 160 samples are read out, and the corresponding addresses are ADDR_rd + Offset_index + 1 to ADDR_rd + Offset_index + 160. The current read address is recorded and ADDR_rd is updated to facilitate the next backward data output.

[0067] S2: The DFT module receives 160 sampling points x0~x from the buffer RAM module 159 , and perform 160-point DFT operation on it to obtain 160 frequency domain sampling points X0~X 159 , sent to the matched filter module.

[0068] S3: The matched filter module receives 160 frequency domain sampling points and performs an equivalent 81-order matched filter. The 81 filter time domain impulse responses are padded to a length of 160 to obtain

[0069] g extend ={g0,g1,…,g 80 ,0,0,…,0} 1×160

[0070] Then the time domain impulse response g after zero padding extend Perform 160-point DFT operation to obtain 160-point frequency domain response G0~G 159 And store the value in local ROM, and compare it with the received frequency domain sampling points X0~X 159 Perform point-by-point multiplication

[0071] Y n =X n G n ,n=0,1,…,159

[0072] Get Y0~Y 159 .

[0073] S4: The symbol timing deviation compensation module receives the frequency domain filtering results Y0~Y 159 Perform timing deviation compensation processing.

[0074] S4.1: For Y0~Y 159 Perform 128-point cyclic shift to obtain the shift sequence Y′0~Y′ 159 satisfy

[0075] {Y′0,Y′1,…,Y′ 159}={Y 128 ,Y 129 ,…,Y 159 , Y0, Y1, …, Y 127}

[0076] S4.2: For Y0~Y 159 and Y′0~Y′ 159 Perform conjugate multiplication, the result is Z0~Z 159 satisfy

[0077] Z n =Y n (Y′ n ) * ,n=0,1,…,159

[0078] S4.3: For Z0~Z 159 Sum and take the normalized phase to get the normalized timing deviation ε

[0079]

[0080] S5: Send the estimated timing deviation ε to the loop filter. The loop filter adopts Jaffe second-order loop. Its structure is shown in Figure 3 ω n is the characteristic frequency, and its value is 1.8868×B L , B L is the loop bandwidth, which is set to 0.1 here; K is the loop gain, which is set to 0.3 here.

[0081] S6: The output of the loop filter is sent to the NCO module, where the NCO overflow threshold is 0.2 (1-1 / 1.25=0.2). For example, if the original NCO residual value is 0.15 and the filtered timing offset value is 0.08, the accumulated NCO is 0.23, indicating a positive overflow. A positive overflow flag signal is output to the RAM control offset module. The NCO also performs an overflow modulo operation, resulting in a final NCO value of 0.03 (0.23-0.2=0.03), which will serve as the compensation value τ for the next timing offset compensation. After receiving the positive overflow flag signal, the RAM control offset module sets the Offset_index signal in the RAM cache module to 1, indicating the output offset of the RAM data for the next iteration.

[0082] S7: compensated frequency domain data Y0~Y in S3 159 In the frequency domain aliasing module, frequency domain aliasing extraction processing is performed to obtain 128 (160 / 1.25=128) frequency domain symbols S0~S 127 , when the roll-off factor α is 0.125 and the number of effective signal frequency domain points is 128, the number of roll-off band frequency domain points is 16 (128×0.125=16), then the aliasing method is as follows:

[0083] (1)S0~S 55 No aliasing, with Y0~Y 55 equal;

[0084] (2)S 56 ~S 63 There is aliasing, its value is equal to Y 56 ~Y 63 With Y 80 ~Y 87 The point-wise summation of

[0085] (3)S 64 ~S 71 There is aliasing, its value is equal to Y 96 ~Y 103 With Y 64 ~Y 71 The point-by-point summation of

[0086] (4)S 72 ~S 127 No aliasing, with Y 104 ~Y 159 equal.

[0087] S8: frequency domain symbols S0~S after frequency domain aliasing 127 Perform 128-point IDFT operation to obtain the final recovered time domain symbols s0~s 127 .

[0088] S9: Repeat step S1 and iterate until the loop gradually converges, completing the entire symbol synchronization process.

[0089] The simulation results of the above process are shown in Figure 4 and Figure 5 At very low non-integer oversampling rates (1.25 times oversampling) and large sampling clock deviations (1×10 -4 ) conditions, from Figure 4 The results show that timing synchronization can perfectly restore the signal, and the 256QAM constellation points are clearly visible; Figure 5 Compared with the theoretical error curve of 256QAM, the error rate of different E b The timing synchronization results under / N0 conditions are close to the theoretical values. Figure 4 、 Figure 5 The results show that the proposed method can adapt to non-integer low oversampling rates and different signal-to-noise ratio conditions, and ensure extremely low performance loss, which can expand the applicability of single-carrier systems.

[0090] The above specific description further illustrates the purpose, technical solutions and beneficial effects of the invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A fully digital single-carrier symbol timing synchronization method under arbitrary oversampling ratio, characterized by: The following steps are included: Step 1: The received signal is sampled by an analog-to-digital converter (ADC) and orthogonally converted to zero frequency to obtain an orthogonal zero-frequency signal; the oversampling rate of the ADC is N / M times the symbol rate, where N>M; The data is stored in the memory, and the data in the subsequent memory will be selected and output in batches according to the output bias control signal; Step 2: Perform DFT transform on the received signal with a transform length of an integer multiple of N, that is, N×L, where L is a positive integer, to obtain the corresponding frequency domain signal. The memory output data length in step 1 is N×L, and matched filtering is performed in the frequency domain. Step 3: Perform timing deviation compensation on the frequency domain signal Y(k) after matched filtering in step 2. The timing deviation to be compensated is Using the frequency domain point-by-point multiplication method, the corrected frequency domain signal is Step 4: Correct the frequency domain signal after timing deviation in step 3 Perform timing deviation estimation; The implementation method of step 4 is: Step 4.1: First Perform a circular shift and get Here||·|| NL Represents the cyclic shift of the NL point; Step 4.2: and Multiply the conjugate of point by point to get Here all components of Z(k) include timing synchronization deviation values; Step 4.3: To maximize the signal-to-noise ratio, sum all components of Z(k) and take their phase to obtain the symbol timing deviation estimate In the formula To find the complex phase, we have The value range of is [-π, π); Step 4.4: For the convenience of subsequent processing, Perform normalization and obtain here The value range of is [-0.5, 0.5), which represents the relative value of the symbol timing deviation estimate to the duration of one symbol; Step 5: The normalized symbol timing deviation obtained in step 4 is Feed into the second-order loop filter; Step 6: The loop output drives the NCO and determines whether the NCO has positive overflow, negative overflow, or no overflow. The offset of the front-end memory output data is determined based on the overflow and overflow direction. At the same time, the residual value of the NCO is used as the timing synchronization deviation compensation. The implementation method of step 6 is: Step 6.1: The loop filtering result is Then the cumulative value of NCO is Step 6.2: After completing one accumulation, the current NCO value is judged, and its threshold is Step 6.3: Memory offset control index O(i) satisfies The value of O(i) determines whether the corresponding data block is advanced by one sampling point (i.e., O(i) = -1) or delayed by one sampling point (i.e., O(i) = 1) when the data is retrieved from the memory next time, or whether no additional offset processing is performed (i.e., O(i) = 0). Step 6.4: After calculating O(i), update the overflow of NCO: Then we get the overflow updated NCO(i), which will be used as Compensation is performed in step 3; Step 7: Transform the signal from step 3 Perform frequency domain aliasing processing; The length of the signal S(n) after aliasing is NL, and the length of the signal S(n) after aliasing is ML; the aliasing process satisfies α is the roll-off factor of the transmitter shaping filter; Step 8: Perform IDFT of length ML on S(n): s(n)=IDFT(S(n)) ML s(n) is the final recovered symbol; Step 9: Return to step 1, and based on O(i) obtained in step 6, control the position of the data output from the memory for the i+1th time, and iterate in a loop to continuously obtain the recovered symbols; The N and M in the process can be selected arbitrarily.

2. The all-digital single-carrier symbol timing synchronization method under arbitrary oversampling ratio according to claim 1, characterized in that: The implementation method of step 2 is: The frequency domain signal obtained after N×L point DFT transformation is X(k), k=0,1,…,NL-1, then the effective signal is In the frequency domain, the effective signal is processed by matched filtering. The matched filtering is in the form of convolution in the time domain and in the form of point-by-point multiplication in the frequency domain. The frequency domain expression of the matched filtering is G(k), which is the same as X s The filtered frequency domain signal is obtained by point-by-point multiplication of (k) Y(k)=X s (k)G(k) Where k = 0, 1,…, NL-1.

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