IV-to-Voltage Conversion Circuit for Dynamic Vision Sensors Achieving Minimal Current Conversion

Abstract

This invention proposes an IV conversion circuit for dynamic vision sensors that realizes micro-current conversion, applicable to the field of dynamic vision sensors. It includes a photodiode, a photodiode clamping circuit, a current mirror, and a logarithmic transistor circuit. The photodiode clamping circuit comprises two NMOS transistors, two PMOS transistors, one NPN transistor, and one PNP transistor, ensuring the negative feedback structure operates normally when the photocurrent is greater than 1pA. Simultaneously, the PNP transistor pre-amplifies the photocurrent. The current mirror amplifies the pre-amplified photocurrent. The logarithmic transistor circuit converts the double-amplified photocurrent into a photovoltage. This invention enables IV conversion of photocurrents greater than 1pA, improving the micro-current conversion capability of the IV conversion circuit and enhancing the imaging performance of dynamic vision sensors in low-light environments.

Description

Technical Field

[0001] This invention belongs to the field of electronic circuit technology and relates to an IV conversion circuit, specifically an IV conversion circuit in the field of microelectronics technology that realizes the conversion of minute currents and can be used in dynamic vision sensors. Background Technology

[0002] Dynamic vision sensors include pixel circuits, line-or circuits, arbitration circuits, encoding circuits, and handshake circuits. Pixel circuits are responsible for the conversion, amplification, and comparison of photoelectric signals. Among them, the IV conversion circuit is a crucial component of the pixel circuit; it converts the light signal received by the photodiode into photocurrent, and then into photovoltage. The smaller the minimum conversion current capability of the IV conversion circuit, the larger the dynamic range of the dynamic vision sensor. The logarithmic conversion slope of the IV conversion circuit in converting photocurrent to photovoltage is negatively correlated with the contrast sensitivity of the dynamic vision sensor. A larger dynamic range and lower contrast sensitivity result in stronger imaging performance of the dynamic vision sensor in low-light environments.

[0003] In 2020, Zhang Zhiyuan disclosed an IV conversion circuit for a dynamic vision sensor in his paper "Design of Bionic Dynamic Vision Sensor Integrated Circuit" (Zhang Zhiyuan, Xi'an University of Electronic Science and Technology, 2020), the structure of which is as follows: Figure 1 As shown, it includes a photodiode (PD), a photodiode clamping circuit, and a logarithmic transistor circuit. The clamping circuit consists of three NMOS transistors (NM1, NM2, and NM3) and two PMOS transistors (PM1 and PM2). The logarithmic transistor circuit consists of two PMOS transistors (PM3 and PM4) connected in a diode configuration. When the PD generates a photocurrent I... PD The IV conversion circuit outputs a photovoltage Vout, realizing the conversion from photocurrent to photovoltage.

[0004] In the IV conversion circuit of this dynamic vision sensor, NM1, PM1, and PM2 provide bias current for NM2. The source follower negative feedback structure composed of NM2 and NM3 clamps the voltage at the negative terminal of the PD at Vbias, ensuring that the PD operates in a stable reverse bias state. PM3 and PM4 both operate in the subthreshold region. The logarithmic relationship between the source drain current and gate source voltage of the MOSFET in the subthreshold region is used to realize the logarithmic conversion of photocurrent to photovoltage. The logarithmic conversion improves the dynamic range of the dynamic vision sensor. However, its shortcomings are as follows: First, when the dynamic vision sensor operates in a low-light environment, the current generated by the PD is relatively small. When the photocurrent is less than 4pA, NM2 cannot work properly, and the source follower negative feedback structure composed of NM2 and NM3 will fail, thereby causing the clamping circuit to fail and failing to clamp the negative terminal voltage of the PD. The PD cannot work in a stable reverse bias state, and the dynamic vision sensor cannot work properly. Second, when the photocurrent generated by the PD is less than 40pA, the logarithmic transistor circuit composed of PM3 and PM4 directly converts the photocurrent, resulting in a reduction in logarithmic amplification capability, an increase in the contrast sensitivity of the dynamic vision sensor, and a reduction in the imaging performance of the dynamic vision sensor in low light. Summary of the Invention

[0005] The purpose of this invention is to address the shortcomings of the existing technologies by proposing a dynamic vision sensor IV conversion circuit that enables the conversion of minute currents. This circuit can achieve IV conversion of currents greater than 1 pA, solving the technical problems in the prior art where it is unable to perform IV conversion of currents less than 4 pA and has poor conversion capability for currents less than 40 pA, thereby improving the imaging performance of dynamic vision sensors in low light conditions.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0007] A dynamic vision sensor IV conversion circuit for achieving micro-current conversion includes a photodiode (PD), a photodiode clamping circuit, and a logarithmic transistor circuit; the photodiode (PD) is used to receive light intensity and generate a photocurrent (I). PD The photodiode clamping circuit includes two NMOS transistors and two PMOS transistors; the logarithmic transistor circuit includes multiple PMOS transistors connected in diode configuration to achieve logarithmic conversion of photocurrent to photovoltage; the photodiode clamping circuit also includes an NPN transistor Q1 and a PNP transistor Q2 for implementing negative feedback control under small photocurrent and pre-amplifying the photocurrent; the IV conversion circuit also includes a current mirror consisting of at least one PMOS current mirror and one NMOS current mirror cascaded together for amplifying the pre-amplified photocurrent.

[0008] The aforementioned dynamic vision sensor IV conversion circuit for achieving micro-current conversion includes a photodiode clamping circuit. A first PMOS transistor PM1 has its source connected to power supply VDD, and its gate connected to its drain, the gate of a second PMOS transistor, and the drain of a first NMOS transistor NM1. A second PMOS transistor PM2 has its source connected to power supply VDD, and its drain connected to the base of Q1 and the drain of the second NMOS transistor NM2. An NPN transistor Q1 has its emitter connected to the emitter of Q2. A PNP transistor Q2 has its base connected to the negative terminal of PD and the gate of the second NMOS transistor NM2, and its collector connected to ground AGND. A first NMOS transistor NM1 has its gate loaded with a bias voltage Vbias, and its source connected to AGND. A second NMOS transistor NM2 has its source connected to AGND.

[0009] The aforementioned dynamic vision sensor IV conversion circuit for realizing minute current conversion includes a PMOS current mirror comprising four PMOS transistors: the third PMOS transistor PM3 has its gate and drain connected, the source of PM5 and the gate of PM4 connected, and its source connected to VDD; the fourth PMOS transistor PM4 has its source connected to VDD and its drain connected to the source of PM6; the fifth PMOS transistor PM5 has its drain connected to the collector of Q1; and a bias voltage Vb1 is applied to the gate of the fifth PMOS transistor PM5 and the gate of the sixth PMOS transistor PM6.

[0010] The aforementioned dynamic vision sensor IV conversion circuit for realizing minute current conversion includes an NMOS current mirror comprising four NMOS transistors: the drain of the third NMOS transistor NM3 is connected to the drain of PM6, and its source is connected to the drain and gate of the fifth NMOS transistor NM5 and the gate of the sixth NMOS transistor NM6; the source of the fourth NMOS transistor NM4 is connected to the drain of the sixth NMOS transistor NM6; the source of the fifth NMOS transistor NM5 is connected to AGND; and the source of the sixth NMOS transistor NM6 is connected to AGND. A bias voltage Vb2 is applied to the gate of both the third NMOS transistor NM3 and the gate of the fourth NMOS transistor NM4.

[0011] The aforementioned dynamic vision sensor IV conversion circuit for achieving minute current conversion uses a third NMOS transistor NM3 and a fourth NMOS transistor NM4, which are deep N-well devices with their substrates connected to their sources.

[0012] The aforementioned dynamic vision sensor IV conversion circuit for realizing micro-current conversion includes a logarithmic transistor circuit containing three PMOS transistors connected in a diode configuration. Specifically, the gate and drain of the seventh PMOS transistor PM7 are connected to the source of the eighth PMOS transistor PM8, and the source is connected to VDD; the gate and drain of the eighth PMOS transistor PM8 are connected to the source of the ninth PMOS transistor PM9; and the gate and drain of the ninth PMOS transistor PM9 are connected to the drain of NM4, serving as the output terminal of the IV conversion circuit.

[0013] The aforementioned dynamic vision sensor IV conversion circuit for achieving micro-current conversion includes a logarithmic transistor circuit containing more than three PMOS transistors in diode-connected configurations to achieve a large logarithmic slope conversion from photocurrent to photovoltage.

[0014] The aforementioned dynamic vision sensor IV conversion circuit for realizing minute current conversion, wherein the current mirror includes multiple PMOS current mirrors and NMOS current mirrors of equal number, is used to achieve a greater amplification factor for the pre-amplified photocurrent.

[0015] The aforementioned dynamic visual sensor IV conversion circuit for achieving micro-current conversion uses a photodiode clamping circuit, which pre-amplifies the photocurrent via a PNP transistor Q2.

[0016] Compared with the prior art, the present invention has the following advantages:

[0017] First, because this invention employs a clamping circuit containing an NPN transistor Q1 and a PNP transistor Q2, when the dynamic vision sensor operates in a low-light environment, the current I generated by the PD... PD When the voltage exceeds 1pA, the gate-source voltage of the existing NM3 transistor cannot control the drain-source current, causing the negative feedback structure to fail. However, the clamping circuit of this invention stabilizes the reverse bias voltage of the PD through the negative feedback structure composed of Q1, Q2 and NM2, enabling the dynamic vision sensor to work in more extreme low-light environments, improving the dynamic range of the dynamic vision sensor, and improving the imaging performance of the dynamic vision sensor in low-light environments.

[0018] Secondly, this invention employs a deep N-well NMOS current mirror and a PMOS current mirror, as well as Q2, where Q2 can control the photocurrent I. PD Pre-amplification is achieved by using NMOS and PMOS current mirrors to amplify the pre-amplified photocurrent step by step. This amplifies the photocurrent without substrate loss, thereby increasing the photocurrent converted by the logarithmic transistor circuit. Compared with existing technologies that directly convert the photocurrent generated by the PD, this improves the contrast sensitivity of the IV conversion circuit and enhances the imaging performance of the dynamic vision sensor. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the structure of an existing dynamic vision sensor chip IV conversion circuit.

[0020] Figure 2 This is a structural schematic diagram of a specific embodiment of the present invention. Detailed Implementation

[0021] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0022] Reference Figure 2 The present invention includes a photodiode (PD), a photodiode clamping circuit, a current mirror, and a logarithmic transistor circuit.

[0023] A photodiode (PD) is used to receive light intensity and generate a photocurrent (I). PD The intensity of light is directly proportional to the magnitude of photocurrent;

[0024] The photodiode clamping circuit comprises a first PMOS transistor PM1, whose source is connected to power supply VDD, and whose gate is connected to its drain, the gate of a second PMOS transistor, and the drain of a first NMOS transistor NM1; a second PMOS transistor PM2, whose source is connected to power supply VDD, and whose drain is connected to the base of Q1 and the drain of the second NMOS transistor NM2; an NPN transistor Q1, whose emitter is connected to the emitter of Q2; a PNP transistor Q2, whose base is connected to the negative terminal of PD and the gate of the second NMOS transistor NM2, and whose collector is connected to ground AGND; and a first NMOS transistor NM1... The first NMOS transistor has a gate biased by a voltage Vbias and its source is connected to AGND. The second NMOS transistor, NM2, has its source connected to AGND. The gate of NM1 is biased by a voltage Vbias, which causes NM1 to generate a source-drain current. This current flows into NM2 through a current mirror composed of PM1 and PM2, making the gate voltage of NM2 approximately equal to Vbias. The source follower negative feedback structure composed of NM2, Q1, and Q2 stabilizes the gate voltage of NM2 at Vbias, ensuring that the PD operates in a stable reverse bias state. At the same time, Q2 can pre-amplify the photocurrent.

[0025] The current mirror includes a PMOS current mirror and an NMOS current mirror to amplify the photocurrent; the amplification factor and number of PMOS and NMOS current mirrors in the current mirror can be determined according to the actual situation.

[0026] The PMOS current mirror comprises four PMOS transistors: PM3 (third PMOS transistor), PM4 (gate and drain connected), PM5 (source connected), and PM4 (gate connected), with its source connected to VDD; PM4 (fourth PMOS transistor), PM4 (source connected to VDD), and PM6 (drain connected to the source of PM6); PM5 (fifth PMOS transistor), PM5 (drain connected to the collector of Q1); and a bias voltage Vb1 is applied to the gates of both PM5 and PM6. PM3 and PM4 amplify the photocurrent, while the cascode structure formed by PM5 and PM6 reduces noise and improves the accuracy of current amplification. PM3-PM6 must operate at a relatively high voltage, and the photocurrent pre-amplification of Q2 ensures the functionality of the PMOS current mirror.

[0027] The NMOS current mirror comprises four NMOS transistors. The drain of the third NMOS transistor, NM3, is connected to the drain of PM6, and its source is connected to the drain and gate of the fifth NMOS transistor, NM5, and the gate of the sixth NMOS transistor, NM6. The source of the fourth NMOS transistor, NM4, is connected to the drain of the sixth NMOS transistor, NM6. The source of the fifth NMOS transistor, NM5, is connected to AGND. The source of the sixth NMOS transistor, NM6, is also connected to AGND. A bias voltage Vb2 is applied to the gates of both the third NMOS transistor, NM3, and the fourth NMOS transistor, NM4. NM3 and NM4 are constructed using a deep N-well process, with the substrate and source connected to eliminate the influence of substrate leakage current on the magnification accuracy of the current mirror.

[0028] The logarithmic transistor circuit contains three PMOS transistors connected in a diode configuration. The seventh PMOS transistor, PM7, has its gate and drain connected to the source of the eighth PMOS transistor, PM8, and its source connected to VDD. The eighth PMOS transistor, PM8, has its gate and drain connected to the source of the ninth PMOS transistor, PM9. The ninth PMOS transistor, PM9, has its gate and drain connected to the drain of NM4 and serves as the output of the IV conversion circuit. A higher number of PMOS transistors and a smaller aspect ratio in the logarithmic transistor circuit result in a steeper IV conversion slope, lower contrast sensitivity of the dynamic vision sensor, and stronger imaging performance. However, a larger area also leads to higher noise. The design parameters of the logarithmic transistor circuit can be determined according to actual needs.

[0029] The working principle of this embodiment is as follows: a photodiode clamping circuit composed of two identical NMOS transistors NM1 and NM2, two identical PMOS transistors PM1 and PM2, and an NPN transistor Q1 and a PNP transistor Q2 clamps the voltage at the negative terminal of the photodiode PD at Vbias. When the voltage at the negative terminal of the PD is higher than Vbias, the negative feedback structure composed of NM2, Q1, and Q2 pulls the voltage at the negative terminal of the PD lower. When the voltage at the negative terminal of the PD is lower than Vbias, the negative feedback structure pulls the voltage at the negative terminal of the PD higher, ensuring that the PD operates under a stable reverse bias voltage. When ambient light shines on the PD, the PD generates a photocurrent I that is related to the light intensity. PD I PD The current flows out from the base of Q2, and utilizing the current characteristics of the transistor, a pre-amplified photocurrent I is obtained at the emitter of Q2. PD1 ;I PD1 I is obtained by stepwise amplification using a current mirror composed of a PMOS current mirror and an NMOS current mirror. PD2 The photocurrent I after two amplifications PD2 A logarithmic transistor circuit consisting of multiple PMOS transistors connected in series with diodes is used. The PMOS transistors operate in the subthreshold region. The subthreshold characteristic of the MOS transistors is used to realize the logarithmic conversion of the current on the MOS transistors to the gate-source voltage. At the output of the IV circuit, a photovoltage signal that is logarithmically amplified with respect to the photocurrent is obtained.

Claims

1. A dynamic vision sensor (IV) conversion circuit for realizing micro-current conversion, comprising a photodiode (PD), a photodiode clamping circuit and a log tube circuit; the photodiode (PD) is configured to receive light intensity to generate a photoelectric current (I PD ); the photodiode clamping circuit comprises two NMOS tubes and two PMOS tubes; the log tube circuit comprises a plurality of PMOS tubes in diode connection mode to realize logarithmic conversion of the photoelectric current to a photoelectric voltage; characterized in that, The photodiode clamping circuit further comprises NPN transistor Q1 and PNP transistor Q2 for realizing negative feedback control under tiny photoelectric current and pre-amplifying the photoelectric current; the IV conversion circuit further comprises current mirrors cascaded by at least one PMOS current mirror and one NMOS current mirror for amplifying the pre-amplified photoelectric current; The photodiode clamping circuit, wherein the first PMOS tube PM1 has its source connected to the power supply VDD, its gate connected to the drain of the second PMOS tube and the drain of the first NMOS tube NM1; the second PMOS tube PM2 has its source connected to the power supply VDD, its drain connected to the base of Q1 and the drain of the second NMOS tube NM2; the NPN transistor Q1 has its emitter connected to the emitter of Q2; the PNP transistor Q2 has its base connected to the negative terminal of PD and the gate of the second NMOS tube NM2, and its collector connected to the ground AGND; the first NMOS tube NM1 has its gate loaded with a bias voltage Vbias, and its source connected to AGND; the second NMOS tube NM2 has its source connected to AGND.

2. The dynamic vision sensor (DVS) conversion circuit for implementing micro-current conversion according to claim 1, wherein, The PMOS current mirror comprises four PMOS tubes; wherein the third PMOS tube PM3 has its gate and drain connected to the source of PM5 and the gate of PM4, and its source connected to VDD; the fourth PMOS tube PM4 has its source connected to VDD, and its drain connected to the source of PM6; the fifth PMOS tube PM5 has its drain connected to the collector of Q1; the gate of PM5 and the gate of PM6 are both loaded with a bias voltage Vb1.

3. The dynamic vision sensor (DVS) conversion circuit for implementing micro-current conversion according to claim 1, wherein, The NMOS current mirror comprises four NMOS tubes; wherein the third NMOS tube NM3 has its drain connected to the drain of PM6, and its source connected to the drain and gate of the fifth NMOS tube NM5 and the gate of the sixth NMOS tube NM6; the fourth NMOS tube NM4 has its source connected to the drain of the sixth NMOS tube NM6; the fifth NMOS tube NM5 has its source connected to AGND; the sixth NMOS tube NM6 has its source connected to AGND; the gate of NM3 and the gate of NM4 are both loaded with a bias voltage Vb2.

4. The dynamic vision sensor (DVS) conversion circuit for implementing micro-current conversion according to claim 3, wherein, The third NMOS tube NM3 and the fourth NMOS tube NM4 are deep N-well process devices, and their substrates are connected to the sources.

5. The dynamic vision sensor (DVS) conversion circuit for implementing micro-current conversion according to claim 1, wherein, The number of PMOS tubes in diode connection form contained in the logarithmic tube circuit is three, wherein the seventh PMOS tube PM7 has its gate and drain connected to the source of the eighth PMOS tube PM8, and its source connected to VDD; the eighth PMOS tube PM8 has its gate and drain connected to the source of the ninth PMOS tube PM9; the ninth PMOS tube PM9 has its gate and drain connected to the drain of NM4, and is the output terminal of the IV conversion circuit.

6. The dynamic vision sensor (DVS) conversion circuit for implementing micro-current conversion according to claim 5, wherein, The number of PMOS tubes in diode connection form contained in the logarithmic tube circuit is greater than three, so as to realize large logarithmic slope conversion of photoelectric current to photoelectric voltage.

7. The dynamic vision sensor (DVS) conversion circuit for implementing micro-current conversion according to claim 1, wherein, The PMOS current mirror and the NMOS current mirror in the current mirror are the same in number, and are used for realizing greater amplification multiple for the pre-amplified photoelectric current.

8. The dynamic vision sensor (DVS) conversion circuit for implementing micro-current conversion according to claim 1, wherein, The photoelectric diode clamping circuit pre-amplifies the photoelectric current through the PNP transistor Q2.

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