Voltage equalization for pillars of memory arrays

Abstract

The present application relates to voltage equalization for pillars of a memory array. In some examples, a memory array may be configured with conductive pillars that are each coupled to a respective group of memory cells and may be selectively coupled to an access line. To support dissipation or equalization of charge from unselected pillars, the memory array may be configured with a material layer or hierarchy that provides a dissipative coupling to a ground voltage or other voltage source, such as a coupling with a relatively high resistance or a degree of capacitance (e.g., to support passive equalization). Additionally or alternatively, a memory array may be configured to support active dissipation of accumulated charge or voltage by selectively coupling pillars that have been operating in a floating condition to a ground voltage or other voltage source (e.g., to perform dynamic equalization).

Description

[0001] Cross Reference

[0002] This patent application is a national phase application of International Patent Application No. PCT / US2021 / 072632, filed on November 30, 2021, entitled “VOLTAGE EQUALIZATION FOR PILLARS OF A MEMORY ARRAY” by Villa et al., which claims priority to U.S. Patent Application No. 17 / 116,893, filed on December 9, 2020, entitled “VOLTAGE EQUALIZATION FOR PILLARS OF A MEMORY ARRAY” by Villa et al., each of which is assigned to its assignee, and the entire contents of each of which are expressly incorporated herein by reference. Technical Field

[0003] The technical field relates to voltage equalization for pillars of a memory array. Background Art

[0004] Memory devices are widely used to store information in various electronic devices, such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell can be programmed to one of two supported states, typically represented by a logical 1 or a logical 0. In some examples, a single memory cell can support more than two states, either of which can be stored. To access stored information, a component can read or sense at least one stored state in a memory device. To store information, a component can write or program a state in a memory device.

[0005] There are various types of memory devices and memory cells, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self-select memory, chalcogenide memory technology, etc. Memory cells may be volatile or non-volatile. Summary of the invention

[0006] An apparatus is described. The apparatus may include an access line, a conductive pillar having a first end configured for coupling with the access line, and the conductive pillar having a second end opposite the first end of the conductive pillar, a memory cell coupled between the conductive pillar and a word line, and a layer adjacent to the second end of the conductive pillar, wherein the layer is configured to support voltage equalization between the conductive pillar and a ground node.

[0007] An apparatus is described. The apparatus may include an access line extending along a first direction; a conductive pillar extending along a second direction orthogonal to the first direction, the conductive pillar having a first end configured to be selectively coupled to the access line via a switching element and a second end opposite to the first end along the second direction; a memory cell coupled between the conductive pillar and a word line; a first layer in contact with the second end of the conductive pillar; and a second layer in contact with a first side of the first layer, the first side being opposite to a second side contacting the conductive pillar, wherein the first layer is configured to dissipate a voltage difference between the conductive pillar and the second layer.

[0008] A method is described. The method may include forming an access line extending along a first direction; forming a memory cell coupled between a conductive pillar and a word line; forming a conductive pillar extending along a second direction orthogonal to the first direction, the conductive pillar having a first end for coupling with the access line, and the conductive pillar having a second end opposite to the first end of the conductive pillar along the second direction; forming a first layer in contact with the second end of the conductive pillar; and forming a second layer adjacent to the first layer and opposite to the conductive pillar along the second direction, wherein the first layer is configured to dissipate a voltage difference between the conductive pillar and the second layer.

[0009] A method is described. The method may include selecting a memory cell coupled between a first conductive pillar and a word line for an access operation; accessing the memory cell as part of the access operation based at least in part on biasing the word line with a first voltage, biasing an access line with a second voltage, and coupling the first conductive pillar with the access line; and dissipating a voltage difference between a second conductive pillar and a ground node based at least in part on accessing the memory cell, wherein the dissipating includes transferring charge through a layer in contact with the first conductive pillar and the second conductive pillar.

[0010] An apparatus is described. The apparatus may include an access line; a first conductive pillar configured to couple with the access line; a first memory cell coupled between the first conductive pillar and a first word line; a second conductive pillar configured to couple with the access line; a second memory cell coupled between the second conductive pillar and a second word line; a first layer in contact with the first conductive pillar and in contact with the second conductive pillar; a second layer in contact with the first layer and opposite the first conductive pillar and the second conductive pillar; and a controller configured to cause the apparatus to: select the first memory cell for an access operation; access the first memory cell based at least in part on biasing the first word line with a first voltage and biasing the access line with a second voltage as part of the access operation; and dissipate a voltage difference between the second conductive pillar and a ground node based at least in part on accessing the first memory cell, wherein dissipating the voltage difference between the second conductive pillar and the ground node includes transferring charge between the second conductive pillar and the second layer via the first layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 An example of a memory array supporting voltage equalization for pillars of the memory array according to examples as disclosed herein is described.

[0012] Figures 2A to 2C An example of a memory array supporting voltage equalization for pillars of the memory array according to examples as disclosed herein is described.

[0013] Figure 3 An example of a memory array supporting voltage equalization for pillars of the memory array according to examples as disclosed herein is described.

[0014] Figure 4 A block diagram of a memory device supporting voltage equalization for a pillar of a memory array is shown according to examples as disclosed herein.

[0015] Figure 5 and 6 A flow chart is shown of a method of supporting voltage equalization for a pillar of a memory array according to examples as disclosed herein. DETAILED DESCRIPTION

[0016] In some memory arrays, some structures may be electrically floating or floating during various operations of the memory array, which may refer to a condition in which the structure is not or does not wish to be coupled or connected to a voltage source, or otherwise driven to a consistent or controlled voltage. For example, the structures of a memory device may float by selectively isolating the structures from a voltage source through transistors or other switching components. However, the floating structures of the memory array may have another coupling (e.g., indirect coupling, secondary coupling, weak coupling), such as capacitive coupling or leakage coupling that allows charge or voltage accumulation of the floating structures, and the voltage of the floating structures may therefore be indeterminate. In some examples, the indeterminate voltage of the floating structures may be associated with impaired performance of the memory array, such as by an accumulated voltage that causes a disturbance in the state stored by the memory cells.

[0017] Some memory arrays may implement chalcogenide memory cells that may be accessed or read by applying a read bias across a selected memory cell. In some examples, such as those involving thresholded memory cells, the logic state (e.g., logic 0 or logic 1) of a memory cell may be determined based on whether the memory cell is "thresholded" in the presence of a read bias, where thresholding may refer to a change in resistance state (e.g., a breakdown or collapse of resistance, an increase in current, or a transfer of charge) caused by the application of a read bias or other bias. In some examples, unselected thresholded memory cells may be expected to provide a degree of electrical isolation between adjacent structures, or otherwise be associated with a relatively high resistance. However, unselected thresholded memory cells may be associated with a degree of capacitive or leakage coupling that may allow charge or voltage to accumulate on floating memory array structures. In some cases, the voltage of a floating structure may reach a level associated with the inadvertent selection or thresholding of one or more thresholded memory cells coupled to the floating structure.

[0018] According to examples as disclosed herein, a memory array may be configured to support dissipation or equalization of charge or voltage of structures that are floating during operation of the memory array. In some examples, the memory array may be configured with conductive pillars that are each coupled to a respective group of memory cells and may be selectively coupled to or isolated from an access line (e.g., a sense line). To support dissipation or equalization of charge from unselected pillars, the memory array may be configured with a material layer or level that provides a dissipative coupling to a ground voltage or other voltage source, such as a coupling with a relatively high resistance or a degree of capacitance (e.g., resistive and capacitive impedances) (e.g., to support passive equalization). Additionally or alternatively, the memory array may be configured to support active dissipation of accumulated charge or voltage by selectively coupling pillars that have been operating in a floating condition to a ground voltage or other voltage source (e.g., to perform dynamic equalization). By implementing techniques according to examples as disclosed herein, a memory array can limit the range of voltage or charge levels of structures that float during operation of the memory array, as compared to other techniques, which can improve the operation of the memory array, such as improving read margins, improving data retention, or improving other aspects of memory array reliability, among other advantages.

[0019] First, in the reference Figures 1 to 3 Features of the present disclosure are described in the context of a memory die and related results described herein. These and other features of the present disclosure are described herein by reference to Figures 4 to 6 The described apparatus diagram and flow chart related to voltage equalization of pillars of a memory array are further illustrated and described with reference to the apparatus diagram and flow chart.

[0020] Figure 1 An example of a memory array 100 supporting voltage equalization for pillars of a memory array according to examples as disclosed herein is illustrated. In some examples, the memory array 100 may be referred to as a memory chip, a memory device, or an electronic memory apparatus. The memory array 100 is operable to provide a physical memory address / space that may be used or referenced by a system (e.g., a host device coupled to the memory array 100 or a host device coupled to a memory device including one or more memory arrays or dies).

[0021] The memory array 100 may include one or more memory cells 105, each of which may be programmed to store a different logic state (e.g., a programmed one of a set of two or more possible states). For example, the memory cells 105 may be operable to store one bit of information at a time (e.g., a logic 0 or a logic 1). In some examples, the memory cells 105 (e.g., multi-level memory cells 105) may be operable to store more than one bit of information at a time (e.g., logic 00, logic 01, logic 10, logic 11). In some examples, the memory cells 105 may be arranged in an array.

[0022] The memory cell 105 may store logic states using a configurable material, which may be referred to as a memory element, a storage element, a memory storage element, a material element, a material storage element, a material portion, or a polarity write material portion, etc. The configurable material of the memory cell 105 may refer to a chalcogenide-based storage component. For example, a chalcogenide storage element may be used in a phase change memory cell, a thresholding memory cell, or a self-selecting memory cell.

[0023] In some examples, the material of the memory cell 105 may include a chalcogenide material or other alloys including selenium (Se), tellurium (Te), arsenic (As), antimony (Sb), carbon (C), germanium (Ge), silicon (Si), or indium (IN), or various combinations thereof. In some examples, a chalcogenide material having primarily selenium (Se), arsenic (As), and germanium (Ge) may be referred to as a SAG alloy. In some examples, a SAG alloy may also include silicon (Si) and such a chalcogenide material may be referred to as a SiSAG alloy. In some examples, a SAG alloy may include silicon (Si) or indium (In), or a combination thereof, and such a chalcogenide material may be referred to as a SiSAG alloy or an InSAG alloy, respectively, or a combination thereof. In some examples, a chalcogenide glass may include additional elements, such as hydrogen (H), oxygen (O), nitrogen (N), chlorine (Cl), or fluorine (F), each in atomic or molecular form.

[0024] In some examples, the memory cell 105 may be an example of a phase change memory cell. In such examples, the material used in the memory cell 105 may be alloy based (such as the alloys listed above) and may be operated so as to undergo a phase change or change to a different physical state during normal operation of the memory cell 105. For example, the phase change memory cell 105 may have an amorphous state (e.g., a relatively disordered configuration of atoms) and a crystalline state (e.g., a relatively ordered configuration of atoms).

[0025] In some examples, such as for thresholded memory cells 105 or self-select memory cells 105, some or all of the set of logical states supported by the memory cell 105 may be associated with an amorphous state of the chalcogenide material (e.g., the material in a single state may be operable to store different logical states). In some examples, the storage element of the memory cell 105 may be an example of a self-select memory element. In such examples, the material used in the memory cell 105 may be alloy-based (e.g., the alloys listed above) and may be operated so as to undergo changes to different physical states during normal operation of the memory cell 105. For example, a self-select memory cell may have a high threshold voltage state and a low threshold voltage state. The high threshold voltage state may correspond to a first logical state (e.g., a reset state), and the low threshold voltage state may correspond to a second logical state (e.g., a set state).

[0026] During a programming operation (e.g., a write operation) of a self-selected memory cell 105, the polarity used for the write operation may affect (e.g., determine, set, program) a particular behavior or characteristic of the material of the memory cell 105, such as the threshold voltage of the material. The difference in the threshold voltage of the material of the memory cell 105 depending on the logical state stored by the material of the memory cell 105 (e.g., the difference between the threshold voltages when the material stores a logical state "0" versus a logical state "1") may correspond to a read window of the memory cell 105.

[0027] Memory array 100 may include access lines (e.g., row lines 110 and column lines 115) arranged in a pattern (e.g., a grid-like pattern). The access lines may be formed of one or more conductive materials. In some examples, row lines 110 or some portion thereof may be referred to as word lines. In some examples, column lines 115 or some portion thereof may be referred to as digit lines or bit lines. References to access lines, row lines, column lines, word lines, digit lines, or bit lines or the like may be interchangeable without loss of understanding or operation. Memory cells 105 may be positioned at the intersections of row lines 110 and column lines 115.

[0028] Operations (e.g., reading and writing) may be performed on the memory cells 105 by activating or selecting access lines (e.g., one or more of the row lines 110 and / or column lines 115). By biasing the row lines 110 and column lines 115 (e.g., applying a voltage to the row lines 110 or the column lines 115), a single memory cell 105 may be accessed at their intersections. The intersection of the row lines 110 and the column lines 115 in a two-dimensional or three-dimensional configuration may be referred to as the address of the memory cell 105. The access lines may be conductive lines coupled to the memory cells 105 and may be used to perform access operations on the memory cells 105. In some examples, the memory array 100 may perform operations in response to commands, which may be issued by a host device or may be generated by a memory device including the memory array 100.

[0029] Access to the memory cells 105 may be controlled by a row decoder 120 or a column decoder 125. For example, the row decoder 120 may receive a row address from the local memory controller 160 and activate the row lines 110 based on the received row address. The column decoder 125 may receive a column address from the local memory controller 160 and activate the column lines 115 based on the received column address.

[0030] The sensing component 130 is operable to detect the state of the memory cell 105 (e.g., material state, resistance, threshold state) and determine the logic state of the memory cell 105 based on the stored state. The sensing component 130 may include one or more sense amplifiers to amplify or otherwise convert the signal from accessing the memory cell 105. The sensing component 130 may compare the signal detected from the memory cell 105 with a reference 135 (e.g., a reference voltage). The detected logic state of the memory cell 105 may be provided as an output of the sensing component 130 (e.g., to the input / output 140), and the detected logic state may be indicated to another component of the memory device including the memory array 100.

[0031] The local memory controller 160 may control access to the memory cells 105 through various components (e.g., row decoder 120, column decoder 125, sensing component 130). In some examples, one or more of the row decoder 120, column decoder 125, and sensing component 130 may be co-located with the local memory controller 160. The local memory controller 160 may be operable to receive one or more of commands or data from one or more different memory controllers (e.g., an external memory controller associated with a host device, another controller associated with the memory array 100), translate the commands or data (or both) into information that can be used by the memory array 100, perform one or more operations on the memory array 100, and transfer data from the memory array 100 to the host device based on performing the one or more operations. The local memory controller 160 may generate row signals and column address signals to activate the target row lines 110 and the target column lines 115. The local memory controller 160 may also generate and control various voltages or currents used during the operation of the memory array 100. In general, the amplitude, shape, or duration of the applied voltages or currents discussed herein may vary and may be different for the various operations discussed in operating the memory array 100 .

[0032] The local memory controller 160 is operable to perform one or more access operations on one or more memory cells 105 of the memory array 100. Examples of access operations may include a write operation, a read operation, a refresh operation, a precharge operation, or an activate operation, among others. In some examples, the access operations may be performed or otherwise coordinated by the local memory controller 160 in response to various access commands (e.g., from a host device). The local memory controller 160 is operable to perform other access operations not listed herein or other operations related to the operation of the memory array 100 that are not directly related to accessing the memory cells 105.

[0033] In some examples, some structures of the memory array 100 may be electrically floating during various access operations, which may refer to a condition in which the structure is not or does not wish to be coupled or connected to a voltage source, or otherwise driven to a consistent or controlled voltage. For example, the structures of one or more row lines 110 or the structures of one or more column lines 115, or some portion thereof or combination thereof, may be floating by selectively isolating the structures from a voltage source by means of transistors or other switching elements. However, the floating structures of the memory array 100 may have another coupling (e.g., indirect coupling, secondary coupling, weak coupling), such as capacitive coupling or leakage coupling that allows charge or voltage accumulation of the floating structures, and the voltage of the floating structures may therefore be indeterminate. In some examples, the indeterminate voltage of the floating structures may be associated with impaired performance of the memory array 100.

[0034] According to examples as disclosed herein, the memory array 100 can be configured to support dissipation or equalization of charge or voltage of structures that are floating during various operations of the memory array 100. In some examples, an array of memory arrays 100 can be configured with conductive pillars that are each coupled to a respective group of memory cells 105 and can be selectively coupled to or isolated from access lines (e.g., row lines 100 or portions thereof, column lines 115 or portions thereof). To support dissipation or equalization of charge from unselected pillars, the array can be configured with a material layer or level that provides a dissipative coupling to a ground voltage or other voltage source, such as a coupling with a relatively high resistance or a degree of capacitance (e.g., resistive and capacitive impedances) (e.g., to support passive equalization). Additionally or alternatively, the memory array 100 can be configured to support active dissipation of accumulated charge or voltage by selectively coupling pillars that have been operated in a floating condition to a ground voltage or other voltage source (e.g., to perform dynamic equalization). By implementing techniques according to examples as disclosed herein, the range of voltage or charge levels of structures that float during operation of the memory array 100 can be relatively limited or reduced compared to other techniques, which can improve the operation of the memory array 100. For example, such dissipation or equalization techniques can support improved read margins, improved data retention, or improved other aspects of reliability, among other benefits.

[0035] Figures 2A to 2C An example of a memory array 200 supporting voltage equalization for pillars of a memory array according to examples as disclosed herein is illustrated. Memory array 200 may be included in memory array 100 and illustrates an example of a three-dimensional arrangement of memory cells 105 accessible by various access lines. Figure 2A The memory array 200 is described with respect to Figure 2B and 2C A top cross-sectional view of cutting plane AA (eg, section AA) is shown in FIG. Figure 2BThe memory array 200 is described with respect to Figure 2A ) is a side cross-sectional view of the cutting plane BB shown in FIG. Figure 2C The memory array 200 is described with respect to Figure 2A 200 (eg, section CC). The sectional view may be an example of a cross-sectional view of a memory array with aspects removed for clarity. The elements of memory array 200 may be described relative to the x-direction, the y-direction, and the z-direction, as shown in FIG. Figures 2A to 2C Although Figure 2A , 2B Some of the elements included in 2C are labeled with numerical indicators, while other corresponding elements are not labeled but are identical or will be understood to be similar, in an attempt to increase visibility and clarity of the features depicted. In addition, although a certain number of repeating elements are shown in the illustrative example of memory array 200, the techniques according to the examples as described herein are applicable to any number of such elements, or the ratio of the number of one repeating element to another.

[0036] In the example of memory array 200, memory cells 105 and word lines 205 may be distributed along the z-direction according to stack 230 (eg, as shown in FIG. 2 ). Figure 2B and 2C 2 (described in ), and the z-direction may be orthogonal to the substrate (not shown) of the memory array 200. Although the illustrative example of the memory array 200 includes four stacks 230, the memory array 200 according to the examples disclosed herein may include 64 stacks 230, 128 stacks 230, or any other number of stacks 230. The word lines 205 may be arranged in a comb-like structure with protrusions extending along the y-direction through alternating gaps between the pillars 220 (e.g., two word lines 205 per stack 230 according to odd word lines 205-a and even word lines 205-b). Each memory cell 105 may be addressed or accessed according to the intersection between the word line 205 and the pillar 220 (e.g., a conductive pillar extending along the z-direction, which may be orthogonal to the y-direction). For example, as illustrated, a selected memory cell 105-a of stack 230-c may be positioned between pillar 220-c-4 and word line 205-b-2 or accessed based on an intersection between pillar 220-c-4 and word line 205-b-2.

[0037] The memory cells 105 may each include a chalcogenide material, and in some examples, may be or include a thresholded memory cell or a thresholded chalcogenide storage element. The memory cells 105 may be read by applying a read bias across the memory cells 105, and the logic state of the memory cells 105 may be determined based on whether the memory cells 105 are thresholded in the presence of the applied read bias. In an example of the memory array 200, the memory cells 105 may be read with a voltage having a magnitude of 2*V (e.g., as a voltage or bias applied across the memory cells 105), and this voltage may cause the memory cells 105 storing a first logic state (e.g., logic 0) to be thresholded, and may not cause the memory cells 105 storing a second logic state (e.g., logic 1) to be thresholded. In an example of the memory array 200, the read bias may be applied by biasing the selected word line 205 with a positive voltage (e.g., +V) and biasing the selected pillars 220 with a negative voltage (e.g., -V). With respect to the selected memory cell 105-a, a read bias voltage of +V may be applied to word line 205-b-2, while other unselected word lines may be grounded (eg, biased to 0V). In some examples, word line 205 or some portion thereof may be a reference Figure 1 The examples of row lines 110 described and the selection or biasing of word lines 205 may be performed or supported by row decoder 120 .

[0038] In order to apply a corresponding read bias voltage to the pillar 220, the pillar 220 can be configured to selectively couple with the sense line 215 (e.g., an access line extending along the y direction) via a corresponding transistor 225 (e.g., a thin film transistor). Thus, a selected pillar 220 or a combination of a selected pillar 220 and a selected sense line 215 can be a reference Figure 1 1 and 2. An example of a selected column line 115 (e.g., a bit line) is described. Transistor 225 can be activated by a pillar line 210 (e.g., extending along an x-direction, which can be orthogonal to the y-direction or z-direction) coupled to the gate of transistor 225. In other words, each pillar 220 can have a first end (e.g., a bottom end facing the negative z-direction) that is configured to couple (e.g., selectively couple) a sense line 215 (e.g., an access line). In some examples, pillar lines 210 and transistor 225 can be considered components of column decoder 125 (e.g., as pillar decoder components). Selection or biasing of pillars 220, sense lines 215, or pillar lines 210, or various combinations thereof, can be performed or supported by column decoder 125, sensing component 130, or both.

[0039] To apply a read bias voltage -V to pillar 220-c-4, sense line 215-d may be biased with the read bias voltage -V, and pillar line 210-c may be grounded (e.g., biased to 0V) or biased to some other voltage relatively higher than the read bias voltage -V. In an example where transistor 225 is an n-type transistor, biasing pillar line 210-c with a voltage relatively higher than sense line 215-d may activate transistor 225-a (e.g., causing transistor 225-a to operate in a conductive state), thereby coupling pillar 220-c-4 with sense line 215-d and biasing pillar 220-c-4 with the associated read voltage -V. When transistor 225-a is activated, the other pillars 220 of the memory array 200 may be electrically floating. For example, applying a ground voltage to pillar line 210-c may not activate other transistors coupled to pillar line 210-c because the ground voltage of pillar line 210-c may not be greater than the voltage of other sense lines 215 (e.g., which may be biased with a ground voltage or may float). In addition, a negative voltage (e.g., -V, or some other negative bias voltage or bias voltage that is relatively close to or lower than a negative read voltage) may be applied to a transistor including a sense line 215. Figure 2B 210-e shown in the figure, so that the transistors 225 along the unselected pillar lines 210 are not activated. Therefore, even the transistor 225-b coupled to the pillar line 210-e can be deactivated (e.g., operated in a non-conductive state), thereby selectively isolating the negative voltage of the sense line 215-d from the pillars 220-a-4 and other pillars 220.

[0040] In some examples, the floating pillars 220 may be charged due to leakage, capacitive coupling (e.g., with the word line 205), or other reasons. For example, activation or biasing of the selected word line 205-b-2 may cause a voltage drift of the unselected pillars 220 (e.g., in addition to the pillars 220-c-4) due to charge leakage through the unselected memory cells 105, or due to capacitive coupling supported between the word line 205-b-2 and the floating pillars 220 by the unselected memory cells 105, as well as other reasons. In some examples, such perturbations of the floating pillars 220 may accumulate over time or with the continuous activation of one or more word lines 205. The voltage drift of the unselected pillars 220 may cause the voltage level across the unselected memory cells 105 to change (e.g., increase), which in some examples may cause unintentional thresholding of the unselected memory cells 105. Such effects may be associated with a reduction in read margin when reading a selected memory cell 105, or a disturbance to the stored logic state of the memory cell 105, or other degraded performance of the memory array 200. Thus, according to examples as disclosed herein, the memory array 200 may be configured with various techniques for managing the charge or voltage of the unselected pillars 220.

[0041] Figure 3 An example of a memory array 300 that supports voltage equalization for pillars of a memory array according to examples as disclosed herein is illustrated. The memory array 300 may be a reference Figure 3 An example of aspects of a memory array 200 is described, including an arrangement of word lines 205 (e.g., odd word lines 205-c and even word lines 205-d), pillars 220 (e.g., unselected pillars 220-f-1 and selected pillars 220-f-2), and memory cells 105 (e.g., selected memory cells 105-b and unselected memory cells 105). Pillar 220-f-1 can have a first end configured for coupling with sense line 215-e via transistor 225-e (e.g., a first end configured to selectively couple with sense line 215-e), which can be activated by pillar line 210-e. Pillar 220-f-2 can have a first end configured for coupling with sense line 215-f via transistor 225-f, which can also be activated by pillar line 210-e. Each of transistors 225 can be coupled to a respective pillar 220 via a respective electrode 305 (e.g., contact, electrical contact), such as electrodes 305-a and 305-b, which can be an electrical contact formed for the purpose of electrically coupling the respective components. Aspects of memory array 300 can be described with reference to the x-direction, the y-direction, and the z-direction, and some elements of memory array 300 can be arranged according to stack 230 (e.g., distributed along the z-direction). In some cases, Figure 3 The memory array 200 is described with respect to Figure 2A ) is a side cross-sectional view of the cutting plane BB shown in FIG.

[0042] When the memory cell 105-b is selected (e.g., for a read operation, for a write operation, or for another type of access operation), the pillar 220-f-1 can be electrically floating. For example, the floating of the pillar 220-f-1 can be based at least in part on the deactivation of the transistor 225-e. In other examples, the floating of the pillar 220 can be based at least in part on the deactivation of the corresponding transistor 225, the floating of the corresponding sense line 215, or a combination thereof. However, the floating pillar 220-f-1 can be coupled to one or more other structures that allow charge or voltage accumulation of the floating pillar 220-f-1 (e.g., via indirect coupling, secondary coupling, weak coupling). For example, the pillar 220-f-1 can be coupled via one or more word lines 205 via one or more unselected memory cells 105, which can support capacitive coupling (e.g., as illustrated), charge leakage coupling, or other coupling that can cause voltage drift or otherwise indeterminate in the absence of a dissipative structure or operation of the pillar 220-f-1. In one example, this drift may be related to activation of word line 205-c-4 (e.g., an odd word line 205 having a comb configuration) and coupling between word line 205-c-4 and pillar 220-f-1 via stack 230-h of unselected memory cells 105. In some cases, the voltage of floating pillar 220-f-1 may reach a level associated with unintentional selection or thresholding of one or more memory cells 105 contacting floating pillar 220-f-1. Although described with reference to an electrically floating pillar 220-f-1 adjacent to a selected pillar 220-f-2 (e.g., along the x-direction), the described phenomena and techniques may be applicable to other pillars 220 (not shown), including other unselected pillars along the x-direction (e.g., sharing a common pillar line 210-e with the selected pillar 220-f-2 and an unselected pillar 220-f-1 or sharing a common pillar line 210-e along different pillar lines 210), or along the y-direction (e.g., sharing a common sensing line 215 with the selected pillar 220-f-2 or an unselected pillar 220-f-1 or sharing a common sensing line 215 along different sensing lines 215).

[0043] According to examples as disclosed herein, the memory array 300 can be configured to support dissipation or equalization of the charge or voltage of the floating pillars 220 during operation of the memory array 200. By implementing such techniques, the memory array 300 can limit the range of voltage or charge levels of the floating pillars 220, which can improve the operation of the memory array 300, such as improving read margins, improving data retention, or improving other aspects of operational reliability, among other advantages.

[0044] In some examples supporting the described techniques, the memory array 300 can be configured with material layers or levels that provide dissipative coupling to a ground voltage or other voltage source (e.g., to support passive equalization), such as coupling with a relatively high resistance or a degree of capacitance (e.g., resistive and capacitive impedance). For example, the memory array 300 can include a first layer 310 adjacent to (e.g., in contact with, directly adjacent to) pillars 220 (e.g., pillars 220-f-1 and 220-f-2, and other pillars 220 of the memory array 300 along the x-direction or y-direction as described but not illustrated). In some examples, the first layer 310 can be an example of a high resistance layer, and can be formed of an oxide material (e.g., a thin oxide material). The contact between the first layer 310 and the pillars 220 can be at respective ends of the pillars 220 along the z-direction, opposite to the corresponding transistors 225 or electrodes 305.

[0045] The memory array 300 may also include a second layer 320 adjacent to (e.g., in contact with) the first layer 310 (e.g., in contact with the first layer 310 on a side opposite to the side in contact with the pillars 220). In some examples, the second layer 320 may be a metal layer, such as a layer of tungsten, graphene, aluminum oxide, tin, titanium nitride, or some other material or combination thereof. The second layer 320 may be coupled or connected to a ground voltage source, or some other reference voltage source or an equalizing voltage source. The coupling of the second layer 320 to ground or other voltage sources may or may not include a selectable coupling (e.g., may or may not be coupling via a switching component such as a transistor). The first layer 310 may be configured to support dissipative coupling with the second layer 320, such as to dissipate or equalize a voltage difference between one or more pillars 220 and the second layer 320 (e.g., when the pillars 220 are electrically floating or selectively isolated from the sense line 215).

[0046] In various examples, the first layer 310 may be configured for a resistive impedance between the pillar 220 and the second layer 320, for a capacitive impedance between the pillar 220 and the second layer 320, or for a combination of resistive and capacitive impedances (e.g., a resistor-capacitor (RC) impedance) between the pillar 220 and the second layer 320. In some examples, this configuration may be interpreted as a set of parallel impedances (e.g., an RC distributed circuit) between the second layer 320 and the pillar 220. For example, the first layer 310 may be associated with a first impedance 315-a between the pillar 220-f-1 and the second layer 320, a second impedance 315-b between the pillar 220-f-2 and the second layer 320, and so on.

[0047] In some examples, the resistance level of impedance 315 can be configured with a relationship to the resistance level of memory cell 105. For example, the resistance level of impedance 315 can be higher than the resistance level of memory cell 105 (e.g., higher than the resistance level of thresholded memory cell 105, higher than the resistance level of unthresholded memory cell 105), such as the resistance of impedance 315 being in the gigaohm range. In some examples, configuring first layer 310 with a high resistance can limit the effect of dissipation on a read operation. For example, leakage charge or current can be maintained at a level below the charge transfer or current associated with detecting the logical state of memory cell 105 (e.g., for an assumed amount of voltage drift of unselected pillars 220, the dissipation current can be configured to be approximately 5 nanoamps, which can be one or more orders of magnitude less than the read current used to detect the state of selected memory cell 105-b).

[0048] In some examples, depending on various goals for balancing charge dynamics between dissipation operations and access operations, the first layer 310 can be configured for a time constant of the voltage difference between the dissipation pillar 220 and the second layer 320 that is related to the duration of performing an access operation of the memory array 300. In some examples, the impedance 315 can be configured with a time constant that is shorter than the duration for reading the memory cell 105, or shorter than the duration for programming the memory cell 105, or shorter than both the duration for reading the memory cell 105 and the duration for programming the memory cell 105. For example, a programming operation can have a duration of approximately 50 nanoseconds, and the dissipation time constant across the first layer 310 (e.g., via the impedance 315) can be on the order of tenths of a nanosecond (e.g., two orders of magnitude shorter than the programming operation). In some examples, this configuration can be supported by a resistance of the impedance 315 on the order of gigaohms and a capacitance of the impedance 315 on the order of femtofarads. In some examples, this configuration can support relatively fast dissipation of leakage charge accumulation, as well as a relatively low probability of inadvertently thresholding unselected memory cells.

[0049] In some examples, the impedance 315 can be configured with a time constant that is longer than a duration for reading the memory cell 105, or longer than a duration for programming the memory cell 105, or longer than both a duration for reading the memory cell 105 and a duration for programming the memory cell 105. For example, a programming operation can have a duration of approximately 50 nanoseconds, and the dissipation time constant across the first layer 310 (e.g., via the impedance 315) can be greater than 50 nanoseconds (e.g., on the order of microseconds), or the dissipation time constant can be longer than or otherwise related to a configured duration between consecutive read operations, a configured duration between consecutive write operations, a configured duration between a read operation and a subsequent write operation, or some other configured duration between access operations. In some examples, such a dissipation duration or rate can be suitable for limiting or avoiding unintentional thresholding of non-selected memory cells, and can have other advantageous properties when compared to relatively faster dissipation. For example, a relatively high impedance 315 associated with a dissipation time constant longer than an access operation may support improved stability of various structures biasing the memory array 300 or may support relatively lower power consumption compared to a configuration having a relatively low impedance 315 associated with a relatively short time constant.

[0050] In some examples supporting the described techniques, the memory array 300 can be configured to support active dissipation of accumulated charge or voltage by selectively coupling the pillars 220 that have been operating in a floating condition to a ground voltage or other voltage source (e.g., to perform dynamic equalization, to perform hard grounding). For example, based at least in part on performing one or more access operations (e.g., access operations using the selected pillar 220-f-2), the memory array 300 can operate by selectively coupling one or more pillars 220 (e.g., unselected pillar 220-f-1, one or more other unselected pillars not shown, selected pillar 220-f-2) to corresponding sense lines 215 when the sense lines 215 are grounded (e.g., coupled to the same or different voltage source as the second layer 320). In various instances, this dynamic balancing may be performed after each access operation using the selected pillar 220, after each access operation of a type (e.g., after a read operation, after a write operation), after a configured number of access operations or a configured type of access operations, after a configured duration, or according to some other periodic or event-initiated criteria.

[0051] When manufacturing the memory array 300, various layers may be deposited or etched to produce the memory array 300. A substrate may be formed, and an electrode 305 may be formed through the substrate. Alternating layers of conductive material (e.g., material forming the word line 205) and insulating material (e.g., material between the word lines 205) are deposited to form a material stack. After forming the material stack, the cavity associated with the pillar 220 may be etched through the material stack until the substrate is exposed. In some cases, an isotropic etching process may be used to remove the conductive material, and thereby a cavity for receiving the material may be made to serve as a memory storage element. After forming the cavity for the pillar and the cavity for the memory storage element, the material for the memory storage element (e.g., a chalcogenide material) may be deposited in the cavity. After depositing the memory material, the cavity associated with the pillar 220 may be (again) etched to remove the memory material filling the cavity until the substrate is exposed. After etching the cavity for the pillar, a conductive material may be deposited into the cavity to form the pillar 220, so that the pillar 220 contacts the electrode 305 and the memory storage material. After forming the pillar, the first layer 310 may be deposited. After forming the first layer 310 , the second layer 320 may be deposited.

[0052] While some examples of described techniques for charge dissipation are provided in the context of material pillars that may float during access operations, the described techniques may be applicable to other types of structures of a memory array, including other examples of access lines or sub-features thereof. For example, configured dissipation paths according to the described techniques may be advantageously provided or implemented for any structure of a memory array that may float (e.g., selectively float, intermittently float), including such structures that are electrically connected or coupled to memory cells (e.g., thresholded memory cells), or other structures that may be unintentionally thresholded or selected based on the accumulation of leakage charge. Furthermore, while examples of leakage dissipation may be supported by coupling or connection to a ground voltage source, the techniques described herein may be supported by coupling or connection to other voltage sources having voltage levels other than ground (e.g., for dissipation of accumulated charge, for dissipation of accumulated voltage differences).

[0053] Figure 4 A block diagram 400 is shown of a memory device 405 that supports voltage equalization for pillars of a memory array according to examples as disclosed herein. The memory device 405 may be a memory device as described in reference to Figures 1 to 3 Memory device 405 may include a memory array 410 (e.g., including a set of memory cells), a cell selection component 415, an access operation component 420, a bias component 425, a pillar selection component 430, and a pillar charge dissipation component 435. Each of these modules may communicate directly or indirectly with each other (e.g., via one or more buses).

[0054] Memory array 410 may include various arrangements of memory cells, including reference Figures 1 to 3 4. The memory array 410 may include a plurality of memory cells configured to be selected for various access operations (e.g., read operations, write operations). In some cases, the memory cells of the memory array 410 may each include a chalcogenide storage element, such as a thresholded chalcogenide storage element. In some examples, the memory cells of the memory array 410 may be coupled between various access lines of the memory array 410 and conductive pillars (e.g., as described in reference to Figures 2A to 3 described).

[0055] The cell selection component 415 may select a memory cell (e.g., a memory cell of the memory array 410) coupled between a first conductive pillar and a word line for an access operation. In some instances, the cell selection component 415 may select a second memory cell coupled between a second conductive pillar and a second word line for a second access operation. In various instances, the cell selection component 415 may select a memory cell based on an access command (e.g., as received from a host device), or based on an internal memory management operation (e.g., as determined by a component of the memory device 405 (e.g., a device memory controller or a local memory controller 160), or based on some other operation. In various instances, the cell selection component 415 may be a component of a device memory controller, or a component of a local memory controller 160, or may otherwise communicate with such a controller.

[0056] The access operation component 420 can access the selected memory cell as part of an access operation based on biasing the word line with a first voltage (e.g., using bias component 425), biasing an access line (e.g., a sense line) with a second voltage (e.g., using bias component 425), and coupling the first conductive pillar with the access line (e.g., using pillar selection component 430). In some examples, the access operation component 420 can access the second memory cell as part of a second access operation based on biasing the second word line with the first voltage, biasing the access line with the second voltage, and coupling the second conductive pillar with the access line. In various examples, the access operation component 420 can be a component of a device memory controller, or a component of a local memory controller 160, or can otherwise communicate with such a controller.

[0057] The pillar charge dissipation component 435 can dissipate a voltage difference between a conductive pillar and a ground node (e.g., based on accessing a memory cell). In some examples, the pillar charge dissipation component 435 can support dissipation by transferring charge through a layer in contact with one or more conductive pillars (e.g., a first conductive pillar, a second conductive pillar) of the memory array 410 (e.g., where the pillar charge dissipation component 435 or a portion thereof includes such a layer). In some examples, the pillar selection component 430 can selectively isolate one or more conductive pillars (e.g., a first conductive pillar, a second conductive pillar) from an access line during accessing a memory cell, and the pillar charge dissipation component 435 can support dissipation of a voltage difference between the selectively isolated conductive pillar and a ground node based on or during the selective isolation.

[0058] In some examples, to support dissipation by pillar charge dissipation component 435 (e.g., in active or selective dissipation), bias component 425 may couple the access line to a ground node, and pillar selection component 430 may selectively couple the second conductive pillar to the access line when the access line is coupled to the ground node. Thus, in some examples, pillar charge dissipation component 435 may include a logic component coupled to bias component 425, pillar selection component 430, or both. Thus, in some examples, at least a portion of pillar charge dissipation component 435 may refer to a component of a device memory controller, or a component of local memory controller 160, or may otherwise communicate with such a controller.

[0059] Figure 5 A flow chart showing a method or methods 500 of supporting voltage equalization for pillars of a memory array according to examples as disclosed herein. The operations of the method 500 may be implemented by a memory device or components thereof as described herein (e.g., by a controller and other components of the memory device). For example, the operations of the method 500 may be implemented by a memory device as described herein. Figure 4 The method 500 may be performed by a memory device described herein. Additionally or alternatively, aspects of the method 500 may be implemented as instructions stored in a memory (e.g., firmware stored in a memory coupled to or otherwise included in the memory device). For example, when executed by a controller of the memory device, the instructions may cause the controller to perform the operations of the method 500. In some examples, the memory device may execute a set of instructions to control functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory device may use dedicated hardware to perform aspects of the described functions.

[0060] At 505, method 500 may include selecting a memory cell coupled between a first conductive pillar and a word line for an access operation. The operation of 505 may be performed according to the methods described herein. In some examples, aspects of the operation of 505 may be described by referring to Figure 4The unit selection component described is implemented.

[0061] At 510, method 500 may include accessing a memory cell as part of an access operation. In various examples, accessing may be based on one or more of: biasing a word line with a first voltage, biasing an access line (e.g., a sense line) with a second voltage, and coupling a first conductive pillar to the access line. The operations of 510 may be performed according to the methods described herein. In some examples, aspects of the operations of 510 may be described by reference to Figure 4 Describes the access operations performed by the component.

[0062] At 515, method 500 may include dissipating a voltage difference between the second conductive pillar and the ground node based on accessing the memory cell. In some examples, dissipating may include transferring charge through a layer in contact with the first conductive pillar and the second conductive pillar. The operations of 515 may be performed according to the methods described herein. In some examples, aspects of the operations of 515 may be described by reference to Figure 4 The described pillar charge dissipation assembly performs.

[0063] In some examples, an apparatus as described herein may perform a method or methods, such as method 500. The apparatus may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: selecting a memory cell coupled between a first conductive pillar and a word line for an access operation; accessing the memory cell as part of the access operation (e.g., based at least in part on one or more of: biasing the word line with a first voltage, biasing an access line (e.g., a sense line) with a second voltage, and coupling the first conductive pillar with the access line); and dissipating a voltage difference between the second conductive pillar and a ground node based on accessing the memory cell (e.g., including transferring charge via a layer in contact with the first conductive pillar and the second conductive pillar).

[0064] Some examples of the method 500 and apparatus described herein may further include operations, features, components, or instructions for selectively isolating the second conductive pillar from an access line during access to a memory cell; and dissipating a voltage difference between the second conductive pillar and a ground node may be based on selectively isolating the second conductive pillar from the access line.

[0065] Some instances of the method 500 and apparatus described herein may further include operations, features, components, or instructions for: selecting a second memory cell coupled between a second conductive pillar and a second word line for a second access operation; accessing the second memory cell as part of the second access operation based on biasing the second word line with a first voltage, biasing the access line with a second voltage, and coupling the second conductive pillar to the access line; and dissipating a voltage difference between the first conductive pillar and a ground node based on accessing the second memory cell, wherein the dissipation includes transferring a second charge through a layer.

[0066] In some examples of the method 500 and apparatus described herein, dissipating a voltage difference between a second conductive pillar and a ground node may include operations, features, means, or instructions for: coupling an access line with a ground node; and selectively coupling the second conductive pillar with the access line when the access line is coupled with the ground node.

[0067] Some examples of the method 500 and apparatus described herein may further include operations, features, components, or instructions for: selectively isolating a third conductive pillar from a second access line (e.g., a second sensing line) during access to a memory cell; and dissipating a voltage difference between the third conductive pillar and a ground node based on accessing the memory cell, wherein dissipating the voltage difference between the third conductive pillar and the ground node may include transferring a third charge via a layer in contact with the first conductive pillar, the second conductive pillar, and the third conductive pillar.

[0068]

[0066] In some examples of the methods 500 and apparatus described herein, the memory cell includes a thresholded chalcogenide storage element.

[0069] Figure 6 A flow chart showing a method or methods 600 of supporting voltage equalization for pillars of a memory array according to examples as disclosed herein. The operations of the method 600 may be implemented by a manufacturing system or one or more controllers associated with a manufacturing system. In some examples, the one or more controllers may execute a set of instructions to control functional elements of the manufacturing system to perform the described functions. Additionally or alternatively, the one or more controllers may perform aspects of the described functions using dedicated hardware.

[0070] At 605, method 600 may include forming an access line (eg, a sense line) extending along a first direction. The operation of 605 may be performed according to techniques described herein.

[0071] At 610, method 600 may include forming a memory cell coupled between a conductive pillar and a word line. The operations of 610 may be performed according to techniques described herein.

[0072] At 615, method 600 may include forming a conductive pillar extending along a second direction orthogonal to the first direction, the conductive pillar having a first end for coupling with the access line, and the conductive pillar having a second end opposite the first end of the conductive pillar along the second direction. The operation of 615 may be performed according to the techniques described herein.

[0073] At 620, method 600 may include forming a first layer in contact with the second end of the conductive pillar. The operation of 620 may be performed according to techniques described herein.

[0074] At 625, method 600 may include forming a second layer adjacent to the first layer along the second direction and opposite the conductive pillar, wherein the first layer is configured to dissipate a voltage difference between the conductive pillar and the second layer. The operation of 625 may be performed according to techniques described herein.

[0075] In some examples, an apparatus as described herein may perform a method or methods, such as method 600. The apparatus may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: forming an access line (e.g., a sense line) extending along a first direction; forming a memory cell coupled between a conductive pillar and a word line; forming a conductive pillar extending along a second direction orthogonal to the first direction, the conductive pillar having a first end for coupling with the access line, and the conductive pillar having a second end opposite the first end of the conductive pillar along the second direction; forming a first layer in contact with the second end of the conductive pillar; and forming a second layer adjacent to the first layer and opposite the conductive pillar, wherein the first layer is configured to dissipate a voltage difference between the conductive pillar and the second layer.

[0076] In some examples of the method 600 and apparatus described herein, forming a memory cell may include operations, features, means, or instructions for: forming an opening through an insulating material to expose a first dielectric layer, a conductive layer, and a second dielectric layer; and forming a chalcogenide component in the opening contacting the conductive layer, the first dielectric layer, and the second dielectric layer.

[0077] In some examples of methods 600 and apparatus described herein, forming a conductive pillar can include operations, features, means, or instructions for depositing a conductive material into the opening to form a first conductive pillar in contact with the memory cell. In some examples, this deposition can be performed after or before depositing the barrier material.

[0078] Some examples of method 600 and apparatus described herein may further include operations, features, means, or instructions for depositing a barrier layer into the openings prior to depositing the conductive material to form the conductive pillars.

[0079] Some examples of method 600 and apparatus described herein may further include operations, features, means, or instructions for forming a contact extending through the substrate and coupled to the switching component, wherein an opening is formed through the insulating material to expose the contact.

[0080] In some examples of the methods 600 and apparatus described herein, a conductive pillar can be formed over a contact.

[0081] In some examples of the methods 600 and apparatus described herein, forming the second layer may include operations, features, means, or instructions for depositing a layer of metal, tungsten, graphene, aluminum oxide, tin, titanium nitride, or a combination thereof in contact with the first layer.

[0082] In some examples of the method 600 and apparatus described herein, forming the first layer can include operations, features, means, or instructions for depositing an oxide layer in contact with the second end of the conductive support.

[0083] It should be noted that the methods described herein describe possible implementations, and that the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Furthermore, portions from two or more of the methods may be combined.

[0084] An apparatus is described. The apparatus may include an access line; a conductive pillar having a first end configured to couple with the access line, the conductive pillar having a second end opposite the first end of the conductive pillar; and a memory cell coupled between the conductive pillar and a word line. The apparatus may also include a layer adjacent to the second end of the conductive pillar, wherein the layer is configured to support voltage equalization between the conductive pillar and a ground node.

[0085] Some examples of the apparatus may further include: a second conductive pillar having a first end configured to couple with an access line, the second conductive pillar having a second end opposite the first end of the second conductive pillar; and a second memory cell coupled between the second conductive pillar and a second word line. In some examples, the layer may be configured to support voltage equalization between the second conductive pillar and a ground node. In some examples, the second word line is a word line.

[0086] In some examples of the apparatus, the first end of the conductive pillar can be configured for selective coupling with an access line via a switching component. In some examples, the layer can be configured to support equalization of a voltage between the conductive pillar and a ground node when the conductive pillar is selectively isolated from the access line via the switching component.

[0087] In some examples of the apparatus, the first end of the conductive pillar can be electrically connected to the access line.

[0088] In some examples of the apparatus, the layer can be configured for resistive and capacitive impedance between a ground node and a conductive pillar.

[0089] In some examples of the apparatus, the layer can be configured to equalize the voltage between the conductive pillar and the ground node with a time constant that is longer than a duration for programming the memory cell.

[0090] In some examples of the apparatus, the layer can be configured with a higher resistance than the memory cell.

[0091] In some examples of the apparatus, the memory cell can include a thresholded chalcogenide storage element.

[0092] Another apparatus is described. The apparatus may include: an access line extending along a first direction; a conductive pillar extending along a second direction orthogonal to the first direction, the conductive pillar having a first end configured to selectively couple with the access line via a switching element and a second end opposite to the first end along the second direction; and a memory cell coupled between the conductive pillar and a word line. The apparatus may further include a first layer in contact with the second end of the conductive pillar, and a second layer in contact with a first side of the first layer, the first side being opposite to the second side contacting the conductive pillar, wherein the first layer may be configured to dissipate a voltage difference between the conductive pillar and the second layer.

[0093] Some examples of the apparatus may further include: a second conductive pillar extending along a second direction, the second conductive pillar having a first end configured to be selectively coupled to an access line via a second switching component and a second end opposite to the first end along the second direction; and a second memory cell coupled between the second conductive pillar and a second word line. In some examples, the first layer may contact the second end of the second conductive pillar, and the first layer may be configured to dissipate a voltage difference between the second conductive pillar and the second layer.

[0094] In some examples of the apparatus, the first layer can be configured for resistive and capacitive impedance between the second layer and the conductive pillars.

[0095] In some examples of the apparatus, the first layer can be configured such that a time constant for dissipating a voltage difference between the conductive pillar and the second layer is longer than a duration for programming the memory cell.

[0096] In some examples of the apparatus, the second layer can be coupled to a ground voltage source.

[0097] In some examples of the apparatus, the first layer can be configured to dissipate a voltage difference between the conductive pillar and the second layer when the conductive pillar is selectively isolated from the access line via the switching component.

[0098] In some examples of the apparatus, the first layer can be configured with a higher resistance than the memory cell.

[0099] Some examples of the apparatus may further include: a second access line extending along the first direction; a third conductive pillar extending along the second direction, the third conductive pillar having a first end configured to be selectively coupled to the second access line via a third switching component, and a second end opposite to the first end along the second direction; and a third memory cell coupled between the third conductive pillar and the word line. In some examples, the first layer may contact the second end of the third conductive pillar, and the first layer may be configured to dissipate a voltage difference between the third conductive pillar and the second layer.

[0100] Some examples of the apparatus may further include a fourth memory cell coupled between the conductive pillar and a fourth word line, the fourth memory cell being separated from the memory cell in the second direction, and the fourth word line being separated from the word line in the second direction.

[0101] Some examples of the apparatus may further include a fifth memory cell coupled between the conductive pillar and the fifth word line, the fifth memory cell located on a side of the conductive pillar opposite the memory cell in a third direction that is orthogonal to the first direction and that is orthogonal to the second direction.

[0102] In some examples of the apparatus, the second layer can include metal, tungsten, graphene, aluminum oxide, tin, titanium nitride, or a combination thereof in contact with the first layer.

[0103] In some examples of the apparatus, the first layer can include an oxide layer in contact with the second end of the conductive support.

[0104] In some examples of the apparatus, the memory cell can include a thresholded chalcogenide storage element.

[0105] Another apparatus is described. The apparatus may include: an access line; a first conductive pillar configured for coupling with the access line; a first memory cell coupled between the first conductive pillar and a first word line; a second conductive pillar configured for coupling with the access line; and a second memory cell coupled between the second conductive pillar and the second word line. The apparatus may further include: a first layer in contact with the first conductive pillar and in contact with the second conductive pillar; and a second layer in contact with the first layer and opposite the first conductive pillar and the second conductive pillar. The apparatus may further include a controller configured to cause the apparatus to select the first memory cell for an access operation, access the first memory cell based at least in part on biasing the first word line with a first voltage and biasing the access line with a second voltage as part of the access operation, and dissipate a voltage difference between the second conductive pillar and a ground node based at least in part on accessing the first memory cell. In some examples, dissipating the voltage difference between the second conductive pillar and the ground node may include transferring charge between the second conductive pillar and the second layer via the first layer.

[0106] In some examples of the apparatus, the controller can be configured to cause the apparatus to select a second memory cell for a second access operation, access the second memory cell based at least in part on biasing the second word line with the first voltage and biasing the access line with the second voltage as part of the second access operation, and dissipate a voltage difference between the first conductive pillar and a ground node based at least in part on accessing the second memory cell. In some examples, dissipating the voltage difference between the first conductive pillar and the ground node can include transferring a second charge between the first conductive pillar and the second layer via the first layer.

[0107] In some examples of the apparatus, the controller may be configured to cause the apparatus to dissipate a voltage difference between the second conductive pillar and the ground node based at least in part on coupling the access line with the ground node and selectively coupling the second conductive pillar with the access line via a switching component when the access line is coupled with the ground node.

[0108] In some examples of the apparatus, the first memory cell and the second memory cell can include thresholded chalcogenide storage elements.

[0109] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, the signal may represent a signal bus, where the bus may have various bit widths.

[0110] The terms "electronic communication," "conductive contact," "connection," and "coupling" may refer to a relationship between components that supports a signal flow between the components. Components are considered to be in electronic communication with each other (or in conductive contact or connected or coupled to each other) if there is any conductive path between the components that can support a signal flow between the components at any time. At any given time, the conductive path between components that are in electronic communication with each other (or in conductive contact or connected or coupled to each other) may be open or closed based on the operation of the device that includes the connected components. The conductive path between the connected components may be a direct conductive path between the components or the conductive path between the connected components may be an indirect conductive path that may include an intermediate component, such as a switch, transistor, or other component. In some examples, the signal flow between the connected components may be interrupted for a period of time, for example, using one or more intermediate components, such as a switch or transistor.

[0111] The term "coupled" refers to a condition that moves from an open circuit relationship between components (where signals cannot currently be communicated between components via conductive paths) to a closed circuit relationship between components (where signals can be communicated between components via conductive paths). When a component (e.g., a controller) couples other components together, the components begin to change to allow signals to flow between the other components via conductive paths that previously did not allow signals to flow.

[0112] The term "isolation" refers to a relationship between components where a signal cannot currently flow between the components. Components are isolated from one another if an open circuit exists between them. For example, two components separated by a switch positioned between the components are isolated from one another when the switch is open. When a controller isolates two components, the controller creates a change that prevents the signal from flowing between the components using a conductive path that previously allowed the signal to flow.

[0113] As used herein, the term "layer" or "level" refers to a stratum or thin layer of a geometric structure (e.g., relative to a substrate). Each layer or level may have three dimensions (e.g., height, width, and depth) and may cover at least a portion of a surface. For example, a layer or level may be a three-dimensional structure in which two dimensions are larger than the third dimension (e.g., a thin film). A layer or level may include different elements, components, and / or materials. In some examples, a layer or level may be composed of two or more sub-layers or sub-levels.

[0114] As used herein, the term "electrode" may refer to an electrical conductor, and in some examples, may serve as an electrical contact to a memory cell or other component of a memory array. An electrode may include a trace, a wire, a conductive line, a conductive layer, or the like that provides an electrically conductive path between elements or components of a memory array.

[0115] The devices discussed herein, including memory arrays, may be formed on a semiconductor substrate such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other examples, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of a semiconductor material on another substrate. The conductivity of a substrate or a sub-region of a substrate may be controlled by doping with various chemical species, including but not limited to phosphorus, boron, or arsenic. Doping may be performed by ion implantation during the initial formation or growth of the substrate or by any other doping means.

[0116] The switching components or transistors discussed herein may represent field effect transistors (FETs) and include three-terminal devices including a source, a drain, and a gate. The terminals may be connected to other electronic components by conductive materials (e.g., metals). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., most carriers are electrons), then the FET may be referred to as an n-type FET. If the channel is p-type (i.e., most carriers are holes), then the FET may be referred to as a p-type FET. The channel may be terminated by an insulating gate oxide. Channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. When a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned on" or "activated". When a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned off" or "deactivated".

[0117] The descriptions set forth herein describe exemplary configurations in conjunction with the accompanying drawings and do not represent all examples that may be implemented or that may be within the scope of the claims. The term "exemplary" as used herein means "used as an example, instance, or illustration," rather than "preferred" or "superior to other examples." The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some examples, well-known structures and devices are shown in block diagram form to avoid making the concepts of the described examples unclear.

[0118] In the accompanying drawings, similar components or features may have the same reference label. In addition, various components of the same type may be distinguished by following the reference label with a dash and a second label that distinguishes the similar components. If only the first reference label is used in the specification, the description applies to any of the similar components with the same first reference label, regardless of the second reference label.

[0119] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0120] The various illustrative blocks and modules described in connection with the disclosure herein may be implemented or executed using a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0121] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on a computer-readable medium or transmitted via a computer-readable medium as one or more instructions or program codes. Other examples and implementations are within the scope of the present disclosure and the appended claims. For example, due to the nature of the software, the functions described herein may be implemented using software executed by a processor, hardware, firmware, hard wiring, or a combination of any of these. The features of the implementation functions may also be physically located at various locations, including portions that are distributed so that the functions are implemented at different physical locations. Moreover, as used herein (included in the claims), the "or" used in a list of items (e.g., a list of items starting with a phrase such as "at least one" or "one or more") indicates a list of inclusions, such that a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). In addition, as used herein, the phrase "based on" should not be interpreted as a reference to a closed set of conditions. For example, without departing from the scope of the present disclosure, the exemplary steps described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on."

[0122] The description herein is provided to enable one skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to one skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not intended to be limited to the examples and designs described herein, but should be in the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A memory device, comprising: Access line; a conductive pillar having a first end configured for coupling with the access line, the conductive pillar having a second end opposite the first end of the conductive pillar; a memory cell coupled between the conductive pillar and a word line; and A layer adjacent to the second end of the conductive pillar and configured with a higher resistance than the memory cell, wherein the layer is configured to support voltage equalization between the conductive pillar and a ground node.

2. The memory device of claim 1 , further comprising: a second conductive pillar having a first end configured to couple with the access line, and the second conductive pillar having a second end opposite the first end of the second conductive pillar; and a second memory cell coupled between the second conductive pillar and a second word line, Wherein the layer is configured to support voltage equalization between the second conductive pillar and the ground node.

3. The memory device of claim 2, wherein the second word line is the word line.

4. The memory device of claim 1, wherein the first end of the conductive pillar is configured for selective coupling with the access line via a switching component.

5. The memory device of claim 4, wherein the layer is configured to support equalization of a voltage between the conductive pillar and the ground node when the conductive pillar is selectively isolated from the access line via the switching component.

6. The memory device of claim 1, wherein: The first end of the conductive pillar is electrically connected to the access line.

7. The memory device of claim 1, wherein the layer is configured for resistive and capacitive impedance between the ground node and the conductive pillar.

8. The memory device of claim 1, wherein the layer is configured such that a time constant for equalizing the voltage between the conductive pillar and the ground node is longer than a duration for programming the memory cell.

9. The memory device of claim 1, wherein the memory cell comprises a thresholded chalcogenide storage element.

10. A memory device comprising: an access line extending along a first direction; a conductive pillar extending along a second direction orthogonal to the first direction, the conductive pillar having a first end configured to be selectively coupled to the access line via a switching element and a second end opposite to the first end along the second direction; a memory cell coupled between the conductive pillar and a word line; a first layer contacting the second end of the conductive pillar and configured to have a higher resistance than the memory cell; and A second layer contacts a first side of the first layer opposite the second side that contacts the conductive pillar, wherein the first layer is configured to dissipate a voltage difference between the conductive pillar and the second layer.

11. The memory device of claim 10, further comprising: a second conductive pillar extending along the second direction, the second conductive pillar having a first end configured to be selectively coupled to the access line via a second switching element and a second end opposite to the first end along the second direction; and a second memory cell coupled between the second conductive pillar and a second word line, The first layer is in contact with the second end of the second conductive pillar, and the first layer is configured to dissipate a voltage difference between the second conductive pillar and the second layer.

12. The memory device of claim 10, wherein the first layer is configured for resistive and capacitive impedance between the second layer and the conductive pillars.

13. The memory device of claim 10, wherein the first layer is configured such that a time constant for dissipating the voltage difference between the conductive pillar and the second layer is longer than a duration for programming the memory cell.

14. The memory device of claim 10, wherein the second layer is coupled to a ground voltage source.

15. The memory device of claim 10, wherein the first layer is configured to dissipate the voltage difference between the conductive pillar and the second layer when the conductive pillar is selectively isolated from the access line via the switching component.

16. The memory device of claim 10, further comprising: a second access line extending along the first direction; a third conductive pillar extending along the second direction, the third conductive pillar having a first end configured to be selectively coupled to the second access line via a third switching element and a second end opposite to the first end along the second direction; and a third memory cell coupled between the third conductive pillar and the word line, The first layer is in contact with the second end of the third conductive pillar, and the first layer is configured to dissipate a voltage difference between the third conductive pillar and the second layer.

17. The memory device of claim 10, further comprising: A fourth memory cell is coupled between the conductive pillar and a fourth word line, the fourth memory cell is separated from the memory cell in the second direction, and the fourth word line is separated from the word line in the second direction.

18. The memory device of claim 10, further comprising: A fifth memory cell is coupled between the conductive pillar and a fifth word line, the fifth memory cell being located on a side of the conductive pillar opposite to the memory cell in a third direction orthogonal to the first direction and to the second direction.

19. The memory device of claim 10, wherein the second layer comprises metal, graphene, aluminum oxide, titanium nitride, or a combination thereof in contact with the first layer.

20. The memory device of claim 19, wherein the metal comprises tungsten, tin, or a combination thereof.

21. The memory device of claim 10, wherein the first layer comprises an oxide layer in contact with the second end of the conductive pillar.

22. The memory device of claim 10, wherein the memory cell comprises a thresholded chalcogenide storage element.

23. A method for forming a memory, comprising: forming an access line extending along a first direction; forming a memory cell coupled between the conductive pillar and the word line; forming the conductive pillar extending along a second direction orthogonal to the first direction, the conductive pillar having a first end for coupling with the access line, and the conductive pillar having a second end opposite to the first end of the conductive pillar along the second direction; forming a first layer in contact with the second end of the conductive pillar and configured to have a higher resistance than the memory cell; and A second layer is formed adjacent to the first layer along the second direction and opposite the conductive pillar, wherein the first layer is configured to dissipate a voltage difference between the conductive pillar and the second layer.

24. The method of claim 23, wherein forming the memory cell comprises: forming an opening through the insulating material to expose the first dielectric layer, the conductive layer, and the second dielectric layer; and A chalcogenide component is formed in the opening contacting the conductive layer, the first dielectric layer, and the second dielectric layer.

25. The method of claim 24, wherein forming the conductive pillar comprises: A conductive material is deposited into the opening to form the conductive pillar in contact with the memory cell.

26. The method of claim 25, further comprising: A barrier layer is deposited into the opening prior to depositing the conductive material to form the conductive pillar.

27. The method of claim 24, further comprising: A contact is formed extending through the substrate and coupled to a switching element, wherein the forming exposes the contact through the opening of the insulating material.

28. The method of claim 27, wherein the conductive pillar is formed over the contact.

29. The method of claim 23, wherein forming the second layer comprises: A layer of metal, graphene, aluminum oxide, titanium nitride, or a combination thereof is deposited in contact with the first layer.

30. The method of claim 29, wherein the metal comprises tungsten, tin, or a combination thereof.

31. The method of claim 23, wherein forming the first layer comprises: An oxide layer is deposited in contact with the second end of the conductive pillar.

32. A method for memory operation, comprising: selecting a memory cell coupled between the first conductive pillar and the word line for an access operation; accessing the memory cell as part of the access operation based at least in part on biasing the word line with a first voltage, biasing an access line with a second voltage, and coupling the first conductive pillar with the access line; and A voltage difference between a second conductive pillar and a ground node is dissipated based at least in part on accessing the memory cell, wherein the dissipation includes transferring charge through a layer in contact with the first conductive pillar and the second conductive pillar, the layer being configured with a higher resistance than the memory cell.

33. The method of claim 32, further comprising: The second conductive pillar is selectively isolated from the access line during the accessing of the memory cell, wherein dissipating the voltage difference between the second conductive pillar and the ground node is based at least in part on selectively isolating the second conductive pillar from the access line.

34. The method of claim 32, further comprising: selecting a second memory cell coupled between the second conductive pillar and a second word line for a second access operation; accessing the second memory cell as part of the second access operation based at least in part on biasing the second word line with the first voltage, biasing the access line with the second voltage, and coupling the second conductive pillar with the access line; and A voltage difference between the first conductive pillar and the ground node is dissipated based at least in part on accessing the second memory cell, wherein the dissipation includes transferring a second charge through the layer.

35. The method of claim 32, wherein dissipating the voltage difference between the second conductive pillar and the ground node comprises: coupling the access line to the ground node; and The second conductive pillar is selectively coupled to the access line when the access line is coupled to the ground node.

36. The method of claim 32, further comprising: selectively isolating a third conductive pillar from a second access line during said accessing of said memory cell; and A voltage difference between the third conductive pillar and the ground node is dissipated based at least in part on accessing the memory cell, wherein dissipating the voltage difference between the third conductive pillar and the ground node includes transferring a third charge through the layer in contact with the first conductive pillar, the second conductive pillar, and the third conductive pillar.

37. The method of claim 32 wherein the memory cell comprises a thresholded chalcogenide storage element.

38. A memory device comprising: Access line; a first conductive pillar configured to couple with the access line; a first memory cell coupled between the first conductive pillar and a first word line; a second conductive pillar configured to couple with the access line; a second memory cell coupled between the second conductive pillar and a second word line; a first layer in contact with the first conductive pillar and in contact with the second conductive pillar, the first layer being configured to have a higher resistance than the first memory cell and the second memory cell; a second layer contacting the first layer and opposite to the first conductive pillar and the second conductive pillar; and A controller configured to cause the memory device to: selecting the first memory unit for an access operation; accessing the first memory cell as part of the access operation based at least in part on biasing the first word line with a first voltage and biasing the access line with a second voltage; and A voltage difference between the second conductive pillar and a ground node is dissipated based at least in part on accessing the first memory cell, wherein dissipating the voltage difference between the second conductive pillar and the ground node includes transferring charge between the second conductive pillar and the second layer via the first layer.

39. The memory device of claim 38, wherein the controller is configured to cause the memory device to: selecting the second memory unit for a second access operation; accessing the second memory cell as part of the second access operation based at least in part on biasing the second word line with the first voltage and biasing the access line with the second voltage; and A voltage difference between the first conductive pillar and the ground node is dissipated based at least in part on accessing the second memory cell, wherein dissipating the voltage difference between the first conductive pillar and the ground node includes transferring a second charge between the first conductive pillar and the second layer via the first layer.

40. The memory device of claim 38, wherein the controller is configured to cause the memory device to: The voltage difference between the second conductive pillar and the ground node is dissipated based at least in part on coupling the access line with the ground node and selectively coupling the second conductive pillar with the access line via a switching component when the access line is coupled with the ground node.

41. The memory device of claim 38, wherein the first memory cell and the second memory cell comprise thresholded chalcogenide storage elements.

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