A processing circuit for a float flowmeter transducer

Abstract

The application provides a processing circuit of a float flowmeter converter, a collection and amplification module collects and amplifies a signal voltage to obtain an amplified voltage; a bias collection module receives the amplified voltage, collects the amplified voltage to obtain a positive peak value of the amplified voltage and a negative peak value of the amplified voltage, performs proportional subtraction operation on the positive peak value and the negative peak value to obtain a bias value of the amplified voltage; an amplitude collection module receives the amplified voltage and the bias value, performs subtraction operation on the amplified voltage and the bias value to obtain a corrected amplified voltage, the corrected amplified voltage is the amplified voltage without bias, collects the corrected amplified voltage to obtain an amplitude of the corrected amplified voltage. The application processes the signal voltage related to the magnetic displacement of the float flowmeter, collects the bias value and the amplitude of the signal voltage, eliminates the bias value of the signal voltage, and obtains the accurate signal voltage amplitude and bias value, thereby improving the accuracy and precision of subsequent flow calculation.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of float flowmeter converter integrated circuit design, and particularly relates to a processing circuit of a float flowmeter converter. BACKGROUND

[0002] With the popularization and development of automatic instruments and devices, the float flowmeter plays an important role in various fields related to people's daily life such as metallurgy, power and agriculture. In the prior art, the circuit part of the float flowmeter converter is generally only responsible for signal acquisition, signal amplification and signal output, and the acquired signals are processed through software; the magnetic displacement of the fluid in the float flowmeter is acquired and output through a displacement magnetic sensor, and the signal is sampled and transmitted to a central processor for processing through an analog-to-digital conversion module, and the angle value is calculated through the related function of the signal voltage output by the displacement magnetic sensor bridge, the material constant and the temperature drift algorithm provided, and the corresponding flow value is obtained. The software calculation method directly ignores the bias of the signal voltage acquired by the displacement magnetic sensor, and the actual amplitude of the signal voltage output estimated through the voltage value acquired by the multimeter is inaccurate, so that the flow value calculated by the float flowmeter converter has deviation and low accuracy.

[0003] Therefore, when measuring the flow through the float flowmeter, how to acquire and eliminate the bias of the output signal voltage in the float flowmeter and accurately acquire the amplitude of the signal voltage is a technical problem to be solved at present. SUMMARY

[0004] In view of the above-mentioned shortcomings of the prior art, the present application provides a processing circuit of a float flowmeter converter, which acquires the signal voltage output by the displacement magnetic sensor and amplifies the signal voltage through hardware design to obtain an amplified voltage, acquires the bias of the amplified voltage and eliminates the bias, acquires the amplitude of the amplified voltage after eliminating the bias, so that the flow value calculated by the software calculation method of the float flowmeter converter is more accurate and precise.

[0005] To achieve the above-mentioned purposes and other related purposes, the technical solutions provided by the present application are as follows.

[0006] A processing circuit of a float flowmeter converter, comprising:

[0007] An acquisition and amplification module acquires a signal voltage and amplifies the signal voltage to obtain an amplified voltage, wherein the signal voltage is related to the magnetic displacement of the fluid in the float flowmeter;

[0008] A bias acquisition module receives the amplified voltage, acquires the amplified voltage to obtain a positive peak value of the amplified voltage and a negative peak value of the amplified voltage, and performs proportional subtraction operation on the positive peak value and the negative peak value to obtain the bias of the amplified voltage.

[0009] An amplitude acquisition module is connected to the amplified voltage and the bias value, and performs subtraction operation on the amplified voltage and the bias value to obtain a corrected amplified voltage, which is the amplified voltage without bias.

[0010] Optionally, the acquisition and amplification module comprises an acquisition unit and an amplification unit, the acquisition unit acquires the magnetic displacement of the fluid in the float flowmeter to obtain the signal voltage, and the amplification unit is connected to the signal voltage and amplifies the signal voltage to obtain the amplified voltage.

[0011] Optionally, the acquisition unit comprises a first chip, a first resistor and a first capacitor, a first ground end of the first chip and a second ground end of the first chip are connected to ground, a bridge end of the first chip is connected to one end of the first resistor, one end of the first resistor is connected to ground through the first capacitor in series, the other end of the first resistor is connected to a first power voltage, a positive output end and a negative output end of the first chip cooperate to output the signal voltage, and the signal voltage is a differential voltage.

[0012] Optionally, the amplification unit comprises a second chip, a second resistor, a third resistor and a fourth resistor, one end of the second resistor is connected to a non-inverting input end of the second chip, one end of the third resistor is connected to an inverting input end of the second chip, a positive power supply end of the second chip is connected to a second power voltage, a negative power supply end of the second chip is connected to a third power voltage, a ground end of the second chip is connected to ground, the second resistor gain end and the second resistor gain end of the second chip are connected in series through the fourth resistor, wherein the other end of the second resistor is a first input end of the amplification unit, the other end of the third resistor is a second input end of the amplification unit, and an output end of the second chip is an output end of the amplification unit.

[0013] Optionally, the bias acquisition module comprises an inverting unit, two detection units, two follower units and a proportional subtraction operation unit, the inverting unit is connected to the amplified voltage and inverts the amplified voltage to obtain a negative phase amplified voltage; the first detection unit is connected to the amplified voltage and acquires the amplitude of the amplified voltage to obtain a positive peak value of the first amplified voltage, the second detection unit is connected to the negative phase amplified voltage and acquires the amplitude of the negative phase amplified voltage to obtain a negative peak value of the first amplified voltage; the first follower unit isolates the positive peak value of the first amplified voltage to obtain a positive peak value of the second amplified voltage, the second follower unit isolates the negative peak value of the first amplified voltage to obtain a negative peak value of the second amplified voltage; the proportional subtraction operation unit performs proportional subtraction operation on the positive peak value of the second amplified voltage and the negative peak value of the second amplified voltage to obtain the bias value of the amplified voltage.

[0014] Optionally, the inverting unit comprises a fifth resistor, a sixth resistor, a seventh resistor and a first operational amplifier, the inverting input end of the first operational amplifier is connected to one end of the fifth resistor, the inverting input end of the first operational amplifier is also connected to one end of the seventh resistor, the other end of the seventh resistor is connected to the output end of the first operational amplifier, the same-phase input end of the first operational amplifier is connected to ground through the sixth resistor in series, the positive power supply end of the first operational amplifier is connected to the second power supply voltage, and the negative power supply end of the first operational amplifier is connected to the third power supply voltage, wherein the other end of the fifth resistor is the input end of the inverting unit, and the output end of the first operational amplifier is the output end of the inverting unit.

[0015] Optionally, the detection unit comprises a second operational amplifier, a diode, an eighth resistor and a second capacitor, the inverting input end of the second operational amplifier is connected to the cathode of the diode, the cathode of the diode is also connected to ground through the eighth resistor in series, the output end of the second operational amplifier is connected to the anode of the diode, the positive power supply end of the second operational amplifier is connected to the second power supply voltage, the ground end of the second operational amplifier is connected to ground, and the second capacitor is connected to the eighth resistor in parallel.

[0016] Optionally, the proportional subtraction operation unit comprises a third operational amplifier, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor and a third capacitor, one end of the ninth resistor is connected to the non-inverting input terminal of the third operational amplifier, the other end of the eleventh resistor is connected to the non-inverting input terminal of the third operational amplifier, one end of the third capacitor is connected to one end of the eleventh resistor, the other end of the third capacitor is connected to ground, the other end of the third capacitor is connected to the output terminal of the third operational amplifier, one end of the tenth resistor is connected to the inverting input terminal of the third operational amplifier, the inverting input terminal of the third operational amplifier is connected to the output terminal of the third operational amplifier through the twelfth resistor, wherein the other end of the ninth resistor is the first input terminal of the proportional subtraction operation unit, the other end of the tenth resistor is the second input terminal of the proportional subtraction operation unit, and the output terminal of the third operational amplifier is the output terminal of the proportional subtraction operation unit.

[0017] Optionally, the amplitude acquisition module comprises a bias elimination unit and a third detection unit, the bias elimination unit is connected to the amplified voltage and the bias value, and the bias elimination unit performs subtraction operation on the amplified voltage and the bias value to obtain the corrected amplified voltage, and the third detection unit performs amplitude acquisition on the corrected amplified voltage to obtain the amplitude of the corrected amplified voltage.

[0018] Optionally, the bias elimination unit comprises a fourth operational amplifier, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor and a sixteenth resistor, one end of the thirteenth resistor is connected to the inverting input terminal of the fourth operational amplifier, the inverting input terminal of the fourth operational amplifier is connected to the output terminal of the fourth operational amplifier through the fifteenth resistor, one end of the fourteenth resistor is connected to the non-inverting input terminal of the fourth operational amplifier, the non-inverting input terminal of the fourth operational amplifier is connected to ground through the sixteenth resistor, the positive power supply terminal of the fourth operational amplifier is connected to the second power supply voltage, and the negative power supply terminal of the fourth operational amplifier is connected to the third power supply voltage, wherein the other end of the thirteenth resistor is the first input terminal of the input terminal of the bias elimination unit, the other end of the fourteenth resistor is the second input terminal of the bias elimination unit, and the output terminal of the fourth operational amplifier is the output terminal of the bias elimination unit.

[0019] The processing circuit of the float flowmeter converter provided by the application collects and amplifies the signal voltage through the amplification module, and obtains an amplified voltage; the signal voltage is input to the bias collection module to collect the positive peak value of the amplified voltage and the negative peak value of the amplified voltage, and the positive peak value of the amplified voltage and the negative peak value of the amplified voltage are subjected to proportional subtraction operation to obtain the bias value of the amplified voltage; the amplitude collection module performs subtraction operation on the amplified voltage and the bias value to eliminate the bias value of the amplified voltage, and obtains the amplitude of the corrected amplified voltage, and the amplitude of the corrected amplified voltage is collected to obtain the amplitude of the corrected amplified voltage. The application processes the signal voltage related to the magnetic displacement of the float flowmeter through the hardware circuit, collects and eliminates the bias value of the related signal voltage, collects the amplitude of the related signal voltage with the corrected bias value, and obtains the bias value and the amplitude of the accurate signal voltage, thereby improving the accuracy and precision of the software flow calculation. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 A structural block diagram of the processing circuit of the float flowmeter converter in the application is shown;

[0021] Figure 2 A circuit schematic diagram of the amplification module in the application is shown;

[0022] Figure 3 A circuit schematic diagram of the bias collection module in the application is shown;

[0023] Figure 4 A circuit schematic diagram of the amplitude collection module in the application is shown;

[0024] Figure 5 A structural block diagram of the actual application of the processing circuit of the float flowmeter converter provided by the application is shown. DETAILED DESCRIPTION

[0025] The embodiments of the application will be described in detail below with specific reference to the drawings. Those skilled in the art can easily understand other advantages and effects of the application from the content disclosed in the specification. The application can also be implemented or applied in other different embodiments, and the details in the specification can be modified or changed in different ways without departing from the spirit of the application. It should be noted that the following examples and features in the examples can be combined with each other without conflict.

[0026] It should be noted that the diagrams provided in the following examples only schematically illustrate the basic concept of the application, and only the components related to the application are shown in the diagrams, not the number, shape and size of the components when actually implemented. The shapes, numbers and proportions of the components when actually implemented can be arbitrarily changed, and the layout pattern of the components can be more complex.

[0027] In the following description, numerous specific details are discussed in order to provide a thorough understanding of embodiments of the present application. However, those skilled in the relevant arts will recognize that the embodiments of the present application can be practiced without these specific details. In other instances, well-known structures and devices are not described in exhaustive detail in order to avoid obscuring the embodiments of the present application.

[0028] At present, the flow measurement of the float flowmeter generally uses anisotropic magnetic resistance sensors to measure the position of moving objects by changes in the magnetic field position of the sensor. The magnetic resistance sensor includes HMC1501, which collects the magnetic displacement of the float flowmeter through the magnetic resistance sensor HMC1501. The magnetic resistance sensor HMC1501 includes a Wheatstone bridge that senses the position within a range of ±45°. The output signal voltage (ΔV) of the bridge is a sine function with a direct current bias. The ideal case is shown in expression (1):

[0029] ΔV = -V s S sin 2θ (1)

[0030] Where ΔV is the output signal voltage, V s is the supply voltage; S is the material constant (12 mV / V); and θ is the magnetic field reference angle.

[0031] However, the output signal voltage (ΔV) of the bridge actually has a deviation value, as shown in expression (2):

[0032] ΔV = -V s S sin 2θ + b (2)

[0033] Where ΔV is the output signal voltage, V s is the supply voltage; S is the material constant (12 mV / V); θ is the magnetic field reference angle; and b is the bias value.

[0034] The inventor found that the traditional float flowmeter converter hardware part is only responsible for collecting and amplifying the output signal voltage and does not involve processing the signal voltage. The processing of the signal voltage is calculated through software, but the accuracy of the flow value calculated through software is poor because the signal voltage calculated through software ignores the bias of the signal voltage. The amplitude of the signal voltage calculated through the material constant and the supply voltage value has an error and cannot truly reflect the amplitude of the signal voltage, thereby making the flow value calculated by the software low in accuracy.

[0035] In order to solve the above problems, the processing circuit of the float flowmeter converter designed by the application can accurately collect the bias value and amplitude value of the signal voltage, collect and amplify the signal voltage through the collection and amplification module to obtain an amplified voltage, input the amplified voltage into the bias collection module to collect the amplified voltage to obtain the positive peak value of the amplified voltage and the negative peak value of the amplified voltage, perform proportional subtraction operation on the positive peak value of the amplified voltage and the negative peak value of the amplified voltage to obtain the bias value of the amplified voltage, input the amplified voltage and the bias value into the amplitude collection module to perform subtraction operation on the amplified voltage and the bias value to obtain a corrected amplified voltage, the corrected amplified voltage is the amplified voltage after the bias is eliminated, and the amplitude of the corrected amplified voltage is collected to obtain the amplitude of the amplified voltage.

[0036] As shown in Figure 1 , the application provides a processing circuit of a float flowmeter converter, which comprises:

[0037] a collection and amplification module, which collects a signal voltage V0 and amplifies the signal voltage V0 to obtain an amplified voltage V i , wherein the signal voltage V0 is related to the magnetic displacement of the fluid in the float flowmeter;

[0038] a bias collection module, which receives the amplified voltage V i , collects the amplified voltage V i , obtains the positive peak value V i_MAX of the amplified voltage and the negative peak value -V i_MAX of the amplified voltage, performs proportional subtraction operation on the positive peak value V i_MAX and the negative peak value -V i_MAX to obtain the bias value V i_offset of the amplified voltage;

[0039] an amplitude collection module, which receives the amplified voltage V i and the bias value V i_offset , performs subtraction operation on the amplified voltage V i and the bias value V i_offset to obtain a corrected amplified voltage V i-b , the corrected amplified voltage is the amplified voltage after the bias is eliminated, collects the corrected amplified voltage V i-b to obtain the amplitude V (i-b)MAX of the corrected amplified voltage.

[0040] In detail, as shown in Figure 2 , the collection and amplification module comprises a collection unit and an amplification unit, the collection unit collects the magnetic displacement of the fluid in the float flowmeter to obtain the signal voltage V0, and the amplification unit receives the signal voltage V0 and amplifies the signal voltage V0 to obtain the amplified voltage V i .

[0041] More specifically, as shown in Figure 2As shown, the acquisition unit includes a first chip U1, a first resistor R1, and a first capacitor C1. The first ground terminal and the second ground terminal of the first chip U1 are grounded. The bridge terminal of the first chip U1 is connected to one end of the first resistor R1. One end of the first resistor R1 is also grounded after passing through the first capacitor C1 in series. The other end of the first resistor R1 is connected to the first power supply voltage VCC1, which includes +5V. The positive and negative output terminals of the first chip U1 work together to output a signal voltage V0, which is a differential voltage. The signal voltage V0 output by the positive and negative output terminals of the first chip is the bridge voltage difference of the first chip U1, which is a sinusoidal function with DC bias.

[0042] More in detail, such as Figure 2 As shown, the amplification unit includes a second chip U2, a second resistor R2, a third resistor R3, and a fourth resistor R4. One end of the second resistor R2 is connected to the non-inverting input of the second chip U2, and one end of the third resistor R3 is connected to the inverting input of the second chip U2. The positive power supply terminal of the second chip U2 is connected to the second power supply voltage VCC2, which includes +15V, and the negative power supply terminal of the second chip U2 is connected to the third power supply voltage VCC3, which includes -15V. The ground terminal of the second chip U2 is grounded. The fourth resistor R4 is connected in series between the first and second resistor gain terminals of the second chip U2. The other end of the second resistor R2 is the first input terminal of the amplification unit, which is connected to the positive output terminal of the first chip. The other end of the third resistor R3 is the second input terminal of the amplification unit, which is connected to the negative output terminal of the first chip. The output terminal of the second chip U2 is the output terminal of the amplification unit, which outputs an amplified voltage V to the subsequent circuit. i .

[0043] In detail, such as Figure 3 As shown, the bias acquisition module includes an inverting unit, two detection units, two follower units, and a proportional subtraction operation unit. The inverting unit is connected to the amplified voltage V. i For the amplified voltage V i Inverting the voltage yields a negative-phase amplified voltage -V i The first detector unit is connected to the amplification voltage V. i For the amplified voltage V i Amplitude acquisition is performed to obtain the positive peak value V of the first amplified voltage. i1_MAX The second detector unit is connected to the negative phase amplification voltage -V i The amplitude of the negative phase amplified voltage is sampled to obtain the negative peak value -V of the first amplified voltage. i1_MAX The first follower unit corresponds to the positive peak value V of the first amplified voltage. i1_MAX Isolation is performed to obtain the positive peak value V of the second amplified voltage. i2_MAX, the second follower unit isolates the negative peak value -V i1_MAX of the second amplified voltage, and obtains the negative peak value -V i2_MAX of the second amplified voltage. i2_MAX The proportional subtraction operation unit performs proportional subtraction operation on the positive peak value V i2_MAX of the second amplified voltage and the negative peak value -V i_offset of the second amplified voltage, and obtains the bias value V i_MAX of the amplified voltage. i_MAX It is emphasized that the first follower unit and the second follower unit isolate the positive peak value V i_offset of the first amplified voltage and the negative peak value -V i2_MAX of the first amplified voltage, and obtain the direct current voltage, so as to reduce the error of the subsequent calculation of the bias value V i1_MAX of the amplified voltage, and thus V i2_MAX = V i1_MAX , -V i = -V i .

[0044] In more detail, as shown in FIG. 5, the inverting unit comprises a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, and a first operational amplifier U5. The inverting input terminal of the first operational amplifier U5 is connected to one end of the fifth resistor R5. The inverting input terminal of the first operational amplifier U5 is also connected to one end of the seventh resistor R7. The other end of the seventh resistor R7 is connected to the output terminal of the first operational amplifier U5. The non-inverting input terminal of the first operational amplifier U5 is connected to ground through the sixth resistor R6. The positive power supply terminal of the first operational amplifier U5 is connected to the second power supply voltage VCC2. The negative power supply terminal of the first operational amplifier U5 is connected to the third power supply voltage VCC3. The other end of the fifth resistor R5 is the input terminal of the inverting unit. The input terminal of the inverting unit is connected to the amplified voltage V i . The output terminal of the first operational amplifier U5 is the output terminal of the inverting unit. The output terminal of the inverting unit outputs the negative phase amplified voltage -V i1_MAX to the subsequent circuit.

[0045] In more detail, as shown in FIG. 6, the first detection unit comprises a second operational amplifier U3, a diode D1, an eighth resistor R8, and a second capacitor C2. The inverting input terminal of the second operational amplifier U3 is connected to the cathode of the diode D1. The cathode of the diode D1 is also connected to ground through the eighth resistor R8. The output terminal of the second operational amplifier U3 is connected to the anode of the diode D1. The positive power supply terminal of the second operational amplifier U3 is connected to the second power supply voltage VCC2. The ground terminal of the second operational amplifier U3 is connected to ground. The second capacitor C2 is connected in parallel with the eighth resistor R8. The non-inverting input terminal of the second operational amplifier U3 is the input terminal of the first detection unit. The input terminal of the first detection unit is connected to the amplified voltage V i1_MAX . The diode D1 is connected in parallel with the second capacitor C2 and the eighth resistor R8., the cathode of the diode is the output terminal of the first detecting unit, and the output terminal of the first detecting unit outputs the positive peak value V i1_MAX .

[0046] It is emphasized that the second detecting unit provided by the above embodiment belongs to the same concept as the first detecting unit provided by the above embodiment, and the specific connection mode of each electronic component has been described in detail in the first detecting unit, which will not be described here.

[0047] In more detail, as shown in Figure 3 , the first follower unit includes an operational amplifier U4, the inverting input terminal of the operational amplifier U4 is connected to the output terminal of the operational amplifier U4, the non-inverting input terminal of the operational amplifier U4 is connected to the positive peak value V i1_MAX of the first amplified voltage, and the output terminal of the operational amplifier U4 outputs the positive peak value V i2_MAX of the second amplified voltage to the subsequent circuit. Wherein the second follower unit provided by the above embodiment belongs to the same concept as the first follower unit provided by the above embodiment, and the specific connection mode of the operational amplifier U7 is the same as that of the operational amplifier U4 in the first follower unit.

[0048] In more detail, as shown in Figure 3 , the proportional subtraction operation unit includes a third operational amplifier U8, a ninth resistor R10, a tenth resistor R11, an eleventh resistor R12, a twelfth resistor R13, and a third capacitor C4. The non-inverting input terminal of the third operational amplifier U8 is connected to one end of the ninth resistor R10, and the non-inverting input terminal of the third operational amplifier U8 is also connected to the other end of the eleventh resistor R12. One end of the eleventh resistor R12 is connected to one end of the third capacitor C4, and the other end of the third capacitor C4 is connected to the ground. The other end of the third capacitor C4 is connected to the output terminal of the third operational amplifier U8. The inverting input terminal of the third operational amplifier U8 is connected to one end of the tenth resistor R11, and the inverting input terminal of the third operational amplifier U8 is also connected to the output terminal of the third operational amplifier U8 through the twelfth resistor R13. Wherein the other end of the ninth resistor R10 is the first input terminal of the proportional subtraction operation unit, the first input terminal of the proportional subtraction operation unit is connected to the positive peak value V i2_MAX of the second amplified voltage, the other end of the tenth resistor R11 is the second input terminal of the proportional subtraction operation unit, the second input terminal of the proportional subtraction operation unit is connected to the negative peak value -V i2_MAX of the second amplified voltage, and the output terminal of the third operational amplifier U8 is the output terminal of the proportional subtraction operation unit. The output terminal of the proportional subtraction operation unit outputs the bias value V i_offset of the amplified voltage to the subsequent circuit.

[0049] In detail, as shown in Figure 4As shown, the amplitude acquisition module includes an offset cancellation unit and a third detection unit. The offset cancellation unit is connected to the amplification voltage V. i and bias value V i_offset For the amplified voltage V i With bias value V i_offset Performing a subtraction operation yields the corrected amplification voltage V. i-b The third detection unit corrects the amplification voltage V. i-b Amplitude acquisition is performed to obtain the amplitude V of the corrected amplification voltage. (i-b)MAX .

[0050] More in detail, such as Figure 4 As shown, the bias cancellation unit includes a fourth operational amplifier U9, a thirteenth resistor R14, a fourteenth resistor R15, a fifteenth resistor R17, and a sixteenth resistor R16. The inverting input of the fourth operational amplifier U9 is connected to one end of the thirteenth resistor R14. The fifteenth resistor R17 is connected in series between the inverting input and the output of the fourth operational amplifier U9. The non-inverting input of the fourth operational amplifier U9 is connected to one end of the fourteenth resistor R15. The non-inverting input of the fourth operational amplifier U9 is grounded after passing through the sixteenth resistor R16. The positive power supply terminal of the fourth operational amplifier U9 is connected to the second power supply voltage VCC2, and the negative power supply terminal is connected to the third power supply voltage VCC3. The other end of the thirteenth resistor R14 is the first input terminal of the bias cancellation unit, and the first input terminal of the bias cancellation unit is connected to the bias value V of the amplified voltage. i_offset The other end of the fourteenth resistor R15 is the second input terminal of the bias cancellation unit, which is connected to the amplified voltage V. i The output of the fourth operational amplifier is the output of the bias cancellation unit, and the output of the bias cancellation unit outputs a corrected amplification voltage V to the subsequent stage circuit. i-b .

[0051] The operational amplifier provided in the above embodiments includes the ADA4084-2.

[0052] It should be emphasized that the third detection unit provided in the above embodiments is based on the same concept as the first detection unit provided in the above embodiments. The specific connection method of each electronic component has been described in detail in the first detection unit, and will not be repeated here.

[0053] More in detail, such as Figures 1-4 As shown, the specific principle of the processing circuit of the float flowmeter converter provided in this application is as follows:

[0054] Figure 1 The block diagram of the processing circuit of the float flowmeter converter clarifies the input-output relationship of the acquisition amplification module, the bias acquisition module, and the amplitude acquisition module.

[0055] 1), first, as shown in the acquisition unit by the first chip HMC1501 acquisition float flowmeter in the fluid magnetic displacement, get signal voltage V0, signal voltage V0 is a DC bias sine function, signal voltage V0 as shown in expression (3): Figure 2

[0056] V0=-Vs sin 2θ+b (3) s

[0057] Where V0 is the signal voltage, V s is the supply voltage; S is the material constant (12mV / V); θ is the magnetic field reference angle; b is the bias value.

[0058] As shown in the first input and second input of the amplification unit as shown in the signal voltage V0, in the amplification unit, the resistance value of the second resistor R2 is 10K, the resistance value of the third resistor R3 is 10K, the resistance value of the fourth resistor R4 is 4.94K, the second chip U2 includes AD8221AR chip, the amplification unit amplifies the signal voltage V0, and the amplified voltage V i , the amplified voltage is shown as expression (4): Figure 2 V i =(1+49.4 / R4)V o (4)

[0059] Where Vi is the amplified voltage; R4 is the fourth resistor, the resistance value is 4.94K, V0 is the signal voltage. So V i =11V0, the signal voltage V0 is amplified by 11 times by the amplification unit, and the amplified voltage Vi is obtained.

[0060] 2), second, as shown in the input of the first detection unit as shown in the amplified signal V i , the peak value of the amplified signal V i is collected, and the first amplified voltage positive peak V i1_MAX is obtained. The relationship between the first amplified voltage positive peak V i1_MAX and the amplified voltage V i is shown as expression (5):

[0061] Figure 3 V i1_MAX =MAX[V i ] (5)

[0062] Where V i1_MAX is the first amplified voltage positive peak; V i is the amplified voltage.

[0063]

[0064] ​​​​The first follower unit is connected to the positive peak value V i1_MAX The isolation is carried out to obtain the positive peak value V i2_MAX of the second amplification voltage i2_MAX The positive peak value V i1_MAX of the first amplification voltage i2_MAX The relationship is shown in expression (6):

[0065] V i1_MAX (6)

[0066] Wherein, V i1_MAX is the positive peak value of the first amplification voltage; V i2_MAX is the positive peak value of the second amplification voltage.

[0067] The input end of the inverting unit is connected to the amplification signal V i The inverting calculation is carried out on the amplification signal V i to obtain the negative phase amplification voltage-V i The relationship between the negative phase amplification voltage-V i and the amplification signal V i is shown in expression (7):

[0068]

[0069] Wherein, -V i is the negative phase amplification voltage; R7 is the seventh resistance; R5 is the fifth resistance; V i is the amplification voltage.

[0070] The input end of the second detection unit is connected to the inverting amplification signal-V i The peak value collection is carried out on the inverting amplification signal-V i to obtain the negative peak value-V i1_MAX of the first amplification voltage, and the relationship between the negative peak value-V i1_MAX of the first amplification voltage and the negative phase amplification voltage-V i is shown in expression (8):

[0071] -V i1_MAX =MAX[-V i ] (8)

[0072] Wherein, -V i1_MAX is the negative peak value of the first amplification voltage; -V i is the negative phase amplification voltage.

[0073] The second follower unit is connected to the negative peak value-V i1_MAX of the first amplification voltage to obtain the negative peak value-V i2_MAX， of the second amplification voltage i1_MAXWith the negative peak value of the second amplified voltage -V i2_MAX The relationship is shown in expression (9):

[0074] -V i2_MAX =-V i1_MAX (9)

[0075] Among them, -V i2_MAX -V is the negative peak value of the second amplified voltage. i1_MAX This is the negative peak value of the first amplification voltage.

[0076] The first input terminal of the proportional subtraction operation unit is connected to the positive peak value V of the second amplified voltage. i2_MAX The negative peak value of the second amplified voltage at the second input terminal of the proportional subtraction operation unit is -V. i2_MAX For the positive peak value V of the second amplified voltage i2_MAX With the negative peak value of the second amplified voltage -V i2_MAX By performing a proportional subtraction operation, the deviation value V of the amplified voltage is obtained. i_0ffset The deviation value V of the amplified voltage i_0ffset With the positive peak value V of the second amplified voltage i2_MAX With the negative peak value of the second amplified voltage -V i2_MAX The relationship is shown in expression (10):

[0077]

[0078] Among them, V i_0ffset R13 is the bias value for the amplified voltage; R13 is the twelfth resistor; V i2_MAX R10 is the positive peak value of the second amplified voltage; R10 is the ninth resistor; -V i2_MAX R11 is the negative peak value of the second amplified voltage; R12 is the tenth resistor.

[0079] It should be emphasized that when the ninth resistor R10 and the tenth resistor R11 are 10K, and the eleventh resistor R12 and the twelfth resistor R13 are 5K, V i_offset =(v i2_MAX -(-V i2_MAX For example, if the positive peak value V of the second amplified voltage is 2 / 2, i2_MAX The negative peak value of the second amplification voltage is 5V -V. i2_MAX The voltage is -3V. The deviation value V of the amplified voltage is obtained by proportional calculation. i_0ffset It is 1V.

[0080] 3) Finally, such as Figure 4 As shown, the first input terminal of the bias cancellation unit is connected to the deviation value V of the amplified voltage. i_0ffset The second input terminal of the bias cancellation unit is connected to the amplified voltage V. i For the amplified voltage V iThe deviation value V of the amplified voltage i_0ffset Performing a subtraction operation yields the corrected amplification voltage V. i-b Correcting the amplification voltage V i-b The expression is shown in (11):

[0081]

[0082] Among them, V i-b To correct the amplified voltage; R17 is the fifteenth resistor; R15 is the fourteenth resistor; R14 is the thirteenth resistor; V i To amplify the voltage; V i_0ffset This represents the deviation value of the amplified voltage.

[0083] The third detection unit corrects the amplification voltage V. i-b Amplitude acquisition is performed to obtain the amplitude V of the corrected amplification voltage. (i-b)MAX Correcting the amplitude V of the amplified voltage (i-b)MAX With the corrected amplification voltage V i-b The relationship is shown in expression (12):

[0084] V (i-b)MAX =MAX[V i-b (12)

[0085] Among them, V (i-b)MAX To correct the amplitude of the amplified voltage; V i-b To correct the amplification voltage.

[0086] It is important to emphasize that the amplitude acquisition of the detector unit is achieved through the storage of electrical charge by a capacitor, ensuring that the voltage output by the detector unit is at its maximum value, T=RC. Setting the capacitor or resistor value to an ideal value can make the amplitude output by the detector unit meet the conditions for acquisition.

[0087] In detail, in one embodiment of the present invention, Figure 5 This is a block diagram of the processing circuit of the float flowmeter converter in practical application. The magnetic displacement related to the fluid in the float flowmeter is acquired through the acquisition and amplification module to obtain a signal voltage. This signal voltage is then amplified to obtain the amplified voltage V. i The amplified voltage V is acquired through the bias acquisition module. i The bias value is used to obtain the bias value V of the amplified voltage. i_offset The amplitude acquisition module amplifies the voltage V i and the bias value V of the amplified voltage i_offset The bias value of the amplified voltage is eliminated to obtain the corrected amplified voltage. The amplitude of the corrected amplified voltage is then acquired to obtain the amplitude V of the corrected amplified voltage. (i_b)MAX The amplified voltage V is acquired through the analog-to-digital acquisition module. i The bias value V of the amplified voltagei_offset and the amplitude V of the corrected amplification voltage (i_b)MAX The data is input into the central processing unit, where software calculates the angle value θ, which is linearly related to the flow rate. The angle value θ is then converted and output to obtain a more accurate flow rate value, which is displayed on the monitor. The bias value V of the amplified voltage can also be... i_offset and the amplitude V of the corrected amplification voltage (i_b)MAX Store it in memory to prevent data loss.

[0088] The processing circuit of the float flowmeter converter provided by this invention acquires and amplifies the signal voltage through an amplification module to obtain an amplified voltage. The signal voltage is then input to a bias acquisition module, which acquires the positive and negative peak values ​​of the amplified voltage. A proportional subtraction operation is performed between the positive and negative peak values ​​to obtain the bias value of the amplified voltage. An amplitude acquisition module subtracts the amplified voltage from the bias value to eliminate the bias value, obtaining a corrected amplified voltage. The amplitude of the corrected amplified voltage is then acquired. This invention processes the signal voltage related to the magnetic displacement of the float flowmeter through hardware circuitry, acquiring both the bias and amplitude values. Compared to existing technologies, this eliminates the bias value of the amplified voltage, resulting in a more accurate amplitude voltage, thereby improving the accuracy and precision of the software calculations for the float flowmeter.

[0089] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A processing circuit for a float flowmeter converter, characterized in that, include: The acquisition and amplification module acquires the signal voltage and amplifies the signal voltage to obtain an amplified voltage, wherein the signal voltage is related to the magnetic displacement of the fluid in the float flowmeter; The bias acquisition module is connected to the amplified voltage, acquires the amplified voltage, obtains the positive peak value and the negative peak value of the amplified voltage, and performs a proportional subtraction operation between the positive peak value and the negative peak value to obtain the bias value of the amplified voltage. An amplitude acquisition module is connected to the amplified voltage and the bias value. It performs a subtraction operation between the amplified voltage and the bias value to obtain a corrected amplified voltage, which is an amplified voltage to eliminate the bias. The module acquires the amplitude of the corrected amplified voltage. The bias acquisition module includes an inverting unit, two detection units, two follower units, and a proportional subtraction unit. The inverting unit is connected to the amplified voltage and inverts it to obtain a negative-phase amplified voltage. The first detection unit is connected to the amplified voltage and acquires its amplitude to obtain a positive peak value of the first amplified voltage. The second detection unit is connected to the negative-phase amplified voltage and acquires its amplitude to obtain a negative peak value of the first amplified voltage. The first follower unit isolates the positive peak value of the first amplified voltage to obtain a positive peak value of the second amplified voltage. The second follower unit isolates the negative peak value of the first amplified voltage to obtain a negative peak value of the second amplified voltage. The proportional subtraction unit performs a proportional subtraction operation on the positive peak value of the second amplified voltage and the negative peak value of the second amplified voltage to obtain the bias value of the amplified voltage.

2. The processing circuit of the float flowmeter converter according to claim 1, characterized in that, The acquisition and amplification module includes an acquisition unit and an amplification unit. The acquisition unit acquires the magnetic displacement of the fluid in the float flowmeter to obtain the signal voltage. The amplification unit receives the signal voltage and amplifies it to obtain the amplified voltage.

3. The processing circuit of the float flowmeter converter according to claim 2, characterized in that, The acquisition unit includes a first chip, a first resistor, and a first capacitor. The first ground terminal and the second ground terminal of the first chip are grounded. The bridge terminal of the first chip is connected to one end of the first resistor. One end of the first resistor is also grounded after passing through the first capacitor connected in series. The other end of the first resistor is connected to a first power supply voltage. The positive output terminal and the negative output terminal of the first chip cooperate to output the signal voltage, which is a differential voltage.

4. The processing circuit of the float flowmeter converter according to claim 2, characterized in that, The amplification unit includes a second chip, a second resistor, a third resistor, and a fourth resistor. One end of the second resistor is connected to the non-inverting input terminal of the second chip, and one end of the third resistor is connected to the inverting input terminal of the second chip. The positive power supply terminal of the second chip is connected to a second power supply voltage, and the negative power supply terminal of the second chip is connected to a third power supply voltage. The ground terminal of the second chip is grounded. The fourth resistor is connected in series between the first and second resistor gain terminals of the second chip. The other end of the second resistor is the first input terminal of the amplification unit, and the other end of the third resistor is the second input terminal of the amplification unit. The output terminal of the second chip is the output terminal of the amplification unit.

5. The processing circuit of the float flowmeter converter according to claim 1, characterized in that, The inverting unit includes a fifth resistor, a sixth resistor, a seventh resistor, and a first operational amplifier. The inverting input terminal of the first operational amplifier is connected to one end of the fifth resistor, and the inverting input terminal of the first operational amplifier is also connected to one end of the seventh resistor. The other end of the seventh resistor is connected to the output terminal of the first operational amplifier. The non-inverting input terminal of the first operational amplifier is grounded after being connected in series with the sixth resistor. The positive power supply terminal of the first operational amplifier is connected to a second power supply voltage, and the negative power supply terminal of the first operational amplifier is connected to a third power supply voltage. The other end of the fifth resistor is the input terminal of the inverting unit, and the output terminal of the first operational amplifier is the output terminal of the inverting unit.

6. The processing circuit of the float flowmeter converter according to claim 1, characterized in that, The detection unit includes a second operational amplifier, a diode, an eighth resistor, and a second capacitor. The inverting input terminal of the second operational amplifier is connected to the cathode of the diode. The cathode of the diode is also grounded after passing through the eighth resistor in series. The output terminal of the second operational amplifier is connected to the anode of the diode. The positive power supply terminal of the second operational amplifier is connected to a second power supply voltage. The ground terminal of the second operational amplifier is grounded. The second capacitor is connected in parallel with the eighth resistor.

7. The processing circuit of the float flowmeter converter according to claim 1, characterized in that, The proportional subtraction operation unit includes a third operational amplifier, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, and a third capacitor. The non-inverting input of the third operational amplifier is connected to one end of the ninth resistor. The non-inverting input of the third operational amplifier is also connected to the other end of the eleventh resistor. One end of the eleventh resistor is connected to one end of the third capacitor. One end of the third capacitor is grounded. The other end of the third capacitor is connected to the output of the third operational amplifier. The inverting input of the third operational amplifier is connected to one end of the tenth resistor. The twelfth resistor is connected in series between the inverting input of the third operational amplifier and the output of the third operational amplifier. The other end of the ninth resistor is the first input of the proportional subtraction operation unit, the other end of the tenth resistor is the second input of the proportional subtraction operation unit, and the output of the third operational amplifier is the output of the proportional subtraction operation unit.

8. The processing circuit of the float flowmeter converter according to claim 1, characterized in that, The amplitude acquisition module includes an offset cancellation unit and a third detection unit. The offset cancellation unit is connected to the amplified voltage and the offset value, and performs a subtraction operation between the amplified voltage and the offset value to obtain the corrected amplified voltage. The third detection unit acquires the amplitude of the corrected amplified voltage to obtain the amplitude of the corrected amplified voltage.

9. The processing circuit of the float flowmeter converter according to claim 8, characterized in that, The bias cancellation unit includes a fourth operational amplifier, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, and a sixteenth resistor. The inverting input terminal of the fourth operational amplifier is connected to one end of the thirteenth resistor. The fifteenth resistor is also connected in series between the inverting input terminal and the output terminal of the fourth operational amplifier. The non-inverting input terminal of the fourth operational amplifier is connected to one end of the fourteenth resistor. The non-inverting input terminal of the fourth operational amplifier is also grounded after passing through the sixteenth resistor. The positive power supply terminal of the fourth operational amplifier is connected to a second power supply voltage, and the negative power supply terminal is connected to a third power supply voltage. The other end of the thirteenth resistor is the first input terminal of the bias cancellation unit, the other end of the fourteenth resistor is the second input terminal of the bias cancellation unit, and the output terminal of the fourth operational amplifier is the output terminal of the bias cancellation unit.

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