Bandgap reference circuit and electronic device

Abstract

The application discloses a band gap reference circuit and electronic equipment. The band gap reference circuit comprises a reference voltage generating module, an operational amplifier and a current biasing module. The operational amplifier is connected with the reference voltage generating module. The operational amplifier makes the reference voltage generating module generate a band gap reference voltage by clamping voltages of an inverting input end and a non-inverting input end of the operational amplifier. The current biasing module is used for generating a biasing current required by the operational amplifier to work according to a first biasing voltage and a sleep mode signal, so that the band gap reference circuit is quickly switched from a sleep mode to a working mode, and the start-up time of the band gap reference circuit is shortened.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and more particularly, to a bandgap reference circuit and an electronic device. BACKGROUND

[0002] With the continuous development of integrated circuit technology, electronic devices are increasingly pursuing low power consumption and low latency performance. When the electronic device is in an idle state, each circuit module in the entire system is in an off state, which can effectively reduce standby power consumption; when the enable signal arrives, each circuit module in the entire system can quickly start to enter the normal working state, but in some application scenarios, in order to be able to monitor the change of the external state in real time, the bandgap reference circuit still needs to provide a reference voltage for some modules in the chip in the sleep, standby and other cases.

[0003] In addition, electronic devices have increasingly high requirements for the startup process. As the most important component of the entire analog circuit system, the startup time of the bandgap reference circuit will greatly affect the startup speed of the entire system. The existing bandgap reference circuit is generally composed of a startup module and a reference voltage generation module. The startup module provides a startup current to the reference core during the startup process, and then the operational amplifier in the reference voltage generation module is adjusted to finally generate a stable bandgap reference voltage. However, the startup time of such a circuit is relatively long, which greatly increases the startup time of the chip and cannot meet the requirement of fast startup. SUMMARY

[0004] In view of the above problems, the purpose of the present application is to provide a bandgap reference circuit and an electronic device, which improves the problem of slow startup speed of the bandgap reference circuit.

[0005] According to an aspect of an embodiment of the present application, a bandgap reference circuit is provided, which includes: a reference voltage generation module having an output node for generating a bandgap reference voltage; an operational amplifier connected to a first node and a second node in the reference voltage generation module, the operational amplifier being configured to clamp the voltage at the first node and the second node; and a current biasing module configured to generate a biasing current required for the operational amplifier to work according to a first biasing voltage and a sleep mode signal, so that the bandgap reference circuit is quickly switched from a sleep mode to a working mode.

[0006] Optionally, the bandgap reference circuit further includes: a startup module, a first end of the startup module being connected to a power supply end, a second end of the startup module being connected to the output node of the reference voltage generation module, the startup module being configured to provide a startup current to the reference voltage generation module when the power supply end is powered on.

[0007] Optionally, the bandgap reference circuit further comprises a first sample-and-hold module, configured to transmit the bandgap reference voltage generated by the reference voltage generating module to a voltage output terminal of the bandgap reference circuit when the bandgap reference circuit is in the working mode, and to hold the voltage of the voltage output terminal when the bandgap reference circuit is in the sleep mode.

[0008] Optionally, the bandgap reference circuit further comprises a second sample-and-hold module, connected to the output terminal of the operational amplifier, and configured to hold the voltage of the output terminal of the operational amplifier when the bandgap reference circuit is in the sleep mode.

[0009] Optionally, the reference voltage generating module further has a third node, which generates a second bias voltage of at least one common-gate structure in the operational amplifier.

[0010] Optionally, the reference voltage generating module comprises a first transistor and a first resistor connected in series between a power supply terminal and the third node, a common node of the first transistor and the first resistor serving as the output node to generate the bandgap reference voltage; a second resistor, a third resistor and a first triode connected in series between the third node and ground, a common node of the second resistor and the third resistor being connected to the inverting input terminal of the operational amplifier as the first node; and a fourth resistor and a second triode connected in series between the third node and ground, a control terminal of the first triode and the second triode being connected to the ground, and a common node of the fourth resistor and the second triode being connected to the non-inverting input terminal of the operational amplifier as the second node.

[0011] Optionally, the starting module comprises a fifth resistor, a second transistor and a third triode connected in series between the power supply terminal and ground, a control terminal and a first terminal of the second transistor being shorted together, and a control terminal and a second terminal of the third triode being shorted together; and a third transistor connected between the power supply terminal and the output node of the reference voltage generating module, a control terminal of the third transistor being connected to the control terminal of the second transistor.

[0012] Optionally, the operational amplifier comprises: a fourth transistor and a fifth transistor, a control terminal of the fourth transistor being connected with the second node, a control terminal of the fifth transistor being connected with the first node, and second terminals of the fourth transistor and the fifth transistor being connected with the current biasing module; a sixth transistor and a seventh transistor, control terminals of the sixth transistor and the seventh transistor being used for receiving the second bias voltage, a second terminal of the sixth transistor being connected with a first terminal of the fourth transistor, and a second terminal of the seventh transistor being connected with a first terminal of the fifth transistor; an eighth transistor and a ninth transistor, the eighth transistor and the ninth transistor being connected in series between a power supply terminal and the first terminal of the sixth transistor, and control terminals of the eighth transistor and the ninth transistor being connected with a second terminal of the ninth transistor; and a tenth transistor and an eleventh transistor, the tenth transistor and the eleventh transistor being connected in series between the power supply terminal and the first terminal of the seventh transistor, a control terminal of the tenth transistor being connected with a control terminal of the eighth transistor, a control terminal of the eleventh transistor being connected with a control terminal of the ninth transistor, and a common node of the eleventh transistor and the seventh transistor being an output terminal of the operational amplifier.

[0013] Optionally, the current biasing module comprises: a twelfth transistor, a sixth resistor and a thirteenth transistor connected in series between an output terminal of the biasing current and a ground, a control terminal of the twelfth transistor being used for receiving the first bias voltage, a control terminal of the thirteenth transistor being used for receiving the sleep mode signal, and the sleep mode signal being used for controlling the bandgap reference circuit to be in a working mode or a sleep mode; and a first capacitor connected between the control terminal of the twelfth transistor and the ground.

[0014] According to another aspect of the embodiments of the present application, an electronic device is provided, which comprises the above bandgap reference circuit.

[0015] The bandgap reference circuit provided by the embodiments of the present application comprises a reference voltage generating module, an operational amplifier and a current biasing module, wherein the operational amplifier is connected with the reference voltage generating module, the operational amplifier makes the reference voltage generating module generate a bandgap reference voltage by clamping voltages of an inverting input terminal and a non-inverting input terminal of the operational amplifier, and the current biasing module is used for generating a biasing current required by the operational amplifier according to a first bias voltage and a sleep mode signal, so that the bandgap reference circuit is quickly switched from a sleep mode to a working mode, and the start-up time of the bandgap reference circuit is shortened.

[0016] Further, the bandgap reference circuit further comprises a sample-and-hold module arranged at the voltage output terminal and the output of the operational amplifier, which can hold the output bandgap reference voltage and the output voltage of the operational amplifier at a stable state when the bandgap reference circuit is in the sleep mode. By this arrangement, when the bandgap reference circuit switches from the sleep mode to the working mode, the bandgap reference voltage and the output voltage of the operational amplifier only need to rise from the stable state, instead of from zero, which can further shorten the start-up time of the bandgap reference circuit.

[0017] Further, the reference voltage generating module is further configured to generate a bias voltage for at least one common-source common-gate structure in the operational amplifier, without the need to arrange an additional voltage bias structure in the circuit, which not only can reduce the area and cost of the circuit, but also can make the bias voltage of the operational amplifier and the reference voltage of the reference voltage generating module be established at the same time, further shortening the start-up time of the bandgap reference circuit. BRIEF DESCRIPTION OF DRAWINGS

[0018] The above and other objects, features and advantages of the present application will become more apparent from the following description when taken in conjunction with the accompanying drawings, in which:

[0019] Figure 1 shows a schematic circuit diagram of a bandgap reference circuit according to the prior art.

[0020] Figure 2 shows a schematic circuit block diagram of a bandgap reference circuit according to an embodiment of the present application.

[0021] Figure 3 shows a schematic circuit diagram of a bandgap reference circuit according to an embodiment of the present application.

[0022] Figure 4 shows a working waveform diagram of a bandgap reference circuit according to an embodiment of the present application.

[0023] Figure 5 shows a schematic circuit block diagram of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0024] Various embodiments of the present application will be described in detail below with reference to the accompanying drawings. In the various drawings, the same elements are denoted by the same or similar reference numerals. For the sake of clarity, each portion in the drawings is not drawn to scale.

[0025] It should be understood that, in the following description, "circuitry" can include a single or multiple components or hardware circuits, programmable circuitry, state machine circuitry, and / or elements storing instructions for execution by programmable circuitry. When an element or circuitry is referred to as being "connected to" another element or "connected between" two nodes, it can be directly coupled or connected to the other element or there can be intervening elements between the elements, the connection between elements can be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled to" or "directly connected to" another element, it implies that the two are connected without intervening elements.

[0026] In this application, a MOS transistor (Metal-Oxide-Semiconductor Field-Effect Transistor) includes a first terminal, a second terminal, and a control terminal, in the on state of the MOS transistor, current flows from the first terminal to the second terminal. The first terminal, the second terminal, and the control terminal of a PMOS transistor are source, drain, and gate, respectively, and the first terminal, the second terminal, and the control terminal of an NMOS transistor are drain, source, and gate, respectively. A transistor (also known as a bipolar transistor) includes a first terminal, a second terminal, and a control terminal, in the on state of the transistor, current flows from the first terminal to the second terminal. The first terminal, the second terminal, and the control terminal of a PNP transistor are emitter, collector, and base, respectively, and the first terminal, the second terminal, and the control terminal of an NPN transistor are collector, emitter, and base, respectively.

[0027] The application is further illustrated below with reference to the accompanying drawings and examples.

[0028] Figure 1 A schematic circuit diagram of a bandgap reference circuit according to the prior art is shown. As Figure 1As shown, the existing bandgap reference circuit 100 includes a reference voltage generation module 110 and a start-up module 120. The reference voltage generation module 110 includes an operational amplifier Al, an NMOS transistor Ml, resistors Rl to R4, and two transistors Ql and Q2. Among them, the transistor Ml is an NMOS transistor, and the transistors Ql and Q2 are PNP transistors. The drain of the NMOS transistor Ml is connected to a power supply voltage VDD, the gate of the NMOS transistor Ml is connected to the output of the operational amplifier Al, the source of the NMOS transistor Ml is connected to the first end of the resistor Rl, the first end of the resistor R2 is connected to the second end of the resistor Rl at a node C, the second end of the resistor R2 is connected to the first end of the resistor R3, the second end of the resistor R3 is connected to the emitter of the PNP transistor Ql, the collector of the PNP transistor Ql is connected to the ground, the first end of the resistor R4 is connected to the second end of the resistor Rl at the node C, the second end of the resistor R4 is connected to the emitter of the PNP transistor Q2, the base of the PNP transistor Q2 is connected to the base of the PNP transistor Ql, and the collector of the PNP transistor Q2 is connected to the ground. The operational amplifier Al has a non-inverting input and an inverting input, the inverting input of which is connected to the node A between the resistors R2 and R3, and the non-inverting input of which is connected to the node B between the resistor R4 and the PNP transistor Q2. One end of the start-up module 120 is connected to the power supply voltage VDD, and the other end of the start-up module 120 is connected to the node C.

[0029] In the start-up process of the existing bandgap reference circuit 100, a start-up current is injected into the reference voltage generation module 110 through the start-up module to turn on the transistors Ql and Q2, and then the feedback regulation of the operational amplifier Al is used to make the voltages between the nodes A and B equal, and finally a stable reference voltage Vref is generated at the source of the transistor Ml.

[0030] In the existing bandgap reference circuit 100, since the operational amplifier Al is added in the reference voltage generation module 110, in order to ensure the stability of the loop, a compensation capacitor Cl needs to be set at the output of the operational amplifier Al. In addition, in order to ensure the normal operation of the operational amplifier Al, an additional bias current needs to be provided to the operational amplifier Al, such as Figure 1 As shown, the additional bias current Ibias2 is provided to the operational amplifier Al through the bias current Ibiasl and the current mirror composed of the transistors M2 and M3. Therefore, when the bandgap reference circuit 100 is restarted, the compensation capacitor Cl needs to be recharged, and the bias current of the operational amplifier Al needs to be re-established, which results in a long start-up time of the entire bandgap reference circuit, greatly increases the start-up time of the chip, and cannot meet the requirement of fast start-up.

[0031] Figure 2 and Figure 3A schematic circuit diagram and a circuit diagram of a bandgap reference circuit according to an embodiment of the present application are shown respectively. As shown in Figure 2 and Figure 3 The bandgap reference circuit 200 of the present embodiment comprises a reference voltage generating module 210, an operational amplifier A2, a current biasing module 220, a start-up module 230, and sample-and-hold modules 240 and 250.

[0032] The reference voltage generating module 210 is configured to generate a bandgap reference voltage with zero temperature coefficient. In one embodiment, the reference voltage generating module 210 comprises an NMOS transistor Ml, PNP transistors Ql and Q2, and resistors Rl, R2, R3 and R4. The drain of the NMOS transistor Ml is connected to a power supply voltage VDD of a power supply terminal, the source of the NMOS transistor Ml is connected to a first terminal of the resistor Rl, a second terminal of the resistor Rl is connected to a node C, and a node D between the NMOS transistor Ml and the resistor Rl is configured to output the bandgap reference voltage with zero temperature coefficient. The resistors R2 and R3 are connected in series between the node C and the emitter of the PNP transistor Ql, and the resistor R4 is connected between the node C and the emitter of the PNP transistor Q2, and the collectors and the bases of the PNP transistors Ql and Q2 are connected to ground.

[0033] The inverting input of the operational amplifier A2 is connected to a node A between the resistors R2 and R3, the non-inverting input of the operational amplifier A2 is connected to a node B between the resistor R4 and the PNP transistor Q2, and the output of the operational amplifier A2 is connected to the gate of the NMOS transistor Ml through the sample-and-hold module 250. The operational amplifier A2 outputs a constant voltage by clamping the voltage Va input to the inverting input and the voltage Vb input to the non-inverting input to be equal, thereby controlling the NMOS transistor Ml to provide a stable reference current to the PNP transistors Ql and Q2, and the reference voltage generating module 210 generates the bandgap reference voltage by utilizing the difference of the emitter-base voltages between the PNP transistors Ql and Q2.

[0034] In one example embodiment, as shown in Figure 3 the operational amplifier A2 comprises NMOS transistors M4, M5, M6 and M7, and PMOS transistors M8, M9, MlO and Ml l.

[0035] The NMOS transistors M4 and M5 form a differential input pair of the operational amplifier A2, and the sources of the NMOS transistors M4 and M5 are connected to the current biasing module 220. The gate of the NMOS transistor M4 is connected to the node B as the non-inverting input of the operational amplifier A2, and the gate of the NMOS transistor M5 is connected to the node A as the inverting input of the operational amplifier A2.

[0036] The NMOS transistors M6-M7 are connected to form a common-source common-gate structure respectively, and the PMOS transistors M8-M11 are connected to form a common-source common-gate structure respectively. The sources of the PMOS transistors M8 and M10 are connected to the power supply voltage VDD, the sources of the PMOS transistors M9 and M11 are connected to the drains of the PMOS transistors M8 and M10 respectively, the gates of the PMOS transistors M8-M11 are connected to the drain of the PMOS transistor M9, the drain of the PMOS transistor M9 is also connected to the drain of the NMOS transistor M6, the drain of the PMOS transistor M11 is connected to the drain of the NMOS transistor M7, and the common node of the two is used as the output terminal of the operational amplifier A2. The source of the NMOS transistor M6 is connected to the drain of the NMOS transistor M4, the source of the NMOS transistor M7 is connected to the drain of the NMOS transistor M5, and the gates of the NMOS transistors M6 and M7 are connected to each other and used for receiving a bias voltage Vbias2.

[0037] For example, the bias voltage Vbias2 of the NMOS transistors M6 and M7 can be provided by the reference voltage generating module 210. For example, the bias voltage Vbias2 of the NMOS transistors M6 and M7 can be provided by the node C in the reference voltage generating module 210, that is, the gates of the NMOS transistors M6 and M7 are connected to the node C in the reference voltage generating module 210. By using the reference voltage generating module 210 to provide the bias voltage of the common-source common-gate structure of the operational amplifier A2, it is not necessary to set an additional voltage bias structure in the circuit, so that the bias voltage of the operational amplifier A2 can be established at the same time as the reference voltage of the reference voltage generating module 210, and the problem of increasing the start-up time of the bandgap reference circuit due to the addition of an additional voltage bias structure can be avoided, and the start-up time of the bandgap reference circuit 200 is preliminarily shortened.

[0038] The current bias module 220 is connected to the tail current terminal of the operational amplifier A2, and is used for generating a bias current required for the operational amplifier A2 to work according to the bias voltage Vbias1 and a sleep mode signal EN, so that the bandgap reference circuit 200 can be quickly switched from the sleep mode to the working mode.

[0039] In an exemplary embodiment, as Figure 3As shown, the current biasing module 220 includes NMOS transistors M12, M13, a resistor R6 and a capacitor C3. Among them, the NMOS transistor M12, the resistor R6 and the NMOS transistor M13 are connected in series between the bias current output end of the current biasing module 220 and the ground, the drain of the NMOS transistor M12 is connected with the output end of the current biasing module 220, the gate of the NMOS transistor M12 is used for receiving the bias voltage Vbias1, the source of the NMOS transistor M12 is connected with the first end of the resistor R6, the second end of the resistor R6 is connected with the drain of the NMOS transistor M13, the gate of the NMOS transistor M13 is connected with the sleep mode signal EN, and the source of the NMOS transistor M13 is connected with the ground. The capacitor C3 is connected between the gate of the NMOS transistor M12 and the ground. When the sleep mode signal EN is valid (for example, low level), the NMOS transistor M13 is turned off, the current biasing module 220 is closed, no bias current is provided to the operational amplifier A2, and then the operational amplifier A2 is closed. Therefore, during the sleep mode, the bandgap reference circuit 200 is closed, no current loss is generated. When the sleep mode signal EN is invalid (for example, high level), the NMOS transistor M13 is turned on, the current biasing module 220 quickly establishes the bias current according to the bias voltage Vbias1, so that the operational amplifier A2 can be quickly turned on, and the bandgap reference circuit 200 can be quickly switched from the sleep mode to the working mode. In the embodiment, the current biasing module 220 generates the bias current according to the bias voltage Vbias1, the NMOS transistor M12 and the resistor R6, that is, the bias current Ibias=(Vbias1-Vth_M12) / R6, wherein Vth_M12 represents the threshold voltage of the NMOS transistor M12. Compared with the prior art bandgap reference circuit, the current biasing module 220 of the embodiment does not need to charge the capacitor C3 when the system is switched from the sleep mode to the working mode, and the start-up time of the bandgap reference circuit can be further shortened.

[0040] The start-up module 230 is connected between the power supply end and the output node D of the reference voltage generating module 210, and is used for providing a start-up voltage to the reference voltage generating module 210 when the power supply voltage VDD of the power supply end is powered on, and starting the entire reference voltage generating module 210 through the start-up module 230 when the power supply voltage VDD starts to rise.

[0041] Further, the start module 230 includes NMOS transistors M2, M3, a resistor R5, and a PNP transistor Q3. A first end of the resistor R5 is connected to the power supply voltage VDD, a second end of the resistor R5 is connected to the gate and the drain of the NMOS transistor M2, the source of the NMOS transistor M2 is connected to the emitter of the PNP transistor Q3, the base and the collector of the PNP transistor Q3 are connected to the ground, the drain of the NMOS transistor M3 is connected to the power supply voltage VDD, the gate of the NMOS transistor M3 is connected to the gate of the NMOS transistor M2, and the source of the NMOS transistor M3 is connected to the output node D of the reference voltage generation module 210.

[0042] The sample-and-hold modules 240 and 250 are respectively used to hold the voltage at the voltage output end of the bandgap reference circuit 200 and the voltage at the output end of the operational amplifier A2 when the bandgap reference circuit 200 is in the sleep mode.

[0043] For example, the sample-and-hold module 240 is connected between the output node D of the reference voltage generation module 210 and the voltage output end of the bandgap reference circuit 200. When the bandgap reference circuit 200 is in the working mode, the sample-and-hold module 240 transmits the bandgap reference voltage Vref generated at the output node D to the voltage output end of the bandgap reference circuit. When the bandgap reference circuit 200 is in the sleep mode, the sample-and-hold module 240 holds the voltage at the voltage output end. Further, the sample-and-hold module 240 includes a switch S1 and a capacitor C1. The switch S1 is connected between the output node D of the reference voltage generation module 210 and the voltage output end of the bandgap reference circuit 200, and is controlled to be turned on and turned off by the sleep enable signal EN. The capacitor C1 is connected between the voltage output end and the ground. When the sleep enable signal EN is invalid (e.g., high), the bandgap reference circuit 200 is in the working mode, and the switch S1 is turned on to provide the bandgap reference voltage Vref generated by the reference voltage generation module 210 to the voltage output end. When the sleep enable signal EN is valid (e.g., high), the bandgap reference circuit 200 is in the sleep mode, and the switch S1 is turned off to hold the bandgap reference voltage Vref at the voltage output end by the capacitor C1.

[0044] Similarly, the sample-and-hold module 250 includes a switch S2 connected between the output of operational amplifier A2 and the gate of NMOS transistor M1, and a capacitor C2 connected between the gate of NMOS transistor M1 and ground. Switch S2 is controlled to be turned on and off by a sleep enable signal EN. When the sleep enable signal EN is invalid (e.g., high level), switch S2 is turned on, and capacitor C2 samples the output voltage of operational amplifier A2. When the sleep enable signal EN is valid (e.g., low level), switch S2 is turned off, and capacitor C2 holds the output voltage of operational amplifier A2, thereby ensuring that the voltage at the gate of NMOS transistor M1 does not drop.

[0045] As described above, the bandgap reference circuit 200 of this embodiment is equipped with a sample-and-hold module at the voltage output terminal and the output of the operational amplifier A2. The capacitor in the sample-and-hold module holds the bandgap reference voltage Vref at the voltage output terminal and the output voltage of the operational amplifier A2 when the bandgap reference circuit 200 is in sleep mode. Thus, when the bandgap reference circuit 200 switches from sleep mode to working mode, the bandgap reference voltage Vref and the output voltage of the operational amplifier A2 rise from a steady-state value without having to rise from zero. Therefore, the startup speed of the bandgap reference circuit can be greatly accelerated.

[0046] Furthermore, when the bandgap reference circuit 200 switches from sleep mode to working mode, the startup current of the reference voltage generation module 210 is provided by the NMOS transistor M1 and the capacitor C1. If the bandgap reference voltage Vref drops, the NMOS transistor M1 can also supplement the current to the capacitor C1 to prevent the bandgap reference voltage Vref from dropping.

[0047] Figure 4 The diagram shows the operating waveforms of a bandgap reference circuit according to an embodiment of the present invention. Figure 4 The waveforms of the power supply voltage VDD, the sleep enable signal EN, and the bandgap reference voltage Vref are shown below. Figure 4 The working principle of the bandgap reference circuit in this embodiment will be explained in detail.

[0048] like Figure 4As shown, at time t1, the power supply voltage VDD starts to build up, the sleep enable signal EN also turns to high level, the bandgap reference circuit 200 starts to enter the working mode, at this time, the starting module 230 provides starting current to the reference voltage generating module 210, the PNP transistors Q1 and Q2 are turned on, the bandgap reference voltage Vref gradually rises, and through the feedback regulation of the operational amplifier A2, the voltages of nodes A and B are equalized, finally the bandgap reference voltage Vref tends to be stable. At time t2, the sleep enable signal EN turns to low level, the bandgap reference circuit 200 switches from the working mode to the sleep mode, the NMOS transistor M13 in the current bias module 220 is turned off, the current bias module 220 no longer provides the bias current to the operational amplifier A2, and then the operational amplifier A2 is turned off, at the same time, the switches S1 and S2 in the sample-and-hold modules 240 and 250 are turned off, and the bandgap reference voltage Vref and the output voltage of the operational amplifier A2 are respectively held by the capacitors C1 and C2. At time t3, the sleep enable signal EN turns to high level again, the current bias module 220 is turned on again to provide the bias current to the operational amplifier A2, and then the operational amplifier A2 is turned on, at this time, the output voltage of the operational amplifier A2 only needs to rise from a steady state value. At the same time, the starting current is provided to the reference voltage generating module 210 through the charge stored in the capacitor C1, the PNP transistors Q1 and Q2 in the reference voltage generating module 210 are turned on, so that the bandgap reference voltage Vref output by the reference voltage generating module 210 can be re-established. At the same time, due to the power supply of the reference voltage generating module 210 by the capacitor C1, the bandgap reference voltage Vref at the voltage output end drops, at this time, the NMOS transistor M1 supplements the current of the capacitor C1 to avoid the drop of the bandgap reference voltage Vref.

[0049] In addition, other embodiments of the present application also provide an electronic device 300.

[0050] Figure 5 A schematic circuit block diagram of an electronic device provided by an embodiment of the present application is shown. As shown in the figure, Figure 5 As shown, the electronic device 300 comprises a bandgap reference circuit 200. The bandgap reference circuit 200 can be combined with the Figures 2-3The above-mentioned embodiments show any one of the bandgap reference circuits. According to the teaching of the embodiments, the electronic device 300 has multiple modes, including but not limited to an operating mode and a sleep mode. When the electronic device 300 is in the operating mode, the bandgap reference circuit 200 is in operation to provide a reference voltage for other circuits or modules in the electronic device 300. When the electronic device 300 is in the sleep mode, the bandgap reference circuit 200 is turned off, and the bandgap reference voltage is kept by the sample-and-hold module, so that the reference voltage can still be provided to some circuits or modules in the electronic device 300 which need to monitor the change of external state in real time. When the electronic device 300 switches from the sleep mode to the operating mode, the bandgap reference circuit 200 can be quickly started, so that the start-up time of the electronic device 300 is shortened, and the requirement of fast start-up is met.

[0051] For example, the electronic device herein refers to a device which can be used in a mobile environment and supports multiple communication modes such as GSM, EDGE, TD_SCDMA, TDD_LTE, FDD_LTE, etc., including a mobile phone, a notebook computer, a tablet computer, a vehicle-mounted computer, etc.

[0052] In summary, the bandgap reference circuit provided by the embodiments of the present application comprises a reference voltage generation module, an operational amplifier and a current biasing module. The operational amplifier is connected with the reference voltage generation module. The operational amplifier makes the reference voltage generation module generate a bandgap reference voltage by clamping the voltage of the inverting input terminal and the non-inverting input terminal thereof. The current biasing module is used to generate a biasing current required by the operational amplifier according to a first biasing voltage and a sleep mode signal, so that the bandgap reference circuit is quickly switched from the sleep mode to the operating mode, and the start-up time of the bandgap reference circuit is shortened.

[0053] Further, the bandgap reference circuit further comprises a sample-and-hold module arranged at the voltage output terminal and the output of the operational amplifier. The sample-and-hold module can keep the output bandgap reference voltage and the output voltage of the operational amplifier in a stable state when the bandgap reference circuit is in the sleep mode. Through this arrangement, when the bandgap reference circuit is switched from the sleep mode to the operating mode, the bandgap reference voltage and the output voltage of the operational amplifier only need to rise from the stable state, and do not need to rise from zero, so that the start-up time of the bandgap reference circuit can be further shortened.

[0054] Further, the reference voltage generation module is further used to generate a biasing voltage of at least one common-source and common-gate structure in the operational amplifier. An additional voltage biasing structure does not need to be arranged in the circuit. Not only the area and cost of the circuit can be reduced, but also the biasing voltage of the operational amplifier can be established at the same time as the reference voltage of the reference voltage generation module, so that the start-up time of the bandgap reference circuit can be further shortened.

[0055] It should be appreciated that, although devices are described herein as being either N-channel or P-channel devices, or as having either N-type or P-type doped regions, one of ordinary skill in the art will understand that complementary devices are also possible in accordance with the present application. One of ordinary skill in the art will appreciate that the conductivity type is the mechanism by which conduction occurs, e.g., by holes or electrons, and thus the conductivity type is not related to the doping concentration but to the type of doping, e.g., P-type or N-type. One of ordinary skill in the art will appreciate that the words "during," "while," and "when" as used herein in relation to one action following another action are not strictly a temporal notion denoting that the actions occur at the same time, but that there can be some minor delay between the actions while still conceptually being dependent. The words "about" or "substantially" as used herein mean that the element value has a parameter that is intended to be close to the stated value or position. However, as is well known in the art, there are always minor variations that make it difficult to be strictly the stated value. It has been appropriately determined in the art that a variation of at least ten percent (10%) (and at least twenty percent (20%) for semiconductor doping concentrations) is a reasonable variation from the described accurate ideal target. When used in connection with a signal state, the actual voltage value or logic state of the signal (e.g., "1" or "0") depends on whether positive logic or negative logic is used.

[0056] Furthermore, it should be appreciated that relational terms such as first and second, and the like can be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0057] In accordance with the present application, embodiments such as those described above do not need to be practiced in their specific detailed form. Obviously, many modifications and variations of the present application are possible in light of the above teachings. The embodiments were chosen and described in order to provide the best illustration of the principles of the application and its practical application to thereby enable one of ordinary skill in the art to utilize the application in its best form and to apply the principles of the application in the best way he or she sees fit. The scope of the application should be determined, however, by the claims that follow.

Claims

1. A bandgap reference circuit, comprising: The reference voltage generation module has an output node for generating a bandgap reference voltage; An operational amplifier is connected to a first node and a second node in the reference voltage generation module, and the operational amplifier is used to clamp the voltage at the first node and the second node. as well as A current bias module is used to generate the bias current required for the operation amplifier to operate based on a first bias voltage and a sleep mode signal, so that the bandgap reference circuit can quickly switch from sleep mode to operating mode. The current bias module includes: A twelfth transistor, a sixth resistor, and a thirteenth transistor are connected in series between the output terminal of the bias current and ground. The control terminal of the twelfth transistor is used to receive the first bias voltage, and the control terminal of the thirteenth transistor is used to receive the sleep mode signal. The sleep mode signal is used to control the bandgap reference circuit to be in operating mode or sleep mode. The first capacitor connected between the control terminal of the twelfth transistor and ground. When the sleep mode signal is invalid, the thirteenth transistor is turned on, and the current bias module quickly establishes a bias current based on the first bias voltage, thereby enabling the operational amplifier to be turned on quickly and the bandgap reference circuit to quickly switch from the sleep mode to the operating mode.

2. The bandgap reference circuit according to claim 1, further comprising: A startup module is provided, with its first end connected to a power supply terminal and its second end connected to the output node of the reference voltage generation module. The startup module is used to provide a startup current to the reference voltage generation module when the power supply terminal is powered on.

3. The bandgap reference circuit according to claim 1, further comprising: The first sample-and-hold module is used to transmit the bandgap reference voltage generated by the reference voltage generation module to the voltage output terminal of the bandgap reference circuit when the bandgap reference circuit is in the working mode. And when the bandgap reference circuit is in sleep mode, the voltage at the voltage output terminal is maintained.

4. The bandgap reference circuit according to claim 1, further comprising: The second sample-and-hold module is connected to the output of the operational amplifier and is used to hold the voltage at the output of the operational amplifier when the bandgap reference circuit is in sleep mode.

5. The bandgap reference circuit according to claim 1, wherein, The reference voltage generation module also has a third node that generates a second bias voltage for at least one cascode structure in the operational amplifier.

6. The bandgap reference circuit according to claim 5, wherein, The reference voltage generation module includes: A first transistor and a first resistor are connected in series between the power supply terminal and the third node, and the common node of the first transistor and the first resistor serves as the output node to generate the bandgap reference voltage; A second resistor, a third resistor, and a first transistor are connected in series between the third node and ground. The common node of the second resistor and the third resistor serves as the first node and is connected to the inverting input of the operational amplifier. A fourth resistor and a second transistor are connected in series between the third node and ground. The control terminals of the first transistor and the second transistor are connected to ground. The common node of the fourth resistor and the second transistor serves as the second node and is connected to the non-inverting input terminal of the operational amplifier.

7. The bandgap reference circuit according to claim 2, wherein, The startup module includes: A fifth resistor, a second transistor, and a third transistor are connected in series between the power supply terminal and ground. The control terminal of the second transistor is shorted to its first terminal, and the control terminal of the third transistor is shorted to its second terminal. A third transistor is connected between the power supply terminal and the output node of the reference voltage generation module, and the control terminal of the third transistor is connected to the control terminal of the second transistor.

8. The bandgap reference circuit according to claim 5, wherein, The operational amplifier includes: The fourth transistor and the fifth transistor, wherein the control terminal of the fourth transistor is connected to the second node, the control terminal of the fifth transistor is connected to the first node, and the second terminals of the fourth transistor and the fifth transistor are connected to the current bias module; The sixth transistor and the seventh transistor have control terminals for receiving the second bias voltage. The second terminal of the sixth transistor is connected to the first terminal of the fourth transistor, and the second terminal of the seventh transistor is connected to the first terminal of the fifth transistor. An eighth transistor and a ninth transistor, the eighth transistor and the ninth transistor being connected in series between the power supply terminal and the first terminal of the sixth transistor, and the control terminals of the eighth transistor and the ninth transistor being connected to the second terminal of the ninth transistor; and The tenth and eleventh transistors are connected in series between the power supply terminal and the first terminal of the seventh transistor. The control terminal of the tenth transistor is connected to the control terminal of the eighth transistor, and the control terminal of the eleventh transistor is connected to the control terminal of the ninth transistor. The common node of the eleventh transistor and the seventh transistor is the output terminal of the operational amplifier.

9. An electronic device, wherein, include: The bandgap reference circuit as described in any one of claims 1-8.

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