A low-power and highly sensitive wake-up receiver

Abstract

The present invention relates to a low-power, high-sensitivity wake-up receiver, comprising: a transformer, an envelope detection circuit, an amplifier based on an inverter structure, an AC coupling circuit, a strong-arm comparator, a serial peripheral interface circuit, and a digital correlator; the transformer, the envelope detection circuit, the amplifier based on the inverter structure, the AC coupling circuit, and the strong-arm comparator are connected in sequence; the input end of the digital correlator is respectively connected to the output end of the strong-arm comparator and the output end of the serial peripheral interface circuit. The present invention amplifies the OOK signal once through the transformer; the envelope detection circuit performs envelope demodulation, and then amplifies it twice through the amplifier based on the inverter structure. This is used for long-distance communication, compensating for the signal attenuation of wireless signals that increases with communication distance and improving the wake-up sensitivity; the wake-up receiver determines the wake-up state based on the digital signal output by the digital correlator, while having low circuit complexity and reducing the power consumption of the receiver.

Description

Technical Field

[0001] The present invention belongs to the field of radio frequency wireless transmission and reception, and in particular relates to a low-power and high-sensitivity wake-up receiver. Background Art

[0002] The majority of IoT device power consumption throughout its lifecycle comes from wireless communication, not information processing. A significant portion of this energy is used for network synchronization, not data transmission and reception. Wireless communication primarily operates synchronously, facilitating real-time information reception. Traditional receivers are typically kept constantly on, only turning on periodically after a predefined sleep timer has expired to conserve energy. However, this technology relies on the accuracy of the sleep timer, and in practice, it cannot guarantee that the receiver will receive useful signals when it is turned on, making it unsuitable for applications with stringent power requirements.

[0003] Asynchronous wakeup—A system with a wakeup receiver uses an auxiliary wakeup receiver to reduce energy consumption when continuous communication is not required. This receiver continuously monitors the RF for a predefined wakeup signal, rather than sending commands to the primary receiver. Upon successful receipt of the wakeup code, the primary receiver performs a burst of high-speed (and power-consuming) communication of one or more packets, then remains dormant until the next wakeup event occurs. The power consumption of the wakeup receiver is maintained in the microwatt or nanowatt range, but under stringent power constraints, the minimum signal power required for wakeup is limited, impacting sensitivity. Summary of the Invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a low-power and high-sensitivity wake-up receiver. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0005] The present invention provides a low-power and high-sensitivity wake-up receiver, comprising: a transformer, an envelope detection circuit, an amplifier based on an inverter structure, an AC coupling circuit, a strong-arm comparator, a serial peripheral interface circuit and a digital correlator;

[0006] The transformer, the envelope detection circuit, the amplifier based on the inverter structure, the AC coupling circuit and the strong-arm comparator are connected in sequence; the input end of the digital correlator is respectively connected to the output end of the strong-arm comparator and the output end of the serial peripheral interface circuit;

[0007] The transformer is used for passive impedance matching, amplifies the input OOK signal, and outputs the amplified OOK signal; the envelope detection circuit performs envelope demodulation on the input amplified OOK signal through the substrate DC voltage and outputs the baseband signal; the amplifier based on the inverter structure amplifies the input baseband signal through the bias voltage and outputs the amplified baseband signal; the AC coupling circuit filters out the DC signal in the input amplified baseband signal, and superimposes a common mode level to output the common mode differential baseband signal; the strong arm comparator compares the common mode differential baseband signal through the first clock signal and outputs a non-return-to-zero digital baseband signal;

[0008] The serial peripheral interface circuit converts the serial reference digital signal into a parallel reference digital signal through an enable signal and a second clock signal and outputs the parallel reference digital signal;

[0009] The digital correlator controls and analyzes the correlation between the input non-return-to-zero digital baseband signal and the parallel reference digital signal through a third clock signal, and outputs a digital signal; the receiver determines the wake-up state according to the digital signal.

[0010] Compared with the prior art, the present invention has the following beneficial effects:

[0011] The wake-up receiver of the present invention has low power consumption and can transmit signals over long distances. It provides passive impedance matching gain through a transformer to amplify the OOK signal once. At the same time, the envelope detection circuit performs envelope demodulation on the baseband signal. The output baseband signal still contains a low-frequency signal component, which is then amplified twice by an amplifier based on an inverter structure for long-distance communication. This compensates for the signal attenuation of the wireless signal that increases with the communication distance, and effectively improves the wake-up sensitivity of the wake-up receiver.

[0012] The present invention uses a low-power transformer and envelope detection circuit, an inverter-based amplifier, a strong-arm comparator, and a digital correlator, which have low complexity and a small circuit area, thereby reducing the power consumption of the receiver. The rated operating voltage of the receiver is lower than 1V, which extends the standby and wake-up time of the receiver.

[0013] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the following preferred embodiments are specifically cited and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 This is a structural block diagram of a low-power and high-sensitivity wake-up receiver provided by an example of the present invention;

[0015] Figure 2is a circuit diagram of a transformer provided by an example of the present invention;

[0016] Figure 3 is a circuit diagram of an envelope detection circuit provided by an example of the present invention;

[0017] Figure 4 is a circuit diagram of an amplifier based on an inverter structure provided by an embodiment of the present invention;

[0018] Figure 5 is a circuit diagram of an AC coupling circuit provided by an example of the present invention;

[0019] Figure 6 1 is a circuit diagram of a strong-arm comparator provided by an embodiment of the present invention;

[0020] Figure 7 is a circuit diagram of a serial peripheral interface circuit unit provided by an example of the present invention;

[0021] Figure 8 is a circuit diagram of a serial peripheral interface circuit provided by an embodiment of the present invention;

[0022] Figure 9 It is a circuit diagram of a signal parallel processing circuit in a digital correlator provided by an example of the present invention;

[0023] Figure 10 This is a timing diagram of different clock operations provided by an example of the present invention. DETAILED DESCRIPTION

[0024] In order to further illustrate the technical means and effects adopted by the present invention to achieve the predetermined purpose of the invention, a low-power and high-sensitivity wake-up receiver proposed according to the present invention is described in detail below with reference to the accompanying drawings and specific implementation methods.

[0025] The aforementioned and other technical contents, features, and effects of the present invention are clearly presented in the following detailed description of the specific embodiments in conjunction with the accompanying drawings. Through the description of the specific embodiments, a deeper and more specific understanding of the technical means and effects adopted by the present invention to achieve the intended purpose can be obtained. However, the accompanying drawings are provided for reference and illustration purposes only and are not intended to limit the technical solutions of the present invention.

[0026] Example 1

[0027] See Figure 1 , Figure 1 This is a structural block diagram of a low-power and high-sensitivity wake-up receiver provided by an example of the present invention.

[0028] As shown in the figure, the low-power and high-sensitivity wake-up receiver of the present invention includes: a transformer 10, an envelope detection circuit 20, an amplifier 30 based on an inverter structure, an AC coupling circuit 40, a strong-arm comparator 50, a serial peripheral interface circuit 60 and a digital correlator 70;

[0029] Among them, the transformer 10, the envelope detection circuit 20, the amplifier 30 based on the inverter structure, the AC coupling circuit 40 and the strong-arm comparator 50 are connected in sequence; the input end of the digital correlator 70 is respectively connected to the output end of the strong-arm comparator 50 and the output end of the serial peripheral interface circuit 60.

[0030] In this embodiment, the transformer 10 is used for passive impedance matching to the input OOK signal SIG IN_OOK After amplification, the amplified OOK signal is output; the envelope detection circuit 20 uses the substrate DC voltage V BULK_ED and V CO_ED The input amplified OOK signal is envelope demodulated and a baseband signal is output; the amplifier 30 based on the inverter structure is biased by the bias voltage V B0 The input baseband signal is amplified and the amplified baseband signal is output; the AC coupling circuit 40 filters out the DC signal in the input amplified baseband signal and superimposes a common mode level V COM ACCOUP Output common mode differential baseband signal; strong arm comparator 50 through the first clock signal CLK COMP The common-mode differential baseband signals are compared and a non-return-to-zero digital baseband signal is output.

[0031] In this embodiment, the serial peripheral interface circuit 60 is enabled by the enable signal EN SPI and the second clock signal CLK SPI The serial reference digital signal DATA SPI Convert to 16-bit parallel codebook and output.

[0032] In this embodiment, the digital correlator 70 uses the third clock signal CLK CORR The correlation between the input non-return-to-zero digital baseband signal and the parallel reference digital signal is controlled and analyzed, and the digital signal D is output. OUT<4:0> ; The receiver is based on the digital signal D OUT<4:0> Determine the wake-up state.

[0033] In an optional embodiment, for the wake-up receiver, the modulation method of its input signal mainly includes: amplitude shift keying, frequency shift keying and phase shift keying. Here, the input signal adopts the binary modulation and demodulation modulation method in amplitude shift keying, also known as the on-off keying method to obtain the signal, that is, the OOK signal.

[0034] See Figure 2 , Figure 2 1 is a circuit diagram of a transformer provided by an example of the present invention.

[0035] As shown in the figure, the transformer 10 of the present invention is a high-Q transformer for providing passive impedance matching gain, and includes a two-stage impedance matching circuit;

[0036] Among them, the primary impedance matching circuit includes: a parallel resistor R1, a primary capacitor C1 and a primary inductor L1; the resistor R1 is used for impedance matching to receive the RF input signal, and the primary capacitor C1 and the primary inductor L1 are used to resonate in the ISM frequency band; the secondary impedance matching circuit includes: a parallel resistor R2, a secondary capacitor C2 and a secondary inductor L2; the primary inductor L1 and the secondary inductor L2 form a transformer for amplifying the input OOK signal, and the secondary capacitor C2 is used to compensate for the passive amplification factor and output it.

[0037] In this embodiment, the transformer 10 receives the OOK signal SIG. IN_OOK After amplification, it is used by the subsequent envelope detection circuit 20, providing a passive voltage gain of 20dB and improving the system sensitivity. The transformer 10 changes the input equivalent impedance of the subsequent circuit from high resistance to an input equivalent of 50Ω when viewed from the transformer, ensuring maximum power transmission and reception between the external transmitting antenna and the signal source, that is, impedance matching, and ensuring that the reflection coefficient is less than -10dB.

[0038] In this embodiment, the two-stage LC network in the transformer 10 is used for narrowband filtering. The output high-impedance node ensures that the signal can be fully delivered to the next-stage circuit. The resonant frequency f, that is, the carrier frequency, is determined by the LC network:

[0039]

[0040] Wherein, w0 is the resonant angular frequency; f is the resonant frequency; L1 is the inductance of the primary inductor; L2 is the inductance of the secondary inductor; C1 is the capacitance of the primary capacitor; C2 is the capacitance of the secondary capacitor.

[0041] Under ideal conditions, the input and output powers of the LC network are equal, that is, losses are not considered:

[0042]

[0043] Wherein, Z1 is the impedance of the primary inductor L1; Z2 is the impedance of the secondary inductor L2; V1 is the voltage on the primary inductor L1; V2 is the voltage on the secondary inductor L2; and n is the turns ratio of the secondary inductor L2 to the primary inductor L1.

[0044]

[0045] That is:

[0046] C2=(1 / n 2 )C1 (3.1);

[0047] L2=n 2 L1 (3.2);

[0048] Among them, C1 is the capacitance value of the primary capacitor C1; C2 is the capacitance value of the secondary capacitor C2; L1 is the inductance value of the primary inductor L1; L2 is the inductance value of the secondary inductor L2; R1 is the equivalent resistance of the external input signal source; R2 is the input equivalent resistance of the envelope detection circuit.

[0049] Since the envelope detection circuit 20 operates in a subthreshold state, R1 is typically a low resistance of 50 ohms, and R2 is a high resistance of tens of megohms to hundreds of megohms. Therefore, the voltage V2 on the secondary inductor L2 is amplified, that is, the transformer 10 provides voltage gain, thereby improving the sensitivity of the receiver.

[0050] In an optional embodiment, transformer 10 is fabricated using an off-chip printed circuit board design. This reduces the trade-off between capacitor and inductor size compared to an on-chip design, enabling wireless long-distance applications below the gigahertz frequency. Matching networks with varying bandwidths and frequencies can be designed to meet specific requirements, broadening the application scope.

[0051] See Figure 3 , Figure 3 1 is a circuit diagram of an envelope detection circuit provided by an example of the present invention.

[0052] As shown in the figure, the envelope detection circuit 20 of the present invention includes: NMOS transistors Mn1, Mn2, Mn3, Mn4, Mn5, Mn6, Mn7, Mn8, Mn9, Mn10, Mn11, Mn12, Mn13, Mn14, Mn15, Mn16, capacitors C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17, and C18.

[0053] In an optional embodiment, NMOS transistors Mn1, Mn2, Mn3, Mn4, Mn5, Mn6, Mn7, and Mn8 are connected in sequence, with the source of the preceding NMOS transistor connected to the drain of the succeeding NMOS transistor, to form a first path; the drain of NMOS transistor Mn1 is input with the first substrate DC voltage V CO The source of the NMOS tube Mn8 serves as the first output terminal V of the envelope detection circuit 20. OUT2 .

[0054] In an optional embodiment, in the first path, the gate of each NMOS transistor is connected to its respective drain; the first plates of capacitors C3, C4, C5, C6, C7, C8, C9, and C10 are connected to the sources of NMOS transistors Mn1, Mn2, Mn3, Mn4, Mn5, Mn6, Mn7, and Mn8 respectively; and the second plates of capacitors C3, C5, C7, and C9 are all connected to the output terminal V of transformer 10. OUT1 The second plates of capacitors C4, C6, C8 and C10 are all connected to the first substrate DC voltage V CO .

[0055] In an optional embodiment, NMOS transistors Mn9, Mn10, Mn11, Mn12, Mn13, Mn14, Mn15, and Mn16 are connected in sequence, with the drain of the preceding NMOS transistor connected to the source of the succeeding NMOS transistor, to form a second path; the source of NMOS transistor Mn9 is input with the first substrate DC voltage V CO The drain of the NMOS tube Mn16 serves as the second output terminal V of the envelope detection circuit 20. OUT3 .

[0056] In an optional embodiment, in the second path, the gate of each NMOS transistor is connected to its respective drain; the first plates of capacitors C11, C12, C13, C14, C15, C16, C17, and C18 are connected to the drains of NMOS transistors Mn9, Mn10, Mn11, Mn12, Mn13, Mn14, Mn15, and Mn16 respectively; and the second plates of capacitors C11, C13, C15, and C17 are all connected to the output terminal V of transformer 10. OUT1The second plates of capacitors C12, C14, C16 and C18 are all input with the first substrate DC voltage V CO .

[0057] In an optional embodiment, in the first path and the second path, the substrates of all NMOS transistors are input with the second substrate DC voltage V BULK .

[0058] In an optional embodiment, since the wake-up receiver only needs to determine whether the received digital signal is a wake-up signal and then wake up according to the wake-up signal, there is no requirement for the linearity of the digital signal. At the same time, considering the low power consumption performance of the wake-up receiver, a passive Dickson detector is used as the envelope detection circuit 20 of this embodiment to perform envelope demodulation on the input amplified OOK signal to obtain the baseband information therein; the resistor, capacitor and MOS tube path in the envelope detection circuit 20 constitute a passive circuit, and its power consumption during demodulation is close to 0W; compared with the active envelope detector, the power consumption of the passive envelope detector is reduced by 2 to 3 orders of magnitude. At the same time, the passive envelope detector reduces the flicker noise of the active device.

[0059] In an optional embodiment, a passive network detector is used, in which each MOS transistor is used only as a diode, that is, the MOS transistor only acts as a capacitor or resistor. When the input amplified OOK signal sends a "1", the input capacitor provides a path, and the MOS transistors in the path form several stages. The output signal of the envelope detection circuit 20 is superimposed as the number of stages increases. When the input is "0", the input coupling capacitor does not provide a DC path, and the output signal is discharged to 0 through envelope detection. Since the excitation signal is extremely weak, the third-order and higher components are ignored. The envelope detection circuit 20 operates under the square law, and its output voltage V OUT It is proportional to the input RF power, that is:

[0060]

[0061] Among them, V OUT is the output voltage of the envelope detection circuit; V D is the input voltage of the envelope detection circuit;

[0062] μ D is the input RF power proportional coefficient of the envelope detection circuit, which is:

[0063]

[0064] Where n′ is the subthreshold slope of the MOS tube in the envelope detection circuit working in the subthreshold region; V T is the thermal voltage, which is 25.9mV at room temperature.

[0065] In an optional embodiment, the output voltage V of the envelope detection circuit 20 is OUT With input voltage V IN It is proportional to the square of , indicating that the reduction of input voltage amplitude further reduces the output voltage amplitude. At the same time, the double-ended output provides a gain of about 2 times for the output voltage amplitude, which helps to improve the sensitivity of the wake-up receiver.

[0066] In an optional embodiment, the envelope detection circuit 20 obtains a double-ended output by using a single-ended input, thereby increasing the output signal swing and the input signal sensitivity to 6 dB.

[0067] In an optional embodiment, the envelope detection circuit 20 uses the substrate DC voltage V BULK_ED and V CO_ED Realize detection and demodulation under different temperatures and process devices.

[0068] See Figure 4 , Figure 4 1 is a circuit diagram of an amplifier based on an inverter structure provided by an example of the present invention.

[0069] As shown in the figure, the amplifier 30 based on the inverter structure of the present invention includes: PMOS transistor Mp1, PMOS transistor Mp2, PMOS transistor Mp3, NMOS transistor Mn17, NMOS transistor Mn18, NMOS transistor Mn19, NMOS transistor Mn20 and NMOS transistor Mn21.

[0070] In an optional embodiment, the source of the PMOS transistor Mp1 is connected to the source of the PMOS transistor Mp2 and to the drain of the PMOS transistor Mp3; the gate of the PMOS transistor Mp1 is connected to the gate of the NMOS transistor Mn17 and to the first output terminal V of the envelope detection circuit 20. OUT2 The drain of the PMOS tube Mp1 is connected to the drain of the NMOS tube Mn17 and serves as the first output terminal V of the amplifier 30 based on the inverter structure. OUT4 .

[0071] In an optional embodiment, the gate of the PMOS transistor Mp2 is connected to the gate of the NMOS transistor Mn18 and is also connected to the second output terminal V of the envelope detection circuit 20. OUT3 The drain of the PMOS tube Mp2 is connected to the drain of the NMOS tube Mn18 and serves as the second output terminal V of the amplifier 30 based on the inverter structure. OUT5 .

[0072] In an optional embodiment, the source of the PMOS transistor Mp3 is connected to its substrate and to the power supply voltage terminal VDD; the gate of the PMOS transistor Mp3 is connected to the gate of the NMOS transistor Mn21 and to the bias voltage terminal VDD. B .

[0073] In an optional embodiment, the source of the NMOS transistor Mn21 is connected to its drain, and the substrate of the NMOS transistor Mn21 is connected to the ground terminal GND; the source of the NMOS transistor Mn17 is respectively connected to the source of the NMOS transistor Mn18, the drain of the NMOS transistor Mn19, and the drain of the NMOS transistor Mn20; the gate of the NMOS transistor Mn19 is connected to the drain of the NMOS transistor Mn17; the gate of the NMOS transistor Mn20 is connected to the gate of the NMOS transistor Mn18; the source of the NMOS transistor Mn19 is connected to the source of the NMOS transistor Mn20, and is connected in parallel to the ground terminal GND.

[0074] In an optional embodiment, the amplifier 30 based on the inverter structure uses a single-stage amplifier structure, which ensures the stability of the amplifier while having lower energy loss than a two-pole comparator with the same amplification factor.

[0075] In an optional embodiment, compared with a traditional common-source amplifier, the amplifier 30 based on the inverter structure distributes the signal to the MOS tube, which increases the input transconductance and improves the gain while saving the bias voltage generation circuit of the load tube, thereby reducing the power consumption of the overall operational amplifier. At the same time, large-size transistors are used to reduce flicker noise, which has a lower noise contribution.

[0076] When the input tube works in low power consumption state, it is in sub-threshold state, and its equivalent current model is:

[0077]

[0078] Among them, I D is the leakage current value flowing through the MOS tube in the amplifier based on the inverter structure; W is the width of the MOS tube; L is the length of the MOS tube; I DO is the process parameter of MOS tube; q is the charge; v GS is the gate-source voltage difference of the MOS tube; T is the Kelvin temperature; n″ is the subthreshold slope; k is the Boltzmann constant;

[0079] Since the operating voltage is below 1V, the v GS , because v GS with I D An exponential relationship, so that I D It is also very small, which means that the power consumption requirements are reduced in terms of both voltage and current.

[0080] See Figure 5 , Figure 5 4 is a circuit diagram of an AC coupling circuit provided by an example of the present invention.

[0081] As shown in the figure, the AC coupling circuit 40 of the present invention includes: an NMOS transistor Mn22, an NMOS transistor Mn23, an NMOS transistor Mn24, a capacitor C19 and a capacitor C20.

[0082] In an optional embodiment, the gate of the NMOS transistor Mn22 is connected to the drain of the NMOS transistor Mn22 and the first plate of the capacitor C19, and serves as the first output terminal V of the AC coupling circuit 40. OUT6 The second plate of capacitor C19 is connected to the first output terminal V of the amplifier 30 based on the inverter structure OUT4 The source of NMOS tube Mn22 is connected to its substrate and the source of NMOS tube Mn23, and is connected to the common mode level terminal V COM .

[0083] In an optional embodiment, the source of the NMOS transistor Mn23 is connected to its substrate; the gate of the NMOS transistor Mn23 is connected to its drain and the first plate of the capacitor C20, and serves as the second output terminal V of the AC coupling circuit 40. OUT7 The second plate of capacitor C20 is connected to the second output terminal V of the amplifier 30 based on the inverter structure OUT5 The gate of the NMOS tube Mn24 is connected to the common-mode level terminal VCOM; the source of the NMOS tube Mn24 is connected to its drain, and the substrate of the NMOS tube Mn24 is connected to the power supply voltage terminal.

[0084] It is worth noting that since the operating frequency and operating current are very low, in order to avoid the capacitor occupying too large a chip area, a small capacitor is used for DC isolation in the AC coupling circuit 40. At the same time, to avoid voltage division by the small capacitor, a diode-connected MOS tube is used as a large resistor.

[0085] See Figure 6 , Figure 6 1 is a circuit diagram of a strong-arm comparator provided by an example of the present invention.

[0086] As shown in the figure, the strong-arm comparator 50 of the present invention includes: PMOS transistor Mp4, PMOS transistor Mp5, PMOS transistor Mp6, PMOS transistor Mp7, PMOS transistor Mp8, PMOS transistor Mp9, PMOS transistor Mp10, PMOS transistor Mp11, NMOS transistor Mn25, NMOS transistor Mn26, NMOS transistor Mn27, NMOS transistor Mn28, NMOS transistor Mn29, NMOS transistor Mn30, NMOS transistor Mn31, NMOS transistor Mn32 and NMOS transistor Mn33.

[0087] In an optional embodiment, the sources of the PMOS transistor Mp4, PMOS transistor Mp5, PMOS transistor Mp6, PMOS transistor Mp7, PMOS transistor Mp8 and PMOS transistor Mp9 are connected and connected to the power supply voltage terminal VDD; the gate of the PMOS transistor Mp4 is respectively connected to the drain of the PMOS transistor Mp5, the drain of the PMOS transistor Mp8, the gate of the NMOS transistor Mn25, the drain of the NMOS transistor Mn26 and the input end of the inverter INV1; the drain of the PMOS transistor Mp4 is respectively connected to the gate of the PMOS transistor Mp5, the drain of the PMOS transistor Mp6, the drain of the NMOS transistor Mn25, the gate of the NMOS transistor Mn26 and the input end of the inverter INV2.

[0088] In an optional embodiment, the gate of the PMOS transistor Mp6 is connected to the gate of the PMOS transistor Mp7 and inputs the first clock signal CLK COMP The gate of the PMOS tube Mp8 is connected to the gate of the PMOS tube Mp9 and inputs the first clock signal CLK COMP The drain of the PMOS tube Mp7 is connected to the source of the NMOS tube Mn25 and the drain of the NMOS tube Mn27 respectively; the drain of the PMOS tube Mp9 is connected to the source of the NMOS tube Mn26 and the drain of the NMOS tube Mn28 respectively.

[0089] In an optional embodiment, the gate of the NMOS transistor Mn27 is connected to the first output terminal V of the AC coupling circuit 40. OUT6 The gate of the NMOS tube Mn28 is connected to the second output terminal V of the AC coupling circuit 40 OUT7 The source of the NMOS tube Mn27 is connected to the source of the NMOS tube Mn28 and the drain of the NMOS tube Mn29; the gate of the NMOS tube Mn29 inputs the first clock signal CLK COMP , the source of the NMOS tube Mn29 is connected to the ground terminal GND.

[0090] In an optional embodiment, the source of the PMOS transistor Mp10 is connected to the source of the PMOS transistor Mp11 and to the power supply voltage terminal VDD; the gate of the PMOS transistor Mp10 is respectively connected to the drain of the PMOS transistor Mp11, the drain of the NMOS transistor Mn31, the gate of the NMOS transistor Mn32 and the drain of the NMOS transistor Mn33, and serves as the second output terminal VDD of the strong-arm comparator 50. OUT9 The drain of the PMOS tube Mp10 is connected to the gate of the PMOS tube Mp11, the drain of the NMOS tube Mn30, the drain of the NMOS tube Mn32 and the gate of the NMOS tube Mn33, and serves as the first output terminal V of the strong arm comparator 50. OUT8 .

[0091] In an optional embodiment, the gate of the NMOS transistor Mn30 is connected to the output end of the inverter INV2; the gate of the NMOS transistor Mn31 is connected to the output end of the inverter INV1; and the sources of the NMOS transistors Mn30, Mn31, Mn32 and Mn33 are all connected to the ground end GND.

[0092] In one optional embodiment, the strong-arm comparator 50 includes a strong-arm latch and an RS latch. The output of the strong-arm latch is fed to the RS latch via an inverter, reducing system kickback noise via input capacitance. The RS latch latches the incoming signal until the next clock signal arrives. The strong-arm comparator 50 acts as a 1-bit analog-to-digital converter to convert the analog signal into a digital signal, which is then directly output to the subsequent digital correlator 70. This avoids the use of current analog-to-digital logic circuits and simplifies the circuit scale.

[0093] Please refer to Figure 7 and Figure 8 , Figure 7 is a circuit diagram of a serial peripheral interface circuit unit provided by an example of the present invention; Figure 8 It is a circuit diagram of a serial peripheral interface circuit provided by an example of the present invention.

[0094] As shown in the figure, the serial peripheral interface circuit 60 of the present invention includes a plurality of serial basic units connected in series, where the output end of the previous serial basic unit is connected to the first input end of the next serial basic unit;

[0095] The serial basic units have the same structure, including: a D flip-flop D1 , a transmission gate S01 , a transmission gate S02 , an inverter INV3 , an inverter INV4 , and an inverter INV5 .

[0096] In an optional embodiment, the first input terminal of the D flip-flop D1 serves as the first input terminal of the serial basic unit and inputs the serial reference digital signal DATA SPI The second input terminal of the D flip-flop D1 serves as the second input terminal of the serial basic unit and inputs the second clock signal CLK SPI , the output of D flip-flop D1 is connected to the input of transmission gate S01, and the parallel output Z <0> :Z <15> .

[0097] In an optional embodiment, the high-level effective end of the transmission gate S01, the low-level effective end of the transmission gate S02 and the input end of the inverter INV5 are all connected to the enable signal end EN, and the output end of the inverter INV5 is respectively connected to the low-level effective end of the transmission gate S01 and the high-level effective end of the transmission gate S02; the input end of the transmission gate S02 is connected to the ground end GND; the output ends of the transmission gate S01 and the transmission gate S02 are both connected to the input end of the inverter INV3; the output end of the inverter INV3 is connected to the input end of the inverter INV4, and the output end of the inverter INV4 serves as the output end of the serial basic unit.

[0098] See Figure 9 , Figure 9 It is a circuit diagram of a signal parallel processing circuit in a digital correlator provided by an example of the present invention.

[0099] As shown in the figure, the digital correlator 70 includes a signal parallel processing circuit and an adder circuit;

[0100] The signal parallel processing circuit includes: a plurality of parallel basic units connected in series, each parallel basic unit has the same structure, and includes: a parallel D flip-flop and an XOR gate; the output end of the parallel D flip-flop of the previous parallel basic unit is connected to the first input end of the parallel D flip-flop of the next parallel basic unit; the output end of the parallel D flip-flop is connected to the first input end of the XOR gate, and the second input end of the parallel D flip-flop is input with a third clock signal CLK CORR The second input end of the XOR gate is connected to the output end of the serial basic unit, and the output end of the XOR gate is connected to the input end of the adder circuit.

[0101] In an optional embodiment, the adder circuit includes several full adder circuits, wherein the full adder circuit includes two cascaded stages of half adder circuits.

[0102] In an optional embodiment, the digital correlator 70 calculates the Hamming distance between the demodulated signal and the 16-bit parallel codebook output by the serial peripheral interface circuit 60 based on the comparison result of the strong-arm comparator 50, determines the circuit logic value, and thus determines whether a wake-up signal exists. The digital correlator 70 uses two times oversampling to ensure that the parallel D flip-flop captures the correct input, and converts the 16-bit comparison result into a binary result through an adder circuit to facilitate the determination of the wake-up signal. As a matched filter, the digital correlator completes signal determination by maximizing the signal-to-noise ratio of the output signal at a certain moment. In addition, the code length of the wake-up signal is typically 10-32 bits. The digital correlator consumes little hardware and can still operate at low voltages.

[0103] See Figure 10 , Figure 10 This is a timing diagram of different clock operations provided by an example of the present invention.

[0104] In this embodiment, the second clock signal CLK SPI After working for several cycles, the data of the serial peripheral interface circuit 60 is no longer updated, and the serial reference digital signal DATA SPI Periodically send data, enable signal EN SPI Before the clock signal starts to arrive, it is set and kept at a high level. After setting, the serial peripheral interface circuit 60 works. The first clock signal CLK COMP and the third clock signal CLK CORR The square wave signal generated at the same frequency is input into the strong arm comparator 50 and the digital correlator 70 .

[0105] The wake-up receiver of the embodiment of the present invention has low power consumption and can transmit signals over long distances. The transformer provides passive impedance matching gain to amplify the OOK signal once. At the same time, the envelope detection circuit performs envelope demodulation on the baseband signal. The output baseband signal still contains a low-frequency signal component, which is then amplified twice by an amplifier based on an inverter structure for long-distance communication. This compensates for the signal attenuation of the wireless signal that increases with the communication distance, and effectively improves the wake-up sensitivity of the wake-up receiver.

[0106] The wake-up receiver of an embodiment of the present invention uses a low-power transformer and envelope detection circuit, an inverter-based amplifier, a strong-arm comparator, and a digital correlator. This reduces complexity and circuit area, reduces receiver power consumption, and allows the rated operating voltage of the receiver to be lower than 1V, thereby extending the receiver's standby and wake-up time.

[0107] It should be noted that, in this document, relational terms such as first and second are used solely to distinguish one entity or operation from another, and do not necessarily require or imply any actual relationship or order between these entities or operations. Furthermore, the terms "comprise," "include," or any other variations thereof are intended to encompass non-exclusive inclusion, such that an article or device comprising a list of elements includes not only those elements but also other elements not explicitly listed. Without further limitation, an element defined by the phrase "comprising a..." does not preclude the presence of additional identical elements in the article or device comprising the element. Terms such as "connected" or "connected" are not limited to physical or mechanical connections but may include electrical connections, whether direct or indirect. References to orientations or positional relationships, such as "upper," "lower," "left," and "right," are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate description and simplify the description of the present invention. They do not indicate or imply that the device or element referred to must have, be constructed, or operate in a specific orientation, and are therefore not to be construed as limiting the present invention.

[0108] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. A low-power and high-sensitivity wake-up receiver, characterized in that: include: A transformer (10), an envelope detection circuit (20), an amplifier based on an inverter structure (30), an AC coupling circuit (40), a strong arm comparator (50), a serial peripheral interface circuit (60), and a digital correlator (70); The transformer (10), the envelope detection circuit (20), the amplifier (30) based on the inverter structure, the AC coupling circuit (40) and the strong-arm comparator (50) are connected in sequence; the input end of the digital correlator (70) is respectively connected to the output end of the strong-arm comparator (50) and the output end of the serial peripheral interface circuit (60); The transformer (10) is used for passive impedance matching, amplifies the input OOK signal, and outputs the amplified OOK signal; the envelope detection circuit (20) performs envelope demodulation on the input amplified OOK signal through the substrate DC voltage and outputs the baseband signal; the amplifier (30) based on the inverter structure amplifies the input baseband signal through the bias voltage and outputs the amplified baseband signal; the AC coupling circuit (40) filters the DC signal in the input amplified baseband signal and superimposes a common mode level to output a common mode differential baseband signal; the strong arm comparator (50) compares the common mode differential baseband signal through the first clock signal and outputs a non-return-to-zero digital baseband signal; The serial peripheral interface circuit (60) converts the serial reference digital signal into a parallel reference digital signal through an enable signal and a second clock signal and outputs the signal; the digital correlator (70) controls and analyzes the correlation between the input non-return-to-zero digital baseband signal and the parallel reference digital signal through a third clock signal and outputs a digital signal; the receiver determines the wake-up state according to the digital signal.

2. The low-power and high-sensitivity wake-up receiver according to claim 1, characterized in that: The envelope detection circuit (20) comprises: an NMOS transistor Mn1, an NMOS transistor Mn2, an NMOS transistor Mn3, an NMOS transistor Mn4, an NMOS transistor Mn5, an NMOS transistor Mn6, an NMOS transistor Mn7, an NMOS transistor Mn8, an NMOS transistor Mn9, an NMOS transistor Mn10, an NMOS transistor Mn11, an NMOS transistor Mn12, an NMOS transistor Mn13, an NMOS transistor Mn14, an NMOS transistor Mn15, an NMOS transistor Mn16, a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6, a capacitor C7, a capacitor C8, a capacitor C9, a capacitor C10, a capacitor C11, a capacitor C12, a capacitor C13, a capacitor C14, a capacitor C15, a capacitor C16, a capacitor C17 and a capacitor C18; The NMOS transistors Mn1, Mn2, Mn3, Mn4, Mn5, Mn6, Mn7, and Mn8 are connected in sequence, with the source of the preceding NMOS transistor connected to the drain of the succeeding NMOS transistor, to form a first path. The drain of the NMOS tube Mn1 inputs the first substrate DC voltage (V CO ), the source of the NMOS tube Mn8 serves as the first output terminal (V OUT2 ); In the first path, the gate of each NMOS tube is connected to its own drain; The first plates of the capacitor C3, the capacitor C4, the capacitor C5, the capacitor C6, the capacitor C7, the capacitor C8, the capacitor C9 and the capacitor C10 are connected to the source electrodes of the NMOS transistors Mn1, the NMOS transistors Mn2, the NMOS transistors Mn3, the NMOS transistors Mn4, the NMOS transistors Mn5, the NMOS transistors Mn6, the NMOS transistors Mn7 and the NMOS transistors Mn8 respectively; the second plates of the capacitors C3, the capacitors C5, the capacitors C7 and the capacitors C9 are all connected to the output terminal (V OUT1 ), the second plates of the capacitors C4, C6, C8 and C10 are all connected to input the first substrate DC voltage (V CO ); The NMOS transistors Mn9, Mn10, Mn11, Mn12, Mn13, Mn14, Mn15, and Mn16 are connected in sequence, with the drain of the preceding NMOS transistor connected to the source of the succeeding NMOS transistor, to form a second path; The source of the NMOS tube Mn9 inputs the first substrate DC voltage (V CO ), the drain of the NMOS tube Mn16 serves as the second output terminal (V OUT3 ); In the second path, the gate of each NMOS tube is connected to its own drain; The first plates of the capacitor C11, the capacitor C12, the capacitor C13, the capacitor C14, the capacitor C15, the capacitor C16, the capacitor C17 and the capacitor C18 are connected to the drains of the NMOS transistors Mn9, the NMOS transistors Mn10, the NMOS transistors Mn11, the NMOS transistors Mn12, the NMOS transistors Mn13, the NMOS transistors Mn14, the NMOS transistors Mn15 and the NMOS transistors Mn16 respectively; the second plates of the capacitors C11, the capacitors C13, the capacitors C15 and the capacitors C17 are all connected to the output terminal (V OUT1 The second plates of the capacitor C12, the capacitor C14, the capacitor C16 and the capacitor C18 are all input with the first substrate DC voltage (V CO ); In the first path and the second path, the substrates of all NMOS transistors are input with the second substrate DC voltage (V BULK ).

3. The low-power and high-sensitivity wake-up receiver according to claim 2, characterized in that: The amplifier (30) based on the inverter structure comprises: a PMOS tube Mp1, a PMOS tube Mp2, a PMOS tube Mp3, an NMOS tube Mn17, an NMOS tube Mn18, an NMOS tube Mn19, an NMOS tube Mn20 and an NMOS tube Mn21; The source of the PMOS transistor Mp1 is connected to the source of the PMOS transistor Mp2 and to the drain of the PMOS transistor Mp3; The gate of the PMOS transistor Mp1 is connected to the gate of the NMOS transistor Mn17 and is also connected to the first output terminal (V OUT2 The drain of the PMOS tube Mp1 is connected to the drain of the NMOS tube Mn17 and serves as the first output terminal (V OUT4 ); The gate of the PMOS transistor Mp2 is connected to the gate of the NMOS transistor Mn18 and is also connected to the second output terminal (V OUT3 The drain of the PMOS tube Mp2 is connected to the drain of the NMOS tube Mn18 and serves as the second output terminal (V OUT5 ); The source of the PMOS transistor Mp3 is connected to its substrate and to the power supply voltage terminal (VDD); the gate of the PMOS transistor Mp3 is connected to the gate of the NMOS transistor Mn21 and to the bias voltage terminal (V B ); The source of the NMOS transistor Mn21 is connected to its drain, and the substrate of the NMOS transistor Mn21 is connected to the ground terminal (GND); The source of the NMOS transistor Mn17 is connected to the source of the NMOS transistor Mn18, the drain of the NMOS transistor Mn19, and the drain of the NMOS transistor Mn20 respectively; the gate of the NMOS transistor Mn19 is connected to the drain of the NMOS transistor Mn17; the gate of the NMOS transistor Mn20 is connected to the gate of the NMOS transistor Mn18; The source of the NMOS transistor Mn19 is connected to the source of the NMOS transistor Mn20 and connected in parallel to the ground terminal (GND).

4. The low-power and high-sensitivity wake-up receiver according to claim 3, characterized in that: The AC coupling circuit (40) includes: an NMOS transistor Mn22, an NMOS transistor Mn23, an NMOS transistor Mn24, a capacitor C19, and a capacitor C20; The gate of the NMOS transistor Mn22 is connected to the drain of the NMOS transistor Mn22 and the first plate of the capacitor C19, respectively, and serves as the first output terminal (V OUT6 The second plate of the capacitor C19 is connected to the first output terminal (V OUT4 The source of the NMOS transistor Mn22 is connected to its substrate and the source of the NMOS transistor Mn23, and is connected to the common mode level terminal (V COM ); The source of the NMOS transistor Mn23 is connected to its substrate; the gate of the NMOS transistor Mn23 is respectively connected to its drain and the first plate of the capacitor C20, and serves as the second output terminal (V OUT7 The second plate of the capacitor C20 is connected to the second output terminal (V OUT5 ); The gate of the NMOS transistor Mn24 is connected to the common-mode level terminal (VCOM); the source of the NMOS transistor Mn24 is connected to its drain; and the substrate of the NMOS transistor Mn24 is connected to the power supply voltage terminal.

5. The low-power and high-sensitivity wake-up receiver according to claim 4, characterized in that: The strong-arm comparator (50) comprises: a PMOS tube Mp4, a PMOS tube Mp5, a PMOS tube Mp6, a PMOS tube Mp7, a PMOS tube Mp8, a PMOS tube Mp9, a PMOS tube Mp10, a PMOS tube Mp11, an NMOS tube Mn25, an NMOS tube Mn26, an NMOS tube Mn27, an NMOS tube Mn28, an NMOS tube Mn29, an NMOS tube Mn30, an NMOS tube Mn31, an NMOS tube Mn32 and an NMOS tube Mn33; The sources of the PMOS transistor Mp4, the PMOS transistor Mp5, the PMOS transistor Mp6, the PMOS transistor Mp7, the PMOS transistor Mp8, and the PMOS transistor Mp9 are connected and connected to the power supply voltage terminal (VDD); The gate of the PMOS transistor Mp4 is respectively connected to the drain of the PMOS transistor Mp5, the drain of the PMOS transistor Mp8, the gate of the NMOS transistor Mn25, the drain of the NMOS transistor Mn26 and the input end of the inverter INV1; The drain of the PMOS transistor Mp4 is respectively connected to the gate of the PMOS transistor Mp5, the drain of the PMOS transistor Mp6, the drain of the NMOS transistor Mn25, the gate of the NMOS transistor Mn26 and the input end of the inverter INV2; The gate of the PMOS transistor Mp6 is connected to the gate of the PMOS transistor Mp7 and inputs the first clock signal; the gate of the PMOS transistor Mp8 is connected to the gate of the PMOS transistor Mp9 and inputs the first clock signal; The drain of the PMOS transistor Mp7 is connected to the source of the NMOS transistor Mn25 and the drain of the NMOS transistor Mn27; the drain of the PMOS transistor Mp9 is connected to the source of the NMOS transistor Mn26 and the drain of the NMOS transistor Mn28; The gate of the NMOS tube Mn27 is connected to the first output terminal (V OUT6 The gate of the NMOS tube Mn28 is connected to the second output terminal (V OUT7 ); The source of the NMOS transistor Mn27 is connected to the source of the NMOS transistor Mn28 and the drain of the NMOS transistor Mn29 respectively; The gate of the NMOS transistor Mn29 inputs the first clock signal, and the source of the NMOS transistor Mn29 is connected to the ground terminal (GND); The source of the PMOS tube Mp10 is connected to the source of the PMOS tube Mp11 and to the power supply voltage terminal (VDD); the gate of the PMOS tube Mp10 is respectively connected to the drain of the PMOS tube Mp11, the drain of the NMOS tube Mn31, the gate of the NMOS tube Mn32 and the drain of the NMOS tube Mn33, and serves as the second output terminal (V OUT9 The drain of the PMOS tube Mp10 is respectively connected to the gate of the PMOS tube Mp11, the drain of the NMOS tube Mn30, the drain of the NMOS tube Mn32 and the gate of the NMOS tube Mn33, and serves as the first output terminal (V OUT8 ); The gate of the NMOS transistor Mn30 is connected to the output end of the inverter INV2; the gate of the NMOS transistor Mn31 is connected to the output end of the inverter INV1; The sources of the NMOS transistor Mn30 , the NMOS transistor Mn31 , the NMOS transistor Mn32 , and the NMOS transistor Mn33 are all connected to the ground terminal (GND).

6. The low-power and high-sensitivity wake-up receiver according to claim 5, characterized in that: The serial peripheral interface circuit (60) comprises a plurality of serial basic units connected in series, wherein the output end of the previous serial basic unit is connected to the first input end of the next serial basic unit; The serial basic units have the same structure, and all include: a D flip-flop D1, a transmission gate S01, a transmission gate S02, an inverter INV3, an inverter INV4 and an inverter INV5; The first input terminal of the D flip-flop D1 serves as the first input terminal of the serial basic unit and inputs the serial reference digital signal. The second input terminal of the D flip-flop D1 serves as the second input terminal of the serial basic unit and inputs the second clock signal. The output terminal of the D flip-flop D1 is connected to the input terminal of the transmission gate S01. The high-level active end of the transmission gate S01, the low-level active end of the transmission gate S02, and the input end of the inverter INV5 are all connected to the enable signal end (EN), and the output end of the inverter INV5 is connected to the low-level active end of the transmission gate S01 and the high-level active end of the transmission gate S02 respectively; The input terminal of the transmission gate S02 is connected to the ground terminal (GND); The output ends of the transmission gate S01 and the transmission gate S02 are both connected to the input end of the inverter INV3; the output end of the inverter INV3 is connected to the input end of the inverter INV4, and the output end of the inverter INV4 serves as the output end of the serial basic unit.

7. The low-power and high-sensitivity wake-up receiver according to claim 6, characterized in that: The digital correlator (70) includes a signal parallel processing circuit and an adder circuit; The signal parallel processing circuit includes: a plurality of parallel basic units connected in series, each of which has the same structure, including: a parallel D flip-flop and an XOR gate; Wherein, the output end of the parallel D flip-flop of the previous parallel basic unit is connected to the first input end of the parallel D flip-flop of the next parallel basic unit; The output end of the parallel D flip-flop is connected to the first input end of the XOR gate, the second input end of the parallel D flip-flop inputs the third clock signal, the second input end of the XOR gate is connected to the output end of the serial basic unit, and the output end of the XOR gate is connected to the input end of the adder circuit.

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