A multi-machine parallel high-speed communication interconnection method and system based on FPGA

Abstract

The application discloses a kind of based on FPGA multi-machine parallel high-speed communication interconnection method and system, the method includes the following steps: communication is carried out using the form of communication structure of annular first and last connection;Data conversion interface definition;Cross clock domain processing;Definition digital frame structure;Real-time fault processing;Communication frame cycle;Network disconnect detection.The application uses electric signal or optical signal for transmission, realizes multi-machine intercommunication, and uses extremely simple frame structure and sufficient reliable frame data checking method, realizes data transmission zero error, low delay, strong interference resistance, data high reliability, real-time control can be realized between multiple machines, better synchronism, with fault real-time transmission and processing capacity, the operation of power system is more stable and reliable.

Description

Technical Field

[0001] The present invention relates to the field of power electronics technology, and in particular to a method and system for high-speed communication interconnection of multiple machines in parallel based on FPGA. Background Art

[0002] In recent years, with the rapid development of the domestic economy, the demand for electricity from industry and users has been rising year by year, and the requirements for the stability of the power supply system have become increasingly higher. The overall system capacity demand has become increasingly larger, which has greatly promoted the digitalization and intelligence of the inverter power supply industry. With the development of inverter technology, especially the multi-machine parallel technology of energy storage inverters, it has also made rapid progress. The single-machine capacity design is getting larger and larger. The inverter products of various manufacturers have begun to support parallel functions to meet the design requirements of high power and redundancy. In centralized power station applications, the power response time and consistency requirements are extremely high. In the multi-machine parallel working mode, the synchronization and operation consistency of different devices are also required to be gradually improved. In order to solve such problems, wireless control methods or CAN communication control methods are usually adopted. Wireless solutions can solve some parallel problems, but due to the hardware differences between multiple inverters, poor consistency leads to cumulative deviations during operation, and the synchronization between multiple machines is very poor, even affecting system operation. Summary of the Invention

[0003] The purpose of the present invention is to provide a method and system for high-speed communication interconnection of multiple machines in parallel based on FPGA, so as to solve the technical problems of long synchronization delay in multi-machine system and communication delay in power station system, as well as high-speed communication of multiple machines in parallel and real-time fault detection and processing in real-time control system.

[0004] The present invention is implemented by adopting the following technical solution: a method for high-speed communication interconnection of multiple machines in parallel based on FPGA, comprising the following steps:

[0005] Communication is carried out in the form of a ring-shaped end-to-end communication structure;

[0006] Data conversion interface definition;

[0007] Cross-clock domain processing;

[0008] Define the digital frame structure;

[0009] Real-time fault handling;

[0010] Communication frame cycle;

[0011] Network disconnect detection.

[0012] Furthermore, the digital frame structure includes a frame start segment, a frame header segment, a frame address segment, a frame data segment, a frame checksum CRC segment, and a frame stop segment.

[0013] Furthermore, the communication structure adopts a communication mode of one host and multiple slaves, where the host actively initiates a data request, and the slaves receive the data and transparently transmit it to the output at the same time.

[0014] Furthermore, when the host writes data, each slave is in a receiving state, receiving data sent by the host; when the host reads data, the host initiates the frame header, and the slave detects the offset position of the communication frame data field.

[0015] Furthermore, optical or electrical signals are used for data transmission, and the optical or electrical signal data conversion interface is defined as: when a high level or light is a valid signal, it is defined as a value 1; when a low level or no light is a valid signal, it is defined as a value 0.

[0016] Furthermore, the cross-clock domain processing is specifically as follows: using a repeated sampling arbitration method, sampling the data bits multiple times and arbitrating, the frame header is a synchronization flag, when the Start frame start flag is detected, the receiving clock calculates a fixed sampling offset, and collects subsequent data and performs data bit arbitration.

[0017] Furthermore, the real-time fault handling includes device faults and external device faults. When the device faults itself, it immediately triggers the communication output port to be pulled down; when an external device fault is detected, the current data transmission is immediately terminated.

[0018] Furthermore, the communication frame cycle is specifically as follows: communication is performed in a frame cycle manner, the real-time frame involved in control is the main transmission frame, the real-time frame communication occupancy rate is high, and the non-real-time frame does not require real-time communication and is transmitted once every period of time.

[0019] Furthermore, the network disconnection detection is specifically as follows: when it is detected that the duration of a continuous low level is greater than a preset value, it is determined that an abnormality has occurred in the input connection, and the abnormal communication status is marked. At the same time, it is displayed on the interactive interface to indicate that the upstream link in the communication network is disconnected, and the user is informed to check the communication connection.

[0020] A high-speed communication interconnection system for multiple machines in parallel based on an FPGA includes a communication module, a definition module, a processing module, and a detection module. The communication module is used to communicate in a ring-shaped end-to-end communication structure and to perform communication frame circulation; the definition module is used to define a data conversion interface and a digital frame structure; the processing module is used to perform cross-clock domain processing and real-time fault processing; and the detection module is used to detect network disconnection.

[0021] The beneficial effects of the present invention are: the present invention adopts electrical signals or optical signals for transmission to realize multi-machine intercommunication, and adopts a very simple frame structure and a sufficiently reliable frame data verification method, thereby realizing zero error, low latency, strong interference resistance, and high data reliability in data transmission, and realizing real-time control between multiple machines, better synchronization, and real-time transmission and processing capabilities of faults, which makes the operation of the power system more stable and reliable. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying any creative work.

[0023] Figure 1 This is a schematic diagram of the communication structure of 1 master and 4 slaves;

[0024] Figure 2 It is a frame data structure diagram;

[0025] Figure 3 This is the schematic diagram of the hardware level implementation of CRC16 check;

[0026] Figure 4 This is the schematic diagram of the communication frame cycle. Implementation Method

[0027] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations.

[0028] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings.

[0029] The following embodiments of the present invention are described in detail with reference to the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments may be combined with each other. Example

[0030] A method for high-speed communication interconnection of multiple machines in parallel based on FPGA includes the following steps:

[0031] Communication is carried out in the form of a ring-shaped end-to-end communication structure; data conversion interface definition; cross-clock domain processing; definition of digital frame structure; real-time fault processing; communication frame circulation; network disconnection detection.

[0032] Among them, the connection of the present invention adopts a ring-shaped end-to-end communication structure, which can save half of the communication connection lines compared with the conventional one-to-one connection, and adopts a one-master-multiple-slave communication mode, in which the host actively initiates a data request, and the slave receives the data and transmits it to the output at the same time. When the host writes data, each slave device is in a receiving state, receiving the data sent by the host; when the host reads data, the host initiates the frame header, and the slave detects the offset position of the communication frame data field. When the communication frame data position points to the position where the local device needs to fill in the data, the current device fills in the data field, and each slave device fills in the field that belongs to itself in turn, and the end slave fills in the CRC check field to complete the transmission of the entire frame. This method can realize the high-speed host sending and reading data to the slave, and improve the communication speed, ensuring the real-time and synchronization of the data. The connection method of this communication can be seen Figure 1 , Figure 1 This is a schematic diagram of the communication structure of 1 host and 4 slaves. As you can imagine, the number of slaves can be set according to actual needs.

[0033] In this embodiment, in order to achieve efficient communication, the data frame structure adopts a simple data structure. Figure 2 The digital frame structure includes a Start segment, an Fhead segment, an Address segment, a Data segment, a CRC segment, and a Stop segment. The Start and Stop segments are used for frame alignment and data sampling clock correction; the Fhead segment is used to identify the validity of the communication frame and determine its type.

[0034] The frame address segment and the frame data segment are used to carry information such as transmission data, control commands, and status. For A5 type real-time frames, the slave distinguishes the data function based on the Address address after receiving it. For B5 type real-time frames, the slave distinguishes the data function based on the Address address after receiving it. For B6 type real-time frames, the slave determines the host request data object based on the Address address after receiving it, and the corresponding slave fills in the data value requested by the host.

[0035] Frame check CRC segment, frame check uses polynomial CRC16 for verification, and the check generator polynomial is shown in formula (1): G(X)=X 16 +X 15 +X 5 +1 (1), CRC16 uses FPGA to perform bit shift calculation when sending / receiving. Its implementation method is as follows Figure 3 shown.

[0036] The frame checksum includes the frame header (Fhead), address (Addr), and data (Data). The FPGA performs checksum calculations simultaneously with the frame data bits being transmitted. This calculation is performed bit by bit synchronously in a data stream, improving frame transmission efficiency. On the transmitter side, the CRC16 checksum register is initialized to 0xFFFF before transmission. Each time a frame data bit is transmitted, the CRC16C checksum module performs a shift XOR operation, synchronously updating the CRC16 checksum register value. After the frame header, address, and data segments are transmitted, the CRC16 checksum result is sent. Receiving end: The CRC16 check register is initialized to 0xFFFF before receiving. Each time a frame data bit is received, the CRC16 check module performs a shift XOR operation and synchronously updates the CRC16 check register value. After receiving the frame header, address segment, and frame data segment, the CRC16 check word generated by the received data is saved, and the CRC16 check field is continued to be received. After receiving the CRC16 field, the CRC16 check word generated by the received data is compared with the CRC16 check word in the received frame data. When the CRC16s are consistent, the frame data is considered valid, and the data field in the frame structure is obtained.

[0037] In this embodiment, optical or electrical signals are used for transmission. When powered on, the host initializes the output data to 1, and the slave is in a data forwarding state.

[0038] In this embodiment, a single bus transmission method is adopted. Since there is no independent clock signal to sample the data, the cross-clock domain problem must be considered. This method adopts a repeated sampling arbitration method to sample and arbitrate the data bits multiple times. The frame header is a synchronization flag. When the frame Start flag is detected, the receiving clock calculates a fixed sampling offset, and then samples the subsequent data and performs data bit arbitration.

[0039] In this embodiment, real-time fault handling is divided into device faults and external device faults, with communication faults receiving the highest priority. When the fiber input data bits are continuously zero for more than 15 bits, an external fault is identified and fault forwarding is initiated. If a device fault occurs internally, the communication output signal is immediately triggered to low for 30 bits to ensure all devices detect the fault. If an external fault is detected, current data transmission is immediately terminated and the fault signal is forwarded.

[0040] Take a five-device network as an example, with one master M and four slaves S1 to S4:

[0041] If S1 fails: S1 continuously outputs a 15-bit low level, and S2-M stops after detecting the 15-bit continuous low level; if S2 fails: S2 continuously outputs a 15-bit low level, S3-M is in the data receiving state, and stops after detecting the 15-bit continuous low level, and M forwards the fault after detecting the 15-bit low level. S1 requires 15-bit transmission time to detect the fault, and a total of 30-bit transmission time is required for S1 to detect the fault; if S3 fails: S3 continuously outputs a 15-bit low level, S4-M is in the data receiving state, and stops after detecting the 15-bit continuous low level, and M forwards the fault after detecting the 15-bit low level. S1-S2 requires 15-bit transmission time to detect the fault, and a total of 30-bit transmission time is required for S1-S2 to detect the fault. For example, if S4 fails, S4 continuously outputs a low level for 15 bits. S5-M, in the data receiving state, detects the 15-bit continuous low level and shuts down. M detects the 15-bit fault and then forwards the fault. Fault detection from S1 to S3 requires 15 bits of transmission time, for a total of 30 bits. This protection mechanism can achieve protection within a 30-bit transmission time. For common 50Mbaud optical fibers, it can achieve 1µs-level fault shutdown protection, meeting the real-time protection requirements of control systems.

[0042] In this embodiment, a frame cycle mode is adopted. The real-time frame involved in the control is the main transmission frame. The real-time frame communication occupancy rate is high. The non-real-time frame does not require real-time communication. A non-real-time frame is inserted into the real-time frame at intervals to realize the cyclic transmission of high-speed frames and slow frames. The communication frame cycle is shown in FIG. Figure 4 A non-real-time frame is inserted into the real-time frame at regular intervals (usually 100ms) to enable the host to send parameters and other data to the slave and read the slave status.

[0043] In this embodiment, when it is detected that the continuous low level duration is greater than 3s, it is determined that the input connection is abnormal, and the communication status abnormal bit is marked. At the same time, it is displayed on the interactive interface to indicate that the upstream link in the communication network is disconnected, and the user is informed to check the communication connection.

[0044] A FPGA-based multi-machine parallel high-speed communication interconnection system is used to implement the above-mentioned FPGA-based multi-machine parallel high-speed communication interconnection method. The system includes a communication module, a definition module, a processing module and a detection module. The communication module is used to communicate in the form of a circular end-to-end communication structure and perform communication frame circulation; the definition module is used to define the data conversion interface and define the digital frame structure; the processing module is used to perform cross-clock domain processing and real-time fault processing; and the detection module is used to detect communication link disconnection.

[0045] The present invention solves the problems of high-speed communication of multiple machines in parallel and real-time fault detection and processing in real-time control systems:

[0046] 1. Conventional communication solutions, such as Ethernet ports, offer high speeds but are complex to implement. Control circuits require additional physical transmission chips, resulting in high costs. 485 and CAN are also commonly used in industrial control, but their transmission rates are clearly limited, generally below 1Mbps. Furthermore, their protocols are complex, their communication frames are long, and their frame data transmission speeds are slow, making them difficult to guarantee in situations where real-time performance is critical. This method achieves low-latency communication based on an FPGA. The communication frame utilizes a streamlined frame structure and employs cyclic transmission of both real-time and non-real-time frames. Non-real-time frames are intermittently inserted into real-time frames, improving real-time communication and ensuring data interconnection between devices. When a device failure occurs in a multi-machine parallel connection, fault transmission has the highest priority and offers rapid response capabilities. The host computer can promptly receive fault information, make adjustments, and redeploy the system's operating mode to ensure robust system operation.

[0047] 2. This method solves the problem of multi-machine synchronization in the control field. It has extremely low transmission delay, sampling clock alignment correction mechanism, data arbitration, and FPGA hardware data stream CRC verification mechanism, which ensures data transmission stability and prevents transmission errors. At the same time, the data frame is verified and the transmission and reception are reliable. When multiple devices run synchronously, it can ensure consistent control performance between multiple devices in real time, and the system operation is more stable.

[0048] 3. The present invention adopts cyclic transmission of real-time frames and non-real-time frames, and intermittently inserts non-real-time frames into real-time frames, thereby improving real-time performance. When equipment failure occurs in multiple machines in parallel, it has a fast response capability, and the host can make timely adjustments to ensure the stable operation of the system.

[0049] 4. The present invention has a short fault transmission time and the fault signal has the highest priority. When a device fails, the system-level fault protection action can be completed within 30-bit data transmission time. It has the ability to quickly respond to faults and the system protection is more sensitive.

[0050] The present invention has at least the following technical effects:

[0051] The communication frame structure of the present invention is simplified and implemented based on FPGA, which can achieve high-speed transmission. The transmission rate is limited by the hardware conversion circuit and can reach 50Mbps based on the commonly used optical fiber converter. The communication data delay is <100us, which meets the real-time requirements of multi-machine parallel control. The frame structure of the present invention contains a frame synchronization bit. When the frame synchronization signal is detected, the sampling clock is aligned and corrected, avoiding the metastable problem existing in asynchronous communication and achieving zero-error data transmission. At the same time, it has a CRC hardware-level verification mechanism, which further guarantees data reliability and achieves high-speed and high-reliability communication. The present invention is based on FPGA multi-machine interconnection communication, and multiple machines achieve synchronous response to the host's instructions. The communication data delay is low, and the multi-machine response has excellent consistency, avoiding the action differences caused by equipment hardware differences and software control cumulative deviations. The present invention has a strong fault handling capability, and fault signal transmission takes precedence over data transmission. Fault information transmission can be completed within a maximum of 30-bit data transmission time, achieving rapid fault response. The host device adjusts the system operation mode in time according to the fault status to ensure that the entire system can continue to operate reliably.

[0052] It should be noted that for the aforementioned embodiments, for simplicity of description, they are all expressed as a series of action combinations, but those skilled in the art should be aware that this application is not limited by the order of the actions described, because according to this application, some steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in this specification are preferred embodiments, and the actions involved are not necessarily required by this application.

[0053] The above embodiments describe the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The above embodiments and descriptions are merely illustrative of the principles of the present invention. Without departing from the spirit and scope of the present invention, modifications and variations made by those skilled in the art without departing from the spirit and scope of the present invention should be within the scope of protection of the appended claims.

Claims

1. A method for high-speed communication interconnection of multiple machines in parallel based on FPGA, characterized in that: The steps include: Communication is carried out in the form of a ring-shaped end-to-end communication structure; Definition of data conversion interface: optical or electrical signals are used for data transmission. The definition of optical or electrical signal data conversion interface is: when high level or light is a valid signal, it is defined as value 1; when low level or no light is a valid signal, it is defined as value 0; Cross-clock domain processing: Cross-clock domain processing specifically involves: using a repeated sampling arbitration method to sample and arbitrate data bits multiple times. The frame header is a synchronization flag. When the frame start flag is detected, the receiving clock calculates a fixed sampling offset, samples subsequent data, and performs data bit arbitration. Define the digital frame structure; The digital frame structure includes the frame start segment, frame header segment, frame address segment, frame data segment, frame checksum CRC segment and frame stop segment; Real-time fault handling: Real-time fault handling includes both device faults and external device faults. When a device fault occurs, it immediately triggers the low-power communication output port. When an external device fault is detected, the current data transmission is immediately terminated and the fault signal is forwarded. Communication frame cycle; The communication frame cycle is specifically as follows: communication is carried out in a frame cycle mode, and the real-time frame involved in control is the main transmission frame. The real-time frame communication occupancy rate is high, and the non-real-time frame does not require real-time communication and is transmitted once every period of time; Network disconnect detection: When it is detected that the duration of a continuous low level is greater than the preset value, it is determined that the input connection is abnormal, and the communication status abnormal bit is marked. At the same time, it is displayed on the interactive interface to indicate that the upstream link in the communication network is disconnected, and the user is informed to check the communication connection.

2. The FPGA-based multi-machine parallel high-speed communication interconnection method according to claim 1, characterized in that: The communication structure adopts a communication mode of one host and multiple slaves, where the host actively initiates a data request, and the slaves receive the data and transmit it to the output at the same time.

3. The FPGA-based multi-machine parallel high-speed communication interconnection method according to claim 2, characterized in that: When the host writes data, each slave is in the receiving state and receives the data sent by the host; when the host reads data, the host initiates the frame header and the slave detects the offset position of the communication frame data field.

4. A FPGA-based multi-machine parallel high-speed communication interconnection system, used to implement the FPGA-based multi-machine parallel high-speed communication interconnection method according to any one of claims 1 to 3, characterized in that: It includes a communication module, a definition module, a processing module and a detection module. The communication module is used to communicate in a ring-shaped end-to-end communication structure and perform communication frame circulation; the definition module is used to define the data conversion interface and define the digital frame structure; the processing module is used to perform cross-clock domain processing and real-time fault processing; The detection module is used for performing network disconnection detection.

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