Binary arithmetic coding structure, apparatus, method and storage medium

Abstract

The application provides a binary arithmetic coding structure, device, method and storage medium. The binary arithmetic coding structure comprises M first coding units connected in stages along a first direction, and a second coding unit connected with the Mth first coding unit arranged along the first direction; the first coding unit comprises a selector, a first regular encoder and a bypass encoder connected with the selector respectively; the second coding unit comprises a second regular encoder; and the binary arithmetic coding structure can improve the coding rate of CABAC.

Description

Technical Field

[0001] This application relates to the field of video coding technology, and in particular to a binary arithmetic coding structure, apparatus, method and storage medium. Background Technology

[0002] CABAC (Context-based Adaptive Binary Arithmetic Coding) was first introduced in H.264. Compared to CAVLC (Context-based Adaptive Variable Length Coding), CABAC can bring a performance improvement of approximately 5% to 14%. CABAC mainly consists of three processes: (1) representing the context syntax information to be encoded in binary form; (2) selecting an appropriate probability model; and (3) binary arithmetic coding.

[0003] In binary arithmetic coding, encoders are divided into conventional encoders and bypass encoders. Designers need to select the conventional encoder or bypass encoder based on the type of context syntax information. In H.264 and H.265, the amount of context syntax information is relatively small, and the computation logic mainly involves lookup table operations. While meeting the bandwidth and PPA (Power Performance Area) requirements of chip design, it can process four bin (binval) values ​​of binary syntax information simultaneously in one clock cycle, thus achieving the expected CABAC output bitstream rate. However, in H.266, the amount of context syntax information increases significantly, and the computation logic changes from lookup tables to linear logic. The traditional CABAC binary arithmetic coding structure struggles to achieve the expected output bitstream rate.

[0004] Therefore, how to improve the CABAC encoding rate in H.266 is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] To address the aforementioned technical problems, this application provides a binary arithmetic encoding structure that can improve the CABAC encoding rate. This application also provides a binary arithmetic encoding apparatus, method, and storage medium, which have the same technical effects.

[0006] The first objective of this application is to provide a binary arithmetic encoding structure.

[0007] The aforementioned objective of this application is achieved through the following technical solution:

[0008] A binary arithmetic encoding structure, comprising:

[0009] M first coding units connected sequentially along the first direction, where M is a positive integer greater than 1;

[0010] And a second coding unit, the second coding unit being connected to the Mth first coding unit arranged along the first direction;

[0011] The first encoding unit includes a selector and a first conventional encoder and a bypass encoder respectively connected to the selector; the second encoding unit includes a second conventional encoder;

[0012] The selector is used to determine the input unit in the first encoding unit based on the received information to be encoded. The input unit is the selector, the first conventional encoder, or the bypass encoder.

[0013] The input units and selectors, as well as the output units, within all the first encoding units along the first direction sequentially form the target encoding path of the information to be encoded. The output unit is either a second conventional encoder or a bypass encoder in the Mth first encoding unit arranged along the first direction.

[0014] Preferably, in the binary arithmetic coding structure, along the first direction, the selector in the (N-1)th first coding unit is connected to the first conventional encoder, the bypass encoder, and the selector in the Nth first coding unit, respectively, where N∈M;

[0015] The selector in the Mth first encoding unit is connected to the second conventional encoder.

[0016] Preferably, the first input unit along the first direction is a first conventional encoder or bypass encoder in the first encoding unit.

[0017] Preferably, the binary arithmetic encoding structure includes 2+2*M*(M-1) encoding paths, and the 2+2*M*(M-1) encoding paths include the target encoding path.

[0018] The second objective of this application is to provide a binary arithmetic encoding device.

[0019] The second objective of this application is achieved through the following technical solution:

[0020] A binary arithmetic encoding device, comprising the binary arithmetic encoding structure described in any of the preceding claims.

[0021] Preferably, the binary arithmetic encoding device has multiple preset encoding modes, each of which corresponds to multiple encoding paths, and the multiple encoding paths include a target encoding path; the device also includes an encoding mode determination module.

[0022] The encoding mode determination module is used to divide the binary syntax information according to the multiple preset encoding modes to obtain the information to be encoded, and to determine the corresponding target encoding path according to the information to be encoded.

[0023] The binary arithmetic encoding structure is used to obtain the information to be encoded, and to perform binary arithmetic encoding on the information to be encoded in the corresponding target encoding path to obtain the target encoded information.

[0024] Preferably, the preset encoding mode is divided according to the number of bin values ​​of the binary grammar information that the binary arithmetic encoding structure can process within one clock cycle, and the encoding order of the conventional encoder and the bypass encoder in the binary arithmetic encoding structure.

[0025] The third objective of this application is to provide a binary arithmetic encoding method.

[0026] The aforementioned objective three of this application is achieved through the following technical solution:

[0027] A binary arithmetic encoding method, the method being applied to the binary arithmetic encoding device described in any of the preceding claims, the method comprising:

[0028] Obtain the binary syntax information;

[0029] Based on multiple preset encoding modes, the binary syntax information is divided to obtain multiple pieces of information to be encoded and the encoding modes corresponding to the multiple pieces of information to be encoded.

[0030] Based on the encoding patterns corresponding to the multiple pieces of information to be encoded, the target encoding paths corresponding to the multiple pieces of information to be encoded are determined;

[0031] In the corresponding target encoding path, multiple pieces of information to be encoded are binary arithmetic encoded to obtain target encoded information.

[0032] Preferably, in the binary arithmetic encoding method, the step of dividing the binaryated syntax information according to multiple preset encoding modes to obtain multiple pieces of information to be encoded includes:

[0033] The bin sequence of the binary syntax information is arranged and divided according to multiple preset encoding modes to obtain the multiple pieces of information to be encoded.

[0034] Preferably, in the binary arithmetic encoding method, the step of performing binary arithmetic encoding on multiple pieces of information to be encoded in the corresponding target encoding path to obtain target encoded information includes:

[0035] The information to be encoded is obtained sequentially, and in each case where the information to be encoded is obtained, binary arithmetic encoding is performed on the information to be encoded in the corresponding target encoding path to obtain target encoding information. When the information to be encoded includes the termination encoding syntax, all the target encoding information is packaged and output.

[0036] The fourth objective of this application is to provide a computer storage medium.

[0037] The fourth objective of this application is achieved through the following technical solution:

[0038] A computer storage medium storing computer execution instructions, which, when executed by a processor, are used to implement any of the methods described above in the binary arithmetic encoding method.

[0039] The above technical solution establishes M first encoding units and a second encoding unit connected sequentially along a first direction in a binary arithmetic encoding structure. The second encoding unit is connected to the Mth first encoding unit arranged along the first direction. The first encoding unit includes a selector and a first conventional encoder and a bypass encoder connected to the selector respectively. The second encoding unit includes a second conventional encoder. The selector is used to determine the input unit in the first encoding unit based on the received information to be encoded. The input unit is either the selector, the first conventional encoder, or the bypass encoder. The input units and selectors in all the first encoding units along the first direction, and the second conventional encoder in the output unit or the bypass encoder in the Mth first encoding unit arranged along the first direction, sequentially form the target encoding path of the information to be encoded. That is, the above binary arithmetic encoding structure forms a pipelined encoding path by selecting the input unit, combining the selector and the output unit, thereby flexibly supporting multiple encoding methods. For example, it can simultaneously encode up to M+1 conventional syntax information or 2n*M bypass syntax information, significantly improving the encoding rate of the VPU (Video Processing Unit) chip. Meanwhile, the binary arithmetic coding structure can reuse conventional encoders and bypass encoders, which can simplify the hardware resource overhead of the binary arithmetic coding structure in CABAC.

[0040] Furthermore, the binary arithmetic coding structure is implemented in a step-by-step pipeline, which has a flexible coding method. It can select the optimal coding mode according to the arrangement order of the bin sequence of the syntax information after CABAC binaryization, which can perfectly match the coding calculation efficiency without affecting the overall system performance. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1 This is a schematic diagram of a binary arithmetic encoding structure provided in the embodiments of this application;

[0043] Figure 2 This is another schematic diagram of a binary arithmetic encoding structure provided in the embodiments of this application;

[0044] Figure 3 This is a schematic diagram of the structure of a binary arithmetic encoding device provided in the embodiments of this application;

[0045] Figure 4 This is a flowchart illustrating a binary arithmetic encoding method provided in an embodiment of this application. Detailed Implementation

[0046] To enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application will be clearly and completely described below. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0047] It should be understood that the use of terms such as "system," "device," "unit," and / or "module" in this application is merely one method of distinguishing different components, elements, parts, sections, or assemblies at different levels. However, if other terms can achieve the same purpose, they may be replaced by other expressions.

[0048] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "a plurality of" or "several" means two or more, unless otherwise explicitly specified.

[0049] If a flowchart is used in this application, it is used to illustrate the operations performed by the system according to embodiments of this application. It should be understood that the preceding or following operations are not necessarily performed in exact order. Instead, the steps can be processed in reverse order or simultaneously. Furthermore, other operations can be added to these processes, or one or more steps can be removed from them.

[0050] It should also be noted that, in this document, terms such as “comprising,” “including,” or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an article or device. Without further limitation, an element defined by the phrase “comprising one…” does not exclude the presence of other identical elements in the article or device that includes the aforementioned element.

[0051] like Figure 1 As shown, this application provides a binary arithmetic encoding structure, including: M first encoding units 1 connected sequentially along a first direction, where M is a positive integer greater than 1; and a second encoding unit 2, which is connected to the Mth first encoding unit 1 arranged along the first direction.

[0052] The first encoding unit 1 includes a selector and a first conventional encoder and a bypass encoder respectively connected to the selector.

[0053] For example, there are N selectors in total, such as Figure 1 In the sequence Sel1 to SelN, there are a total of M first conventional encoders, such as... Figure 1 There are Z bypass encoders, Re1 to ReM, as shown below. Figure 1 By1 to ByZ.

[0054] A single first encoding unit 1 may include several bypass encoders and several first regular encoders. The number of bypass encoders and first regular encoders in a single first encoding unit can be customized according to hardware consumption and supported video codec protocol standards.

[0055] For example, the quantities of N, M, and Z may be at least partially the same or different.

[0056] For example, a single first encoding unit 1 may include a first bypass encoder, a first conventional encoder and a selector.

[0057] The second encoding unit 2 includes a second conventional encoder; wherein, there is one second conventional encoder in total, such as... Figure 1 Re(M+1) in the equation.

[0058] In other examples, the number of selectors, first conventional encoders and adjacent encoders in the first encoding unit 1 may also be inconsistent, and the second encoding unit 2 may include multiple second conventional encoders.

[0059] The selector is used to determine the input unit in the first encoding unit 1 based on the received information to be encoded. The input unit is the selector, the first conventional encoder, or the bypass encoder.

[0060] The input units, selectors, and output units within all the first encoding units 1 along the first direction can sequentially form the target encoding path of the information to be encoded.

[0061] The output unit can be a second conventional encoder or a bypass encoder in the Mth first encoding unit 1 arranged along the first direction. The output unit can be determined by the Mth selector arranged along the first direction.

[0062] It should be noted that the first direction can be the execution direction of the binary encoding or the direction closer to the second conventional encoder. The first encoding unit 1 and the second encoding unit 2 are mainly used to describe the arrangement order of the binary arithmetic encoding structure. This is merely a logical functional division; in actual implementation, there can be other division methods. For example, multiple first encoding units 1 can be combined, integrated into another system, or some features can be ignored or not executed. Furthermore, the coupling, direct coupling, or communication connection between the units shown or discussed can be through some interfaces. The indirect coupling or communication connection between units can be electrical or other forms.

[0063] The binary arithmetic coding structure in this application can be applied to the H.266 video codec standard, and this binary arithmetic coding structure can be a CABAC encoder. The regular encoder is used for the regular coding mode, and the bypass encoder is used for fast encoding of symbols. The regular encoder is the core of CABAC encoding; it can encode one bit, that is, it is used to perform binary arithmetic encoding on the bin value of one binaryized syntax information.

[0064] In reality, some syntax elements may not use the conventional encoding described above after binarization, but rather bypass encoding. A bypass encoder can be used to perform binary arithmetic encoding on the bin values ​​of 1 to 2n binary syntax information, where n is a positive integer. The value of n can be determined based on the hardware conditions of the bypass encoder; for example, n can be 3.

[0065] The selector determines the input unit in the first encoding unit 1 based on the received information to be encoded, thereby enabling the selection of the input and / or output of the first encoding unit 1.

[0066] For example, the selector described above can be used to select the input unit in the first encoding unit 1.

[0067] For example, the selector described above can be used to select which input unit in the next first encoding unit 1 to connect the output of the first encoding unit 1 to.

[0068] For example, the selector can also trigger the next first encoding unit to encode after the first encoding unit 1 has completed encoding.

[0069] In some embodiments, one implementation of the selector determining the input unit in the first encoding unit 1 based on the received information to be encoded is as follows: based on the received information to be encoded, a first conventional encoder, a bypass encoder, or a selector in the first encoding unit 1 at the same level is selected as the input unit of the encoding unit 1 at the same level. For example, a selector in a first encoding unit 1 can be used as an input unit.

[0070] Alternatively, in some optional examples, the selector can connect its input to the output of the first conventional encoder or bypass encoder in the first encoding unit 1 of the current stage, based on the received information to be encoded. Alternatively, the selector can connect its input to the output of the selector in the first encoding unit 1 of the preceding stage. The output of the selector can then be connected to the input of the first conventional encoder, bypass encoder, or selector in the first encoding unit 1 of the following stage.

[0071] In some alternative examples, the selector may also connect the input of the current selector to the output of the first conventional encoder in the first encoding unit 1 of the current stage, or connect the output of the current selector to the input of the bypass encoder in the first encoding unit 1 of the current stage, based on the received information to be encoded.

[0072] It should also be noted that the selector in the Mth first encoding unit 1 arranged along the first direction can also choose to connect its input to the output of the first conventional encoder in the current level first encoding unit 1, or the input of the current selector can also be connected to the output of the selector in the previous level first encoding unit 1. The current selector can also choose to connect to the input of the second conventional encoder in the second encoding unit 2.

[0073] The first encoding unit 1 and the second encoding unit 2, which are connected step by step along the first direction, form a hierarchical pipelined encoding path by selecting the input unit, combining the selector and the output unit.

[0074] The aforementioned hierarchical pipeline structure includes multiple encoding paths. The information to be encoded can be obtained from the CABAC binary syntax information, which may include part or all of the bin sequence of the CABAC binary syntax information. Based on the selection results of M selectors, the input units and selectors in all first encoding units 1 along the first direction, as well as the second conventional encoder or the bypass encoder in the Mth first encoding unit 1 arranged along the first direction, can sequentially form the target encoding path of the information to be encoded.

[0075] Therefore, the binary arithmetic coding structure described in the above embodiments can flexibly support multiple encoding methods, such as simultaneously encoding a maximum of M+1 bin values ​​of regular syntax information, or 2n*M bin values ​​of bypass syntax information, significantly improving the encoding rate of the VPU chip. Simultaneously, the binary arithmetic coding structure can reuse both regular encoders and bypass encoders, simplifying the hardware resource overhead of the binary arithmetic coding structure in CABAC.

[0076] Furthermore, the binary arithmetic coding structure is implemented in a step-by-step pipeline, which has a flexible coding method. It can select the optimal coding mode according to the arrangement order of the bin sequence of the syntax information after CABAC binaryization, which can perfectly match the coding calculation efficiency without affecting the overall system performance.

[0077] In summary, the above embodiments improve the CABAC encoding rate in H.266 in many ways.

[0078] In some embodiments, in the binary arithmetic coding structure, along the first direction, the selector in the (N-1)th first coding unit 1 is connected to the first conventional encoder, the bypass encoder and the selector in the Nth first coding unit 1, respectively, N∈M; the selector in the Mth first coding unit 1 is connected to the second conventional encoder.

[0079] In other embodiments, in the binary arithmetic coding structure, the first input unit along the first direction is the first conventional encoder or bypass encoder in the first first coding unit 1. That is, encoding starts from the first first coding unit 1, and the first conventional encoder or bypass encoder in the first first coding unit 1 is selected as the input to obtain as many flexible coding methods as possible, thereby improving the coding flexibility of the VPU chip.

[0080] In order to facilitate finding the optimal encoding method among various flexible encoding methods, in other embodiments of this application, the binary arithmetic encoding structure includes 2+2*M*(M-1) encoding paths, and the 2+2*M*(M-1) encoding paths include the target encoding path.

[0081] In a specific embodiment, the binary arithmetic encoding structure is illustrated by including two first encoding units and one second encoding unit. That is, the binary encoding structure may include two first regular encoders, two bypass encoders, two selectors, and one second regular encoder. The bypass encoder is used to perform binary arithmetic encoding on the bin values ​​of one to six binaryized syntax information.

[0082] like Figure 2 As shown, the binary arithmetic encoding structure includes: a conventional encoder Re1, a conventional encoder Re2, a conventional encoder Re3 (i.e., the second encoding unit), a bypass encoder By1, a bypass encoder By2, and selectors Sel1 and Sel2, wherein: a pipelined structure is formed between the conventional encoder Re1 in one first encoding unit and the conventional encoder Re2 in another first encoding unit by connecting selector Sel1; a pipelined structure is formed between the conventional encoder Re2 and the conventional encoder Re3 in one first encoding unit by connecting selector Sel2; a pipelined structure is formed between the bypass encoder By1 in one first encoding unit and the bypass encoder By2 in another first encoding unit by connecting selector Sel1; and a pipelined structure is also formed between the bypass encoder By1 in one first encoding unit and the bypass encoder By2 in another first encoding unit by connecting selectors Sel1 and Sel2 in sequence.

[0083] Among them, selector Sel1 can determine the first input unit based on the received information to be encoded. The first input unit is a conventional encoder Re1 or a bypass encoder By1. Selector Sel2 can determine the second input unit based on the received information to be encoded. The second input unit is selector Sel1, conventional encoder Re2 or bypass encoder By2. The first input unit, selector Sel1, second input unit, selector Sel2, and conventional encoder Re3 or bypass encoder By2 in the output unit along the first direction sequentially form the target encoding path of the information to be encoded.

[0084] Based on selectors Sel1 and Sel2, it is possible to achieve Figure 2 The selection of inputs and / or outputs for the conventional encoder and bypass encoder in the binary arithmetic coding structure shown. Specifically, Figure 2 The binary arithmetic encoding structure shown can include the following six encoding paths:

[0085] Path 1: Conventional encoder Re1 → Selector Sel1 → Conventional encoder Re2 → Selector Sel2 → Conventional encoder Re3;

[0086] Path 2: Conventional encoder Re1 → Selector Sel1 → Bypass encoder By2;

[0087] Path 3: Conventional encoder Re1 → Selector Sel1 → Conventional encoder Re2 → Selector Sel2 → Bypass encoder By2;

[0088] Path 4: Bypass encoder By1 → Selector Sel1 → Bypass encoder By2;

[0089] Path 5: Bypass encoder By1 → Selector Sel1 → Conventional encoder Re2 → Selector Sel2 → Conventional encoder Re3;

[0090] Path 6: Bypass encoder By1 → Selector Sel1 → Selector Sel2 → Conventional encoder Re3;

[0091] From the above encoding path, it can be seen that selector Sel1 can be used to select the connection between the output of conventional encoder Re1 and the input of conventional encoder Re2; selector Sel1 can also be used to select the connection between the output of conventional encoder Re1 and the input of bypass encoder By2; selector Sel1 can also be used to select the connection between the output of bypass encoder By1 and the input of bypass encoder By2; selector Sel1 can also be used to select the connection between the output of bypass encoder By1 and the input of selector Sel2; correspondingly, selector Sel2 can be used to select the connection between the output of conventional encoder Re2 and the input of conventional encoder Re3; selector Sel2 can also be used to select the connection between the output of conventional encoder Re2 and the input of bypass encoder By2; selector Sel2 can also be used to connect the output of selector Sel1 to the input of conventional encoder Re3.

[0092] Based on the selection results of selectors Sel1 and Sel2, the target encoding path of the information to be encoded can be determined, that is, the optimal target encoding path can be found among the above six encoding paths.

[0093] In other embodiments of this application, such as Figure 3 As shown, a binary arithmetic encoding device 3 is also provided, including the binary arithmetic encoding structure 31 described in any of the above claims. The binary arithmetic encoding device 3 can acquire information to be encoded and use the binary arithmetic encoding structure 31 to perform binary arithmetic encoding on the information to be encoded to obtain target encoded information, thereby improving the CABAC encoding rate in H.266.

[0094] In some embodiments, the binary arithmetic encoding device 3 has multiple preset encoding modes, each of which corresponds to multiple encoding paths, including a target encoding path; the binary arithmetic encoding device 3 further includes an encoding mode determination module 32; the encoding mode determination module 32 is used to divide the binaryized syntax information according to the multiple preset encoding modes to obtain information to be encoded, and to determine the corresponding target encoding path according to the information to be encoded; the binary arithmetic encoding structure 31 is used to obtain the information to be encoded, and to perform binary arithmetic encoding on the information to be encoded in the corresponding target encoding path to obtain the target encoded information.

[0095] In a specific embodiment, binary arithmetic coding structure 31 is adopted. Figure 2Taking the binary arithmetic encoding structure shown as an example, the binary arithmetic encoding device 3 may include the following six preset encoding modes. For other embodiments, multiple encoding modes can be formed by referring to the number of different first encoding units and the selection of the selector therein, and binary encoding can be implemented accordingly. No further details are provided here.

[0096] Mode 1: Encode 1 to 3 binary versions of standard syntax information within one clock cycle;

[0097] Mode 2: Within one clock cycle, first encode one binary version of the regular syntax information, then encode one to six binary versions of the bypass syntax information;

[0098] Mode 3: Within one clock cycle, first encode two binaryized regular syntax information, then encode one to six binaryized bypass syntax information;

[0099] Mode 4: Encode 1 to 12 binary bypass syntax messages within one clock cycle;

[0100] Mode 5: Within one clock cycle, first encode 1 to 6 binary bypass syntax information, then encode 2 binary regular syntax information;

[0101] Mode 6: Within one clock cycle, first encode 1 to 6 binary bypass syntax messages, then encode 1 binary regular syntax message.

[0102] The above six preset encoding modes correspond one-to-one with the above six encoding paths, wherein the above six encoding paths include the target encoding path corresponding to the information to be encoded.

[0103] The encoding mode determination module 32 can divide the binaryized syntax information according to the above six preset encoding modes to obtain the information to be encoded. That is, according to the above six preset encoding modes, the bin sequence of the binaryized CABAC syntax information is divided to obtain the information to be encoded. The information to be encoded may include part or all of the bin sequence of the binaryized CABAC syntax information. Then, according to the information to be encoded, the corresponding target encoding path is determined from the above six preset encoding paths.

[0104] The binary arithmetic encoding structure 31 obtains the target encoding information by acquiring the information to be encoded and performing binary arithmetic encoding on the information to be encoded in the corresponding target encoding path.

[0105] In other embodiments, the preset encoding mode can be divided according to the number of bin values ​​of the binary grammar information that the binary arithmetic encoding structure 31 can process within one clock cycle, and the encoding order of the conventional encoder and the bypass encoder in the binary arithmetic encoding structure 31.

[0106] The preset encoding mode can be used, but other reasonable division methods can also be adopted; this application is not limited to this.

[0107] In the above embodiments, the binary arithmetic encoding structure 31 in the binary arithmetic encoding device 3 adopts... Figure 2 The binary arithmetic encoding structure shown can encode up to 12 binary syntax information bin values ​​simultaneously through 3 conventional encoders, 2 bypass encoders and 2 selectors. It can significantly improve the encoding rate of VPU chips while meeting the requirements of chip design bandwidth, PPA and other factors.

[0108] Furthermore, based on the above embodiments, the optimal encoding mode and encoding path can be selected according to the arrangement order of the binary sequence of the syntax information after CABAC binaryization, thereby further improving the encoding rate of CABAC in H.266.

[0109] like Figure 4 As shown, this application provides a binary arithmetic encoding method, which is applied to the binary arithmetic encoding device described in any of the above claims. The method includes:

[0110] S1. Obtain the binary syntax information;

[0111] In S1, the syntax information can be the syntax information to be encoded, which can be pre-loaded into the cache and then retrieved from the cache, or it can be retrieved through other means.

[0112] CABAC is a binary arithmetic coding system. Non-binary symbols such as motion vectors, macroblock types, reference frame numbers, and residual data after transform quantization need to be pre-binded.

[0113] The CABAC binary scheme consists of a basic scheme and a concatenated scheme.

[0114] There are four basic schemes: unary binarization (U), truncated unary binarization (TU), Kthorder Exp_golomb binarization (UEGK), and fixed-length binarization (FL).

[0115] The concatenation scheme is formed by concatenating basic schemes. Different binaryization schemes are suitable for different types of syntax elements. For residual data with a large range of numerical variation (such as residual data between motion vectors and predicted motion vector values), UEGK codes are used; for simple symbolic elements, FL codes are used. In this step, different binaryization schemes can be selected based on the type of syntax information to perform binaryization processing and obtain the binary syntax information.

[0116] In some embodiments, one implementation of this step specifically includes:

[0117] S10. Before the video processing unit starts CABAC, obtain the syntax information required by the current task and load the syntax information into the cache;

[0118] S20. According to the order of H.266 syntax information, retrieve the syntax information from the cache, load the syntax information into CABAC for binary conversion, and obtain the binary syntax information;

[0119] The video processing unit can be a Video Processing Unit (VPU), a new type of video processing platform core engine that features hardware decoding capabilities and reduces CPU load. Additionally, the VPU can reduce server load and network bandwidth consumption.

[0120] Specifically, syntax information can be loaded from the parent module into the cache.

[0121] H.266 is the latest generation video coding standard. Compared to its predecessor, H.265, H.266 can save 50% of the bitrate while maintaining comparable subjective quality, significantly reducing bandwidth costs. Based on the order of H.266 syntax information, after retrieving the syntax information from the cache and loading it into CABAC, the aforementioned CABAC binary conversion scheme can be used for binary conversion to obtain the binary syntax information.

[0122] It should be noted that the binary syntax information can also be obtained directly through other means, and this application does not impose any restrictions on this.

[0123] In other embodiments, the probability model can be selected for updating based on the binary syntax information.

[0124] There are four ways to design a context model in CABAC:

[0125] The first type of model must be constructed based on its adjacent encoded grammatical elements, generally the corresponding grammatical elements to its left and above, to build the corresponding probabilistic model and make model predictions for the current grammatical element.

[0126] The second model is limited to applications of macroblock and submacroblock types, where the selection of the probability model for the m-th bit should refer to the model used for the previously encoded m-1 bits.

[0127] The third and fourth models are only used for encoding residual data. Both models depend on the type of coded block. The third model depends not on the already encoded coefficients, but on the position of the coefficient in the scan path. The fourth model calculates the number of coefficients encoded before the coefficient containing that bit.

[0128] In CABAC, besides these conditional context models, there are also some fixed probability models that provide fixed probability predictions for the bits to be encoded; the models for already encoded bits are not applied. Specifically, a suitable probability model can be selected for the encoded symbol based on the contextual relevance of the binary syntax information, and the probability model is updated based on the value of the current encoded symbol. By constructing the context model, the basic probability model can adapt to the changing statistical characteristics of the video image, reduce redundancy between symbols, and significantly reduce computational overhead.

[0129] S2. Based on multiple preset encoding modes, the binary syntax information is divided to obtain multiple pieces of information to be encoded and the encoding modes corresponding to the multiple pieces of information to be encoded.

[0130] In S2, a preset encoding mode can be established based on the number of bin values ​​of the binary syntax information that the binary arithmetic encoding structure in the binary arithmetic encoding device can process within one clock cycle, and the encoding order of the conventional encoder and the bypass encoder in the binary arithmetic encoding structure. Specifically, this step can be performed by the encoding mode determination module in the binary arithmetic encoding device.

[0131] S3. Determine the target encoding path corresponding to the multiple pieces of information to be encoded based on the encoding modes corresponding to the multiple pieces of information to be encoded respectively;

[0132] In S3, the encoding modes corresponding to the multiple pieces of information to be encoded can be one or more of a variety of preset encoding modes, and the multiple preset encoding modes can each correspond to an encoding path. The multiple encoding paths include a target encoding path. The purpose of this step is to determine the target encoding path from the multiple encoding paths. Specifically, this step can be performed by the encoding mode determination module in the binary arithmetic encoding device.

[0133] S4. Perform binary arithmetic encoding on multiple pieces of information to be encoded in the corresponding target encoding path to obtain the target encoding information.

[0134] In S4, based on the target encoding path and the binary arithmetic encoding structure in the binary arithmetic encoding device, a conventional encoding mode and / or a bypass encoding mode can be selected to perform binary arithmetic encoding on the information to be encoded, thereby obtaining the target encoding information.

[0135] As can be seen from the pipeline structure of the binary arithmetic encoding structure, the above binary arithmetic encoding method can encode a maximum of M+1 bin values ​​of regular syntax information or 2n*M bin values ​​of bypass syntax information at the same time, which greatly improves the encoding rate of the VPU chip.

[0136] The binary arithmetic coding structure has a flexible coding method. It can match the optimal coding mode and coding path according to the arrangement order of the bin sequence of the CABAC binary syntax information, thereby further improving the coding rate of CABAC in H.266.

[0137] In some embodiments, one implementation of the step of dividing the binaryized syntax information into multiple pieces of information to be encoded according to multiple preset encoding modes in the binary arithmetic encoding method specifically includes: arranging and dividing the bin sequence of the binaryized syntax information according to multiple preset encoding modes to obtain the multiple pieces of information to be encoded.

[0138] Specifically, based on the binary arithmetic coding structure, the arrangement of the bin sequence of the binary syntax information can be pre-divided into 2+2*M*(M-1) kinds, and the arrangement can correspond to the preset coding mode and coding path of the binary arithmetic coding structure.

[0139] In a specific embodiment, the binary arithmetic encoding structure adopts... Figure 2 Taking the binary arithmetic encoding structure shown as an example, the specific arrangement includes:

[0140] Arrangement 1: The bin values ​​of the three binary-processed regular syntax information are arranged sequentially;

[0141] Arrangement 2: The bin value of one binaryized regular syntax information and the bin values ​​of one to six binaryized bypass syntax information are arranged in sequence;

[0142] Arrangement 3: The bin values ​​of the two binaryized regular syntax information and the bin values ​​of the 1 to 6 binaryized bypass syntax information are arranged in sequence;

[0143] Arrangement 4: The bin values ​​of the 1 to 12 binary-coded bypass syntax information are arranged sequentially;

[0144] Arrangement 5: The bin values ​​of the 1st to 6th binary-processed bypass syntax information and the bin values ​​of the 2nd binary-processed regular syntax information are arranged in sequence;

[0145] Arrangement 6: The bin values ​​of 1 to 6 binaryized bypass syntax information and the bin value of 1 binaryized regular syntax information are arranged in sequence.

[0146] For any binaryized syntax information, the order of its bin sequence is fixed. In this embodiment, the arrangement of the bin sequence of the binaryized syntax information is matched with the arrangement of the bin sequence of the binaryized syntax information according to the arrangement of various preset encoding modes to obtain the arrangement of the bin sequence of the binaryized syntax information. According to the arrangement, the bin sequence of the binaryized syntax information is arranged and divided to obtain multiple pieces of information to be encoded.

[0147] In other embodiments, one implementation of the step of performing binary arithmetic encoding on multiple pieces of information to be encoded in the corresponding target encoding path to obtain target encoded information in the binary arithmetic encoding method specifically includes:

[0148] The system sequentially acquires the information to be encoded, and performs binary arithmetic encoding on the information to be encoded in the corresponding target encoding path for each acquired information to be encoded, so as to obtain the target encoded information. This process continues until the information to be encoded includes the termination encoding syntax, at which point all target encoded information is packaged and output.

[0149] Specifically, when the information to be encoded includes a termination encoding syntax, the encoding can be terminated by calling the `EncodeTerminate` process. All the obtained target encoded information is then packaged and output as a final bitstream. For example, when the information to be encoded includes a termination encoding syntax, the encoding process continues until all the information to be encoded obtained from the binary-encoded syntax information has completed binary arithmetic encoding in the corresponding target encoding path. Then, all the obtained target encoded information is packaged and output as a final bitstream. The information to be encoded, including the termination encoding syntax, can also complete binary arithmetic encoding in the corresponding target encoding path, and corresponding target encoded information also exists there.

[0150] In some embodiments, when none of the current information to be encoded includes the termination encoding syntax, the process continues to return to the step of obtaining the binary syntax information until the information to be encoded includes the termination encoding syntax, and then all target encoded information is packaged and output.

[0151] In the binary arithmetic encoding method described in the above embodiments, the binary syntax information can be divided according to the binaryized syntax information of CABAC and the characteristics of the binary arithmetic encoding structure to obtain multiple pieces of information to be encoded, and the corresponding encoding mode and target encoding path can be selected. Then, the binary arithmetic encoding of the information to be encoded can be performed according to the target encoding path to obtain the target encoded information.

[0152] The above encoding method can flexibly handle different bin value arrangements generated by CABAC in H.266, increasing the encoding flexibility of the VPU chip. It can also select the optimal encoding mode and encoding path based on the binary syntax information, which can perfectly match the encoding calculation efficiency without affecting the overall system performance, and can improve the encoding rate of CABAC in H.266.

[0153] In another embodiment of this application, a computer storage medium is also provided, wherein computer execution instructions are stored in the computer storage medium, and the computer execution instructions are executed by a processor to implement any of the methods described above in the binary arithmetic encoding method.

[0154] The computer-readable storage medium can be any medium capable of storing program code, such as a USB flash drive, portable hard drive, read-only memory, random access memory, or optical disc.

[0155] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A binary arithmetic encoding structure, characterized in that, include: M first coding units connected sequentially along the first direction, where M is a positive integer greater than 1; And a second coding unit, the second coding unit being connected to the Mth first coding unit arranged along the first direction; The first encoding unit includes a selector and a first conventional encoder and a bypass encoder respectively connected to the selector; The second encoding unit includes a second conventional encoder; The selector is used to determine the input unit in the first encoding unit based on the received information to be encoded. The input unit is the selector, the first conventional encoder, or the bypass encoder. The input units and selectors in all the first coding units along the first direction, and the output units sequentially form the target coding path of the information to be encoded. The output unit is either the second conventional encoder or the bypass encoder in the Mth first coding unit arranged along the first direction. Along the first direction, the selector in the (N-1)th first coding unit is connected to the first conventional encoder, the bypass encoder, and the selector in the Nth first coding unit, respectively, where N∈M; The selector in the Mth first encoding unit is connected to the second conventional encoder.

2. The binary arithmetic encoding structure as described in claim 1, characterized in that, The first input unit along the first direction is the first conventional encoder or bypass encoder in the first encoding unit.

3. The binary arithmetic encoding structure as described in claim 1, characterized in that, The binary arithmetic coding structure includes Each encoded path, the Each encoding path includes the target encoding path.

4. A binary arithmetic encoding device, characterized in that, Includes the binary arithmetic coding structure as described in any one of claims 1-3.

5. The apparatus according to claim 4, characterized in that, The binary arithmetic encoding device has multiple preset encoding modes, each of which corresponds to multiple encoding paths, including a target encoding path; the device also includes an encoding mode determination module. The encoding mode determination module is used to divide the binary syntax information according to the multiple preset encoding modes to obtain the information to be encoded, and to determine the corresponding target encoding path according to the information to be encoded. The binary arithmetic encoding structure is used to obtain the information to be encoded, and to perform binary arithmetic encoding on the information to be encoded in the corresponding target encoding path to obtain the target encoded information.

6. The apparatus according to claim 5, characterized in that, The preset encoding mode is divided based on the number of bin values ​​of the binary syntax information that the binary arithmetic encoding structure can process within one clock cycle, and the encoding order of the conventional encoder and the bypass encoder in the binary arithmetic encoding structure.

7. A binary arithmetic encoding method, characterized in that, The method is applied to the binary arithmetic encoding apparatus according to any one of claims 4 to 6, the method comprising: Obtain the binary syntax information; Based on multiple preset encoding modes, the binary syntax information is divided to obtain multiple pieces of information to be encoded and the encoding modes corresponding to the multiple pieces of information to be encoded. Based on the encoding patterns corresponding to the multiple pieces of information to be encoded, the target encoding paths corresponding to the multiple pieces of information to be encoded are determined; In the corresponding target encoding path, multiple pieces of information to be encoded are binary arithmetic encoded to obtain target encoded information.

8. The binary arithmetic encoding method as described in claim 7, characterized in that, The binary syntax information is divided according to multiple preset encoding modes to obtain multiple pieces of information to be encoded, including: The bin sequence of the binary syntax information is arranged and divided according to multiple preset encoding modes to obtain the multiple pieces of information to be encoded.

9. The binary arithmetic encoding method as described in claim 7, characterized in that, The step of performing binary arithmetic encoding on multiple pieces of information to be encoded in the corresponding target encoding path to obtain target encoded information includes: The information to be encoded is obtained sequentially, and in each case where the information to be encoded is obtained, binary arithmetic encoding is performed on the information to be encoded in the corresponding target encoding path to obtain target encoding information. When the information to be encoded includes the termination encoding syntax, all the target encoding information is packaged and output.

10. A computer storage medium, characterized in that, The computer storage medium stores computer execution instructions, which, when executed by a processor, are used to implement the method as described in any one of claims 7 to 9.

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