A slope controllable linear current output circuit

Abstract

The application provides a linear current output circuit with controllable slope, comprising: a first delay driving module, a first input end of which is connected to a host computer to receive a first control signal and process the first control signal to obtain a first driving signal and a second control signal, and output the first driving signal to a first output end and output the second control signal to a second output end after a preset time interval; at least one second delay driving module, which is used to receive the second control signal and process the second control signal to obtain a second driving signal and output the second driving signal to an output end; a current limiting module, which is used to receive an externally input first current and output a limited current as the first driving signal and the second driving signal according to the first current; and a linear current output module, which is used to output a first working current when the first driving signal is received and output a second working current which is linearly increased after a preset time interval when the second driving signal is received. The application has the beneficial effect that the number of power tubes that are turned on can be controlled to output a linearly increased current.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and in particular to a linear current output circuit with controllable slope. Background Technology

[0002] Many integrated circuits are currently used in applications with high requirements for electromagnetic interference, which poses a great challenge to circuit output design. According to signal spectrum analysis, the larger the slew rate of the output signal, the more high-frequency components it contains, and the greater the electromagnetic interference generated.

[0003] The traditional way to reduce electromagnetic interference from the output current is to insert a resistor in series with the gate of the power transistor. The principle of this structure is to use the resistor and gate capacitance to delay the signal, so that the gate voltage of the power transistor rises or falls slowly, and the output current of the power transistor also increases or decreases slowly, thereby reducing the electromagnetic interference of the output current. However, the output current of this structure is non-linear, and the slope of the output current cannot be adjusted. Summary of the Invention

[0004] To address the problems existing in the prior art, the present invention provides a linear current output circuit with controllable slope, comprising:

[0005] A first delay driving module, wherein the first input terminal of the first delay driving module is connected to an external preceding circuit, the first delay driving module receives a first control signal output by the preceding circuit and processes it according to the first control signal to obtain a first driving signal and a second control signal, and outputs the first driving signal to a first output terminal and outputs the second control signal to a second output terminal after a preset time interval;

[0006] At least one second delay driving module, wherein the first input terminal of the second delay driving module is connected to the second output terminal of the first delay driving module, the second delay driving module receives the second control signal and processes it according to the second control signal to obtain a second driving signal, and outputs the first driving signal to the output terminal;

[0007] A current limiting module is provided, wherein the input terminal of the current limiting module is connected to an external current source, and the output terminal of the current limiting module is connected to the second input terminal of the first delay driving module and the second input terminal of the second delay driving module, respectively. The current limiting module receives a first current input from the external current source and outputs a limiting current to the first delay driving module and the second delay driving module as the first driving signal and the second driving signal, respectively, based on the first current.

[0008] A linear current output module, wherein the first input terminal of the linear current output module is connected to the first output terminal of the first delay drive module, and the second input terminal of the linear current output module is connected to the output terminal of the second delay drive module. The linear current output module outputs a first operating current when it receives the first drive signal and outputs a second operating current that is linearly increased when it receives the second drive signal after the preset time interval.

[0009] Preferably, the first delay driving module includes:

[0010] A first delay unit is provided, the input terminal of the first delay unit is connected to the preceding circuit, the output terminal of the first delay unit is connected to the first input terminal of the second delay driving module, the first delay unit receives the first control signal and processes it according to the first control signal to obtain a first conduction signal and a second control signal, and outputs the first conduction signal to the output terminal and outputs the second control signal to the second delay driving module after the preset time interval;

[0011] A first driving unit, the input terminal of the first driving unit is connected to the output terminal of the first delay unit, and the first driving unit outputs a first selection signal according to the first conduction signal when it receives the first conduction signal;

[0012] A first output selection unit, wherein a first input terminal of the first output selection unit is connected to the output terminal of the first driving unit, a second input terminal of the first output selection unit is connected to an external current source and receives a second current output by the external current source, and a third input terminal of the first output selection unit is connected to the output terminal of the current limiting module and receives the limiting current; the first output selection unit outputs the second current as the first driving signal when it does not receive the first selection signal; and

[0013] Upon receiving the first selection signal, the limiting current is output as the first driving signal;

[0014] The input terminal of the first delay unit serves as the first input terminal of the first delay driving module, the third input terminal of the first output selection unit serves as the second input terminal of the first delay driving module, the output terminal of the first output selection unit serves as the first output terminal of the first delay driving module, and the output terminal of the first delay unit serves as the second output terminal of the first delay driving module.

[0015] Preferably, the first delay unit is a buffer, and the first driving unit is a driver.

[0016] Preferably, the first output selection unit includes:

[0017] A first field-effect transistor, the gate of the first field-effect transistor is connected to the output terminal of the first driving unit, the source of the first field-effect transistor is connected to the external current source, and the drain of the first field-effect transistor is connected to the first input terminal of the linear current output module;

[0018] A second field-effect transistor (FET) is provided, the source of which is connected to the drain of the first FET, and the drain of the second FET is connected to the output terminal of the current limiting module.

[0019] A first inverter, the input terminal of the first inverter is connected to the gate of the first field-effect transistor, and the output terminal of the first inverter is connected to the gate of the second field-effect transistor;

[0020] The gate of the first field-effect transistor serves as the first input terminal of the first output selection unit, the source of the first field-effect transistor serves as the second input terminal of the first output selection unit, the drain of the second field-effect transistor serves as the third input terminal of the first output selection unit, and the drain of the first field-effect transistor serves as the output terminal of the first output selection unit.

[0021] When the first selection signal is not received, the first field-effect transistor is turned on, the second field-effect transistor is turned off, and the second current is output as the first drive signal; and

[0022] Upon receiving the first selection signal, the first field-effect transistor is turned off, the second field-effect transistor is turned on, and the limiting current is output as the first driving signal.

[0023] Preferably, the second delay driving module includes:

[0024] A second delay unit is provided, wherein the input terminal of the second delay unit is connected to the second output terminal of the first delay driving module, the second delay unit receives the second control signal and processes it according to the second control signal to obtain a second conduction signal, and outputs the second conduction signal to the output terminal;

[0025] A second driving unit, the input terminal of the second driving unit is connected to the output terminal of the second delay unit, and the second driving unit outputs a second selection signal according to the second conduction signal when it receives the second conduction signal;

[0026] A second output selection unit, wherein the first input terminal of the second output selection unit is connected to the output terminal of the second drive unit, the second input terminal of the second output selection unit is connected to an external current source and receives a second current output by the external current source, and the third input terminal of the second output selection unit is connected to the output terminal of the current limiting module and receives the limiting current; the second output selection unit outputs the second current as the second drive signal when it does not receive the second selection signal; and

[0027] Upon receiving the second selection signal, the limiting current is output as the second drive signal;

[0028] The input terminal of the second delay unit serves as the first input terminal of the second delay driving module, the third input terminal of the second output selection unit serves as the second input terminal of the second delay driving module, and the output terminal of the second output selection unit serves as the output terminal of the second delay driving module.

[0029] Preferably, the second delay unit is a buffer.

[0030] Preferably, the second driving unit is a driver.

[0031] Preferably, the second output selection unit includes:

[0032] A third field-effect transistor, wherein the gate of the third field-effect transistor is connected to the output terminal of the second driving unit, the source of the third field-effect transistor is connected to the external current source, and the drain of the third field-effect transistor is connected to the second input terminal of the linear current output module;

[0033] A fourth field-effect transistor, the source of which is connected to the drain of the third field-effect transistor, and the source of which is connected to the output of the current limiting module;

[0034] A second inverter, the input terminal of which is connected to the gate of the third field-effect transistor, and the output terminal of which is connected to the gate of the fourth field-effect transistor;

[0035] The gate of the third field-effect transistor serves as the first input terminal of the second output selection unit, the source of the third field-effect transistor serves as the second input terminal of the second output selection unit, the drain of the fourth field-effect transistor serves as the third input terminal of the second output selection unit, and the drain of the third field-effect transistor serves as the output terminal of the second output selection unit.

[0036] When the second selection signal is not received, the third field-effect transistor is turned on, the fourth field-effect transistor is turned off, and the second current is output as the second drive signal; and

[0037] Upon receiving the second selection signal, the third field-effect transistor is turned off, the fourth field-effect transistor is turned on, and the limiting current is output as the second driving signal.

[0038] Preferably, the linear current output module includes:

[0039] A first power transistor, the gate of the first power transistor is connected to the first output terminal of the first delay drive module, the source of the first power transistor is connected to an external current source, and the drain of the first power transistor is connected to an external load module.

[0040] A second power transistor, the gate of which is connected to the output terminal of the second delay drive module, the source of which is connected to the source of the first power transistor, and the drain of which is connected to the load module;

[0041] The gate of the first power transistor serves as the first input terminal of the linear current output module, the gate of the second power transistor serves as the second input terminal of the linear current output module, and the drain of the second power transistor serves as the output terminal of the linear current output module.

[0042] When the first drive signal received by the first power transistor is the second current, the first power transistor is turned off; when the first drive signal received by the first power transistor is the limiting current, the first power transistor is turned on and outputs the first operating current.

[0043] When the second drive signal received by the second power transistor is the second current, the second power transistor is turned off; when the second drive signal received by the second power transistor is the limiting current, the second power transistor is turned on and outputs the second operating current after the first operating current is linearly increased.

[0044] Preferably, the current limiting module includes:

[0045] A constant current source, the input terminal of which is connected to the external current source, receives the first current through the constant current source and outputs the limiting current according to the first current;

[0046] A fifth field-effect transistor, wherein the gate and drain of the fifth field-effect transistor are connected to the output terminal of the constant current source;

[0047] A sixth field-effect transistor, wherein the gate of the sixth field-effect transistor is connected to the gate of the fifth field-effect transistor, the source of the sixth field-effect transistor is connected to the source of the fifth field-effect transistor, and the drain of the sixth field-effect transistor is connected to the second input terminal of the first delay driving module and the second input terminal of the second delay driving module, respectively.

[0048] The input terminal of the constant current source serves as the input terminal of the current limiting module, and the drain of the sixth field-effect transistor serves as the output terminal of the current limiting module.

[0049] The limiting current is mirrored to the drain of the sixth field-effect transistor through the fifth field-effect transistor, and the limiting current is output through the drain of the sixth field-effect transistor.

[0050] The above technical solution has the following advantages or beneficial effects: The linear current output circuit in this invention outputs a first drive signal and a second drive signal that are delayed between each other through the first delay drive module and the second delay drive module to control the power transistors to turn on in sequence and thus output a linearly increasing output current. At the same time, the slope of the output current can be adjusted by adjusting the number of the second delay drive module and the power transistors. Attached Figure Description

[0051] Figure 1 The electrical schematic diagram of this circuit is shown in a preferred embodiment of the present invention.

[0052] Figure 2 The electrical schematic diagram of the first output selection unit is shown in a preferred embodiment of the present invention.

[0053] Figure 3 The electrical schematic diagram of the second output selection unit is shown in a preferred embodiment of the present invention. Detailed Implementation

[0054] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments. The present invention is not limited to this embodiment; other embodiments that conform to the spirit of the present invention may also fall within the scope of the present invention.

[0055] In a preferred embodiment of the present invention, based on the above-mentioned problems existing in the prior art, a linear current output circuit with controllable slope is provided, such as... Figure 1 As shown, it includes:

[0056] A first delay driving module 1, the first input terminal of the first delay driving module 1 is connected to an external preceding circuit, the first delay driving module 1 receives a first control signal output by the preceding circuit and processes it according to the first control signal to obtain a first driving signal and a second control signal, and outputs the first driving signal to the first output terminal and outputs the second control signal to the second output terminal after a preset time interval.

[0057] At least one second delay driving module 2, the first input terminal of the second delay driving module 2 is connected to the second output terminal of the first delay driving module 1, the second delay driving module 2 receives a second control signal and processes it according to the second control signal to obtain a second driving signal, and outputs the first driving signal to the output terminal;

[0058] A current limiting module 3 is provided. The input terminal of the current limiting module 3 is connected to an external current source. The output terminal of the current limiting module 3 is connected to the second input terminal of the first delay drive module 1 and the second input terminal of the second delay drive module 2, respectively. The current limiting module 3 receives the first current input from the external current source and outputs a limiting current to the first delay drive module 1 and the second delay drive module 2 as the first drive signal and the second drive signal, respectively.

[0059] A linear current output module 4 is provided. The first input terminal of the linear current output module 4 is connected to the first output terminal of the first delay drive module 1, and the second input terminal of the linear current output module 4 is connected to the output terminal of the second delay drive module 2. When the linear current output module 4 receives the first drive signal, it outputs a first working current and when it receives the second drive signal after a preset time interval, it outputs a second working current that is linearly increased.

[0060] Specifically, in this embodiment, considering that the output current of the linear current output module 4 is continuously increasing linearly, this circuit includes two cases: setting one second delay drive module 2 and setting multiple second delay drive modules 2. When setting one second delay drive module 2, the second delay drive module 2 only outputs the second drive signal to the linear current output module 4 to control the linear current output module 4 to output the second working current after linear increase.

[0061] Preferably, after a preset time interval when the first delay drive module 1 outputs the first drive signal, the second delay drive module 2 outputs the second drive signal to ensure that the output current can increase linearly.

[0062] Preferably, when multiple second delay drive modules 2 are set, the second delay drive modules 2 are connected in series. The second delay drive module 2 connected to the first delay drive module 1 not only outputs the second drive signal, but also needs to process the second control signal output by the first delay drive module 1 to obtain a third control signal and output the third control signal to the output terminal of the connected second delay drive module 2 so that the connected second delay drive module 2 outputs the third drive signal and the fourth control signal according to the third control signal, and is sequentially transmitted to the nth second delay drive module 2 according to the above processing method.

[0063] Preferably, due to the increase in the number of second delay drive modules 2, the linear current output module 4 can output a linearly increased third working current up to the nth working current after a preset time interval of outputting the second working current.

[0064] Preferably, by adjusting the number of the second delay drive modules 2, the slope of the first working current, the second working current to the nth working current can be adjusted, so as to achieve controllable slope.

[0065] Specifically, in this embodiment, according to the current formula I=k*m*(W / L)*(Vgs-Vth)2, the magnitude of the output current is linearly proportional to the number of power transistors turned on m. Therefore, as long as the power transistors are turned on one after another, the output current will increase linearly.

[0066] In a preferred embodiment of the present invention, the first delay driving module 1 includes:

[0067] A first delay unit B1 is provided. The input terminal of the first delay unit B1 is connected to the preceding circuit, and the output terminal of the first delay unit B1 is connected to the first input terminal of the second delay driving module 2. The first delay unit B1 receives a first control signal and processes it to obtain a first conduction signal and a second control signal. The first conduction signal is output to the output terminal, and the second control signal is output to the second delay driving module 2 after a preset time interval.

[0068] A first driving unit X1, the input terminal of the first driving unit X1 is connected to the output terminal of the first delay unit B1, and the first driving unit X1 outputs a first selection signal according to the first conduction signal when it receives the first conduction signal;

[0069] A first output selection unit mux1 has a first input terminal connected to the output terminal of a first drive unit X1, a second input terminal connected to an external current source and receiving a second current output from the external current source, and a third input terminal connected to the output terminal of a current limiting module 3 and receiving a current limit. When no first selection signal is received, the first output selection unit mux1 outputs the second current as a first drive signal.

[0070] Upon receiving the first selection signal, the current limit is output as the first drive signal;

[0071] The input terminal of the first delay unit B1 serves as the first input terminal of the first delay driving module 1, the third input terminal of the first output selection unit mux1 serves as the second input terminal of the first delay driving module 1, the output terminal of the first output selection unit mux1 serves as the first output terminal of the first delay driving module 1, and the output terminal of the first delay unit B1 serves as the second output terminal of the first delay driving module 1.

[0072] Specifically, in this embodiment, the delay unit B2 receives the first control signal input from the outside and processes it to obtain the first conduction signal and the second control signal. After a preset time interval between outputting the first conduction signal to the first drive unit X1, the second control signal is output to the second delay drive module 2 to ensure that there is a preset time interval between the final output first drive signal and the second drive signal.

[0073] Preferably, since there is a preset time interval between the first drive signal and the second drive signal, the linear increasing relationship between the first operating current and the second operating current is more obvious.

[0074] Preferably, the first conduction signal and the second control signal are the same output signal.

[0075] In a preferred embodiment of the present invention, the first delay unit B1 is a buffer and the first driving unit X1 is a driver.

[0076] In a preferred embodiment of the present invention, such as Figure 2 As shown, the first output selection unit mux1 includes:

[0077] A first field-effect transistor S1, the gate of the first field-effect transistor S1 is connected to the output terminal of the first driving unit X1, the source of the first field-effect transistor S1 is connected to an external current source, and the drain of the first field-effect transistor S1 is connected to the first input terminal of the linear current output module 4.

[0078] A second field-effect transistor S2 is connected to the drain of the first field-effect transistor S1, and the drain of the second field-effect transistor S2 is connected to the output terminal of the current limiting module 3.

[0079] A first inverter T1 is connected to the gate of a first field-effect transistor S1, and the output of the first inverter T1 is connected to the gate of a second field-effect transistor S2.

[0080] The gate of the first field-effect transistor S1 serves as the first input terminal of the first output selection unit mux1, the source of the first field-effect transistor S1 serves as the second input terminal of the first output selection unit mux1, the drain of the second field-effect transistor S2 serves as the third input terminal of the first output selection unit mux1, and the drain of the first field-effect transistor S1 serves as the output terminal of the first output selection unit mux1.

[0081] When no first selection signal is received, the first field-effect transistor S1 is turned on, the second field-effect transistor S2 is turned off, and the second current is output as the first drive signal; and

[0082] When the first selection signal is received, the first field-effect transistor S1 is turned off and the second field-effect transistor S2 is turned on, and the current is limited as the first driving signal for output.

[0083] Specifically, in this embodiment, both the first field-effect transistor S1 and the second field-effect transistor S2 are PMOS transistors. Therefore, at any given time, only one of the first field-effect transistor S1 and the second field-effect transistor S2 can be turned on. When the first output selection unit mux1 receives the first selection signal, the first field-effect transistor S1 is turned off, and the first inverter T1 outputs a low-level signal to turn on the second field-effect transistor S2. When the first output selection unit mux1 does not receive the first selection signal, the second field-effect transistor S2 is turned off, and the first inverter T1 outputs a high-level signal to turn on the first field-effect transistor S1.

[0084] In a preferred embodiment of the present invention, the second delay driving module 2 includes:

[0085] A second delay unit B2 is provided. The input terminal of the second delay unit B2 is connected to the second output terminal of the first delay driving module 1. The second delay unit B2 receives a second control signal and processes it to obtain a second conduction signal, and outputs the second conduction signal to the output terminal.

[0086] A second driving unit X2, the input terminal of the second driving unit X2 is connected to the output terminal of the second delay unit B2, and the second driving unit X2 outputs a second selection signal according to the second conduction signal when it receives the second conduction signal;

[0087] A second output selection unit mux2 has its first input connected to the output of the second drive unit X2, its second input connected to an external current source and receiving a second current output from the external current source, and its third input connected to the output of the current limiting module 3 and receiving a current limit. When no second selection signal is received, the second output selection unit mux2 outputs the second current as a second drive signal.

[0088] Upon receiving the second selection signal, the current limit is output as the second drive signal;

[0089] The input terminal of the second delay unit B2 serves as the first input terminal of the second delay driving module 2, the third input terminal of the second output selection unit mux2 serves as the second input terminal of the second delay driving module 2, and the output terminal of the second output selection unit mux2 serves as the output terminal of the second delay driving module 2.

[0090] Specifically, in this embodiment, when multiple second delay driving modules 2 are provided, the output terminal of the delay unit in each second delay driving module 2 serves as the second output terminal of the second delay driving module 2 to output the processed control signal to the connected second delay driving module 2.

[0091] Preferably, when the number of second delay driving modules 2 is n, the current limiting module 3 needs to be connected to the output selection unit in each second delay driving module 2. The output selection unit includes the first output selection unit mux1, the second output selection unit mux2 to the nth output selection unit muxn.

[0092] In a preferred embodiment of the present invention, the second delay unit B2 is a buffer.

[0093] In a preferred embodiment of the present invention, the second driving unit X2 is a driver.

[0094] In a preferred embodiment of the present invention, such as Figure 3 As shown, the second output selection unit mux2 includes:

[0095] A third field-effect transistor S3, the gate of the third field-effect transistor S3 is connected to the output terminal of the second driving unit X2, the source of the third field-effect transistor S3 is connected to an external current source, and the drain of the third field-effect transistor S3 is connected to the second input terminal of the linear current output module 4.

[0096] A fourth field-effect transistor S4 is connected to the drain of the third field-effect transistor S3, and the drain of the fourth field-effect transistor S4 is connected to the output terminal of the current limiting module 3.

[0097] A second inverter T2 is connected to the gate of a third field-effect transistor S3, and its output is connected to the gate of a fourth field-effect transistor S4.

[0098] The gate of the third field-effect transistor S3 serves as the first input terminal of the second output selection unit mux2, the source of the third field-effect transistor S3 serves as the second input terminal of the second output selection unit mux2, the drain of the fourth field-effect transistor S4 serves as the third input terminal of the second output selection unit mux2, and the drain of the third field-effect transistor S3 serves as the output terminal of the second output selection unit mux2.

[0099] When no second selection signal is received, the third field-effect transistor S3 is turned on, the fourth field-effect transistor S4 is turned off, and the second current is output as the second drive signal; and

[0100] When the second selection signal is received, the third field-effect transistor S3 is turned off and the fourth field-effect transistor S4 is turned on, limiting the current as the second drive signal for output.

[0101] Specifically, in this embodiment, both the third field-effect transistor S3 and the fourth field-effect transistor S4 are PMOS transistors. Therefore, at any given time, only one of the third field-effect transistor S3 and the fourth field-effect transistor S4 can be turned on. When the second output selection unit mux2 receives the second selection signal, the third field-effect transistor S3 is turned off, and the second inverter T2 outputs a low-level signal to turn on the fourth field-effect transistor S4. When the second output selection unit mux2 does not receive the second selection signal, the third field-effect transistor S3 is turned off, and the second inverter T2 outputs a high-level signal to turn on the fourth field-effect transistor S4.

[0102] Preferably, when the number of second delay drive modules 2 is n, the control method of the field effect transistors in the third output selection unit mux3 to the nth output selection unit muxn is the same as that in the first output selection unit mux1 and the second output selection unit mux2.

[0103] In a preferred embodiment of the present invention, the linear current output module 4 includes:

[0104] A first power transistor Q1, the gate of the first power transistor Q1 is connected to the first output terminal of the first delay drive module 1, the source of the first power transistor Q1 is connected to an external current source, and the drain of the first power transistor Q1 is connected to an external load module.

[0105] A second power transistor Q2 is connected to the output terminal of the second delay drive module 2, the source of the second power transistor Q2 is connected to the source of the first power transistor Q1, and the drain of the second power transistor Q2 is connected to the load module.

[0106] The gate of the first power transistor Q1 serves as the first input terminal of the linear current output module 4, the gate of the second power transistor Q2 serves as the second input terminal of the linear current output module 4, and the drain of the second power transistor Q2 serves as the output terminal of the linear current output module 4.

[0107] When the first drive signal received by the first power transistor Q1 is the second current, the first power transistor Q1 is cut off; when the first drive signal received by the first power transistor Q1 is the limiting current, the first power transistor Q1 is turned on and outputs the first working current.

[0108] When the second drive signal received by the second power transistor Q2 is the second current, the second power transistor Q2 is turned off. When the second drive signal received by the second power transistor Q2 is the limiting current, the second power transistor Q2 is turned on and outputs the second operating current after the first operating current is linearly increased.

[0109] In a preferred embodiment of the present invention, the current limiting module 3 includes:

[0110] A constant current source A1 is connected to an external current source. The constant current source A1 receives a first current and outputs a limiting current based on the first current.

[0111] A fifth field-effect transistor S5, the gate and drain of the fifth field-effect transistor S5 are connected to the output terminal of the constant current source A1;

[0112] A sixth field-effect transistor S6 is connected to the gate of the fifth field-effect transistor S5, the source of the sixth field-effect transistor S6 is connected to the source of the fifth field-effect transistor S5, and the drain of the sixth field-effect transistor S6 is connected to the second input terminal of the first delay driving module 1 and the second input terminal of the second delay driving module 2.

[0113] The input terminal of the constant current source A1 serves as the input terminal of the current limiting module 3, and the drain of the sixth field-effect transistor S6 serves as the output terminal of the current limiting module 3.

[0114] The limiting current is mirrored to the drain of the sixth field-effect transistor S6 through the fifth field-effect transistor S5, and the limiting current is output through the drain of the sixth field-effect transistor S6.

[0115] Specifically, in this embodiment, the fifth field-effect transistor S5 and the sixth field-effect transistor S6 form a current mirror structure so as not to change the magnitude of the limiting current.

[0116] Preferably, when the first drive signal output by the first output selection unit mux1 is the second current, the first output selection unit mux1 is disconnected from the current limiting module 3. When the first drive signal output by the first output selection unit mux1 is the limiting current, the gate of the first power transistor Q1 and the drain of the sixth field-effect transistor S6 are connected, and the maximum gate current of the first power transistor Q1 is set as the limiting current, thereby limiting the spike voltage or current generated instantaneously when the first power transistor Q1 is turned on, thereby reducing the electromagnetic interference of the first operating current.

[0117] Preferably, when the second drive signal output by the second output selection unit mux2 is the second current, the second output selection unit mux2 is disconnected from the current limiting module 3. When the second drive signal output by the second output selection unit mux2 is the limiting current, the gate of the second power transistor Q2 and the drain of the sixth field-effect transistor S6 are connected, and the maximum gate current of the second power transistor Q2 is set as the limiting current, thereby limiting the spike voltage or current generated instantaneously when the second power transistor Q2 is turned on, thereby reducing the electromagnetic interference of the second operating current.

[0118] Preferably, if the circuit has multiple second delay drive modules 2, the corresponding power transistors are handled in the same way.

[0119] The above description is merely a preferred embodiment of the present invention and does not limit the implementation and protection scope of the present invention. Those skilled in the art should realize that any equivalent substitutions and obvious changes made using the content of this specification and illustrations should be included within the protection scope of the present invention.

Claims

1. A linear current output circuit with controllable slope, characterized in that, include: A first delay driving module, wherein the first input terminal of the first delay driving module is connected to an external preceding circuit, the first delay driving module receives a first control signal output by the preceding circuit and processes it according to the first control signal to obtain a first driving signal and a second control signal, and outputs the first driving signal to a first output terminal and outputs the second control signal to a second output terminal after a preset time interval; Multiple second delay drive modules are provided. The first input terminal of the second delay drive module is connected to the second output terminal of the first delay drive module. The second delay drive module receives the second control signal, processes it according to the second control signal to obtain a second drive signal, and outputs the second drive signal to the output terminal. A current limiting module is provided, wherein the input terminal of the current limiting module is connected to an external current source, and the output terminal of the current limiting module is connected to the second input terminal of the first delay driving module and the second input terminal of the second delay driving module, respectively. The current limiting module receives a first current input from the external current source and outputs a limiting current to the first delay driving module and the second delay driving module as the first driving signal and the second driving signal, respectively, based on the first current. A linear current output module, wherein the first input terminal of the linear current output module is connected to the first output terminal of the first delay drive module, and the second input terminal of the linear current output module is connected to the output terminal of the second delay drive module. The linear current output module outputs a first operating current when it receives the first drive signal and outputs a second operating current that is linearly increased when it receives the second drive signal after the preset time interval.

2. The linear current output circuit according to claim 1, characterized in that, The first delay driving module includes: A first delay unit is provided, the input terminal of the first delay unit is connected to the preceding circuit, the output terminal of the first delay unit is connected to the first input terminal of the second delay driving module, the first delay unit receives the first control signal and processes it according to the first control signal to obtain a first conduction signal and a second control signal, and outputs the first conduction signal to the output terminal and outputs the second control signal to the second delay driving module after the preset time interval; A first driving unit, the input terminal of the first driving unit is connected to the output terminal of the first delay unit, and the first driving unit outputs a first selection signal according to the first conduction signal when it receives the first conduction signal; A first output selection unit, wherein a first input terminal of the first output selection unit is connected to the output terminal of the first driving unit, a second input terminal of the first output selection unit is connected to an external current source and receives a second current output by the external current source, and a third input terminal of the first output selection unit is connected to the output terminal of the current limiting module and receives the limiting current; the first output selection unit outputs the second current as the first driving signal when it does not receive the first selection signal; and Upon receiving the first selection signal, the limiting current is output as the first driving signal; The input terminal of the first delay unit serves as the first input terminal of the first delay driving module, the third input terminal of the first output selection unit serves as the second input terminal of the first delay driving module, the output terminal of the first output selection unit serves as the first output terminal of the first delay driving module, and the output terminal of the first delay unit serves as the second output terminal of the first delay driving module.

3. The linear current output circuit according to claim 2, characterized in that, The first delay unit is a buffer, and the first drive unit is a driver.

4. The linear current output circuit according to claim 2, characterized in that, The first output selection unit includes: A first field-effect transistor, the gate of the first field-effect transistor is connected to the output terminal of the first driving unit, the source of the first field-effect transistor is connected to the external current source, and the drain of the first field-effect transistor is connected to the first input terminal of the linear current output module; A second field-effect transistor (FET) is provided, the source of which is connected to the drain of the first FET, and the drain of the second FET is connected to the output terminal of the current limiting module. A first inverter, the input terminal of the first inverter is connected to the gate of the first field-effect transistor, and the output terminal of the first inverter is connected to the gate of the second field-effect transistor; The gate of the first field-effect transistor serves as the first input terminal of the first output selection unit, the source of the first field-effect transistor serves as the second input terminal of the first output selection unit, the drain of the second field-effect transistor serves as the third input terminal of the first output selection unit, and the drain of the first field-effect transistor serves as the output terminal of the first output selection unit. When the first selection signal is not received, the first field-effect transistor is turned on, the second field-effect transistor is turned off, and the second current is output as the first drive signal; and Upon receiving the first selection signal, the first field-effect transistor is turned off, the second field-effect transistor is turned on, and the limiting current is output as the first driving signal.

5. The linear current output circuit according to claim 1, characterized in that, The second delay driving module includes: A second delay unit is provided, wherein the input terminal of the second delay unit is connected to the second output terminal of the first delay driving module, the second delay unit receives the second control signal and processes it according to the second control signal to obtain a second conduction signal, and outputs the second conduction signal to the output terminal; A second driving unit, the input terminal of the second driving unit is connected to the output terminal of the second delay unit, and the second driving unit outputs a second selection signal according to the second conduction signal when it receives the second conduction signal; A second output selection unit, wherein the first input terminal of the second output selection unit is connected to the output terminal of the second drive unit, the second input terminal of the second output selection unit is connected to an external current source and receives a second current output by the external current source, and the third input terminal of the second output selection unit is connected to the output terminal of the current limiting module and receives the limiting current; the second output selection unit outputs the second current as the second drive signal when it does not receive the second selection signal; and Upon receiving the second selection signal, the limiting current is output as the second drive signal; The input terminal of the second delay unit serves as the first input terminal of the second delay driving module, the third input terminal of the second output selection unit serves as the second input terminal of the second delay driving module, and the output terminal of the second output selection unit serves as the output terminal of the second delay driving module.

6. The linear current output circuit according to claim 5, characterized in that, The second delay unit is a buffer.

7. The linear current output circuit according to claim 5, characterized in that, The second driving unit is a driver.

8. The linear current output circuit according to claim 5, characterized in that, The second output selection unit includes: A third field-effect transistor, wherein the gate of the third field-effect transistor is connected to the output terminal of the second driving unit, the source of the third field-effect transistor is connected to the external current source, and the drain of the third field-effect transistor is connected to the second input terminal of the linear current output module; A fourth field-effect transistor, the source of which is connected to the drain of the third field-effect transistor, and the drain of which is connected to the output of the current limiting module; A second inverter, the input terminal of which is connected to the gate of the third field-effect transistor, and the output terminal of which is connected to the gate of the fourth field-effect transistor; The gate of the third field-effect transistor serves as the first input terminal of the second output selection unit, the source of the third field-effect transistor serves as the second input terminal of the second output selection unit, the drain of the fourth field-effect transistor serves as the third input terminal of the second output selection unit, and the drain of the third field-effect transistor serves as the output terminal of the second output selection unit. When the second selection signal is not received, the third field-effect transistor is turned on, the fourth field-effect transistor is turned off, and the second current is output as the second drive signal; and Upon receiving the second selection signal, the third field-effect transistor is turned off, the fourth field-effect transistor is turned on, and the limiting current is output as the second driving signal.

9. The linear current output circuit according to claim 1, characterized in that, The linear current output module includes: A first power transistor, the gate of the first power transistor is connected to the first output terminal of the first delay drive module, the source of the first power transistor is connected to an external current source, and the drain of the first power transistor is connected to an external load module. A second power transistor, the gate of which is connected to the output terminal of the second delay drive module, the source of which is connected to the source of the first power transistor, and the drain of which is connected to the load module; The gate of the first power transistor serves as the first input terminal of the linear current output module, the gate of the second power transistor serves as the second input terminal of the linear current output module, and the drain of the second power transistor serves as the output terminal of the linear current output module. When the first drive signal received by the first power transistor is the second current, the first power transistor is turned off; when the first drive signal received by the first power transistor is the limiting current, the first power transistor is turned on and outputs the first operating current. When the second drive signal received by the second power transistor is the second current, the second power transistor is turned off; when the second drive signal received by the second power transistor is the limiting current, the second power transistor is turned on and outputs the second operating current after the first operating current is linearly increased.

10. The linear current output circuit according to claim 1, characterized in that, The current limiting module includes: A constant current source, the input terminal of which is connected to the external current source, receives the first current through the constant current source and outputs the limiting current according to the first current; A fifth field-effect transistor, wherein the gate and drain of the fifth field-effect transistor are connected to the output terminal of the constant current source; A sixth field-effect transistor, wherein the gate of the sixth field-effect transistor is connected to the gate of the fifth field-effect transistor, the source of the sixth field-effect transistor is connected to the source of the fifth field-effect transistor, and the drain of the sixth field-effect transistor is connected to the second input terminal of the first delay driving module and the second input terminal of the second delay driving module, respectively. The input terminal of the constant current source serves as the input terminal of the current limiting module, and the drain of the sixth field-effect transistor serves as the output terminal of the current limiting module. The limiting current is mirrored to the drain of the sixth field-effect transistor through the fifth field-effect transistor, and the limiting current is output through the drain of the sixth field-effect transistor.

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