A touch display structure capable of improving TIC dark blocks

Abstract

The present invention provides a touch display structure capable of improving TIC dark blocks. The structure comprises a display area, an IC chip bonding area, and wiring. A fan-out area divides the wiring into a first routing area and a second routing area, wherein the first routing area is located in the IC chip bonding area. The first routing area comprises a first M1 line, a first M2 line, and a first M3 line. The first M1 line and the first M3 line do not overlap in a vertical direction, the second end of the first M2 line overlaps with the first M3 line in a vertical direction, and the width of the second end of the first M2 line is smaller than that of the first M3 line. The above arrangement enables the first M3 line to cover the first M2 material, thereby preventing the problem of poor photoresist coverage at the edge of the first M2 material, the infiltration of chemical solution into the side etching of the first M3 material, and the resulting M3 routing disconnection. Moreover, the arrangement of the first M1 line and the first M3 line not overlapping in the vertical direction enables the first M3 line to achieve single-layer crossover, thereby increasing the process margin and effectively improving the TIC dark block.

Description

Technical Field

[0001] The present invention relates to the technical field of display screens, and in particular to a touch display structure capable of improving TIC dark blocks. Background Art

[0002] In recent years, the touch screen display market has entered a period of product diversification, ranging from small-sized mobile phones to medium and large-sized NBs, tablets, car-mounted products and even IT products.

[0003] Touchscreen technology is primarily categorized as out-cell and in-cell. For mobile phones, tablets, and notebook computers, in-cell solutions are gradually replacing out-cell solutions due to cost, weight, and thickness considerations. Figure 1 This is a structural diagram of an embedded product. Figure 2 yes Figure 1 In the cross-sectional view at AA, the touch display structure includes an M1 layer, a GI layer, an M2 layer, a PV layer, an OC layer, and a CH layer.

[0004] However, currently, in-cell products are trending towards narrower bezels. Therefore, in the fanout area, Figure 1 and Figure 2 The touch display structure shown is modified as follows Figure 3 、 Figure 4 and Figure 5 The touch display structure shown in FIG. Figure 3 As can be seen from the figure, the improvement is to coat one side of the OC layer (planarization layer) in the area except the ICBonding (IC chip bonding) area, and Figure 1 On the basis of the M3 layer and the VA layer, Figure 4 shown.

[0005] However, due to the ICBonding area, there is no OC layer, which causes M3 to climb M1 and M2, and there will be M3 climbing disconnection problems, such as Figure 5 and Figure 6 As shown, when displaying the picture, dark squares will appear in the display area within the surface. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide a touch display structure that can improve TIC dark blocks, avoid M3 disconnection, and achieve the purpose of improving TIC dark blocks.

[0007] The present invention is achieved in that:

[0008] A touch display structure capable of improving TIC dark blocks includes a display area, an IC chip bonding area, and wiring for connecting the display area and the IC chip bonding area. The touch display structure also includes a fan-out area, which divides the wiring into a first routing area and a second routing area. The first routing area is located in the IC chip bonding area, and the second routing area is located in the fan-out area.

[0009] The first routing area includes a first M1 line, a first M2 line, and a first M3 line, the first M1 line is arranged below the first M2 line, and a first GI layer is arranged between the first M1 line and the first M2 line, the first M2 line is arranged below the first M3 line, and a first PV layer is arranged between the first M2 line and the first M3 line;

[0010] The first M1 line and the first M3 line do not overlap in the vertical direction, the first end of the first M2 line overlaps with the first M1 line in the vertical direction, the second end of the first M2 line overlaps with the first M3 line in the vertical direction, and the width of the second end of the first M2 line is smaller than the width of the first M3 line.

[0011] Furthermore, the width of the first end of the first M2 line is smaller than the width of the first M1 line.

[0012] Furthermore, the second routing area includes a second M1 line, a second M2 line and a second M3 line, a second GI layer is arranged on the top of the second M1 line, the second M2 line is arranged on the top of the second GI layer, a second PV layer that can cover the second M2 line is arranged on the top of the second GI layer, an OC layer is arranged on the top of the second PV layer, the second M3 line is arranged on the top of the OC layer, a VA layer that can cover the second M3 line is arranged on the top of the OC layer, and a CH layer is arranged on the top of the VA layer.

[0013] Furthermore, the width of the second M1 line is greater than the width of the second M2 line, and the width of the second M2 line is greater than the width of the second M3 line.

[0014] The advantages of the present invention are that the width of the second end of the first M2 line is smaller than the width of the first M3 line, allowing the first M3 to cover the first M2 material, thereby preventing the problem of poor photoresist coverage at the edge of the first M2 material, which would cause the solution to penetrate and laterally etch the first M3 material, causing the M3 line to break. Moreover, the first M1 line and the first M3 line are arranged without overlapping in the vertical direction, so that the first M3 line can be single-layered, thereby increasing the process margin. Through the above-mentioned arrangement, the problem of M3 breaking due to climbing M1 and M2 caused by the lack of an OC layer between M1 and M2 in the prior art is avoided, thereby effectively achieving the purpose of improving TIC dark blocks and effectively saving manpower, resources, and costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0016] Figure 1 It is a structural diagram of a traditional embedded product.

[0017] Figure 2 yes Figure 1 Cross-sectional view at AA in the middle.

[0018] Figure 3 It is based on the existing technology Figure 1 The schematic diagram of the improved structure of the embedded product.

[0019] Figure 4 for Figure 3 Partial cross-sectional view at the middle BB.

[0020] Figure 5 for Figure 3 A partial enlarged view of point C in the middle.

[0021] Figure 6 for Figure 3 Partial cross-sectional view at DD in the middle.

[0022] Figure 7 It is a schematic structural diagram of the improvement made by the present invention for wiring in the ICBonding area.

[0023] Figure 8 yes Figure 7 Cross-sectional view at EE.

[0024] Description of the numbers in the figure:

[0025] 1. Display area; 2. IC chip bonding area; 3. Wiring; 4. Fan-out area; 5. First routing area; 6. Second routing area; 7. First M1 line; 8. First M2 line; 9. First M3 line; 10. First GI layer; 11. First PV layer; 12. Second M1 line; 13. Second M2 line; 14. Second M3 line; 15. Second GI layer; 16. Second PV layer; 17. OC layer; 18. VA layer; 19. CH layer. DETAILED DESCRIPTION

[0026] See also Figure 3 、 Figure 7 and Figure 8 As shown, the present invention provides a touch display structure capable of improving TIC dark blocks, comprising a display area 1, an IC chip bonding area 2, and wiring 3 for connecting the display area 1 and the IC chip bonding area 2. The touch display structure further comprises a fan-out area 4, which divides the wiring 3 into a first routing area 5 and a second routing area 6. The first routing area 5 is located in the IC chip bonding area 2, and the second routing area 6 is located in the fan-out area 4.

[0027] The first routing area 5 includes a first M1 line 7, a first M2 line 8, and a first M3 line 9. The first M1 line 7 is arranged below the first M2 line 8, and a first GI layer 10 is arranged between the first M1 line 7 and the first M2 line 8. The first M2 line 8 is arranged below the first M3 line 9, and a first PV layer 11 is arranged between the first M2 line 8 and the first M3 line 9.

[0028] The first M1 line 7 and the first M3 line 9 do not overlap in the vertical direction. The first M2 line 8 has a first end and a second end opposite the first end. The first end of the first M2 line 8 overlaps with the first M1 line 7 in the vertical direction, and the second end of the first M2 line 8 overlaps with the first M3 line 9 in the vertical direction. To prevent poor photoresist coverage at the edge of the M2 material, which could cause the chemical solution to penetrate and laterally etch the M3 material, thereby causing M3 line disconnection, the width of the second end of the first M2 line 8 is set to be smaller than the width of the first M3 line 9, so that the M3 material can cover the M2 material.

[0029] The width of the first end of the first M2 line 8 is smaller than the width of the first M1 line 7 .

[0030] like Figure 4 As shown, the second routing area 6 includes a second M1 line 12, a second M2 line 13 and a second M3 line 14, a second GI layer 15 is arranged on the top of the second M1 line 12, the second M2 line 13 is arranged on the top of the second GI layer 15, a second PV layer 16 that can cover the second M2 line 13 is arranged on the top of the second GI layer 15, an OC layer 17 is arranged on the top of the second PV layer 16, the second M3 line 14 is arranged on the top of the OC layer 17, a VA layer 18 that can cover the second M3 line 14 is arranged on the top of the OC layer 17, and a CH layer 19 is arranged on the top of the VA layer 18.

[0031] The first M1 line 7 and the second M1 line 12 form a complete wiring. For the sake of convenience, the portion of this wiring located within the IC chip bonding area 2 is named the first M1 line 7, and the portion within the fan-out area is named the second M1 line 12. Similarly, the first M2 line 8 and the second M2 line 13 form a complete wiring. For the sake of convenience, the portion of this wiring located within the IC chip bonding area 2 is named the first M2 line 8, and the portion within the fan-out area is named the second M2 line 13. The first M3 line 9 and the second M3 line 14 form a complete wiring. For the sake of convenience, the portion of this wiring located within the IC chip bonding area 2 is named the first M3 line 9, and the portion within the fan-out area is named the second M3 line 14.

[0032] The width of the second M1 line 12 is greater than the width of the second M2 line 13 , and the width of the second M2 line 13 is greater than the width of the second M3 line 14 .

[0033] The present invention sets the width of the second end of the first M2 line in the IC chip bonding area 2 to be smaller than the width of the first M3 line. Figure 7 As shown, the first M3 can cover the first M2 material, which can prevent the poor coverage of the photoresist at the edge of the first M2 material, the liquid from penetrating into the side etching of the first M3 material, and causing the M3 line to be broken. Moreover, the first M1 line and the first M3 line are arranged without overlapping in the vertical direction, so that the first M3 line can be single-layered, that is, the first M3 line only jumps over the first M2 line, as shown in FIG. Figure 8 As shown, this increases process margin. In the prior art, the M3 line needs to jumper over the M2 and M1 lines within the IC chip bonding area 2. This arrangement avoids the prior art problem of M3 breaking due to climbing over M1 and M2, which occurs when there is no OC layer between M1, M2, and M3. This effectively improves TIC dark blocks and saves manpower, resources, and costs.

[0034] Although the specific embodiments of the present invention are described above, those skilled in the art should understand that the specific embodiments described are merely illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included within the scope of protection of the claims of the present invention.

Claims

1. A touch display structure capable of improving TIC dark blocks, comprising a display area, an IC chip bonding area, and wiring for connecting the display area and the IC chip bonding area, the touch display structure also including a fan-out area, characterized in that: The fan-out area divides the wiring into a first routing area and a second routing area, the first routing area is located in the IC chip bonding area, and the second routing area is located in the fan-out area; The first routing area includes a first M1 line, a first M2 line, and a first M3 line, the first M1 line is arranged below the first M2 line, and a first GI layer is arranged between the first M1 line and the first M2 line, the first M2 line is arranged below the first M3 line, and a first PV layer is arranged between the first M2 line and the first M3 line; The first M1 line and the first M3 line do not overlap in the vertical direction, the first end of the first M2 line overlaps with the first M1 line in the vertical direction, the second end of the first M2 line overlaps with the first M3 line in the vertical direction, and the width of the second end of the first M2 line is smaller than the width of the first M3 line; The width of the first end of the first M2 line is smaller than the width of the first M1 line; The second routing area includes a second M1 line, a second M2 line and a second M3 line. A second GI layer is arranged on the top of the second M1 line, the second M2 line is arranged on the top of the second GI layer, a second PV layer that can cover the second M2 line is arranged on the top of the second GI layer, an OC layer is arranged on the top of the second PV layer, the second M3 line is arranged on the top of the OC layer, a VA layer that can cover the second M3 line is arranged on the top of the OC layer, and a CH layer is arranged on the top of the VA layer.

2. The touch display structure capable of improving TIC dark blocks according to claim 1, characterized in that: The width of the second M1 line is greater than the width of the second M2 line, and the width of the second M2 line is greater than the width of the second M3 line.

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