Ramp voltage generator and operation method thereof

Abstract

The present invention provides a ramp voltage generator and an operating method thereof. The ramp voltage generator includes an output stage circuit, a voltage stabilization circuit, a voltage adjustment circuit, and a load variation detection circuit. The output stage circuit generates a ramp signal at an output terminal based on a node voltage at a first control terminal. The voltage stabilization circuit stabilizes the output terminal based on a clock signal. The voltage adjustment circuit adjusts the node voltages at a first detection terminal and a first control terminal based on a second control signal, a third control signal, and a fourth control signal. The load variation detection circuit is used to detect output load variation at the output terminal through a detection path, and adjusts the node voltages at the first detection terminal and a second detection terminal based on the output load variation and based on the first control signal and the fourth control signal.

Description

Technical Field

[0001] The present invention relates to a voltage generator, and more particularly to a ramp voltage generator and an operating method thereof. Background Art

[0002] In existing display technologies, pixel circuits typically receive a ramp signal from an external digital-to-analog converter and use this signal and programmed data to determine the current width or light-emitting duration of a light-emitting diode (LED). However, the slope of the ramp signal generated by the existing ramp voltage generator is easily affected by variations in the output load and / or the threshold voltage of the transistor, resulting in inconsistency. This, in turn, reduces the pixel circuit's grayscale control capability.

[0003] Therefore, how to effectively compensate for load variation and / or transistor threshold voltage variation so that the output waveform of the ramp signal is not affected by the variation and thus improve the grayscale control accuracy of the pixel circuit will be an important issue for those skilled in the art. Summary of the Invention

[0004] The present invention provides a ramp voltage generator and an operating method thereof, which can detect and compensate for load variations at the output end and threshold voltage variations of transistors, thereby unaffecting the output waveform of the ramp signal and improving the accuracy of grayscale control of pixel circuits controlled by pulse-width modulation (PWM).

[0005] The ramp voltage generator of the present invention includes: an output stage circuit, a voltage stabilizing circuit, a voltage adjustment circuit, and a load variation detection circuit. The output stage circuit has a first control terminal and an output terminal, and generates a ramp signal at the output terminal based on the node voltage of the first control terminal. The voltage stabilizing circuit has a second control terminal, is coupled to the output terminal, and regulates the output terminal based on a clock signal. The voltage adjustment circuit has a first detection terminal, is coupled to the first control terminal and the voltage stabilizing circuit, and adjusts the node voltage between the first detection terminal and the first control terminal based on a second control signal, a third control signal, and a fourth control signal. The load variation detection circuit has a second detection terminal, is coupled to the first detection terminal and the output terminal, and is used to detect output load variation of the output terminal through a detection path, and adjusts the node voltage between the first detection terminal and the second detection terminal based on the output load variation and based on the first control signal and the fourth control signal.

[0006] The operating method of the ramp voltage generator of the present invention includes: providing an output stage circuit having a first control terminal and an output terminal, and causing the output stage circuit to generate a ramp signal at the output terminal based on a node voltage of the first control terminal; providing a voltage regulator circuit having a second control terminal, and causing the voltage regulator circuit to regulate the output terminal based on a clock signal; providing a voltage adjustment circuit having a first detection terminal, and causing the voltage adjustment circuit to adjust the node voltage between the first detection terminal and the first control terminal based on a second control signal, a third control signal, and a fourth control signal; and providing a load variation detection circuit having a second detection terminal, and causing the load variation detection circuit to detect output load variation at the output terminal through a detection path, and adjust the node voltage between the first detection terminal and the second detection terminal based on the output load variation and based on the first control signal and the fourth control signal.

[0007] Based on the foregoing, the ramp voltage generator and its operating method according to the embodiments of the present invention can effectively detect and compensate for load variations at the output terminal and threshold voltage variations of transistors, thereby ensuring that the output waveform of the ramp signal is not affected by these variations, thereby increasing the accuracy of grayscale control of a pixel circuit controlled by pulse width modulation.

[0008] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 FIG. 1 is a schematic diagram of a ramp voltage generator according to an embodiment of the present invention.

[0010] Figure 2 According to the present invention Figure 1 Operation waveform diagram of the ramp voltage generator according to the embodiment.

[0011] Figures 3A to 3F According to the present invention Figure 1 Equivalent circuit diagram of a ramp voltage generator according to an embodiment.

[0012] Figure 4 is a flow chart of an operating method of a ramp voltage generator according to an embodiment of the present invention.

[0013] Description of reference numerals:

[0014] 100: Ramp voltage generator

[0015] 110: Output stage circuit

[0016] 120: Voltage stabilization circuit

[0017] 130: Voltage regulation circuit

[0018] 140: Load variation detection circuit

[0019] C1~C4:Capacitors

[0020] CT1, CT2: control terminals

[0021] CK: clock signal

[0022] CP: Compensation phase

[0023] CP1, CP2: Sub-stages

[0024] DT1, DT2: detection end

[0025] DP: Detection phase

[0026] EM[N]: Lighting control signal

[0027] IBIAS: Current source

[0028] K[N], P[N], Q[N], T[N]: node voltage

[0029] NOP: output terminal

[0030] PT: Detection Path

[0031] RP: Reset Phase

[0032] S1[N], S1[N-1], S1[N-2], S1[N-4]: control signals

[0033] SWEEP[N]: ramp signal

[0034] SP: voltage stabilization stage

[0035] T1~T15:Transistors

[0036] TFR: Pixel Period

[0037] VREF1, VREF2: reference voltage

[0038] VL: Low voltage

[0039] VSH: High Voltage

[0040] VOP: voltage output stage

[0041] XCK: reverse clock signal DETAILED DESCRIPTION

[0042] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present invention, and will not be interpreted as idealized or overly formal unless explicitly defined as such herein.

[0043] It should be understood that although the terms "first," "second," "third," etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Thus, a "first element," "component," "region," "layer," or "portion" discussed below may be referred to as a second element, component, region, layer, or portion without departing from the teachings herein.

[0044] The terms used herein are for the purpose of describing specific embodiments only and are not restrictive. As used herein, unless the content clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms, including "at least one". "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items. It should also be understood that when used in this specification, the terms "include" and / or "including" specify the presence and / or parts of the features, regions, entireties, steps, operations, elements, components and / or parts, but do not exclude the presence or addition of one or more other features, regions, entireties, steps, operations, elements, components and / or combinations thereof.

[0045] Figure 1 is a schematic diagram of a ramp voltage generator according to an embodiment of the present invention. Figure 1 The ramp voltage generator 100 includes an output stage circuit 110, a voltage stabilizing circuit 120, a voltage adjusting circuit 130, and a load variation detecting circuit 140. In this embodiment, the output stage circuit 110 has a control terminal CT1 and an output terminal NOP.

[0046] The output stage circuit 110 includes transistors T1 to T5 and a capacitor C1. A first terminal of transistor T1 is coupled to a low voltage VL, and a control terminal of transistor T1 receives a light-emission control signal EM[N]. A first terminal of transistor T2 is coupled to a second terminal of transistor T1, a second terminal of transistor T2 is coupled to a control terminal CT1, and a control terminal of transistor T2 receives a control signal S1[N-1] (i.e., a second control signal). A first terminal of transistor T3 is coupled to a second terminal of transistor T1, and a control terminal of transistor T3 is coupled to a control terminal CT1. A first terminal of transistor T4 is coupled to a reference voltage VREF1, a second terminal of transistor T4 is coupled to a second terminal of transistor T3, and a control terminal of transistor T4 receives a control signal S1[N-1]. A first terminal of transistor T5 is coupled to a second terminal of transistor T4, a second terminal of transistor T5 is coupled to an output terminal NOP, and a control terminal of transistor T5 receives a light-emission control signal EM[N]. Capacitor C1 is coupled between the control terminal CT1 and the output terminal NOP.

[0047] Specifically, the output stage circuit 110 of this embodiment can generate a ramp signal SWEEP[N] at the output terminal NOP to a corresponding pixel circuit (not shown) according to the node voltage Q[N] at the control terminal CT1 , where N is a pilot number.

[0048] The voltage regulator circuit 120 is coupled to the output terminal NOP. The voltage regulator circuit 120 has a control terminal CT2. The voltage regulator circuit 120 includes transistors T6 to T8 and a capacitor C2. The first terminal of transistor T6 is coupled to the low voltage VL, the second terminal of transistor T6 is coupled to the control terminal CT2, and the control terminal of transistor T6 receives the control signal S1[N-2] (i.e., the third control signal). The first terminal of transistor T7 is coupled to the high voltage VSH, the second terminal of transistor T7 is coupled to the control terminal CT2, and the control terminal of transistor T7 receives the light-emitting control signal EM[N]. The first terminal of transistor T8 is coupled to the high voltage VSH, the second terminal of transistor T8 is coupled to the output terminal NOP, and the control terminal of transistor T8 is coupled to the control terminal CT2. The first terminal of capacitor C2 is coupled to the control terminal CT2, and the second terminal of capacitor C2 receives the clock signal CK.

[0049] Specifically, the voltage regulator circuit 120 of this embodiment can regulate the output terminal NOP according to the state of the clock signal CK (or the inverse clock signal XCK). An external clock generator (not shown) can provide the periodically transitioning clock signal CK or the inverse clock signal XCK to the ramp voltage generator 100.

[0050] On the other hand, the voltage regulating circuit 130 is coupled to the control terminal CT1 and the voltage regulating circuit 120. The voltage regulating circuit 130 has a detection terminal DT1. The voltage regulating circuit 130 includes transistors T9-T12 and a capacitor C3. The first terminal of transistor T9 is coupled to the high voltage VSH, the second terminal of transistor T9 is coupled to the detection terminal DT1, and the control terminal of transistor T9 receives a control signal S1[N-4] (i.e., the fourth control signal). The first terminal of transistor T10 is coupled to the low voltage VL, the second terminal of transistor T10 is coupled to the control terminal CT1, and the control terminal of transistor T10 receives a control signal S1[N-2]. The first terminal of transistor T11 is coupled to the high voltage VSH, the second terminal of transistor T11 is coupled to the detection terminal DT1, and the control terminal of transistor T11 receives a control signal S1[N-1]. The first terminal of transistor T12 is coupled to the high voltage VSH, the second terminal of transistor T12 is coupled to the detection terminal DT1, the control terminal of transistor T12 is coupled to the control terminal of transistor T6 and receives the control signal S1[N-2]. Capacitor C3 is coupled between the detection terminal DT1 and the control terminal CT1.

[0051] Specifically, the voltage adjustment circuit 130 of this embodiment can adjust the node voltage K[N] of the detection terminal DT1 and the node voltage Q[N] of the control terminal CT1 according to the states of the control signals S1[N-1], S1[N-2], and S1[N-4].

[0052] The load variation detection circuit 140 is coupled to the detection terminal DT1. The load variation detection circuit 140 has a detection terminal DT2. The load variation detection circuit 140 includes transistors T13 to T15, a capacitor C4, and a current source IBIAS. The first terminal of transistor T13 is coupled to the reference voltage VREF2, the second terminal of transistor T13 is coupled to the detection terminal DT2, and the control terminal of transistor T13 receives the control signal S1[N] (i.e., the first control signal). The first terminal of transistor T14 is coupled to the output terminal NOP and receives the ramp signal SWEEP[N]. The second terminal of transistor T14 is coupled to the detection terminal DT2, and the control terminal of transistor T14 is coupled to the control terminal of transistor T9 and receives the control signal S1[N-4]. The first terminal of transistor T15 is coupled to the detection terminal DT2, and the control terminal of transistor T15 receives the control signal S1[N-4]. Capacitor C4 is coupled between the detection terminal DT1 and the detection terminal DT2. A first terminal of the current source IBIAS is coupled to the second terminal of the transistor T15 , and a second terminal of the current source IBIAS is coupled to the low voltage VL.

[0053] Specifically, the load variation detection circuit 140 of this embodiment can detect the output load variation of the output terminal NOP through the detection path PT, and adjust the node voltage K[N] of the detection terminal DT1 and the node voltage T[N] of the detection terminal DT2 based on the output load variation and in accordance with the states of the control signal S1[N] and the control signal S1[N-4].

[0054] Incidentally, in the design of transistors T1-T15, the transistors T1-T15 of this embodiment can be P-type transistors, but the present invention is not limited thereto. In addition, in this embodiment, the voltage level of reference voltage VREF1 can be higher than the voltage level of reference voltage VREF2.

[0055] In addition, in this embodiment, the control signal S1[N-2] differs from the control signal S1[N-1] by one delay unit (e.g., half a clock cycle), and the control signal S1[N-1] differs from the control signal S1[N] by one delay unit (e.g., half a clock cycle). The control signal S1[N-1] is the control signal S1[N] of the previous stage, the control signal S1[N-2] is the control signal S1[N] of the previous two stages, and the control signal S1[N-4] is the control signal S1[N] of the previous four stages.

[0056] Figure 2 According to the present invention Figure 1 Please also refer to the operation waveform diagram of the ramp voltage generator of the embodiment. Figure 1 as well as Figure 2 In this embodiment, a pixel period TFR of the ramp voltage generator 100 can be divided into a detection phase DP, a reset phase RP, a compensation phase CP, a voltage output phase VOP, and a voltage regulation phase SP. The ramp voltage generator 100 can sequentially operate in the detection phase DP, the reset phase RP, the compensation phase CP, the voltage output phase VOP, and the voltage regulation phase SP. The detection phase DP, the reset phase RP, the compensation phase CP, the voltage output phase VOP, and the voltage regulation phase SP do not overlap. The compensation phase CP can include a sub-phase CP1 and a sub-phase CP2.

[0057] For details on the implementation of the ramp voltage generator 100, please refer to Figure 2 as well as Figures 3A to 3F , Figures 3A to 3F According to the present invention Figure 1 The equivalent circuit diagram of the ramp voltage generator of the embodiment is shown in FIG. Figures 3A to 3F A transistor that is turned off is indicated by a cross, while a transistor that is turned on is indicated by an uncross.

[0058] Please also refer to Figure 2 as well as Figure 3A , Figure 3A FIG. 1 is an equivalent circuit diagram of the ramp voltage generator 100 operating in the detection phase DP. Specifically, in the detection phase DP, the control signal S1[N-4] may be set to a low voltage level (equal to the gate low voltage VGL), while the clock signal CK, the control signal S1[N], the control signal S1[N-1], the control signal S1[N-2], and the emission control signal EM[N] may be set to a high voltage level (equal to the gate high voltage VGH).

[0059] Specifically, during the detection phase DP, the load variation detection circuit 140 detects output load variation at the output terminal NOP via a detection path PT in response to the low control signal S1[N-4]. The detection path PT in this embodiment may include transistors T14 and T15, and a current source IBIAS. In this embodiment, the entire display panel may share a single current source IBIAS. This current source IBIAS can discharge the load on the display panel during the detection phase DP, storing the discharge value in capacitor C4.

[0060] For example, the load variation detection circuit 140 can detect the output load variation of the output terminal NOP via the detection path PT and the current source IBIAS. Based on the output load variation, the circuit provides a variation voltage ΔVRC to the detection terminal DT2 via the conduction path of the transistor T14. This adjusts the node voltage T[N] at the detection terminal DT2 to the voltage difference between the high voltage VSH and the variation voltage ΔVRC (i.e., VSH-ΔVRC). The variation voltage ΔVRC can be the voltage change at the output terminal NOP caused by the output load variation.

[0061] On the other hand, the voltage adjustment circuit 130 can provide the high voltage VSH to the detection terminal DT1 via the conductive path of the transistor T9 in response to the low control signal S1[N-4]. This causes the node voltage K[N] at the detection terminal DT1 to be pulled up to the voltage level of the high voltage VSH. In other words, during the detection phase DP, the load variation detection circuit 140 can store the variation voltage ΔVRC in the capacitor C4.

[0062] Please also refer to Figure 2 as well as Figure 3B , Figure 3BFIG. 1 is an equivalent circuit diagram of the ramp voltage generator 100 operating in the reset phase RP. Specifically, in the reset phase RP, the control signal S1[N-2] may be set to a low voltage level (equal to the gate low voltage VGL), while the clock signal CK, the control signal S1[N], the control signal S1[N-1], the control signal S1[N-4], and the emission control signal EM[N] may be set to a high voltage level (equal to the gate high voltage VGH).

[0063] Specifically, in the reset phase RP, the voltage adjustment circuit 130 can provide the low voltage VL to the control terminal CT1 through the conduction path of the transistor T10 according to the pulled-down control signal S1[N-2], thereby pulling down the node voltage Q[N] of the control terminal CT1 to the voltage level of the low voltage VL.

[0064] Then, the voltage adjustment circuit 130 can provide the high voltage VSH to the detection terminal DT1 through the conduction path of the transistor T12 according to the pulled-down control signal S1[N-2], thereby pulling the node voltage K[N] of the detection terminal DT1 up to the voltage level of the high voltage VSH.

[0065] On the other hand, the voltage regulator circuit 120 can provide a low voltage VL to the control terminal CT2 via the conduction path of the transistor T6 in response to the pulled-down control signal S1[N-2], thereby pulling down the node voltage P[N] of the control terminal CT2 to the voltage level of the low voltage VL. In this case, the voltage regulator circuit 120 can turn on the transistor T8 in response to the pulled-down node voltage P[N] and provide a high voltage VSH to the output terminal NOP via the conduction path of the transistor T8, thereby causing the output stage circuit 110 to generate the ramp signal SWEEP[N] pulled up to the voltage level of the high voltage VSH.

[0066] It is worth mentioning that since the detection terminal DT2 of the load variation detection circuit 140 is in a floating state at this time, the voltage level of the node voltage T[N] of the detection terminal DT2 can be maintained at the voltage difference between the high voltage VSH and the variation voltage ΔVRC.

[0067] Please also refer to Figure 2 as well as Figure 3C , Figure 3C FIG. 1 is an equivalent circuit diagram of the ramp voltage generator 100 operating in sub-phase CP1 of the compensation phase CP. Specifically, in sub-phase CP1 of the compensation phase CP, the clock signal CK and the control signal S1[N-1] may be set to a low voltage level (equal to the gate low voltage VGL), while the control signals S1[N], S1[N-2], S1[N-4], and the emission control signal EM[N] may be set to a high voltage level (equal to the gate high voltage VGH).

[0068] Specifically, in the sub-phase CP1 of the compensation phase CP, the output stage circuit 110 can provide the reference voltage VREF1 through the conduction path of the transistors T2, T3, and T4 according to the pulled-down control signal S1[N-1] to charge the control terminal CT1, thereby pulling down the node voltage Q[N] of the control terminal CT1 to the voltage difference between the reference voltage VREF1 and the threshold voltage VTH3 of the transistor T3 (i.e., VREF1-|VTH3|).

[0069] Here, the transistor T3 can form a diode according to the diode connection through the conduction path of the transistor T2 to compensate for the threshold voltage VTH3, thereby improving the compensation accuracy.

[0070] Then, the voltage adjustment circuit 130 can provide the high voltage VSH to the detection terminal DT1 through the conduction path of the transistor T11 according to the pulled-down control signal S1[N−1], thereby maintaining the node voltage K[N] of the detection terminal DT1 at the voltage level of the high voltage VSH.

[0071] On the other hand, since the clock signal CK transitions from a high voltage level to a low voltage level during the ramp voltage generator 100 operating in the sub-phase CP1 of the compensation phase CP, the voltage regulator circuit 120 can, through the coupling effect of the capacitor C2 and in accordance with the state of the clock signal CK, pull down the voltage level of the node voltage P[N] at the control terminal CT2 to a voltage difference between the low voltage VL and the voltage change ΔVCK of the clock signal CK (i.e., VL−ΔVCK). In this case, the voltage regulator circuit 120 can turn on the transistor T8 in response to the pulled-down node voltage P[N] and provide the high voltage VSH to the output terminal NOP through the conduction path of the transistor T8, thereby maintaining the ramp signal SWEEP[N] at the output terminal NOP at the high voltage VSH.

[0072] It is worth mentioning that since the detection terminal DT2 of the load variation detection circuit 140 is in a floating state at this time, the voltage level of the node voltage T[N] of the detection terminal DT2 can still be maintained at the voltage difference between the high voltage VSH and the variation voltage ΔVRC.

[0073] Please also refer to Figure 2 as well as Figure 3D , Figure 3DFIG. 1 is an equivalent circuit diagram of the ramp voltage generator 100 operating in the sub-phase CP2 of the compensation phase CP. Specifically, in the sub-phase CP2 of the compensation phase CP, the control signal S1[N] may be set to a low voltage level (equal to the gate low voltage VGL), while the clock signal CK, the control signal S1[N-1], the control signal S1[N-2], the control signal S1[N-4], and the emission control signal EM[N] may be set to a high voltage level (equal to the gate high voltage VGH).

[0074] Specifically, in the sub-phase CP2 of the compensation phase CP, the load variation detection circuit 140 can provide the reference voltage VREF2 to the detection terminal DT2 through the conduction path of the transistor T13 according to the pulled-down control signal S1[N], so that the node voltage T[N] of the detection terminal DT2 is adjusted to the voltage level of the reference voltage VREF2.

[0075] Next, the voltage adjustment circuit 130 can adjust the node voltage K[N] of the detection terminal DT1 based on the output load variation of the output terminal NOP through the coupling effect of the capacitor C4, and according to the node voltage T[N], the variation voltage ΔVRC stored in the capacitor C4, and the voltage division state between the capacitors C1, C3, and C4. The voltage level of the node voltage K[N] at this time can be expressed as the following formula (1):

[0076]

[0077] Furthermore, the voltage adjustment circuit 130 can further adjust the node voltage Q[N] of the control terminal CT1 based on the output load variation of the output terminal NOP through the coupling effect of the capacitor C3, and in accordance with the node voltage K[N], the variation voltage ΔVRC stored in the capacitor C4, and the voltage division state between the capacitors C3 and C4. The voltage level of the node voltage Q[N] at this time can be expressed as the following equation (2):

[0078]

[0079] Among them, the above-mentioned K[N] and Q[N] are the voltage values of the node voltages K[N] and Q[N] respectively; VSH is the voltage value of the high voltage VSH; VREF1 and VREF2 are the voltage values of the reference voltages VREF1 and VREF2 respectively; △VRC is the voltage value of the variation voltage △VRC; VTH3 is the voltage value of the threshold voltage VTH3 of the transistor T3; C1, C3 and C4 are the capacitance values of the capacitors C1, C3 and C4 respectively.

[0080] According to the above description, when the ramp voltage generator 100 operates in the sub-phase CP2 of the compensation phase CP, the voltage adjustment circuit 130 and the load variation detection circuit 140 can couple the variation voltage ΔVRC stored in the capacitor C4 to the control terminal CT1 through the coupling effect of the capacitors C3 and C4, thereby causing the transistor T3 to operate in the saturation region.

[0081] On the other hand, since the clock signal CK transitions from a low voltage level to a high voltage level during the operation of the ramp voltage generator 100 in the sub-phase CP2 of the compensation phase CP, the voltage regulator circuit 120 can adjust the node voltage P[N] at the control terminal CT2 back to the voltage level of the low voltage VL through the coupling effect of the capacitor C2 and in accordance with the state of the clock signal CK. In this case, the voltage regulator circuit 120 can turn on the transistor T8 in accordance with the node voltage P[N] and provide the high voltage VSH to the output terminal NOP through the conduction path of the transistor T8, thereby maintaining the ramp signal SWEEP[N] at the output terminal NOP at the voltage level of the high voltage VSH.

[0082] Please also refer to Figure 2 as well as Figure 3E , Figure 3E FIG. 1 is an equivalent circuit diagram of the ramp voltage generator 100 operating in the voltage output phase VOP. Specifically, in the voltage output phase VOP, the emission control signal EM[N] may be set to a low voltage level (equal to the gate low voltage VGL), while the control signals S1[N], S1[N-1], S1[N-2], and S1[N-4] may be set to a high voltage level (equal to the gate high voltage VGH), and the clock signal CK may be periodically transitioned.

[0083] Specifically, during the voltage output phase VOP, the output stage circuit 110 can discharge the low voltage VL from the output terminal NOP via the conductive path of transistors T1, T3, and T5 in response to the low-voltage light control signal EM[N]. Furthermore, the output stage circuit 110 can stabilize the voltage across the second terminal of transistor T3 and the control terminal (i.e., control terminal CT1) via capacitor C1, while compensating for variations in the threshold voltage VTH3 of transistor T3. Furthermore, transistor T3 can operate in a saturation region in response to the node voltage Q[N] and generate a constant current, thereby enabling the output stage circuit 110 to generate a ramp signal SWEEP[N] with the constant slope required for pixels driven by pulse-width modulation (PWM).

[0084] Next, the voltage adjustment circuit 130 can adjust the node voltage Q[N] at the control terminal CT1 based on the voltage change ΔVI of the ramp signal SWEEP[N] during discharge, and in accordance with the state of the node voltage Q[N] during the sub-phase CP2 of the compensation phase CP, through the coupling effect of the capacitor C1. The voltage level of the node voltage Q[N] at this time can be expressed as follows:

[0085]

[0086] Furthermore, the voltage adjustment circuit 130 can further adjust the node voltage K[N] at the detection terminal DT1 based on the voltage change ΔVI of the ramp signal SWEEP[N] during discharge, and according to the state of the node voltage K[N] during the sub-phase CP2 of the compensation phase CP, through the coupling effect of the capacitor C3. The voltage level of the node voltage K[N] at this time can be expressed as the following equation (4):

[0087]

[0088] Next, the load variation detection circuit 140 can adjust the voltage level of the node voltage T[N] at the detection terminal DT2 to the voltage difference between the reference voltage VREF2 and the voltage variation ΔVI (i.e., VREF2-ΔVI) based on the voltage variation ΔVI during the discharge of the ramp signal SWEEP[N] and the state of the node voltage T[N] during the sub-phase CP2 of the compensation phase CP through the coupling effect of the capacitor C4.

[0089] As can be seen from the above description, when the ramp voltage generator 100 operates in the voltage output phase VOP, the voltage adjustment circuit 130 can adjust the voltage at the control terminal (i.e., control terminal CT1) of the transistor T3 based on the output load variation (i.e., variation voltage ΔVRC) at the output terminal NOP. In this way, the transistor T3 of the output stage circuit 110 can operate in the saturation region based on the node voltage Q[N] and further compensate for the output load variation, thereby achieving the ability to accurately control the grayscale of the pixel.

[0090] On the other hand, the voltage regulator circuit 120 can provide a high voltage VSH to the control terminal CT2 via the conduction path of the transistor T7 in response to the low emission control signal EM[N], thereby raising the node voltage P[N] of the control terminal CT2 to the voltage level of the high voltage VSH. In this case, the voltage regulator circuit 120 can turn off the transistor T8 in response to the raised node voltage P[N].

[0091] Please also refer to Figure 2 as well as Figure 3F , Figure 3FFIG1 is an equivalent circuit diagram of the ramp voltage generator 100 operating in the voltage regulation phase SP. Specifically, in the voltage regulation phase SP, the control signals S1[N], S1[N-1], S1[N-2], S1[N-4], and the emission control signal EM[N] may be set to a high voltage level (equal to the gate high voltage VGH), and the clock signal CK may be periodically switched.

[0092] Specifically, during the voltage regulation phase SP, the voltage regulation circuit 120 couples the clock signal CK to the node voltage P[N] via the capacitor C2 and periodically turns on the transistor T8. In this case, the voltage regulation circuit 120 provides the high voltage VSH to the output terminal NOP via the conduction path of the transistor T8 to regulate the output terminal NOP.

[0093] On the other hand, regarding Figure 3F The voltage states of the node voltages Q[N], K[N] and T[N] in the ramp voltage generator 100 can be referred to Figure 3D The voltage states of the node voltages Q[N], K[N] and T[N] of the ramp voltage generator 100 can be analogously described and are not further elaborated herein.

[0094] Figure 4 This is a flow chart of an operation method of a ramp voltage generator according to an embodiment of the present invention. Figure 1 as well as Figure 4 In step S410, the ramp voltage generator 100 may provide an output stage circuit 110 having a control terminal CT1 and an output terminal NOP, and the output stage circuit 110 generates a ramp signal SWEEP[N] at the output terminal NOP according to the node voltage Q[N] at the control terminal CT1. In step S420, the ramp voltage generator 100 may provide a voltage regulator circuit 120 having a control terminal CT2, and the voltage regulator circuit 120 regulates the output terminal NOP according to the clock signal CK.

[0095] In step S430, the ramp voltage generator 100 may include a voltage adjustment circuit 130 having a detection terminal DT1, and the voltage adjustment circuit 130 may adjust a node voltage K[N] at the detection terminal DT1 and a node voltage Q[N] at the control terminal CT1 according to control signals S1[N-1], S1[N-2], and S1[N-4]. In step S440, the ramp voltage generator 100 may include a load variation detection circuit 140 having a detection terminal DT2, and the load variation detection circuit 140 may detect an output load variation at the output terminal NOP via a detection path PT. Based on the output load variation and in accordance with the control signals S1[N] and S1[N-4], the voltage adjustment circuit 130 may adjust a node voltage K[N] at the detection terminal DT1 and a node voltage T[N] at the detection terminal DT2.

[0096] about Figure 4 The implementation details of each step are fully described in the aforementioned embodiments and implementation methods and will not be repeated here.

[0097] In summary, the ramp voltage generator and its operating method according to the embodiments of the present invention can effectively detect and compensate for load variations at the output terminal and threshold voltage variations of transistors, thereby ensuring that the output waveform of the ramp signal is not affected by these variations, thereby increasing the accuracy of grayscale control of pixel circuits controlled by pulse width modulation.

Claims

1. A ramp voltage generator, comprising: An output stage circuit has a first control terminal and an output terminal, and generates a ramp signal at the output terminal according to a node voltage of the first control terminal; a voltage stabilizing circuit having a second control terminal, the voltage stabilizing circuit being coupled to the output terminal and stabilizing the output terminal according to a clock signal; a voltage regulating circuit having a first detection terminal, the voltage regulating circuit being coupled to the first control terminal and the voltage stabilizing circuit and regulating a node voltage between the first detection terminal and the first control terminal according to a second control signal, a third control signal, and a fourth control signal; as well as A load variation detection circuit has a second detection terminal. The load variation detection circuit is coupled to the first detection terminal and the output terminal, and is configured to detect an output load variation of the output terminal through a detection path, and to adjust a node voltage between the first detection terminal and the second detection terminal based on the output load variation and in accordance with a first control signal and a fourth control signal.

2. The ramp voltage generator of claim 1 , wherein in a detection phase, the load variation detection circuit detects the output load variation of the output terminal according to the fourth control signal being pulled low, and provides a variation voltage according to the output load variation to adjust the node voltage of the second detection terminal.

3. The ramp voltage generator of claim 1 , wherein in a reset phase, the voltage adjustment circuit provides a low voltage to pull down the node voltage of the first control terminal in response to the third control signal being pulled down, and the voltage regulation circuit provides the low voltage to pull down the node voltage of the second control terminal in response to the third control signal being pulled down. 4 . The ramp voltage generator as claimed in claim 1 , wherein in a first sub-phase of a compensation phase, the output stage circuit provides a first reference voltage to pull down the node voltage of the first control terminal according to the pulled-down second control signal.

5. The ramp voltage generator of claim 4 , wherein in a second sub-phase of the compensation phase, the load variation detection circuit provides a second reference voltage to the second detection terminal in response to the first control signal being pulled low, and the voltage adjustment circuit adjusts the node voltages of the first detection terminal and the first control terminal based on the output load variation and the node voltage of the second detection terminal. 6 . The ramp voltage generator as claimed in claim 1 , wherein in a voltage output stage, the output stage circuit generates the pulled-down ramp signal according to the pulled-down node voltage of the first control terminal and a pulled-down light control signal. 7 . The ramp voltage generator as claimed in claim 1 , wherein in a voltage regulation phase, the voltage regulation circuit provides a high voltage according to the clock signal, so that the output stage circuit generates the ramp signal that is pulled high.

8. The ramp voltage generator as claimed in claim 1 , wherein the output stage circuit comprises: a first transistor, a first terminal of which is coupled to a low voltage, and a control terminal of which receives a light-emitting control signal; a second transistor, having a first terminal coupled to the second terminal of the first transistor, a second terminal coupled to the first control terminal, and a control terminal receiving the second control signal; a third transistor, having a first terminal coupled to the second terminal of the first transistor and a control terminal coupled to the first control terminal; a fourth transistor, having a first terminal coupled to a first reference voltage, a second terminal coupled to the second terminal of the third transistor, and a control terminal receiving the second control signal; a fifth transistor, having a first terminal coupled to the second terminal of the fourth transistor, a second terminal coupled to the output terminal, and a control terminal receiving the light-emitting control signal; as well as A first capacitor is coupled between the first control terminal and the output terminal.

9. The ramp voltage generator as claimed in claim 8, wherein the voltage stabilizing circuit comprises: a sixth transistor, having a first terminal coupled to the low voltage, a second terminal coupled to the second control terminal, and a control terminal receiving the third control signal; a seventh transistor, a first terminal of which is coupled to a high voltage, a second terminal of which is coupled to the second control terminal, and a control terminal of which receives the light-emitting control signal; an eighth transistor, having a first terminal coupled to the high voltage, a second terminal coupled to the output terminal, and a control terminal coupled to the second control terminal; and A second capacitor has a first terminal coupled to the second control terminal and a second terminal receiving the clock signal.

10. The ramp voltage generator as claimed in claim 9, wherein the voltage adjustment circuit comprises: a ninth transistor, having a first terminal coupled to the high voltage, a second terminal coupled to the first detection terminal, and a control terminal receiving the fourth control signal; a tenth transistor, having a first terminal coupled to the low voltage, a second terminal coupled to the first control terminal, and a control terminal receiving the third control signal; an eleventh transistor, having a first terminal coupled to the high voltage, a second terminal coupled to the first detection terminal, and a control terminal receiving the second control signal; a twelfth transistor, having a first terminal coupled to the high voltage, a second terminal coupled to the first detection terminal, and a control terminal coupled to the control terminal of the sixth transistor; as well as A third capacitor is coupled between the first detection terminal and the first control terminal.

11. The ramp voltage generator as claimed in claim 10 , wherein the load variation detection circuit comprises: a thirteenth transistor, having a first terminal coupled to a second reference voltage, a second terminal coupled to the second detection terminal, and a control terminal receiving the first control signal; a fourteenth transistor, having a first terminal coupled to the output terminal, a second terminal coupled to the second detection terminal, and a control terminal coupled to the control terminal of the ninth transistor; a fifteenth transistor, a first terminal of which is coupled to the second detection terminal, and a control terminal of which receives the fourth control signal; a current source having a first terminal coupled to the second terminal of the fifteenth transistor and a second terminal coupled to the low voltage; as well as A fourth capacitor is coupled between the first detection terminal and the second detection terminal.

12. A method for operating a ramp voltage generator, comprising: Providing an output stage circuit having a first control terminal and an output terminal, and making the output stage circuit generate a ramp signal at the output terminal according to the node voltage of the first control terminal; Providing a voltage stabilizing circuit having a second control terminal, and making the voltage stabilizing circuit stabilize the output terminal according to a clock signal; Providing a voltage adjustment circuit having a first detection terminal, and making the voltage adjustment circuit adjust the node voltage of the first detection terminal and the first control terminal according to a second control signal, a third control signal and a fourth control signal; and A load variation detection circuit having a second detection terminal is provided. The load variation detection circuit detects an output load variation of the output terminal through a detection path, and adjusts the node voltages of the first detection terminal and the second detection terminal based on the output load variation and in accordance with a first control signal and a fourth control signal.

13. The operating method according to claim 12, further comprising: In a detection phase, the load variation detection circuit detects the output load variation of the output terminal according to the fourth control signal being pulled low, and provides a variation voltage according to the output load variation to adjust the node voltage of the second detection terminal.

14. The operating method according to claim 12, further comprising: In a reset phase, the voltage adjustment circuit provides a low voltage according to the third control signal that is pulled low, so as to pull down the node voltage of the first control terminal; as well as The voltage stabilizing circuit provides the low voltage according to the third control signal that is pulled low, so as to pull down the node voltage of the second control terminal.

15. The operating method according to claim 12, further comprising: In a first sub-phase of a compensation phase, the output stage circuit provides a first reference voltage according to the second control signal that is pulled down, so as to pull down the node voltage of the first control terminal.

16. The operating method according to claim 15, further comprising: In a second sub-phase of the compensation phase, the load variation detection circuit provides a second reference voltage to the second detection terminal according to the first control signal being pulled low; as well as The voltage regulating circuit is configured to regulate the node voltages of the first detection terminal and the first control terminal based on the output load variation and the node voltage of the second detection terminal.

17. The operating method according to claim 12, further comprising: In a voltage output stage, the output stage circuit generates the pulled-down ramp signal according to the pulled-down node voltage of the first control terminal and a pulled-down light control signal.

18. The operating method according to claim 12, further comprising: In a voltage stabilization phase, the voltage stabilization circuit provides a high voltage according to the clock signal, so that the output stage circuit generates the ramp signal that is pulled high.

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