Storage device and method of operating the same

Abstract

The present disclosure provides a storage device and an operating method thereof. The storage device includes a plurality of resistive memory cells and a control circuit electrically connected to the plurality of resistive memory cells. The control circuit provides a plurality of operating modes to operate the plurality of resistive memory cells. The operating modes include a first program operation and an update operation. The first program operation includes applying a first program bias to a selected resistive memory cell of the plurality of resistive memory cells to cause the selected resistive memory cell to have a low resistance state. The first program operation causes the storage device to have a first threshold voltage. The update operation includes applying an update bias to the selected resistive memory cell to update the selected resistive memory cell. An absolute value of the update bias is greater than the first threshold voltage.

Description

Technical Field

[0001] This disclosure relates to storage devices and methods of operation thereof, and more particularly to programmable resistive storage devices and methods of operation thereof. Background Technology

[0002] Resistive memory devices are an emerging technology for non-volatile storage. They operate by changing the resistance of the storage material, and the resistance can be read and written to indicate the stored data. However, one of the challenges of resistive memory devices is data retention time. Specifically, the resistance state of the storage cells can change over time, affecting the reliability or accuracy of the storage device.

[0003] Therefore, new storage devices and operating methods are needed to effectively extend data retention time. Summary of the Invention

[0004] This disclosure provides a storage device and a method for operating the same.

[0005] According to one aspect of this disclosure, a storage device is provided, comprising: a plurality of resistive memory cells; and control circuitry electrically connected to the plurality of resistive memory cells. The control circuitry provides a plurality of operating modes for operating the plurality of resistive memory cells. The operating modes include a first programming operation and an update operation. The first programming operation includes applying a first programming bias voltage to a selected resistive memory cell among the plurality of resistive memory cells to give the selected resistive memory cell a low-resistance state. The first programming operation gives the storage device a first threshold voltage. The update operation includes applying an update bias voltage to the selected resistive memory cell to update the selected resistive memory cell. The absolute value of the update bias voltage is greater than the first threshold voltage.

[0006] According to another aspect of this disclosure, a method for operating a storage device is provided for a storage device including a plurality of resistive storage cells. The method includes: applying a first programming bias voltage to a selected resistive storage cell among the plurality of resistive storage cells to cause the selected resistive storage cell to have a low resistance state, wherein the step of applying the first programming bias voltage causes the storage device to have a first threshold voltage; and applying a refresh bias voltage to the selected resistive storage cell to refresh the selected resistive storage cell, wherein the absolute value of the refresh bias voltage is greater than the first threshold voltage.

[0007] To provide a better understanding of the above and other aspects of this disclosure, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0008] Figure 1 A cross-sectional schematic diagram of a storage device according to one embodiment is shown;

[0009] Figure 2 An equivalent circuit diagram of a storage device according to one embodiment is shown;

[0010] Figure 3A A cross-sectional schematic diagram of a storage device having a low-resistance state according to an embodiment is illustrated; and

[0011] Figure 3B A cross-sectional schematic diagram of a storage device having a high resistance state according to an embodiment is shown;

[0012] Explanation of reference numerals in the attached figures:

[0013] 10: Storage device;

[0014] 101: First electrode;

[0015] 102: Storage layer;

[0016] 103: Adhesive layer;

[0017] 104: Ion-providing layer;

[0018] 105: Second electrode;

[0019] 106: Interlayer dielectric layer;

[0020] 201: Ion;

[0021] 202: Conductive bridge;

[0022] 211~214: Resistive memory cells;

[0023] BL: Bitline layer;

[0024] SL0, SL1: Source lines;

[0025] WL0, WL1: Word lines. Detailed Implementation

[0026] In the embodiments of this disclosure, a storage device and its operation method are proposed. The embodiments of this disclosure can be applied to a variety of different two-terminal resistive memory devices. For example, the embodiments can be applied to resistive random-access memory (ReRAM) of the conducting bridge type, resistive random-access memory (ReRAM) of the transition metal oxide (TMO) type, phase change memory devices, etc., but this disclosure is not limited to these applications.

[0027] It should be noted that this disclosure does not show all possible embodiments. Those skilled in the art can make variations and modifications to the structure and manufacturing methods of the embodiments without departing from the spirit and scope of this disclosure to meet the needs of practical applications. Therefore, other aspects not presented in this disclosure may also be applicable. The accompanying drawings are simplified to clearly illustrate the embodiments, and the dimensions in the drawings are not drawn to scale according to the actual product. Therefore, the specification and drawings are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure. The following description uses the same / similar symbols to denote the same / similar elements.

[0028] Furthermore, the ordinal numbers used in the specification and claims, such as "first," "second," and "third," are for modifying elements of the claims. They do not imply or represent any prior ordinal number for the element, nor do they represent the order of one element with another, or the order of manufacturing methods. The use of multiple ordinal numbers is only to make it clear that an element with a certain name can be distinguished from another element with the same name.

[0029] Furthermore, the term "electrical connection" used in the specification and appended claims can mean that multiple elements form an ohmic contact, that current flows between multiple elements, or that multiple elements have an operational relationship. An operational relationship can be, for example, that one element drives another element, but the current may not flow directly between the two elements. For instance, a bit line electrically connected to a memory cell can represent a bit line used to drive a memory cell, meaning that when the voltage applied to any bit line changes, the electric field acting on the memory cell electrically connected to that bit line can change accordingly. Similarly, a word line electrically connected to a memory cell can represent a word line used to drive a memory cell, meaning that when the voltage applied to any word line changes, the electric field acting on the memory cell electrically connected to that word line can change accordingly.

[0030] Figure 1 A cross-sectional schematic diagram of a storage device 10 according to an embodiment of the present disclosure is illustrated. The storage device 10 includes a first electrode 101, a storage layer 102, an adhesive layer 103, an ion providing layer 104, a second electrode 105, and an interlayer dielectric layer 106.

[0031] The first electrode 101 may be formed in the interlayer dielectric layer 106. A storage layer 102, an adhesive layer 103, and an ion-providing layer 104 may be disposed between the first electrode 101 and the second electrode 105. In this embodiment, the storage layer 102, adhesive layer 103, and ion-providing layer 104 are sequentially stacked on the first electrode 101. The storage layer 102 may directly contact the first electrode 101, and the ion-providing layer 104 may directly contact the second electrode 105. The adhesive layer 103 may be disposed between the storage layer 102 and the ion-providing layer 104. The second electrode 105 and the storage layer 102 may be located on opposite sides of the ion-providing layer 104.

[0032] The first electrode 101 and the second electrode 105 can be used to conduct current. The first electrode 101 and the second electrode 105 may include conductive materials. The ion-providing layer 104 can serve as an ion source. The ion-providing layer 104 can provide metal ions that can form conducting bridges / filaments in the storage device 10. The ion-providing layer 104 can provide metal ions with high mobility, such as copper ions, silver ions, or zinc ions. The ion-providing layer 104 may include copper, silver, or zinc. The adhesive layer 103 can be used to improve the adhesion between the storage layer 102 and the ion-providing layer 104, and can allow ions from the ion-providing layer 104 to pass through. The adhesive layer 103 may include a metal, such as titanium. Ions from the ion-providing layer 104 can aggregate in the storage layer 102 to form conducting bridges. The storage layer 102 may include a tellurium-based material, such as zinc telluride (ZnTe). The interlayer dielectric layer 106 may include a dielectric material.

[0033] Please refer to the following at the same time Figure 1-2 . Figure 2 An equivalent circuit diagram of a storage device 10 according to an embodiment of the present disclosure is shown. Figure 2 As shown, the storage device 10 also includes a plurality of resistive memory cells 211-214, a plurality of word lines WL0, WL1 electrically connecting the plurality of resistive memory cells 211-214, a bit line layer BL and a plurality of source lines SL0, SL1, and control circuitry (not shown). The resistive memory cells 211-214 can be defined on the storage layer 102 (e.g., ...). Figure 1 As shown in the diagram. The bitline layer BL may include one or more bitlines. For simplicity, Figure 2Only four resistive memory cells 211-214, two word lines WL0 and WL1, and two source lines SL0 and SL1 are shown, but this disclosure is not limited thereto; the memory device may include more resistive memory cells, word lines, and source lines. Control circuitry can electrically connect multiple resistive memory cells 211-214 via word lines WL0 and WL1, bit line layer BL, and source lines SL0 and SL1. The control circuitry can provide multiple operating modes to operate multiple resistive memory cells 211-214. The multiple operating modes may include a first programming operation and a second programming operation. During a programming operation, the control circuitry can apply an appropriate bias voltage to the resistive memory cells 211-214 via word lines WL0 and WL1, bit line layer BL, and source lines SL0 and SL1 to program the resistive memory cells 211-214 to have one of multiple resistive states, each resistive state corresponding to a data state. This disclosure is illustrated using resistive memory cells 211-214 having two resistive states as an example, but this disclosure can also be applied to memory devices having more resistive states.

[0034] when Figure 1-2 When the storage device 10 shown is in the first programming operation, one of a plurality of resistive memory cells 211-214 is selected for programming, while the other resistive memory cells can be understood as not being selected. The following description uses resistive memory cell 211 as the selected resistive memory cell and resistive memory cells 212-214 as unselected resistive memory cells as an example, but this disclosure is not limited thereto. The first programming operation includes applying a first programming bias voltage to the selected resistive memory cell 211 by electrically connecting the word line WL1, bit line layer BL, and source line SL0, so that the selected resistive memory cell 211 has a low resistance state. The first programming bias voltage may represent the potential difference between the first electrode 101 and the second electrode 105 of the storage device 10. The first programming bias voltage may have a first polarity. Figure 3A As shown, during the first programming operation, applying a first programming bias voltage to the selected resistive memory cell 211 drives a plurality of ions 201 provided by the ion providing layer 104 to move into the memory layer 102, and at least some of the ions 201 aggregate in the memory layer 102 to form a conductive bridge 202 extending through the memory layer 102. In this case, the selected resistive memory cell 211 has a low resistance state.

[0035] when Figure 1-2When the storage device 10 shown is in a second programming operation, one of a plurality of resistive memory cells is selected for programming, while the other resistive memory cells can be understood as not being selected. The following description uses resistive memory cell 211 as the selected resistive memory cell and resistive memory cells 212-214 as unselected resistive memory cells as examples, but this disclosure is not limited thereto. The second programming operation involves applying a second programming bias voltage to the selected resistive memory cell 211 by electrically connecting the word line WL1, bit line layer BL, and source line SL0, so that the selected resistive memory cell 211 has a high-resistance state. The second programming bias voltage may represent the potential difference between the first electrode 101 and the second electrode 105 of the storage device 10. The second programming bias voltage may have a second polarity. Figure 3B As shown, during the second programming operation, applying a second programming bias voltage to the selected resistive memory cell 211 drives the ions 201 of the conductive bridge 202 to move towards the ion providing layer 104, thereby disrupting the conductive bridge 202 between the first electrode 101 and the second electrode 105. For example, the conductive bridge 202 may break during the second programming operation. In this case, the selected resistive memory cell 211 has a high resistance state. The low resistance state and the high resistance state correspond to different data states, respectively. In one embodiment, the resistive memory cells 211-214 can be switched between different resistance states by applying different programming bias voltages to them. Switching the resistive memory cells 211-214 from a low resistance state to a high resistance state can also be understood as a reset operation. Switching the resistive memory cells 211-214 from a high resistance state to a low resistance state can also be understood as a set operation.

[0036] The first polarity of the first programming bias voltage may be different from the second polarity of the second programming bias voltage. In one embodiment, the first programming bias voltage may be a positive bias voltage, and the second programming bias voltage may be a negative bias voltage. A first programming operation induces a first programming current through a selected resistive memory cell. A second programming operation induces a second programming current through a selected resistive memory cell. The first programming current may be different from the second programming current. The first programming operation causes the selected resistive memory cell of the storage device 10 to have a first threshold voltage. The second programming operation causes the selected resistive memory cell of the storage device 10 to have a second threshold voltage. The first threshold voltage is different from the second threshold voltage. In one embodiment, the second threshold voltage may be greater than the first threshold voltage.

[0037] The control circuit provides multiple operating modes, which may also include an update operation. After programming the resistive memory cells 211-214, such as after the first programming operation, the conductive bridge 202 may spontaneously decompose, thereby changing the resistance state of the resistive memory cells 211-214 and affecting the correctness of the stored data. Therefore, the update operation may be performed after the programming operation, such as after the first programming operation, to extend the retention time of the resistance state of the resistive memory cells 211-214. The following description uses resistive memory cell 211 as the selected resistive memory cell and resistive memory cells 212-214 as the unselected resistive memory cells as examples, but this disclosure is not limited thereto. The update operation includes applying an update bias voltage to the selected resistive memory cell 211 by electrically connecting the word line WL1, the bit line layer BL, and the source line SL0 of the selected resistive memory cell 211 to update the selected resistive memory cell 211. The update bias voltage may represent the potential difference between the first electrode 101 and the second electrode 105 of the storage device 10. The update bias may have a first polarity. The absolute value of the update bias may differ from the absolute value of the first programming bias. In one embodiment, the update operation may not include applying the first programming bias to the selected resistive memory cell 211.

[0038] When an update operation is performed after the first programming operation, i.e., an update bias is applied to the selected resistive memory cell 211 having a low-resistance state, the update operation can induce a first update current through the selected resistive memory cell 211, which can improve the stability of the conductive bridge, reduce or suppress spontaneous disintegration of the conductive bridge, and extend the holding time of the low-resistance state. The first update current can be greater than half of the first programming current. In one embodiment, the update operation may include applying an update bias multiple times (e.g., periodically) during the holding period of the conductive bridge of the selected resistive memory cell 211. In one embodiment, the increased number of times the update bias is applied increases the holding time of the low-resistance state.

[0039] When the update operation occurs after the second programming operation, i.e., when an update bias is applied to the selected resistive memory cell 211 which is in a high-resistance state, the update operation can induce a second update current through the selected resistive memory cell 211. The second update current does not affect this high-resistance state. The first update current can be greater than the second update current.

[0040] The control circuit can also provide multiple operating modes, including a read operation. When... Figure 1-2When the storage device 10 shown is in a read operation, one of a plurality of resistive memory cells is selected for reading, while the other resistive memory cells can be understood as not being selected. The following description uses resistive memory cell 211 as the selected resistive memory cell and resistive memory cells 212-214 as unselected resistive memory cells as examples, but this disclosure is not limited thereto. The read operation may include applying a read bias voltage to the selected resistive memory cell 211 through the word line WL1, bit line layer BL, and source line SL0 electrically connecting the selected resistive memory cell 211, and reading the data state stored in the selected resistive memory cell 211 based on the induced read current. The read bias voltage may represent the potential difference between the first electrode 101 and the second electrode 105 of the storage device 10. The read bias voltage may have a first polarity. The absolute value of the update bias voltage may be equal to the absolute value of the read bias voltage.

[0041] Table 1

[0042]

[0043] In one embodiment, the voltage values ​​applied to the bit lines, source lines, and word lines under different operating modes may be as shown in Table 1 above. A first programming operation may include: applying a bit line voltage, for example, 2.5V, to the bit line layer electrically connected to the selected resistive memory cell; applying a source line voltage, for example, 0V, to the source line electrically connected to the selected resistive memory cell; and applying a word line voltage, for example, 1.8V, to the word line electrically connected to the selected resistive memory cell. A second programming operation may include: applying a bit line voltage, for example, 0V, to the bit line layer electrically connected to the selected resistive memory cell; applying a source line voltage, for example, 1.6V, to the source line electrically connected to the selected resistive memory cell; and applying a word line voltage, for example, 2.2V, to the word line electrically connected to the selected resistive memory cell. An update operation may include: applying a bit line voltage, for example, 0.8V, to the bit line layer electrically connected to the selected resistive memory cell; applying a source line voltage, for example, 0V, to the source line electrically connected to the selected resistive memory cell; and applying a word line voltage, for example, 5.0V, to the word line electrically connected to the selected resistive memory cell. Read operations may include: applying a bit line voltage, such as 0.8V, to the bit line layer electrically connected to the selected resistive memory cell; applying a source line voltage, such as 0V, to the source line electrically connected to the selected resistive memory cell; and applying a word line voltage, such as 5.0V, to the word line electrically connected to the selected resistive memory cell.

[0044] According to embodiments of this disclosure, the memory device can be operated in multiple operating modes, including a first programming operation applying a first programming bias voltage to establish a low-resistance state in the memory device, and an update operation applying a refresh bias voltage to update the memory device, wherein the absolute value of the refresh bias voltage is greater than a first threshold voltage of the memory device in the first programming operation. This configuration effectively improves the stability of the conductive bridge, suppresses or reduces spontaneous decomposition of the conductive bridge, thereby extending the retention time of the resistance state (or data state) of the memory device and improving the reliability or accuracy of the memory device. Furthermore, the update operation of this disclosure can apply a refresh bias voltage one or more times to extend the retention time of the resistance state, and the update operation may not include applying the first programming bias voltage. This configuration reduces the number of voltage switching operations applied to the bit lines and / or source lines, reduces power consumption, simplifies the operation of the memory device, and efficiently and easily extends the retention time of the data state. The update operation of this disclosure is a self-defined refresh operation.

[0045] In summary, although this disclosure has been presented above with reference to embodiments, it is not intended to limit the scope of this disclosure. Those skilled in the art to which this disclosure pertains can make various modifications and variations without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of this disclosure shall be determined by the appended claims.

Claims

1. A storage device, characterized in that, include: Multiple resistive memory cells; as well as A control circuit is electrically connected to the plurality of resistive memory cells. This control circuit provides multiple operating modes for operating the plurality of resistive memory cells, including: A first programming operation includes applying a first programming bias voltage to a selected resistive memory cell among a plurality of resistive memory cells to give the selected resistive memory cell a low resistance state, wherein the first programming operation gives the memory device a first threshold voltage. as well as An update operation includes applying an update bias voltage to the selected resistive memory cell to update the selected resistive memory cell, wherein the absolute value of the update bias voltage is greater than the first threshold voltage.

2. The storage device of claim 1, wherein the plurality of operating modes further comprises a second programming operation, the second programming operation comprising applying a second programming bias voltage to the selected resistive memory cell to give the selected resistive memory cell a high resistance state, the second programming operation giving the storage device a second threshold voltage, the second threshold voltage being greater than the first threshold voltage.

3. The storage device of claim 2, wherein the absolute value of the update bias is less than the second threshold voltage.

4. The storage device of claim 1, wherein the first programming operation induces a programming current through the selected resistive memory cell. Performing the update operation on the selected resistive memory cell that has this low resistance state induces an update current to pass through the selected resistive memory cell. The update current is greater than half of the programming current.

5. The storage device of claim 1, wherein the plurality of operating modes further comprises a read operation, the read operation comprising applying a read bias voltage to the selected resistive memory cell to read the selected resistive memory cell, the absolute value of the read bias voltage being equal to the absolute value of the update bias voltage.

6. The storage device of claim 1, wherein the update operation includes applying the update bias multiple times.

7. The storage device of claim 1, wherein the update operation is performed after the first programming operation.

8. The storage device of claim 1, wherein the update operation does not include applying the first programming bias to the selected resistive memory cell.

9. The storage device according to claim 1, further comprising: A first electrode; A second electrode; A storage layer is disposed between the first electrode and the second electrode; as well as An ion-providing layer is disposed between the first electrode and the second electrode, with the second electrode and the storage layer located on opposite sides of the ion-providing layer. The multiple resistive memory cells are located in this memory layer.

10. The storage device of claim 9, wherein the ion-providing layer comprises copper, silver, or zinc.

11. The storage device of claim 9, wherein the storage layer comprises a tellurium (Te-based) material.

12. The storage device of claim 9, further comprising an adhesive layer between the storage layer and the ion providing layer, wherein the adhesive layer comprises a metal.

13. The storage device of claim 9, wherein the first programming operation causes a conductive bridge to be formed between the first electrode and the second electrode.

14. A method of operating a storage device, the method comprising a plurality of resistive storage cells, the method comprising: A first programming bias is applied to a selected resistive memory cell among a plurality of resistive memory cells to give the selected resistive memory cell a low resistance state, wherein the step of applying the first programming bias gives the memory device a first threshold voltage. as well as A refresh bias is applied to the selected resistive memory cell to refresh the selected resistive memory cell, wherein the absolute value of the refresh bias is greater than the first threshold voltage.

15. The method of claim 14, further comprising: A second programming bias is applied to a selected resistive memory cell among the plurality of resistive memory cells to give the selected resistive memory cell a high resistance state, wherein the step of applying the second programming bias gives the memory device a second threshold voltage, the second threshold voltage being greater than the first threshold voltage.

16. The method of claim 15, wherein the absolute value of the updated bias is less than the second threshold voltage.

17. The method of claim 14, wherein the step of applying the update bias is performed after the step of applying the first programming bias.

18. The method of claim 17, wherein The step of applying the first programming bias voltage induces a programming current through the selected resistive memory cell. Applying the update bias voltage induces an update current through the selected resistive memory cell. The update current is greater than half of the programming current.

19. The method of claim 14, further comprising applying a read bias to the selected resistive memory cell to read the selected resistive memory cell, the read bias being equal to the update bias.

20. The method of claim 14, wherein the step of applying the update bias includes applying the update bias multiple times.

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