Fefet unit cell for neuromorphic computing

Abstract

The circuit structure includes a first ferroelectric field effect transistor (FeFET) having a first gate electrode, a first source electrode, and a first drain electrode, and a second FeFET having a second gate electrode, a second source electrode, and a second drain electrode. The first gate electrode is connected to a word line, and the first source electrode and the second source electrode are connected to a bit line. The first drain electrode is connected to the second gate electrode and the second drain electrode is connected to a bias line. A weight synapse structure is constructed by combining the two circuit structures. A plurality of weight synapse structures are incorporated into a crossbar array.

Description

TECHNICAL FIELD

[0001] The present invention relates generally to semiconductor devices, and more particularly to ferroelectric field effect transistor (FeFET) unit cells for neuromorphic computing. BACKGROUND

[0002] FeFETs are emerging devices in which a ferroelectric layer (FE) is integrated in the gate stack above the dielectric (DE) of a transistor. An optional metal can also be used between the FE and DE layers. The polarization of the FE is coupled to the polarization of the underlying FET, resulting in unique characteristics such as non-volatile transistor operation (due to P retention without external E). Experimental studies have shown simulated computing or non-volatile (memory) characteristics of FeFETs by employing design time / static device optimization (e.g., by modifying the composition of the gate stack). SUMMARY

[0003] According to an embodiment, a circuit structure is provided. The circuit structure includes a first ferroelectric field effect transistor (FeFET) and a second FeFET, the first FeFET including a first gate electrode, a first source electrode, and a first drain electrode, the second FeFET including a second gate electrode, a second source electrode, and a second drain electrode, wherein the first gate electrode is connected to a word line, and wherein the first source electrode and the second source electrode are connected to a bit line.

[0004] According to another embodiment, a weight synapse structure is provided. The weight synapse structure includes a first circuit structure and a second circuit structure, the first circuit structure being incorporated between a first word line and a first bit line, wherein the first circuit structure includes a first ferroelectric field effect transistor (FeFET) and a second FeFET, the second circuit structure being incorporated between a second word line and a second bit line, wherein the second circuit structure includes a third FeFET and a fourth FeFET, the first circuit structure being electrically connected to the second circuit structure by electrically connecting the first word line to the second word line to define a single synapse.

[0005] According to yet another embodiment, a method is provided. The method includes: constructing a first ferroelectric field effect transistor (FeFET) including a first gate electrode, a first source electrode, and a first drain electrode; constructing a second FeFET including a second gate electrode, a second source electrode, and a second drain electrode, the first FeFET and the second FeFET being combined to form a first circuit structure; connecting the first gate electrode to a first word line; and connecting the first source electrode and the second source electrode to a first bit line.

[0006] It should be noted that the example embodiments are described with reference to different subject matters. Specifically, some embodiments are described with reference to method type claims whereas other embodiments are described with reference to device type claims. However, a person skilled in the art will gather from the above and the following description that, unless otherwise indicated, any aspect or feature described as pertaining to a type of subject matter also pertains to other subject types, in particular, features described in terms of a type of subject matter also pertain to subject matters of other types.

[0007] These and other features and advantages will be apparent from the following detailed description, which, by way of illustration, is BRIEF DESCRIPTION OF DRAWINGS

[0008] The present application will be provided in the following description with reference to the following drawings wherein:

[0009] Figure 1 is a ferroelectric field effect transistor (FeFET) structure;

[0010] Figure 2 is a unit cell including two FeFETs according to embodiments of the present application;

[0011] Figure 3 is a synaptic weight including four FeFETs according to embodiments of the present application;

[0012] Figure 4 is a block / flow diagram for training or setting synaptic weights according to embodiments of the present application;

[0013] Figure 5 is a block / flow diagram for resetting synaptic weights according to embodiments of the present application;

[0014] Figure 6 is a block / flow diagram for resetting pass transistors and reading synaptic weights according to embodiments of the present application;

[0015] Figure 7 is an n-type field effect transistor (nFET) and p-type field effect transistor (pFET) configuration with a first set of bias conditions according to embodiments of the present application;

[0016] Figure 8 is an nFET configuration and a pFET configuration with a second set of bias conditions according to embodiments of the present application;

[0017] Figure 9 is an exemplary neuromorphic and synaptic electronic network including an interconnection of electronic neurons and crossbars of electronic synapses according to embodiments of the present application;

[0018] Figure 10 is a block diagram of components of a computing system including a computing device and a neuromorphic chip capable of employing unit cells and / or synaptic weights, according to embodiments of the present application;

[0019] Figure 11 is a block diagram / flowchart of a method for showing unit cell connection (two FeFETs), according to embodiments of the present application; and

[0020] Figure 12 is a block diagram / flowchart of a method for showing synaptic weight connection (four FeFETs), according to embodiments of the present application.

[0021] Throughout the drawings, identical or similar reference numbers indicate identical or similar elements. DETAILED DESCRIPTION

[0022] Embodiments according to the present application provide methods and devices for employing unit cells to improve linearity of neuromorphic computation. A unit cell includes two ferroelectric field effect transistors (FeFETs). In the unit cell, one FeFET is used as an access (or pass) transistor and the other FeFET is used to store information proportional to conductance (G). A weight is represented by two unit cells (i.e., four FeFETs). The weight is represented proportional to the difference of (G+, G-). The FeFETs can be n-type field effect transistors (nFETs) or p-type field effect transistors (pFETs) or a combination thereof.

[0023] Linearity is a factor for analog memory elements to be used for weight update. For the purpose of online training, the spikes need to have the same amplitude and duration. However, it is still a challenge to obtain the necessary linearity when using existing FeFETs under voltage pulses. In one approach, the gate voltage of the FeFET synapse can be adjusted to improve the linearity response. This can be achieved by using the FeFET as a pass transistor such that the voltage applied to the synapse is modulated.

[0024] Embodiments according to the present application provide methods and devices for a structure including two FeFETs, one FeFET is used as a pass transistor and the other FeFET is used for analog computation to improve linearity of weight update. One FeFET is used for enhancement, while the other FeFET is used for inhibition. Thus, exemplary embodiments of the present application focus on a two FeFET unit cell structure to improve linearity of neuromorphic computation, where two ferroelectric memories are used for training purposes.

[0025] Examples of semiconductor materials that can be used to form such FeFETs include silicon (Si), germanium (Ge), silicon-germanium alloys (SiGe), silicon carbide (SiC), silicon-germanium carbide (SiGeC), III-V compound semiconductors, and / or II-VI compound semiconductors. III-V compound semiconductors are materials that include at least one element from Group III of the periodic table and at least one element from Group V of the periodic table. II-VI compound semiconductors are materials that include at least one element from Group II of the periodic table and at least one element from Group VI of the periodic table.

[0026] It should be appreciated that the present application will be described in terms of a given illustrative architecture; however, other architectures, structures, substrates, materials, and processing features and steps / blocks could be used without departing from the scope of the present application. It should be noted that for clarity's sake, certain features could not be shown in all of the figures. This is not intended to be limiting in any way.

[0027] Figure 1 is a ferroelectric field effect transistor (FeFET) structure.

[0028] The FeFET device 5 includes a source region 12 and a drain region 14 formed on a portion of the substrate 10. An interface layer (IL) 16 is formed in direct contact with the top surface of the substrate 10, the source region 12, and the drain region 14. A ferroelectric oxide layer 18 is formed on the IL 16. A top electrode 20 is then formed on the ferroelectric oxide layer 18. A gate voltage 22 (VGS) can be applied via the top electrode 20.

[0029] The substrate 10 can be crystalline, semi-crystalline, microcrystalline, or amorphous. The substrate 10 can be substantially a single element (e.g., silicon), predominantly a single element (e.g., with doping) (e.g., silicon (Si) or germanium (Ge)), or the substrate 10 can include a compound (e.g., GaAs, SiC, or SiGe). The substrate 10 can also have multiple layers of material. In some embodiments, the substrate 10 includes a semiconductor material including, but not necessarily limited to, silicon (Si), silicon germanium (SiGe), silicon carbide (SiC), Si:C (carbon-doped silicon), silicon germanium carbide (SiGeC), silicon germanium carbon-doped (SiGe:C), III-V (e.g., GaAs, AlGaAs, InAs, InP, etc.), II-V compound semiconductors (e.g., ZnSe, ZnTe, ZnCdSe, etc.), or other similar semiconductors. Further, multiple layers of semiconductor material can be used as the semiconductor material of the substrate 10. In some embodiments, the substrate 10 includes both semiconductor material and dielectric material. The semiconductor substrate 10 can also include an organic semiconductor or a layered semiconductor, such as Si / SiGe, silicon on insulator, or SiGe on insulator. Some or all of the semiconductor substrate 10 can be amorphous, polycrystalline, or single crystalline. In addition to the types of semiconductor substrates described above, the semiconductor substrate 10 employed in the present application can also include a hybrid orientation (HOT) semiconductor substrate, where the HOT substrate has surface regions of different crystal orientations.

[0030] The terms "epitaxial growth" and "epitaxial deposition" refer to the growth of a semiconductor material on a deposition surface of a semiconductor material, where the grown semiconductor material has substantially the same crystal characteristics as the semiconductor material of the deposition surface. The term "epitaxial material" denotes a material formed using epitaxial growth. In some embodiments, when the chemical reactants are controlled and the system parameters are set correctly, the deposited atoms arrive at the deposition surface with sufficient energy to move around on the surface and orient themselves to the crystal arrangement of the atoms of the deposition surface. Thus, in some instances, an epitaxial film deposited on a {100} crystal surface will exhibit a {100} orientation.

[0031] The top electrode 20 can include a conductive material, such as Cu, Al, Ag, Au, Pt, W, Ta, Ru, etc. In some embodiments, the top electrode 20 can include a nitride, such as TiN, TaN, etc.

[0032] The ferroelectric oxide layer 18 can include a hafnium oxide (Hf02) layer or Hf02with a dopant, such as Si, Al, Zr, N, etc. For example, the ferroelectric oxide layer 18 can include Hf02in an orthorhombic phase (ferroelectric phase).

[0033] Figure 2is a unit cell including two FeFETs according to embodiments of the present invention.

[0034] Unit cell 30 includes two FeFETs, that is, a first FeFET 40 and a second FeFET 42. First FeFET 40 functions as a pass transistor and second FeFET 42 functions as a non-volatile memory (NVM) for analog computation.

[0035] In various exemplary embodiments, unit cell 30 is incorporated between a bit line 34 and a word line 32. Thus, an array can be obtained with perpendicular conductive word lines (rows) 32 and bit lines (columns) 34, with unit cell structures 30 present at the intersection between each row and each column. Cell structures 30 can be accessed for reading and writing by biasing the corresponding word line 32 and bit line 34. Unit cell 30 represents a conductance (G) value 36.

[0036] Figure 3 is a synaptic weight including four FeFETs according to embodiments of the present invention.

[0037] Weight synapse 50 includes two unit cells and four FeFETs. Specifically, G+ (66) or unit cell 60 includes two FeFETs 62, 64 and G- (76) or unit cell 70 includes two FeFETs 72, 74. FeFET 62 of unit cell 60 is a pass transistor and FeFET 64 of unit cell 60 is a NVM for analog computation. Similarly, FeFET 72 of unit cell 70 is a pass transistor and FeFET 74 of unit cell 70 is a NVM for analog computation. Each unit cell includes a word line and a bit line. For example, unit cell 60 includes word line 52 and bit line 54, while unit cell 70 includes word line 56 and bit line 58.

[0038] Thus, according to Figures 1-3The FeFET device 5 includes a single transistor structure (source region 12, drain, gate region 14, substrate 10) with a ferroelectric oxide layer 18 used as a gate dielectric. Two FeFETs (one used as a pass transistor and one used as NVM for analog computation) represent a unit cell structure 30, which represents a conductance (G) value for analog computation. G+ (two FeFETs) and G- (additional two FeFETs) together represent a synaptic weight 50, where W is proportional to the difference between G+ and G-. The concept of a double unit cell represents one synapse for a phase change memory (PCM) based synapse application, where two PCM devices represent one weight (G+-G-). According to exemplary embodiments of the present application, two unit cells are needed to represent a synapse, and for each unit cell, two FeFETs are needed (one pass transistor and one NVM for analog computation).

[0039] Figure 4 is a block / flow diagram for training or setting a synaptic weight according to embodiments of the present application.

[0040] For training 80, when setting a synapse, Vp can gradually change the Vt of the FeFET (pass transistor) with respect to the word line 82. Vb-Vt can modulate the channel conductance of the synapse with respect to the bit line 84. Thus, to program a FeFET device, a positive voltage pulse above the threshold voltage Vt must be applied. In this way, a sufficient electric field is created on the ferroelectric layer to cause a polarization reversal. Thus, for each access of a positive pulse Vp, the FeFET turns on.

[0041] Figure 5 is a block / flow diagram for resetting a synaptic weight according to embodiments of the present application.

[0042] For synapse reset 90, Vw_rst is large and turns on the pass transistor with respect to the word line 92. Vb_rst is negative and large enough in absolute value to reset the synapse device with respect to the bit line 94.

[0043] Figure 6 is a block / flow diagram for resetting the pass transistor and reading a synaptic weight according to embodiments of the present application.

[0044] For read of synapse 100, Vp_full is large to program the polarization fully to the initial condition with respect to the word line 102. Vb_read is small and does not disturb the FeFET with respect to the bit line 104.

[0045] Figure 7 is an nFET configuration and a pFET configuration with a first set of bias conditions according to embodiments of the present application.

[0046] In the first configuration 110, two nFETs 112, 114 are connected to each other in a unit cell. In a first set of conditions 116, Vbias < Vbl and VGS(synapse) = Vbl - Vt - Vbias, where the synapse decreases as Vt increases. Note that if Vbias is chosen to be 0, then this configuration becomes equivalent to the configuration described with respect to Figure 2 the described configuration.

[0047] In the second configuration 120, one nFET 122 and one pFET 124 are connected to each other in a unit cell. In a first set of conditions 126, Vbias < Vbl and -VGS(synapse) = Vt, where the synapse increases as Vt increases.

[0048] In the third configuration 130, one pFET 132 and one nFET 134 are connected to each other in a unit cell. In a first set of conditions 136, Vbias > Vbl and VGS(synapse) = Vt, where the synapse decreases as -Vt increases.

[0049] In the fourth configuration 140, two pFETs 142, 144 are connected to each other in a unit cell. In a first set of conditions 146, Vbias > Vbl and -VGS(synapse) = Vbias - Vbl - Vt, where the synapse increases as -Vt increases.

[0050] Figure 8 are nFET configurations and pFET configurations with a second set of bias conditions according to embodiments of the present invention.

[0051] In the first configuration 110, two nFETs 112, 114 are connected to each other in a unit cell. In a second set of conditions 118, Vbias > Vbl and VGS(synapse) = -Vt, where the synapse decreases as Vt increases.

[0052] In the second configuration 120, one nFET 122 and one pFET 124 are connected to each other in a unit cell. In a second set of conditions 128, Vbias > Vbl and -VGS(synapse) = Vbias - (Vbl - Vt), where the synapse increases as Vt increases.

[0053] In the third configuration 130, one pFET 132 and one nFET 134 are connected to each other in a unit cell. In a first set of conditions 138, Vbias < Vbl and VGS(synapse) = (Vbl + Vt) - Vbias, where the synapse decreases as -Vt increases.

[0054] In a fourth configuration 140, two pFETs 142, 144 are connected to each other in a unit cell. In a first set of conditions 148, Vbias < Vbl and -VGS(synapse) = -Vt, where the synapse is strengthened as -Vt increases.

[0055] In one non-limiting example of a pulse train of the same amplitude (V) and duration, where n is the number of pulses applied after resetting the FeFET, assuming the channel conductivity and thus Vt factorizes on V and n based on the empirical FeFET expression:

[0056] AVt, PASS = Vt, PASS - Vt0, PASS = a1V [1 - exp(-l1n)],

[0057] where a1, l1are empirical parameters.

[0058] Thus, the AVt of the synapse can be expressed as:

[0059] AVt, SYNAPSE = a2(C + AVt, PASS) [1 - exp(-l2n)],

[0060] where C is a constant depending on Vt0, PASS, Vbias, and Vbl.

[0061] Thus, Veffective, SYNAPSE = C + a1V [1 - exp(-l1n)], which increases as a function of n, and thus improves the linearity.

[0062] Quantitatively, without the pass transistor FeFET, the synapse linearity at n ~ 1 / l2 would be (1 - exp(-1)) x 100 ~ 64%.

[0063] With the addition of the pass transistor FeFET, the synapse linearity increases by [1 + a1(V / C).(1 - exp(-l1 / l2)] times, which for l1~ l2 is about [1 + 0.64a1(V / C)].

[0064] Figure 9 An exemplary neuromorphic and synaptronic electronic network comprising a crossbar of interconnected electronic neurons and electronic synapses of axons, in accordance with an embodiment of the present application.

[0065] According to one embodiment of the present application, exemplary tile circuit 200 has a crossbar 212. In one instance, the entire circuit can comprise a "super dense crossbar array" that can have a pitch in the range of about 10 nm to 500 nm. However, one skilled in the art can also consider smaller and larger pitches. Neuromorphic and synaptic electronic circuit 200 includes a crossbar 212 that interconnects a plurality of digital neurons 211, including neurons 214, 216, 218, and 220. These neurons 211 are also referred to herein as "electronic neurons." For purposes of illustration, exemplary circuit 200 provides symmetric connections between two pairs of neurons (e.g., N1 and N3). However, embodiments of the present application are useful not only for such symmetric connections of neurons, but also for asymmetric connections of neurons (neurons N1 and N3 need not be connected with the same connections). The crossbar in a tile accommodates the proper ratio of synapses to neurons, and thus need not be square.

[0066] In exemplary circuit 200, neurons 211 are connected to crossbar 212 via dendrite paths / leads (dendrites) 213, such as dendrites 226 and 228. Neurons 211 are also connected to crossbar 212 via axon paths / leads (axons) 215, such as axons 234 and 236. Neurons 214 and 216 are dendrite neurons, while neurons 218 and 220 are axon neurons connected to dendrites 213. Specifically, neurons 214 and 216 are shown as having outputs 222 and 224 connected to dendrites (e.g., bit lines) 226 and 228, respectively. Axon neurons 218 and 220 are shown as having outputs 230 and 232 connected to axons (e.g., word lines or access lines) 234 and 236, respectively.

[0067] When any of neurons 214, 216, 218, and 220 fire, they will send a pulse to their axon and dendrite connections. Each synapse provides contact between an axon of a neuron and a dendrite on another neuron, and with respect to the synapse, the two neurons are referred to as the presynaptic and postsynaptic neurons, respectively.

[0068] Each connection between dendrites 226, 228 and axons 234, 236 is made through a digital synapse device 231 (synapse). The junction at which the synapse device resides can be referred to herein as a "crosspoint junction." Generally, in accordance with embodiments of the present application, neurons 214 and 216 will "fire" (transmit a pulse) in response to input received from their axon input connections (not shown) exceeding a threshold value. Each individual synapse 231 can include a first circuit structure and a second circuit structure that are electrically connected to each other, either directly or indirectly through peripheral circuitry. The first circuit structure can be referred to as a first unit cell and the second circuit structure can be referred to as a second unit cell. Each individual synapse 231 includes four FeFETs, as shown. Figure 3 Thus, in one example, Figure 3 one or more weight synapse structures are incorporated into Figure 9 the neuromorphic and synaptronics network of

[0069] Neurons 218 and 220 will "fire" (transmit a pulse) in response to input received from their external input connections (not shown), typically from other neurons, exceeding a threshold value. In one embodiment, when neurons 214 and 216 fire, they maintain a decaying post-synaptic spike-time-dependent plasticity (STDP) (post-STDP) variable. For example, in one embodiment, the decay period can be 50 ps (which is 1000 times shorter than the decay period of actual biological systems, corresponding to an operational speed that is 1000 times higher). The post-STDP variable is employed to implement STDP by encoding the time since the last firing of the associated neuron. This STDP is used to control long-term potentiation or "strengthening," which in this context is defined as increasing the synaptic conductance. When neurons 218, 220 fire, they maintain a pre-STDP (pre-synaptic STDP) variable that decays in a similar manner to neurons 214 and 216.

[0070] For example, the pre-STDP variable and the post-STDP variable can decay according to an exponential, linear, polynomial, or quadratic function, among others. In another embodiment of the present application, the variable can increase over time rather than decrease. In any case, this variable can be used to implement STDP by encoding the time since the last firing of the associated neuron. The STDP is used to control long-term depression or "weakening," which in this context is defined as decreasing the synaptic conductance. Note that the roles of the pre-STDP variable and the post-STDP variable can be reversed, where the pre-STDP implements strengthening and the post-STDP implements depression.

[0071] An external bidirectional communication environment can supply sensory input and consume motor output. Digital neurons 211 implemented using complementary metal-oxide-semiconductor (CMOS) logic gates receive and integrate the pulse inputs. In one embodiment, a neuron 211 includes a comparator circuit that generates a pulse when the integrated input exceeds a threshold. In one embodiment, a flash memory cell is used to implement a synapse, where each neuron 211 can be an excitatory or inhibitory neuron (or both). Each learning rule on each neuron axon and dendrite can be reconfigurable, as described below. This assumes transposable access to a crossbar memory array. Neurons that select pulses one at a time send the pulse event to the corresponding axon, which can reside on the core or elsewhere in a larger system with many cores.

[0072] The term electronic neuron as used herein refers to an architecture configured to mimic a biological neuron. The electronic neuron creates connections between processing elements that are roughly functionally equivalent to neurons of a biological brain. As such, a neuromorphic and synaptronic electronic system including electronic neurons according to embodiments of the present application can include various electronic circuits modeled on biological neurons, although in many useful embodiments they can operate on a faster timescale (e.g., 1000 times faster) than their biological counterparts. Further, a neuromorphic and synaptronic electronic system including electronic neurons according to embodiments of the present application can include various processing elements (including computer simulations) modeled on biological neurons. While certain illustrative embodiments of the present application are described herein using electronic neurons including electronic circuits, the present application is not limited to electronic circuits. A neuromorphic and synaptronic electronic system according to embodiments of the present application can be implemented as a neuromorphic and synaptronic electronic architecture including circuits, and additionally can also be implemented as a computer simulation. Indeed, embodiments of the present application can take the form of a purely hardware embodiment, a purely software embodiment, or an embodiment including both hardware and software elements.

[0073] Figure 10 is a block diagram of components of a computing system according to embodiments of the present application, including a computing device and a neuromorphic chip capable of employing unit cells and / or synapse weights.

[0074] Figure 10 A block diagram of components of a system 300, including a computing device 305, is depicted. It should be appreciated that, Figure 10 Only one implemented illustration is provided and no implication is made that any particular environment is used for implementation. Many modifications can be made to the depicted environments.

[0075] The computing device 305 includes a communication structure 302 that provides communications between the computer processor(s) 304, the memory 306, the persistent storage 308, the communication units 310, and the input / output (I / O) interface(s) 312. The communication structure 302 can be implemented with any architecture designed for the

[0076] The memory 306, the cache memory 316, and the persistent storage 308 are computer readable storage media. In this embodiment, the memory 306 includes random access memory (RAM) 314. In another embodiment, the memory 306 can be flash memory. Generally, the memory 306 can include any suitable volatile or non-volatile computer readable storage media.

[0077] In some embodiments of the application, the deep learning program 325 is included and operated by the neuromorphic chip 322 as a component of the computing device 305. In other embodiments, the deep learning program 325 is stored in the persistent storage 308 for execution by the neuromorphic chip 322 in conjunction with one or more of the respective computer processors 304 via one or more of the memories 306. In this embodiment, the persistent storage 308 includes a magnetic hard disk drive. Alternatively, or in addition to a magnetic hard disk drive, the persistent storage 308 can include a solid-state hard drive, semiconductor memory device, read-only memory (ROM), erasable programmable read-only memory (EPROM), flash memory, or any other computer readable storage media that is capable of storing program instructions or digital information.

[0078] The media used by the persistent storage 308 can also be removable. For example, a removable hard drive can be used for persistent storage 308. Other examples include optical and magnetic disks, thumb drives, and smart cards that are inserted into a drive, respectively, to transfer software programs or digital information to another computer readable storage media, also a part of the persistent storage 308.

[0079] In these examples, the communication units 310 provide communication with other data processing systems or devices, including resources of the distributed data processing environment. In these examples, the communication units 310 include one or more network interface cards. The communication units 310 can provide communication through the use of either or both physical and wireless communications links. The deep learning program 325 can be downloaded to the persistent storage 308 through the communication units 310.

[0080] The I / O interface 312 allows for input and output of data to other devices that can be connected to the computing system 300. For example, the I / O interface 312 can provide a connection to external devices 318 such as a keyboard, a keypad, a touch screen, and / or some other suitable input device. The external devices 318 can also include portable computer-readable storage media, such as, for example, thumb drives, portable optical or magnetic disks, and memory cards.

[0081] The display 320 provides a mechanism to display data to a user, and can be, for example, a computer monitor.

[0082] Figure 11 is a block diagram / flowchart of a method for showing a unit cell connection (2 FeFETs) according to embodiments of the present invention.

[0083] At block 410, a first FeFET is employed that includes a first gate electrode, a first source electrode, and a first drain electrode.

[0084] At block 420, a second FeFET is employed that includes a second gate electrode, a second source electrode, and a second drain electrode.

[0085] At block 430, the first gate electrode is connected to a word line.

[0086] At block 440, the first source electrode and the second source electrode are connected to a bit line.

[0087] At block 450, the first drain electrode is connected to the second gate electrode.

[0088] At block 460, the second drain electrode is connected to a bias line.

[0089] Figure 12 is a block diagram / flowchart of a method for showing a synapse weight connection (4 FeFETs) according to embodiments of the present invention.

[0090] At block 510, a first FeFET and a second FeFET defining a first unit cell are employed.

[0091] At block 520, a third FeFET and a fourth FeFET defining a second unit cell are employed.

[0092] At block 530, the first unit cell is connected to the second unit cell to represent a synapse weight in neuromorphic computing.

[0093] At block 540, the synapse weight is trained, read, and reset.

[0094] It should be understood that the application will be described in terms of a given illustrative architecture; however, other architectures, structures, substrates, and processing features and steps / blocks could be varied within the scope of the application.

[0095] It should also be understood that when an element such as a layer, region, or substrate is referred to as being "on" or "over" another element, it can be directly on the other element or intervening elements can also be present. In contrast, when an element is referred to as being "directly on" or "directly over" another element, there are no intervening elements present. It will also be appreciated by those of skill in the art that references to a structure or feature that is positioned "adjacent" to another feature can have the same meaning as a structure that is "on" or "over" the adjacent feature, unless indicated otherwise.

[0096] The embodiments can include a design for an integrated circuit chip created in a graphical computer programming language, and stored in a computer storage medium (such as a disk, tape, physical hard drive, or virtual hard drive such as in storage access networks). If the designer does not fabricate chips or the photolithographic masks used to fabricate the chips, the designer can transmit the resulting design by physical means (for example, by providing a copy of the storage medium storing the design) or electronically (for example, through the Internet) to such entities, either directly or indirectly. The stored design is then converted into the appropriate format (for example, GDSII) and used to fabricate the physical structures, i.e., the masters, that will ultimately be processed into the chips.

[0097] The methods described herein can be used to fabricate integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricant in raw wafer form (i.e., as a single wafer having many unpackaged chips), as bare dies, or in a packaged form. In the latter case, the chip is mounted in a single-chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either one or both of surface interconnections or buried interconnections). In any case, the chip, when packaged, is then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer

[0098] It should also be understood that material compounds will be described in terms of listed elements (e.g., SiGe). These compounds include different proportions of the elements within the compound, e.g., SiGe includes six Gei-x, where x is less than or equal to 1, and the like. In addition, other elements can be included in the compound and still function in accordance with the embodiments of the application. Compounds with additional elements will be referred to herein as alloys.

[0099] Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, characteristic, and / or

[0100] It should be understood that any further "or" herein is used to mean "and / or", that "at least" when used before a list of items suggests that different combinations of the items from the list can be used, and that items in such a list are presented as examples and not as prerequisites or requirements. As used in this specification and the appended claims, the singular forms "a," "an" and "the" include plural referents unless the content clearly dictates otherwise. Thus, for example, reference to "a compound" includes a single compound as well as a combination or mixture of two or more compounds. As used herein, the term "exemplary" is used interchangeably with "for example," and refers to an example.

[0101] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms "a," "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" "comprising," "includes" and / or "including" when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0102] For ease of description, spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for describing an element's or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. For example, if a device is inverted or flipped over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. Furthermore, it will be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or one or more intervening layers can also be present. Figure 1

[0103] It is to be understood that the terms so far as expressions of a possible relationship of one described element to another described element can also encompass many other dependencies or connections not expressly stated. For example, if a first element is described as being connected to a second element, this can also imply that a third element can be connected to the first element, etc.

[0104] Having described preferred embodiments for a method and system for improving linearity of neuromorphic computation by employing two FeFET unit-cell structures (which are intended to be illustrative and not limiting), it is noted that modifications and variations can be affected by those skilled in the art by virtue of the teachings of the above disclosure without departing from the scope of the concept. It is, therefore, to be understood that changes can be made in the particular embodiments described, which are within the scope of the concept, as outlined in the appended claims, and that the application is not restricted to the details of the foregoing disclosure. Having thus described various aspects of the present application, with the details and particularity required by the patent laws, what is claimed and desired protected by Letters Patent is set forth in the appended claims.​

Claims

1. A circuit structure, comprising: a first ferroelectric field effect transistor (FeFET) comprising a first gate electrode, a first source electrode, and a first drain electrode; and a second FeFET comprising a second gate electrode, a second source electrode, and a second drain electrode; wherein the first gate electrode is connected to a word line; and wherein the first source electrode and the second source electrode are connected to a same bit line.

2. The circuit structure of claim 1, wherein the first drain electrode is connected to the second gate electrode.

3. The circuit structure of claim 1, wherein the second drain electrode is connected to a bias line.

4. A weight synapse structure, comprising: a first circuit structure comprising the circuit structure of any one of claims 1-3 in combination between a first word line and a first bit line; and a second circuit structure comprising the circuit structure of any one of claims 1-3 in combination between a second word line and a second bit line, wherein the first circuit structure is electrically connected to the second circuit structure to define a single synapse.

5. The weight synapse structure of claim 4, wherein a voltage pulse is applied to the first word line and a bias voltage is applied to the first bit line to train the single synapse.

6. The weight synapse structure of claim 5, wherein the voltage pulse gradually changes a threshold voltage of the first FeFET of the first circuit structure.

7. The weight synapse structure of claim 6, wherein the bias voltage modulates a channel conductivity of the single synapse.

8. The weight synapse structure of claim 4, wherein a word line reset voltage is applied to the first word line to reset the single synapse.

9. The weight synapse structure of claim 4, wherein a bit line reset voltage is applied to the first bit line to reset the single synapse.

10. The weight synapse structure of claim 4, wherein a bit line read voltage is applied to the first bit line to read the single synapse.

11. A method, comprising: constructing a first ferroelectric field effect transistor (FeFET) comprising a first gate electrode, a first source electrode, and a first drain electrode; constructing a second FeFET comprising a second gate electrode, a second source electrode, and a second drain electrode, the first FeFET and the second FeFET combined to form a first circuit structure; connecting the first gate electrode to a first word line; and connecting the first source electrode and the second source electrode to a same first bit line.

12. The method of claim 11, further comprising connecting the first drain electrode to the second gate electrode.

13. The method of claim 12, further comprising connecting the second drain electrode to a first bias line.

14. The method of claim 13, further comprising: constructing a third FeFET comprising a third gate electrode, a third source electrode, and a third drain electrode; ​ constructing a fourth FeFET including a fourth gate electrode, a fourth source electrode, and a fourth drain electrode, the third FeFET and the fourth FeFET combined to form a second circuit structure; connecting the third gate electrode to a second word line; and connecting the third source electrode and the second source electrode to a second bit line.

15. The method of claim 14, further comprising connecting the third drain electrode to the fourth gate electrode.

16. The method of claim 15, further comprising connecting the fourth drain electrode to a second bias line.

17. The method of claim 16, further comprising electrically connecting the first circuit structure to the second circuit structure for differential reading of channel conductance of the second FeFET and the fourth FeFET to define a single synapse.

18. The method of claim 17, further comprising applying a voltage pulse to the first word line and a bias voltage to the first bit line to train the single synapse.

19. The method of claim 18, further comprising gradually changing threshold voltages of the first FeFET of the first circuit structure and the third FeFET of the second circuit structure via the voltage pulse.

20. The method of claim 19, further comprising modulating channel conductance of the single synapse via the bias voltage.

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