Power conversion device

Abstract

In the power conversion device of the present invention, the modulation control unit (6) calculates the voltage offset based on the basic voltage command, and calculates the corrected voltage command by superimposing the voltage offset on the basic voltage command. The inverter (3) converts the DC voltage into a three-phase voltage based on the corrected voltage command calculated by the modulation control unit (6) and applies the voltage to the three-phase windings of the AC rotating motor. When the basic voltage command is converted into a three-phase voltage command, and the three-phase voltage command is set as the maximum phase, the middle phase, and the minimum phase in descending order, the modulation control unit (6) calculates the first voltage offset based on the sum of the squares of the DC voltage, the maximum phase, and the basic voltage command.

Description

Technical Field

[0001] This application relates to a power conversion device that converts DC voltage into three-phase voltage based on a three-phase voltage command and outputs it. Background Technology

[0002] Previously, voltage modulation techniques were widely known for improving the voltage utilization of PWM inverters. In addition to improving voltage utilization, modulation methods for various purposes have been proposed. For example, in Patent Document 1, when the three-phase voltage commands are set in descending order as the maximum phase, intermediate phase, and minimum phase, modulation that fixes the maximum phase and modulation that fixes the minimum phase are switched based on the difference between the maximum and minimum phases.

[0003] Hereinafter, modulation that fixes the maximum phase will be referred to as upper-level held modulation, and modulation that fixes the minimum phase will be referred to as lower-level held modulation. Upper-level held modulation aims to reduce losses caused by the voltage drop of the current sensing element mounted on the lower arm, while lower-level held modulation aims to maximize the current detection time. In upper-level held modulation, modulation is performed so that the maximum phase becomes a predetermined voltage value; similarly, lower-level held modulation is performed so that the maximum phase becomes a predetermined voltage value. In Patent Document 2, the range of two-phase modulation is reduced, and the output voltage is kept within the inverter's output range by using a voltage amplitude switching modulation method.

[0004] Existing technical documents

[0005] Patent documents

[0006] Patent Document 1: Japanese Patent No. 5161985

[0007] Patent Document 2: Japanese Patent No. 6525364 Summary of the Invention

[0008] The technical problem that the invention aims to solve

[0009] When the amplitude of the three-phase voltage command is large, the maximum phase peak value also increases, and the duty cycle also increases. If each lower arm of the inverter has a three-phase current sensing resistor, a large duty cycle shortens the energizing time of the current sensing resistor in the lower arm, thus degrading the current sensing accuracy.

[0010] In order to maximize the energization time of the lower arm used for current sensing, lower-level hold modulation is performed. However, due to the occurrence of the maximum phase peak after modulation six times within one electrical angle cycle, timing deterioration of current sensing accuracy occurs six times per cycle. It is known that when using an inverter for motor control, the motor is structurally prone to induced voltage ripples at a frequency six times the electrical angle cycle, and this torque ripple causes vibration and noise problems. If current sensing is used for current control with a deterioration of six times per cycle, there is a further problem of torque ripple at a frequency six times the electrical angle cycle.

[0011] In Patent Document 1, the lower-level hold modulation is selected at the moment when the difference between the maximum and minimum phases is large. However, the duty cycle is large at this moment, causing the aforementioned problem. Furthermore, a method is proposed to modulate the average value of the maximum and minimum phases as an overlap voltage when the difference between the maximum and minimum phases exceeds the power supply voltage. However, even with this modulation method, the peak value of the maximum phase occurs six times within one electrical angle cycle, thus causing the aforementioned problem.

[0012] Patent Document 2 illustrates an implementation where upper-layer hold modulation is selected when the amplitude of the three-phase voltage command is small, and lower-layer hold modulation is selected when the amplitude of the three-phase voltage command is large. However, in this method, the duty cycle is also large when the amplitude of the three-phase voltage command is large, thus causing the same problem as in Patent Document 1. Furthermore, other embodiments also show examples of performing only upper-layer hold modulation. However, as described above, upper-layer hold modulation, since modulation is performed to fix the maximum phase at a predetermined voltage value, if this modulation is performed when the voltage command exceeds the predetermined value, the line-to-line voltage distortion occurs because the voltage command exceeds the lower limit of the output, thereby leading to the generation of new vibrations and noise.

[0013] Furthermore, when a predetermined value is set as the output upper limit, the maximum phase is always modulated to the output upper limit even at moments when the voltage command is small. Therefore, the voltage value of the minimum phase will inevitably become large, making it difficult to detect current in all three phases at that moment, thus hindering control. Additionally, a method has been disclosed that uses upper-level hold modulation to make the maximum phase a detectable current value when the voltage command amplitude is small, and uses upper-level hold modulation to make the maximum phase the output upper limit when the voltage command amplitude is large. However, in this method, the maximum phase is discontinuous during switching, which may cause other vibrations and noise due to its discontinuity.

[0014] This application was made to solve the above-mentioned problems, and its purpose is to provide a power conversion device that calculates voltage offset by using the sum of squares of the basic voltage command, so that the current detection accuracy does not deteriorate. In addition, by using the sum of squares of the basic voltage command, the maximum phase can be fixed with a voltage value corresponding to the basic voltage command instead of a predetermined voltage value, so that it will not fall below the lower limit of the inverter output.

[0015] Technical means for solving technical problems

[0016] The power conversion device disclosed in this application includes: a basic voltage command unit that outputs a basic voltage command; a modulation control unit that calculates a voltage offset based on the basic voltage command and calculates a corrected voltage command by superimposing the voltage offset onto the basic voltage command; and an inverter that converts a DC voltage into a three-phase voltage based on the corrected voltage command calculated by the modulation control unit and applies the voltage to the three-phase windings of an AC rotating motor, and has a current detection unit that detects the current flowing through each phase of the three-phase windings by measuring the voltage drop of a current detection resistor element connected in series with a switching element. When the basic voltage command is converted into a three-phase voltage command, and the three-phase voltage commands are set in descending order as the maximum phase, intermediate phase, and minimum phase, the modulation control unit calculates a first voltage offset based on the sum of the squares of the DC voltage, the maximum phase, and the basic voltage command.

[0017] Invention Effects

[0018] According to the power conversion device of this application, the voltage offset is calculated by using the sum of squares of the basic voltage command, so that the current detection accuracy does not deteriorate.

[0019] In addition, by using the sum of squares of the basic voltage command, the maximum phase can be fixed with a voltage value corresponding to the basic voltage command instead of a predetermined voltage value, so it will not fall below the lower limit of the inverter output. Attached Figure Description

[0020] Figure 1 This is an overall structural diagram of the power conversion device involved in Embodiment 1.

[0021] Figure 2 This is a flowchart illustrating the computational processing of the modulation control unit in the power conversion device according to Embodiment 1.

[0022] Figure 3 This is a diagram showing the output waveform of the power conversion device according to Embodiment 1.

[0023] Figure 4 This is a diagram showing the output waveform of the power conversion device according to Embodiment 1.

[0024] Figure 5 This is a flowchart illustrating the computational processing of the modulation control unit in the power conversion device according to Embodiment 2.

[0025] Figure 6 This is a diagram showing the output waveform of the power conversion device according to Embodiment 2.

[0026] Figure 7 This is a flowchart illustrating the computational processing of the modulation control unit in the power conversion device according to Embodiment 3.

[0027] Figure 8 This is a flowchart illustrating the computational processing of the modulation control unit in the power conversion device according to Embodiment 4.

[0028] Figure 9 This is a diagram showing the output waveform of the power conversion device according to Embodiment 4.

[0029] Figure 10 This is a diagram showing the output waveform of the power conversion device according to Embodiment 4.

[0030] Figure 11 This is a flowchart illustrating the computational processing of the modulation control unit in the power conversion device according to Embodiment 5.

[0031] Figure 12 This is a diagram showing the output waveform of the power conversion device according to Embodiment 5.

[0032] Figure 13 This is a flowchart illustrating the computational processing of the modulation control unit in the power conversion device according to Embodiment 6.

[0033] Figure 14 This is a diagram showing the output waveform of the power conversion device according to Embodiment 6.

[0034] Figure 15 This is a flowchart illustrating the computational processing of the modulation control unit in the power conversion device according to Embodiment 7.

[0035] Figure 16 This is a diagram showing the output waveform of the power conversion device according to Embodiment 7.

[0036] Figure 17 This is a flowchart illustrating other computational processes of the modulation control unit in the power conversion device according to Embodiment 7.

[0037] Figure 18 This is a diagram showing other output waveforms of the power conversion device according to Embodiment 7.

[0038] Figure 19 This is a diagram illustrating an example of the hardware structure of the modulation control unit in the power conversion control device according to the embodiment. Detailed Implementation

[0039] Implementation method 1.

[0040] Figure 1 This is an overall structural diagram showing the power conversion device according to Embodiment 1. Figure 1 In this context, the AC rotating motor 1 is an AC rotating motor with three-phase windings U, V, and W, such as a permanent magnet synchronous rotating motor, a winding-excited synchronous rotating motor, an induction rotating motor, a synchronous reluctance motor, etc.

[0041] DC power supply 2 applies a DC voltage Vdc to inverter 3. Inverter 3, based on the three-phase corrected voltage commands Vu, Vv, Vw and the DC voltage Vdc, performs PWM modulation with a carrier period Tc to apply voltages to the three-phase windings U, V, W of the AC rotating motor. The switches (switching elements) Sup, Svp, Swp, Sun, Svn, and Swn are devices obtained by connecting semiconductor switching elements such as IGBTs, bipolar transistors, and MOS power transistors in reverse parallel with diodes.

[0042] Resistive elements Ru, Rv, and Rw for current sensing are connected in series with the lower arm elements (switching elements) Sun, Svn, and Swn of inverter 3, respectively. Resistive element Ru acquires its voltage at the timing when the lower arm element Sun is turned on, thereby detecting the current flowing through the U-phase winding of the AC rotating motor 1. Resistive element Rv acquires its voltage at the timing when the lower arm element Svn is turned on, thereby detecting the current flowing through the V-phase winding of the AC rotating motor 1. Resistive element Rw acquires its voltage at the timing when the lower arm element Swn is turned on, thereby detecting the current flowing through the W-phase winding of the AC rotating motor 1. Filter capacitor 4 is a capacitor that stabilizes the DC voltage Vdc of the DC power supply 2. Additionally, the basic voltage command unit 5 issues three-phase basic voltage commands Vub, Vvb, and Vwb for driving the AC rotating motor 1.

[0043] The modulation control unit 6 calculates the first voltage offset Voffset1 based on the three-phase basic voltage commands Vub, Vvb, and Vwb, and superimposes it on the three-phase basic voltage commands Vub, Vvb, and Vwb.

[0044] Figure 2 This is a flowchart illustrating the computational processing of the modulation control unit 6. Figure 2In step S101, the maximum phase Vmax is calculated when the three-phase basic voltage commands Vub, Vvb, and Vwb are set in descending order as the maximum phase, intermediate phase, and minimum phase. In step S102, the sum of the squares of the three-phase basic voltage commands Vub, Vvb, and Vwb is multiplied by 2, and the positive square root of the result is calculated to obtain the peak voltage Vpeak. In step S103, the peak voltage Vpeak calculated in step S102 is subtracted from the maximum phase Vmax calculated in step S101, and the value obtained by multiplying the DC voltage Vdc by 0.5 is subtracted to calculate the first voltage offset Voffset1. In step S104, the first voltage offset Voffset1 is subtracted from the three-phase basic voltage commands Vub, Vvb, and Vwb respectively to calculate the three-phase corrected voltage commands Vu, Vv, and Vw. The peak voltage Vpeak is represented by equation (1), and the first voltage offset Voffset1 is represented by equation (2).

[0045] [Mathematical Expression 1]

[0046]

[0047] [Mathematical Expression 2]

[0048] V offset1 =V max -V pcak -0.5V dc …(2)

[0049] Figure 3 This is an explanatory diagram showing the output waveforms of the power conversion device when the modulation rates of the three-phase basic voltage commands Vub, Vvb, and Vwb according to Embodiment 1 exceed the modulation rate of the current detection upper limit voltage value. Figure 4 This is an explanatory diagram showing the output waveforms of the power conversion device when the modulation rates of the three-phase basic voltage commands Vub, Vvb, and Vwb do not exceed the modulation rate of the current detection upper limit voltage value.

[0050] exist Figure 3 , Figure 4 In the middle, from top to bottom, level 1 represents the three-phase basic voltage commands Vub, Vvb, and Vwb; level 2 represents the value obtained by subtracting the DC voltage Vdc and 0.5 from the peak voltage Vpeak; level 3 represents the first voltage offset Voffset1; and level 4 represents the three-phase corrected voltage commands Vu, Vv, and Vw.

[0051] Here, the inverter's upper output limit IOup is Vdc / 2, and the lower output limit IOlo is -Vdc / 2. The upper limit of current detection is determined by the lower limit of the energizing time of the lower arm switching elements Sun, Svn, and Swn required for current detection at the current detection resistors Ru, Rv, and Rw. For example, if the lower limit of the energizing time of the lower arm switching elements Sun, Svn, and Swn required for current detection is 5μs, and the carrier period Tc is 50μs, then the ratio of the lower limit of 5μs to the carrier period is 10%.

[0052] Therefore, in current sensing, the minimum duty cycle of the lower conduction side needs to be 10%, meaning the duty cycle of the upper conduction side needs to be below 90%. If Vdc is 12V, then the upper limit of the output is 6V. 10% of 12V is 1.2V. Therefore, the current sensing condition is a voltage at least 1.2V lower than the upper limit of 6V, i.e., below 4.8V. This means that the upper limit voltage value of current sensing, UBi, is 4.8V.

[0053] from Figure 3 , Figure 4 It can be seen that the maximum phase value of the three-phase corrected voltage commands Vu, Vv, and Vw is always fixed by subtracting the DC voltage Vdc and 0.5 from the peak voltage Vpeak.

[0054] In the aforementioned problem, the detection accuracy of the current detection resistors Ru, Rv, and Rw deteriorates due to the value of the maximum phase varying at a frequency six times that of one electrical angle cycle, which in turn causes vibration and noise at that frequency. However, according to the modulation method of this embodiment, the maximum phase is always fixed, thus achieving the effect of reducing vibration and noise at a frequency six times that of the electrical angle.

[0055] In addition, in the method for calculating the peak voltage, it is also possible to use known coordinate transformation methods to convert the three-phase basic voltage commands Vub, Vvb, and Vwb into the αβ-phase basic voltage commands Vα and Vβ in the αβ-axis coordinate system, or into the dq-phase basic voltage commands Vd and Vq in the dq-axis coordinate system, for calculation. Equations (3) and (4) show the calculation formulas for the peak voltage Vpeak when the three-phase basic voltage commands Vub, Vvb, and Vwb are converted into the αβ-phase basic voltage commands Vα and Vβ, or into the dq-phase basic voltage commands Vd and Vq, through absolute transformation.

[0056] [Mathematical Expression 3]

[0057]

[0058] [Mathematical Expression 4]

[0059]

[0060] Next, the effect on Patent Document 1 will be explained. Patent Document 1 discloses an example of modulation in which, when the difference between the maximum and minimum phases is less than the upper limit voltage value for current detection, the maximum phase is fixed at a predetermined value (the upper limit voltage value for current detection), and when the difference between the maximum and minimum phases is greater than the upper limit voltage value for current detection, the minimum phase is fixed at a predetermined value (the lower limit value for inverter output). In this example, when the difference between the maximum and minimum phases is greater than the upper limit voltage value UPi for current detection, if the minimum phase is modulated to a predetermined fixed value, the maximum phase has 6 peak values ​​in one electrical angle cycle.

[0061] At this moment, the conduction time of the lower arm switching element becomes minimal at the instant the maximum phase reaches its peak, and the current detection accuracy is at its worst at this instant. When using the current detected at this moment for current feedback control, the moment when the detection accuracy is worst occurs six times within one electrical angle cycle. Therefore, the controllability of the current decreases at this instant, resulting in current oscillations at a frequency six times the electrical angle. Since torque ripples at six times the electrical angle frequency are already generated due to motor control and other factors, the current oscillations at six times the electrical angle frequency caused by the deterioration in current detection accuracy further worsen the torque ripples, making vibration or noise problems significant.

[0062] In this embodiment, as described above, since the maximum phase is fixed at a value obtained by subtracting the DC voltage Vdc from the peak voltage Vpeak and multiplying it by 0.5, the vibration of the current at six times the electrical angle frequency caused by the current detection accuracy can be reduced. Patent Document 1 also proposes a method for modulating the average value of the maximum and minimum phases as an overlap voltage when the difference between the maximum and minimum phases exceeds the power supply voltage. However, in this modulation method, since the peak value of the maximum phase also occurs six times in one electrical angle cycle, this method cannot solve the problem even when the difference between the maximum and minimum phases does not exceed the power supply voltage.

[0063] Furthermore, by using only the upper-layer hold modulation described in Patent Document 1, it is possible to avoid the maximum phase peak occurring 6 times within one electrical angle cycle. However, since modulation is performed in a manner that fixes the maximum phase at a predetermined value, if the modulation rate of the three-phase basic voltage command is greater than the predetermined value, the minimum phase of the three-phase corrected voltage command will fall below the inverter output lower limit. If it falls below the output lower limit, other problems such as line-to-line voltage distortion, vibration, or increased noise will occur. In this viewpoint, the modulation method in this embodiment is as follows: Figure 3As shown, modulation is performed based on the calculated peak voltage Vpeak, so that the maximum phase is fixed by the value obtained by subtracting the DC voltage Vdc from the peak voltage Vpeak and multiplying it by 0.5, thus achieving the desired effect. Figure 3 In this way, fixing the maximum phase at a value exceeding the current sensing upper limit voltage value URi can prevent the minimum phase from falling below the inverter lower limit.

[0064] Furthermore, regarding the upper-level hold modulation described in Patent Document 1, if a predetermined value is used as the upper limit of the inverter output, the minimum phase of the three-phase corrected voltage command will not be lower than the lower limit of the inverter output.

[0065] However, when the amplitude of the three-phase basic voltage command is small, since the maximum phase is modulated to the upper limit of the inverter output, the minimum phase will inevitably also become close to the upper limit of the inverter output. This shortens the conduction time of the lower arm switching elements of all three phases, and drastically degrades the current detection accuracy of all three phases. In this viewpoint, the modulation method in this embodiment is as follows: Figure 4 As shown, modulation is performed based on the calculated peak voltage Vpeak, so that the maximum phase becomes the value obtained by subtracting the DC voltage Vdc and 0.5 from the peak voltage Vpeak. Therefore, the maximum phase is not fixed with a large value in vain, and the deterioration of the current detection accuracy of all three phases can be avoided.

[0066] Patent Document 2 also shows an example using only upper-layer hold modulation, but it is the same as Patent Document 1 in that the value for fixing the maximum phase needs to be predetermined, and the comparison with this embodiment is also the same. In addition, in other embodiments of Patent Document 2, an example is shown in which the maximum phase is fixed with a current-sensing upper limit voltage value when the amplitude of the three-phase basic voltage command is less than a threshold, and the maximum phase is fixed with an inverter output upper limit value when the amplitude of the three-phase basic voltage command is greater than the threshold.

[0067] In this example, if, for instance, the amplitude of the three-phase basic voltage command is less than a threshold at one instant, and then becomes greater than the threshold at the next instant, the maximum phase value of the three-phase corrected voltage command jumps from the current detection upper limit to the inverter output upper limit. Conversely, if the opposite is true, the maximum phase value of the phase corrected voltage command jumps from the inverter output upper limit to the current detection upper limit. That is, in this example, sometimes the voltage offset is discontinuous, which can lead to increased vibration and noise. In contrast, in the method of this embodiment, the voltage offset is not discontinuous.

[0068] As described above, according to Embodiment 1, when the modulation control unit sets the three-phase basic voltage command in descending order as the maximum phase, intermediate phase, and minimum phase, it calculates the first voltage offset based on the sum of the squares of the DC voltage, the maximum phase, and the three-phase basic voltage command. By subtracting the first voltage offset from the three-phase basic voltage command and outputting the three-phase correction voltage command, the voltage offset will not be lower than the lower limit of the inverter's output when the amplitude of the three-phase basic voltage command is large, and the current detection accuracy of the three phases will not deteriorate even when the amplitude of the three-phase basic voltage command is small, and the offset voltage will not be discontinuous.

[0069] Based on this, by avoiding the peak value of the maximum phase occurring 6 times in 1 electrical angle cycle, it is possible to prevent the vibration of the current at 6 times the frequency of 1 electrical angle cycle caused by the timing of the current detection occurring 6 times in 1 electrical angle cycle due to the deterioration of the current detection accuracy.

[0070] Implementation method 2.

[0071] In Implementation 1, the first voltage offset is modulated such that the maximum phase is fixed by the product of the peak voltage Vpeak and the DC voltage Vdc, plus 0.5. At this time, as... Figure 4 As shown, if the amplitudes of the three-phase basic voltage commands Vub, Vvb, and Vwb are small, the three-phase corrected voltage commands Vu, Vv, and Vw will be closer to the inverter output lower limit IOlo side. This increases current detection accuracy, but also prolongs the energizing time of the lower arm and increases heat generation in the lower arm. In cases where heat generation or other problems arise due to proximity to the inverter output lower limit IOlo side, modulation can be performed as shown below, causing the value of the maximum phase (obtained by subtracting the DC voltage Vdc and 0.5 from the peak voltage Vpeak) to begin shifting.

[0072] Descriptions of parts that are repeated in Implementation Method 1 are omitted. Figure 5 This is a flowchart illustrating the computational processing of the modulation control unit 6 in Embodiment 2. Figure 5 In step S201, the maximum phase Vmax is calculated when the three-phase basic voltage commands Vub, Vvb, and Vwb are set in descending order as the maximum phase, intermediate phase, and minimum phase.

[0073] In step S202, the sum of the squares of the three-phase basic voltage commands Vub, Vvb, and Vwb is multiplied by 2, and the positive square root of the resulting value is calculated to obtain the peak voltage Vpeak. Furthermore, as described in Embodiment 1, the peak voltage calculation method can also be performed by converting the three-phase basic voltage commands Vub, Vvb, and Vwb into the αβ-phase basic voltage commands Vα and Vβ in the αβ-axis coordinate system using a known coordinate transformation method, or by converting them into the dq-phase basic voltage commands Vd and Vq in the dq-axis coordinate system using the same known coordinate transformation method.

[0074] In step S203, the second voltage offset Voffset2 is calculated by subtracting the peak voltage Vpeak calculated in step S202 multiplied by 0.5 from the maximum phase Vmax calculated in step S201, and then subtracting the value obtained by multiplying the value obtained by subtracting 0.5 from the first constant k1 and the DC voltage Vdc.

[0075] In step S204, the three-phase corrected voltage commands Vu, Vv, and Vw are calculated by subtracting the second voltage offset Voffset2 from the three-phase basic voltage commands Vub, Vvb, and Vwb, respectively. The second voltage offset Voffset2 is represented by equation (5).

[0076] [Mathematical Expression 5]

[0077] V offset2 =V max -0.5V peak -(k1-0.5)V dc …(5)

[0078] Here, the first constant k1 is the number used to determine the center values ​​of the three-phase corrected voltage commands Vu, Vv, and Vw. For example, when the inverter's output range is -6V to 6V, the center values ​​of the three-phase corrected voltage commands Vu, Vv, and Vw are set to the center value of the inverter's output range, i.e., 0V, and k1 is set to 0.5. In this embodiment, by setting k1 to 0.5, if the modulation rate of the three-phase basic voltage command is less than 1, the three-phase corrected voltage command will not exceed the upper and lower limits of the output.

[0079] Figure 6 This represents the output waveforms of the power conversion device in Embodiment 2 when k1 = 0.5. Using this modulation method, the center value of the three-phase corrected voltage commands Vu, Vv, and Vw is (k1 - 0.5) * Vdc. Figure 6In the middle, from top to bottom, level 1 represents the three-phase basic voltage commands Vub, Vvb, and Vwb; level 2 represents the value obtained by subtracting the DC voltage Vdc and 0.5 from the peak voltage Vpeak; level 3 represents the second voltage offset Voffset2; and level 4 represents the three-phase corrected voltage commands Vu, Vv, and Vw.

[0080] according to Figure 6 By shifting the three-phase correction voltage commands Vu, Vv, and Vw from the state of Implementation Method 1 to the inverter output upper limit value IOup side, the energizing time of the lower arm is shortened, and heat generation is reduced. Furthermore, by avoiding the occurrence of the maximum phase peak value six times within the electrical angle 1 cycle, it is possible to prevent the current from oscillating at a frequency six times the electrical angle 1 cycle due to deterioration in current detection accuracy.

[0081] Implementation method 3.

[0082] In Implementation 1, the first voltage offset is modulated such that the maximum phase is fixed by the value obtained by subtracting the DC voltage Vdc and 0.5 from the peak voltage Vpeak. At this time, as... Figure 4 As shown, if the amplitude of the three-phase basic voltage command is small, the three-phase corrected voltage command will be closer to the lower limit of the inverter output. This increases current detection accuracy, but also prolongs the energizing time of the lower arm and increases heat generation in the lower arm. In cases where heat generation or other problems arise due to proximity to the lower limit of the inverter output, control can be implemented as follows to ensure that the first voltage offset is zero when the modulation rate of the three-phase basic voltage command is below the modulation rate threshold.

[0083] Descriptions of parts that are repeated in Implementation Method 1 are omitted. Figure 7 This is a flowchart illustrating the computational processing of the modulation control unit 6 in Embodiment 3. Figure 7 In step S301, the sum of the squares of the three-phase basic voltage commands Vub, Vvb, and Vwb is multiplied by 2, and the positive square root of the resulting value is calculated to obtain the peak voltage Vpeak. Furthermore, as described in Embodiment 1, the peak voltage calculation method can also be performed by converting the three-phase basic voltage commands Vub, Vvb, and Vwb into the αβ-phase basic voltage commands Vα and Vβ in the αβ-axis coordinate system using a known coordinate transformation method, or by converting them into the dq-phase basic voltage commands Vd and Vq in the dq-axis coordinate system using the same known coordinate transformation method.

[0084] In step S302, the peak voltage Vpeak obtained in step S301 is divided by the DC voltage Vdc to calculate the modulation rate M.

[0085] In step S303, it is determined whether the modulation rate M calculated in step S302 is greater than the modulation rate threshold Mth. Here, Mth is set to a value that prevents the voltage value of the largest phase of the three-phase basic voltage command from exceeding the current detection upper limit. For example, if the current detection upper limit is a duty cycle of 90%, then the current detection upper limit voltage value UBi is (0.9-0.5)*Vdc=0.4Vdc, so Mth is set to a value below 0.4√3.

[0086] If it is determined in step S303 that the modulation rate M is a value above the modulation rate threshold Mth, then proceed to step S304. In step S304, the maximum phase Vmax is calculated when the three-phase basic voltage commands Vub, Vvb, and Vwb are set in descending order as the maximum phase, intermediate phase, and minimum phase.

[0087] In step S305, the peak voltage Vpeak calculated in step S301 is subtracted from the maximum phase Vmax calculated in step S304, and then the value obtained by multiplying the DC voltage Vdc by 0.5 is subtracted from its value to calculate the first voltage offset Voffset1.

[0088] If it is determined in step S303 that the modulation rate M is less than the modulation rate threshold Mth, then proceed to step S306. In step S306, the first voltage offset Voffset1 is set to 0.

[0089] In step S307, the three-phase corrected voltage commands Vu, Vv, and Vw are calculated by subtracting the first voltage offset Voffset1 calculated in step S305 or step S306 from the three-phase basic voltage commands Vub, Vvb, and Vwb, respectively. The modulation rate M is represented by equation (6).

[0090] [Mathematical Expression 6]

[0091]

[0092] According to Embodiment 3, when the modulation rate M is less than the modulation rate threshold Mth, although no new illustration is provided, the three-phase corrected voltage commands Vu, Vv, and Vw are consistent with the three-phase basic voltage commands Vub, Vvb, and Vwb, and the average energizing time of the lower arm of each phase is equal to the average energizing time of the upper arm. Furthermore, when the modulation rate M is greater than or equal to the modulation rate threshold Mth, by avoiding the occurrence of the maximum phase peak value six times within one electrical angle cycle, it is possible to prevent the current from oscillating at a frequency six times within one electrical angle cycle due to the deterioration of current detection accuracy.

[0093] Implementation method 4.

[0094] In Implementation 3, modulation is performed when the modulation rate of the three-phase basic voltage command is lower than the modulation rate threshold, so that the voltage offset is 0. However, in this case, modulation can also be performed so that the value obtained by subtracting the DC voltage Vdc and 0.5 from the peak voltage Vpeak begins to shift.

[0095] Descriptions of parts that are repeated in Implementation Method 3 are omitted. Figure 8 This is a flowchart illustrating the computational processing of the modulation control unit 6 in Embodiment 4. Figure 8 In step S401, the sum of the squares of the three-phase basic voltage commands Vub, Vvb, and Vwb is multiplied by 2, and the positive square root of the resulting value is calculated to obtain the peak voltage Vpeak. Furthermore, as described in Embodiment 1, the peak voltage calculation method can also be performed by converting the three-phase basic voltage commands Vub, Vvb, and Vwb into the αβ-phase basic voltage commands Vα and Vβ in the αβ-axis coordinate system using a known coordinate transformation method, or by converting them into the dq-phase basic voltage commands Vd and Vq in the dq-axis coordinate system using the same known coordinate transformation method.

[0096] In step S402, the peak voltage Vpeak obtained in step S401 is divided by the DC voltage Vdc to calculate the modulation rate M.

[0097] In step S403, the maximum phase Vmax is calculated when the three-phase basic voltage commands Vub, Vvb, and Vwb are set in descending order as the maximum phase, intermediate phase, and minimum phase.

[0098] In step S404, it is determined whether the modulation rate M calculated in step S402 is greater than the modulation rate threshold Mth. Here, Mth is set to be below the modulation rate of the voltage value at the upper limit of current detection. For example, when the upper limit of current detection is 90% duty cycle, Mth is set to a value of 0.9 or less.

[0099] If it is determined in step S404 that the modulation rate M is a value above the modulation rate threshold Mth, then proceed to step S405.

[0100] In step S405, the first voltage offset Voffset1 is calculated by subtracting the peak voltage Vpeak calculated in step S401 from the maximum phase Vmax calculated in step S403, and then subtracting the value obtained by multiplying the DC voltage Vdc by 0.5 from its value.

[0101] In step S406, the three-phase corrected voltage commands Vu, Vv, and Vw are calculated by subtracting the first voltage offset Voffset1 calculated in step S405 from the three-phase basic voltage commands Vub, Vvb, and Vwb, respectively.

[0102] If it is determined in step S404 that the modulation rate M is less than the modulation rate threshold Mth, then proceed to step S407.

[0103] In step S407, the second voltage offset Voffset2 is calculated by subtracting the peak voltage Vpeak calculated in step S401 multiplied by 0.5 from the maximum phase Vmax calculated in step S403, and then subtracting the value obtained by multiplying the value obtained by subtracting 0.5 from the first constant k1 and the DC voltage Vdc.

[0104] In step S408, the three-phase corrected voltage commands Vu, Vv, and Vw are calculated by subtracting the second voltage offset Voffset2 calculated in step S407 from the three-phase basic voltage commands Vub, Vvb, and Vwb, respectively. The second voltage offset Voffset2 is represented by equation (5).

[0105] Here, the first constant k1 is the number that determines the center values ​​of the three-phase corrected voltage commands Vu, Vv, and Vw. In this embodiment, by setting k1 to a value that is 0.5 times the modulation rate threshold Mth, if the modulation rate M of the three-phase basic voltage command is close to the modulation rate threshold Mth, the largest phase of the three-phase corrected voltage command based on the second voltage offset Voffset2 becomes the voltage value equivalent to the modulation rate threshold Mth, and the voltage offset is continuous even when switching to Voffset1.

[0106] Figure 9 , Figure 10 This example shows how to set the modulation rate threshold Mth to 0.9 and k1 to 0.5 times the modulation rate threshold Mth, i.e., 0.45. Figure 9 In this configuration, the modulation rate M is above the modulation rate threshold Mth, the minimum values ​​of the three-phase correction voltage commands Vu, Vv, and Vw are the lower limit of the inverter, and the maximum value of the phase is fixed at Vpeak-0.5Vdc. Figure 10 In this context, the modulation rate M is a value less than the modulation rate threshold Mth, and the central value of the three-phase corrected voltage commands Vu, Vv, and Vw is (k1-0.5)Vdc.

[0107] According to this embodiment, by avoiding the occurrence of the maximum phase peak value 6 times in the electrical angle 1 cycle, it is possible to prevent the vibration of the current at 6 times the frequency of the electrical angle 1 cycle caused by the timing of the current detection occurring 6 times in the electrical angle 1 cycle due to the deterioration of the current detection accuracy.

[0108] Implementation method 5.

[0109] Hereinafter, Embodiment 5 will be described, but the parts that are repeated in Embodiment 1 will be omitted. Figure 11 This is a flowchart illustrating the operation of the modulation control unit 6 in embodiment 5.

[0110] exist Figure 11 In step S501, the maximum phase Vmax is calculated when the three-phase basic voltage commands Vub, Vvb, and Vwb are set in descending order as the maximum phase, intermediate phase, and minimum phase.

[0111] In step S502, the minimum phase Vmin is calculated. In step S503, the intermediate phase Vmid is calculated based on the maximum phase Vmax and the minimum phase Vmin. In step S504, it is determined whether the intermediate phase Vmid calculated in step S503 is below the intermediate phase threshold Vmidth. Here, the intermediate phase threshold Vmidth is 0.

[0112] If it is determined in step S504 that the intermediate phase Vmid is a value below the intermediate phase threshold Vmidth, then proceed to step S505.

[0113] In step S505, the sum of the squares of the three-phase basic voltage commands Vub, Vvb, and Vwb is multiplied by 2, and the positive square root of the resulting value is calculated to obtain the peak voltage Vpeak. Furthermore, as described in Embodiment 1, the peak voltage calculation method can also be performed by converting the three-phase basic voltage commands Vub, Vvb, and Vwb into the αβ-phase basic voltage commands Vα and Vβ in the αβ-axis coordinate system using a known coordinate transformation method, or by converting them into the dq-phase basic voltage commands Vd and Vq in the dq-axis coordinate system using the same known coordinate transformation method.

[0114] In step S506, the first voltage offset Voffset1 is calculated by subtracting the peak voltage Vpeak calculated in step S505 from the maximum phase Vmax calculated in step S501, and then subtracting the value obtained by multiplying the DC voltage Vdc by 0.5 from its value.

[0115] In step S507, the three-phase corrected voltage commands Vu, Vv, and Vw are calculated by subtracting the first voltage offset Voffset1 calculated in step S506 from the three-phase basic voltage commands Vub, Vvb, and Vwb, respectively.

[0116] If it is determined in step S504 that the intermediate phase Vmid is greater than the intermediate phase threshold Vmidth, then proceed to step S508.

[0117] In step S508, the minimum phase Vmin calculated in step S502 is multiplied by the DC voltage Vdc by the value obtained by subtracting the second constant k2 from 0.5, to calculate the third voltage offset Voffset3.

[0118] In step S509, the three-phase corrected voltage commands Vu, Vv, and Vw are calculated by subtracting Voffset3 calculated in step S508 from the three-phase basic voltage commands Vub, Vvb, and Vwb.

[0119] The third voltage offset Voffset3 is represented by equation (7).

[0120] [Mathematical Expression 7]

[0121] V offset3 =V min +(0.5-k2)V dc …(7)

[0122] Here, the second constant k2 is the number that determines the value of the minimum phase of the three-phase correction voltage commands Vu, Vv, and Vw. When the minimum phase is fixed by the lower limit of the inverter output, the second constant k2 is set to 0. To avoid two-phase modulation, if the second constant k2 is set to the minimum pulse duty cycle of the PWM, for example, a carrier period of 50μs and a minimum pulse width of 0.5μs for the inverter, then k2 is set to 0.5 / 50 = 0.01.

[0123] Figure 12 This represents an example where the second constant k2 = 0. In Figure 12 In the middle phase, where the intermediate phase value is greater than the intermediate phase threshold Vmidth, the minimum phase becomes a fixed value; where the intermediate phase value is less than the intermediate phase threshold Vmidth, the maximum phase becomes a fixed value. For example... Figure 12 As shown, it can avoid the peak value of the maximum phase of the three-phase correction voltage command occurring 6 times in the electrical angle 1 cycle, and prevent the current from oscillating at 6 times the frequency of the electrical angle 1 cycle due to the deterioration of the current detection accuracy.

[0124] Implementation method 6.

[0125] The following describes Implementation 6, but details that overlap with Implementation 5 are omitted. If the modulation rate of the three-phase basic voltage command is close to 1, the maximum phase is close to the upper limit of the inverter output, and the duty cycle is close to 100%. In current detection, if current detection is performed at the moment when the carrier reaches its maximum value, current detection cannot be performed because the duty cycle of the maximum phase is around 100%, and the other two phases are detected instead.

[0126] If the duty cycle of the maximum phase is not 100%, switching will occur even in the maximum phase. In this case, since the switching timing of the maximum phase is near the moment when the carrier reaches its maximum value, the switching noise of the maximum phase may adversely affect the current detection of other phases. To avoid the adverse effects of this switching noise, when the modulation rate of the three-phase basic voltage command is near 1, the duty cycle of the maximum phase is fixed at the upper limit of the inverter output, thus preventing switching. Figure 13 This is a flowchart illustrating the computational processing of the modulation control unit 6 in embodiment 6.

[0127] exist Figure 13 In step S601, the sum of the squares of the three-phase basic voltage commands Vub, Vvb, and Vwb is multiplied by 2, and the positive square root of the resulting value is calculated to obtain the peak voltage Vpeak. Furthermore, as described in Embodiment 1, the peak voltage calculation method can also be performed by converting the three-phase basic voltage commands Vub, Vvb, and Vwb into the αβ-phase basic voltage commands Vα and Vβ in the αβ-axis coordinate system using a known coordinate transformation method, or by converting them into the dq-phase basic voltage commands Vd and Vq in the dq-axis coordinate system using the same known coordinate transformation method.

[0128] In step S602, the peak voltage Vpeak is divided by the DC voltage Vdc to calculate the modulation rate M.

[0129] In step S603, the maximum phase Vmax is calculated when the three-phase basic voltage commands Vub, Vvb, and Vwb are set in descending order as the maximum phase, intermediate phase, and minimum phase.

[0130] In step S604, it is determined whether the modulation rate M is below the modulation rate threshold Mth. The modulation rate threshold Mth is a value that is above the modulation rate of the current detection upper limit and below the modulation rate that the inverter can output.

[0131] If it is determined in step S604 that the modulation rate M is below the modulation rate threshold Mth, then proceed to step S605.

[0132] In step S605, the minimum phase Vmin is calculated. In step S606, the intermediate phase Vmid is calculated based on the maximum phase Vmax and the minimum phase Vmin. In step S607, it is determined whether the intermediate phase Vmid is below the intermediate phase threshold Vmidth. Here, the intermediate phase threshold Vmidth is 0.

[0133] If it is determined in step S607 that the intermediate phase Vmid is a value below the intermediate phase threshold Vmidth, then proceed to step S608.

[0134] In step S608, the peak voltage Vpeak is subtracted from the maximum phase Vmax, and the DC voltage Vdc multiplied by 0.5 is subtracted from this value to calculate the first voltage offset Voffset1.

[0135] In step S609, the three-phase corrected voltage commands Vu, Vv, and Vw are calculated by subtracting the first voltage offset Voffset1 calculated in step S608 from the three-phase basic voltage commands Vub, Vvb, and Vwb, respectively.

[0136] If it is determined in step S607 that the intermediate phase Vmid is greater than the intermediate phase threshold Vmidth, then proceed to step S610.

[0137] In step S610, the third voltage offset Voffset3 is calculated by adding the value obtained by subtracting the second constant k2 from 0.5 and multiplying it with the DC voltage Vdc in the minimum phase Vmin.

[0138] In step S611, the three-phase corrected voltage commands Vu, Vv, and Vw are calculated by subtracting the third voltage offset Voffset3 calculated in step S610 from the three-phase basic voltage commands Vub, Vvb, and Vwb, respectively.

[0139] If it is determined in step S604 that the modulation rate M is greater than the modulation rate threshold Mth, then proceed to step S612.

[0140] In step S612, the fourth voltage offset Voffset4 is calculated by subtracting the value obtained by subtracting 0.5 from the third constant k3 from the maximum phase Vmax and multiplying it with the DC voltage Vdc.

[0141] In step S613, the three-phase corrected voltage commands Vu, Vv, and Vw are calculated by subtracting the fourth voltage offset Voffset4 calculated in step S612 from the three-phase basic voltage commands Vub, Vvb, and Vwb.

[0142] The fourth voltage offset Voffset4 is represented by equation (8).

[0143] [Mathematical Expression 8]

[0144] V offset4 =V max -(k3-0.5)V dc …(8)

[0145] Here, k3 is a number that determines the value of the maximum phase of the three-phase correction voltage commands Vu, Vv, and Vw. When the maximum phase is fixed by the upper limit of the inverter output, k3 is set to 1. Figure 14 This represents an example where the modulation rate threshold Mth is set to 0.95. Figure 14 In this embodiment, when the modulation rate is greater than the modulation rate threshold, the maximum phase is fixed by the upper limit of the inverter output. Furthermore, although there is no new illustration, when the modulation rate is below the modulation rate threshold, the process is the same as in embodiment 6.

[0146] Implementation method 7.

[0147] Hereinafter, Embodiment 7 will be described, but the parts that are repeated in Embodiment 1 will be omitted. Figure 15 This is a flowchart illustrating the computational processing of the modulation control unit 6 in Embodiment 7.

[0148] In step S701, the maximum phase Vmax is calculated when the three-phase basic voltage commands Vub, Vvb, and Vwb are set in descending order as the maximum phase, intermediate phase, and minimum phase. In step S702, the minimum phase Vmin is calculated. In step S703, it is determined whether the difference between the maximum phase Vmax and the minimum phase Vmin is above the voltage threshold Vth.

[0149] If it is determined in step S703 that the difference between the maximum phase Vmax and the minimum phase Vmin is greater than or equal to the voltage threshold Vth, then proceed to step S704. In step S704, the intermediate phase Vmid is calculated based on the maximum phase Vmax and the minimum phase Vmin.

[0150] In step S705, it is determined whether the intermediate phase Vmid is below the intermediate phase threshold Vmidth. Here, the intermediate phase threshold Vmidth is 0.

[0151] If it is determined in step S705 that the intermediate phase Vmid is below the intermediate phase threshold Vmidth, then proceed to step S706.

[0152] In step S706, it is determined whether the modulation prior to one control cycle was modulated using the third voltage offset Voffset3 described later.

[0153] In step S706, if it is determined that the modulation before one control cycle is not modulation using the third voltage offset Voffset3, then proceed to step S707.

[0154] In step S707, the sum of the squares of the three-phase basic voltage commands Vub, Vvb, and Vwb is multiplied by 2, and the positive square root of the resulting value is calculated to obtain the peak voltage Vpeak. Furthermore, as described in Embodiment 1, the peak voltage calculation method can also be performed by converting the three-phase basic voltage commands Vub, Vvb, and Vwb into the αβ-phase basic voltage commands Vα and Vβ in the αβ-axis coordinate system using a known coordinate transformation method, or by converting them into the dq-phase basic voltage commands Vd and Vq in the dq-axis coordinate system using the same known coordinate transformation method.

[0155] In step S708, the peak voltage Vpeak is subtracted from the maximum phase Vmax, and the DC voltage Vdc multiplied by 0.5 is subtracted from this value to calculate the first voltage offset Voffset1.

[0156] In step S709, the three-phase corrected voltage commands Vu, Vv, and Vw are calculated by subtracting the first voltage offset Voffset1 calculated in step S708 from the three-phase basic voltage commands Vub, Vvb, and Vwb, respectively.

[0157] If it is determined in step S705 that the intermediate phase Vmid is greater than the intermediate phase threshold Vmidth, or in step S706 it is determined that the modulation before one control cycle was using the third voltage offset Voffset3, then proceed to step S710.

[0158] In step S710, the third voltage offset Voffset3 is calculated by adding the value obtained by subtracting the second constant k2 from 0.5 to the DC voltage Vdc in the minimum phase Vmin.

[0159] In step S711, the three-phase corrected voltage commands Vu, Vv, and Vw are calculated by subtracting the third voltage offset Voffset3 calculated in step S710 from the three-phase basic voltage commands Vub, Vvb, and Vwb, respectively.

[0160] If it is determined in step S703 that the difference between the maximum phase Vmax and the minimum phase Vmin is less than the voltage threshold Vth, then proceed to step S712.

[0161] In step S712, it is determined whether the modulation one control cycle prior was modulation using the first voltage offset Voffset1.

[0162] In step S712, if it is determined that the modulation before one control cycle was using the first voltage offset Voffset1, then proceed to step S704.

[0163] In step S712, if it is determined that the modulation before one control cycle is not the modulation using the first voltage offset Voffset1, then proceed to step S713.

[0164] In step S713, the fourth voltage offset Voffset4 is calculated by subtracting the value obtained by subtracting 0.5 from the third constant k3 from the maximum phase Vmax and multiplying it with the DC voltage Vdc.

[0165] In step S714, the three-phase corrected voltage commands Vu, Vv, and Vw are calculated by subtracting the fourth voltage offset Voffset4 calculated in step S713 from the three-phase basic voltage commands Vub, Vvb, and Vwb.

[0166] The third voltage offset Voffset3 is represented by equation (7). k2 is the number that determines the minimum phase value of the three-phase correction voltage commands Vu, Vv, and Vw. When the minimum phase is fixed by the lower limit of the inverter output, k2 is set to 0. In the case of avoiding two-phase modulation, k2 is set to the minimum pulse duty cycle of the PWM. For example, when the carrier period is 50μs and the minimum pulse width of the inverter is 0.5μs, k2 is set to 0.5 / 50 = 0.01.

[0167] The fourth voltage offset Voffset4 is represented by equation (8). k3 is the number that determines the maximum phase value of the three-phase correction voltage commands Vu, Vv, and Vw, and is set here as the modulation rate of the upper limit voltage value of the current detection. Figure 16 This shows an example of the output waveform in this embodiment.

[0168] This implementation method switches the modulation method based on the difference between the maximum and minimum phases.

[0169] The voltage threshold Vth, which determines the difference between the maximum and minimum phases, is set as the voltage value of the upper limit of current detection. In this configuration, it is set up with reference to... Figure 15 The modulation method preceding one control cycle in steps S706 and S712 is used to determine the next modulation method.

[0170] Explain the reasons for adopting this configuration.

[0171] During electrical angle 1 cycle, even with a fixed modulation rate for the three-phase basic voltage command, the difference between the maximum and minimum phases is not fixed but varies. Therefore, even if the modulation rate of the three-phase basic voltage command is fixed, the modulation method will switch as needed.

[0172] Both steps S709 and S714 involve setting the maximum phase to a fixed value, but in step S709, the maximum phase is fixed at Vpeak - 0.5Vdc, while in step S714 it is fixed at a predetermined value. Figure 17 This flowchart illustrates the process without steps S706 and S712. Figure 17 In this case, even if the modulation rate of the three-phase basic voltage command is fixed, the difference between the maximum and minimum phases is not fixed. Therefore, after modulation in step S709, there may be a moment when modulation is performed in step S714 during the determination of the next control cycle. Of course, the reverse is also true; there may be a moment when modulation is performed in step S709 during the next determination after modulation in step S714.

[0173] The output waveform in this case is Figure 18 As shown in [the image]. Figure 18 At locations θ1, θ3, and θ5, the process switches from step S709 to step S714; at locations θ2, θ4, and θ6, the process switches from step S714 to step S709. Therefore, at this instant, the maximum phase jump occurs, resulting in six maximum phase peaks within one electrical angle cycle. If six maximum phase peaks occur, the current pulsates at a frequency of six electrical angle cycles, which is associated with vibration and noise. Therefore, in this embodiment, the system is configured to introduce... Figure 15 The conditions for steps S706 and S712 do not result in a switch from step S709 to step S714, or from step S714 to step S709.

[0174] By introducing steps S706 and S712, the system switches from step S709 to step S711, and then from step S711 to step S714. The same applies to the reverse case. If the system switches from step S709 to step S711, no maximum phase jump occurs during the switch from step S714 to step S711, and the voltage offset remains continuous. According to this embodiment, it is possible to avoid the peak value of the maximum phase of the three-phase corrected voltage command occurring six times in one electrical angle cycle, and to prevent the current from oscillating at a frequency six times the electrical angle cycle due to the deterioration of current detection accuracy.

[0175] In addition, the modulation control unit 6, as Figure 19 As shown in the example hardware illustration, it comprises a processor 601 and a storage device 602. The storage device 602 includes, for example, a volatile storage device such as random access memory (RAM) and a non-volatile auxiliary storage device such as flash memory. Alternatively, an auxiliary storage device such as a hard disk can be used instead of flash memory. The processor 601 executes a program input from the storage device 602. In this case, the program is input from the auxiliary storage device to the processor 601 via the volatile storage device. Furthermore, the processor 601 can output data such as calculation results to the volatile storage device of the storage device 602, and can also save data to the auxiliary storage device via the volatile storage device.

[0176] Although this application describes various exemplary embodiments and examples, the various features, methods and functions described in one or more embodiments are not limited to the application of a particular embodiment and can be applied to the embodiment individually or in various combinations.

[0177] Therefore, it can be assumed that numerous variations not illustrated are also included within the scope of the technology disclosed in this application. For example, this includes cases where at least one constituent element is modified, added to, or omitted, and cases where at least one constituent element is extracted and combined with constituent elements of other embodiments.

[0178] Label Explanation

[0179] 3 inverters

[0180] 5. Basic Voltage Command Section

[0181] 6 Modulation Control Unit

[0182] Sup, Svp, Swp, Sun, SVn, Swn switches (switching elements)

[0183] Resistive elements for Ru, Rv, and Rw current detection.

Claims

1. A power conversion device, characterized by, comprises: a basic voltage command section that outputs a basic voltage command; a modulation control section that calculates a voltage offset based on the basic voltage command and calculates a modified voltage command by superimposing the voltage offset on the basic voltage command; and an inverter that converts a direct current voltage into a three-phase voltage based on the modified voltage command calculated by the modulation control section and applies the voltage to three-phase windings of an alternating current rotating electric machine, and has a current detection section that detects currents flowing through the respective phases of the three-phase windings by voltage drops of current detection resistive elements connected in series with switching elements, in a case where the basic voltage command is converted into a three-phase voltage command, when the three-phase voltage command is set in order from large to small as a maximum phase, an intermediate phase, and a minimum phase, a square sum of the basic voltage command is multiplied by 2, a positive square root of a value obtained after the multiplication is calculated to obtain a peak voltage, the peak voltage is subtracted from the maximum phase, and a value obtained after the subtraction is subtracted from the direct current voltage multiplied by a coefficient to calculate a first voltage offset.

2. The power conversion device according to claim 1, wherein the modulation control section calculates a second voltage offset based on the direct current voltage, the maximum phase, a first constant, and a square sum of the basic voltage command.

3. The power conversion device according to claim 1, wherein the modulation control section sets the first voltage offset to 0 when a modulation rate of the basic voltage command is lower than a first threshold value.

4. The power conversion device according to claim 2, wherein the modulation control section calculates the second voltage offset in a case where the modulation rate of the basic voltage command is lower than a second threshold value.

5. The power conversion device according to claim 1, wherein the modulation control section calculates a third voltage offset based on the direct current voltage, the minimum phase, and a second constant in a case where the modulation rate of the basic voltage command in the intermediate phase exceeds a third threshold value.

6. The power conversion device according to claim 1 or 5, wherein the modulation control section calculates a fourth voltage offset based on the direct current voltage, the maximum phase, and a third constant in a case where the modulation rate of the basic voltage command exceeds the second threshold value.

7. The power conversion device according to claim 1, wherein the modulation control section selects a modulation method in accordance with a modulation method calculated in a previous control period.

8. The power conversion device according to claim 1 or 7, wherein the modulation control section calculates a fourth voltage offset based on the direct current voltage, the maximum phase, and a third constant in a case where a difference between the maximum phase and the minimum phase is lower than a fourth threshold value and a voltage offset calculated in the previous control period is not the first voltage offset.

9. The power conversion device according to claim 8, wherein The modulation control section calculates a third voltage offset based on the minimum phase, the DC voltage, and a second constant, when the difference between the maximum phase and the minimum phase exceeds the fourth threshold value and the intermediate phase exceeds a third threshold value set in advance.

10. The power conversion device according to claim 9, wherein The modulation control section calculates a third voltage offset based on the minimum phase, the DC voltage, and a second constant, when the difference between the maximum phase and the minimum phase exceeds the fourth threshold value and the intermediate phase is lower than the third threshold value and the voltage offset calculated one control cycle before is the fourth voltage offset.

11. The power conversion device according to any one of claims 8 to 10, wherein The modulation control section calculates the first voltage offset when the difference between the maximum phase and the minimum phase exceeds the fourth threshold value and the modulation rate of the fundamental voltage command in the intermediate phase is lower than a first threshold value and the voltage offset calculated one control cycle before is not the fourth voltage offset.

12. The power conversion device according to any one of claims 8 to 11, wherein The modulation control section calculates the first voltage offset when the difference between the maximum phase and the minimum phase is lower than the fourth threshold value and the voltage offset calculated one control cycle before is the first voltage offset.

13. The power conversion device according to claim 3, wherein The modulation control section sets the first threshold value to a modulation rate at which the fundamental voltage command becomes lower than an upper limit voltage value at which current detection is possible by the current detection resistor element.

14. The power conversion device according to claim 4 or 6, wherein The modulation control section sets the second threshold value to a value that is higher than a modulation rate at which current detection is possible by the current detection resistor element and lower than a modulation rate at which the inverter can output.

15. The power conversion device according to any one of claims 5, 9, and 10, wherein The modulation control section sets the third threshold value to a center value of the output range of the inverter.

16. The power conversion device according to any one of claims 8 to 12, wherein The modulation control section sets the fourth threshold value to a value obtained by multiplying an upper limit value of a modulation rate at which current detection is possible by the current detection resistor element by the DC voltage.

17. The power conversion device according to claim 2 or 4, wherein The modulation control section sets the first constant so that a center value of the corrected voltage command is lower than a center value of the output range of the inverter.

18. The power conversion device according to any one of claims 5, 9, and 10, wherein The modulation control section sets the second constant so that the minimum phase is a lower limit value set in advance.

19. The power conversion device according to claim 6 or 8, wherein The modulation control section sets the third constant so that the maximum phase is an upper limit value set in advance.

20. The power conversion device of claim 19, wherein the third constant is an upper limit value of an output range of the inverter. ​

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