Techniques for performing write operations

Abstract

This application relates to techniques for performing write operations. In response to receiving a sequential write command from a host system, a memory system can determine a non-linear offset for a request set of data portions. The memory system can determine a first subset of data containing data segments with logical addresses having gaps corresponding to the offsets between the data segments to be stored in a first memory device. The memory system can store the first subset in a buffer and program the first subset into the first memory device. Additionally, the memory system can determine a second subset of data using the offset and can transmit a second request set for the second subset, which can be stored in the buffer and programmed into a second memory device.

Description

[0001] Cross-referencing

[0002] This patent application claims priority to U.S. Patent Application No. 17 / 651,214, filed February 15, 2022, entitled “Techniques to Perform a Write Operation”, which is assigned to the assignee and is expressly incorporated herein by reference. Technical Field

[0003] The technical field relates to techniques for performing write operations. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, user devices, wireless communication devices, cameras, and digital displays. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed to typically correspond to one of two supported states, logic 1 or logic 0. In some instances, a single memory cell can support more than two possible states, any of which can be stored by the memory cell. To access the information stored by the memory device, a component can read or sense the state of one or more memory cells within the memory device. To store information, a component can write or program one or more memory cells within the memory device into corresponding states.

[0005] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), 3D crosspoint memory, NOR (Non-OR), and NAND (NAND) memory devices. Memory devices can be volatile or non-volatile. Volatile memory cells (e.g., DRAM cells) can lose their programmed state over time unless periodically updated by an external power supply. Non-volatile memory cells (e.g., NAND memory cells) can maintain their programmed state for a long period of time even in the absence of an external power supply. Summary of the Invention

[0006] Describe an apparatus. The apparatus may include a controller associated with a memory device, wherein the controller is configured to cause the apparatus to: receive, at a controller of a memory system and from a host system, a write command associated with a plurality of data segments available at the host system, the memory system including a plurality of memory devices; transmit to the host system a first plurality of requests for a first subset of the plurality of data segments, wherein the first plurality of requests includes a first request and at least one additional request indicating an offset of a data segment associated with the at least one additional request relative to a previous request in the first plurality of requests, the offset being at least partially based on the number of the plurality of memory devices; receive, at least partially based on transmitting the first plurality of requests, each of the first subset of the plurality of data segments from the host system; store the first subset of the plurality of data segments in a buffer at the memory system; and write the first subset of the plurality of data segments into a first memory device among the plurality of memory devices.

[0007] A non-transitory computer-readable medium is described. The non-transitory computer-readable medium may store code including instructions executable by a processor to perform the following operations: receiving, at a controller of a memory system and from a host system, a write command associated with a plurality of data segments available at the host system, the memory system including a plurality of memory devices; transmitting to the host system a first plurality of requests for a first subset of the plurality of data segments, wherein the first plurality of requests includes a first request and at least one additional request indicating an offset of a data segment associated with the at least one additional request relative to a previous request in the first plurality of requests, the offset being at least partially based on the number of the plurality of memory devices; receiving, at least partially based on transmitting the first plurality of requests, each of the first subset of the plurality of data segments from the host system; storing the first subset of the plurality of data segments in a buffer at the memory system; and writing the first subset of the plurality of data segments into a first memory device among the plurality of memory devices.

[0008] Describe a method. The method may include: receiving, at a controller of a memory system and from a host system, a write command associated with a plurality of data segments available at the host system, the memory system including a plurality of memory devices; transmitting to the host system a first plurality of requests for a first subset of the plurality of data segments, wherein the first plurality of requests includes a first request and at least one additional request indicating an offset of a data segment associated with the at least one additional request relative to a previous request in the first plurality of requests, the offset being at least partially based on the number of the plurality of memory devices; receiving, at least partially based on transmitting the first plurality of requests, each of the first subset of the plurality of data segments from the host system; storing the first subset of the plurality of data segments in a buffer at the memory system; and writing the first subset of the plurality of data segments into a first memory device among the plurality of memory devices. Attached Figure Description

[0009] Figure 1 Examples of systems that support techniques for performing write operations based on the examples disclosed herein are shown.

[0010] Figure 2 Examples of systems that support techniques for performing write operations based on the examples disclosed herein are shown.

[0011] Figure 3 Examples of systems that support techniques for performing write operations based on the examples disclosed herein are shown.

[0012] Figure 4A and 4B Examples of process flows that support the execution of write operations based on the examples disclosed herein are shown.

[0013] Figure 5 A block diagram of a memory system that supports techniques for performing write operations according to examples disclosed herein is shown.

[0014] Figure 6 The flowchart illustrates one or more methods that support the performance of write operations based on the examples disclosed herein. Detailed Implementation

[0015] In some memory systems, such as managed NAND systems or other managed flash memory systems, the bandwidth and speed of access operations, such as sequential read operations, can be increased by performing certain operations associated with read operations in at least partially parallel. For example, if the data associated with a read operation is stored in a pattern across a set of segments spanning multiple memory devices, such that a first memory device stores a first segment and a second segment of data, a second memory device stores a third segment of data consecutive to the first segment and a fourth segment of data consecutive to the second segment, and so on (e.g., data stored in an interleaved or z-pattern), the memory system can retrieve data segments from the multiple memory devices in parallel for sequential read operations and transfer the data sequentially (e.g., in contiguous blocks of logical addresses) to the host system. In some systems, in order to store data in the aforementioned pattern (e.g., as part of a sequential write operation), the memory system may first retrieve all or a substantial portion of the data from the host system using a set of requests having block offsets corresponding to the amount of data written to each memory device, such as ready-to-transfer (RTT) commands. That is, data can be retrieved sequentially from the host system for each memory device. In some cases, the memory system can store data in a buffer within the memory system before programming the data across memory devices in the aforementioned mode. That is, the data can be initially "temporarily stored" in the memory system's buffer. However, tiering data in this way can unnecessarily consume large amounts of buffer space (e.g., large enough to store all or a significant portion of the data corresponding to sequential read operations), which can reduce the bandwidth and power efficiency of sequential write operations, as well as the overall lifetime of the memory system.

[0016] As described herein, a memory system can use a relatively small buffer to hierarchically manage data segments associated with sequential write operations. In some cases, in response to receiving a sequential write command, the memory system can determine a non-linear or interleaved offset for a portion of the data, such as a ready-to-transfer (RTT) command. For example, the memory system can determine a first subset of data containing data segments with logical addresses having gaps corresponding to offsets between the data segments to be stored in a first memory device. Subsequently, the memory system can transmit a first set of requests for the first subset, store the first subset in a buffer, and program the first subset into the first memory device. Additionally, the memory system can determine a second subset of data containing at least one data segment with logical addresses between the data segments of the first subset, using offsets, and can transmit a second set of requests for the second subset, which can be stored in a buffer and subsequently programmed into a second memory device. In some cases, the memory system can reuse the buffer, for example, by storing the second subset in the same set of registers used to store the first subset. In some cases, programming the first data subset into the first memory device and retrieving the second data subset can be performed at least partially in parallel. Therefore, the memory system can sequentially read data stored in the chosen pattern, while reducing the storage space used by the buffer, increasing data transfer speed and bandwidth, and reducing power consumption. Although the above example involves two memory devices, the techniques described herein can be applied to memory systems that include or use any number of memory devices to store data.

[0017] Firstly, in reference Figures 1 to 2 The features of this disclosure are described in the context of systems, apparatus, and circuits. (Referencing...) Figure 3-4B The features of this disclosure are described in the context of systems and process flows. References to this disclosure are also included. Figure 5-6 These and other features of this disclosure are further illustrated and described in the context of device diagrams and flowcharts of the technology for performing write operations.

[0018] Figure 1 An example of a system 100 is shown, which supports techniques for performing write operations according to the examples disclosed herein. System 100 includes a host system 105 coupled to a memory system 110.

[0019] The memory system 110 may be or include any device or set of devices, wherein the device or set of devices includes at least one memory array. For example, the memory system 110 may be or include a universal flash memory (UFS) device, an embedded multimedia controller (eMMC) device, a flash device, a universal serial bus (USB) flash device, a secure digital card (SD card), a solid-state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small form factor DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), and other possibilities.

[0020] System 100 may be contained in a computing device such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), device with Internet of Things (IoT) capability, embedded computer (e.g., embedded computer contained in a vehicle, industrial equipment or networked business device), or any other computing device containing memory and processing means.

[0021] System 100 may include a host system 105, which may be coupled to a memory system 110. In some instances, this coupling may include an interface to a host system controller 106, which may be an instance of a controller or control component configured to cause the host system 105 to perform various operations according to the examples described herein. The host system 105 may include one or more devices, and in some cases, may include a processor chipset and a software stack executed by the processor chipset. For example, the host system 105 may include an application configured to communicate with the memory system 110 or devices therein. The processor chipset may include one or more cores, one or more caches (e.g., memory native to the host system 105 or included in the host system), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a Peripheral Component Interconnect High Speed ​​(PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller). The host system 105 may use the memory system 110, for example, to write data to the memory system 110 and to read data from the memory system 110. Although Figure 1 A memory system 110 is shown, but the host system 105 can be coupled to any number of memory systems 110.

[0022] Host system 105 may be coupled to memory system 110 via at least one physical host interface. In some cases, host system 105 and memory system 110 may be configured to communicate via the physical host interface using associated protocols (e.g., to exchange or otherwise transmit control, address, data, and other signals between memory system 110 and host system 105). Examples of physical host interfaces may include, but are not limited to, SATA interfaces, UFS interfaces, eMMC interfaces, PCIe interfaces, USB interfaces, Fibre Channel interfaces, Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Dual Data Rate (DDR) interfaces, DIMM interfaces (e.g., DDR-enabled DIMM sockets), Open NAND Flash Interface (ONFI), and Low Power Dual Data Rate (LPDDR) interfaces. In some instances, one or more such interfaces may be contained in or otherwise supported between host system controller 106 of host system 105 and memory system controller 115 of memory system 110. In some instances, host system 105 may be coupled to memory system 110 via a corresponding physical host interface for each memory device 130 included in memory system 110, or via a corresponding physical host interface for each type of memory device 130 included in memory system 110 (e.g., host system controller 106 may be coupled to memory system controller 115).

[0023] Memory system 110 may include memory system controller 115 and one or more memory devices 130. Memory device 130 may include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Although Figure 1 The example shows two memory devices 130-a and 130-b, but the memory system 110 may contain any number of memory devices 130. Furthermore, if the memory system 110 contains more than one memory device 130, the different memory devices 130 within the memory system 110 may contain the same or different types of memory cells.

[0024] The memory system controller 115 may be coupled to and communicate with the host system 105 (e.g., via a physical host interface) and may be an example of a controller or control component configured to cause the memory system 110 to perform various operations as described herein. The memory system controller 115 may also be coupled to and communicate with the memory device 130 to perform operations generally referred to as access operations at the memory device 130, such as reading data, writing data, erasing data, or updating data, and other such operations. In some cases, the memory system controller 115 may receive commands from the host system 105 and communicate with one or more memory devices 130 to execute such commands (e.g., at a memory array within the one or more memory devices 130). For example, the memory system controller 115 may receive commands or operations from the host system 105 and may translate these commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. In some cases, the memory system controller 115 may exchange data with the host system 105 and one or more memory devices 130 (e.g., in response to or otherwise in conjunction with commands from the host system 105). For example, the memory system controller 115 may translate responses associated with the memory device 130 (e.g., data packets or other signals) into corresponding signals for the host system 105.

[0025] The memory system controller 115 can be configured for other operations associated with the memory device 130. For example, the memory system controller 115 can perform or manage operations such as wear leveling, garbage collection, error control operations such as error detection or error correction, encryption, caching, media management, background refresh, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 130.

[0026] The memory system controller 115 may include hardware, such as one or more integrated circuits or discrete components, buffer memories, or combinations thereof. The hardware may include circuitry with dedicated (e.g., hard-coded) logic to perform the operations described herein that pertain to the memory system controller 115. The memory system controller 115 may be or include a microcontroller, a dedicated logic circuitry system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry system.

[0027] The memory system controller 115 may also include local memory 120. In some cases, local memory 120 may include read-only memory (ROM) or other memory capable of storing operational code (e.g., executable instructions) that can be executed by the memory system controller 115 to perform the functions belonging to the memory system controller 115 herein. In some cases, local memory 120 may additionally or alternatively include static random access memory (SRAM) or other memory available for internal storage or computation by the memory system controller 115, for example, internal storage or computation related to the functions belonging to the memory system controller 115 herein. Additionally or alternatively, local memory 120 may be used as a cache for the memory system controller 115. For example, if data is read from or written to memory device 130, then data may be stored in local memory 120, and the data may be available within local memory 120 for subsequent retrieval or manipulation (e.g., updating) by the host system 105 (e.g., with reduced latency relative to memory device 130) according to a caching strategy.

[0028] although Figure 1 An example of memory system 110 has been shown to include memory system controller 115, but in some cases memory system 110 may not include memory system controller 115. For example, memory system 110 may additionally or alternatively rely on an external controller (e.g., implemented by host system 105) or one or more local controllers 135, each located within memory device 130, to perform the functions belonging to memory system controller 115 herein. Generally, one or more functions belonging to memory system controller 115 herein may, in some cases, be alternatively performed by host system 105, local controller 135, or any combination thereof. In some cases, memory device 130, at least partially managed by memory system controller 115, may be referred to as a managed memory device. An example of a managed memory device is a managed NAND (MNAND) device.

[0029] Memory device 130 may include one or more arrays of non-volatile memory cells. For example, memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase-change memory (PCM), auto-select memory, other chalcogenide-based memories, ferroelectric random access memory (RAM) (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), electrically erasable programmable ROM (EEPROM), or any combination thereof. Alternatively or additionally, memory device 130 may include one or more arrays of volatile memory cells. For example, memory device 130 may include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0030] In some instances, memory device 130 may (e.g., on the same die or within the same package) include a local controller 135, which can perform operations on one or more memory cells of the respective memory device 130. The local controller 135 may operate in conjunction with memory system controller 115, or may perform one or more functions belonging to memory system controller 115 herein. For example, as Figure 1 As shown, memory device 130-a may include local controller 135-a, and memory device 130-b may include local controller 135-b.

[0031] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a memory die 160. For example, in some cases, memory device 130 may be a package containing one or more dies 160. In some instances, die 160 may be a block of electronic-grade semiconductor diced from a wafer (e.g., a silicon die diced from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a set of corresponding blocks 170, wherein each block 170 may include a set of corresponding pages 175, and each page 175 may include a set of memory cells.

[0032] In some cases, the NAND memory device 130 may include memory cells configured to each store one bit of information, which may be referred to as a single-level cell (SLC). Alternatively, the NAND memory device 130 may include memory cells configured to each store multiple bits of information; if configured to store two bits of information, it may be referred to as a multi-level cell (MLC); if configured to store three bits of information, it may be referred to as a three-level cell (TLC); if configured to store four bits of information, it may be referred to as a four-level cell (QLC), or more generally, a multi-level memory cell. Multi-level memory cells can provide greater storage density compared to SLC memory cells, but in some cases, this may involve narrower read or write margins or greater complexity for supporting circuitry.

[0033] In some cases, plane 165 may refer to a group of blocks 170, and in some cases, parallel operations may occur within different planes 165. For example, parallel operations may be performed on memory cells within different blocks 170, provided that the different blocks 170 are in different planes 165. In some cases, a single block 170 may be referred to as a physical block, and a virtual block may refer to a group of blocks 170 within which parallel operations can occur. For example, parallel operations may be performed on blocks 170-a, 170-b, 170-c, and 170-d, respectively, within planes 165-a, 170-b, 170-c, and 170-d, and blocks 170-a, 170-b, 170-c, and 170-d may be collectively referred to as a virtual block. In some cases, a virtual block may contain blocks 170 from different memory devices 130 (e.g., blocks in one or more planes containing memory devices 130-a and 130-b). In some cases, blocks 170 within a virtual block may have the same block address within their respective planes 165 (e.g., block 170-a may be “block 0” of plane 165-a, block 170-b may be “block 0” of plane 165-b, etc.). In some cases, parallel operations in different planes 165 may be subject to one or more restrictions, such as parallel operations on memory cells within different pages 175 that have the same page address within their respective planes 165 (e.g., related to command decoding, page address decoding circuitry, or other circuitry shared across planes 165).

[0034] In some cases, block 170 may contain memory cells organized into rows (page 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 may share a common word line (e.g., coupled thereto), and memory cells in the same string may share a common digital line (which may alternatively be referred to as a bit line) (e.g., coupled thereto).

[0035] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first granularity level (e.g., at the page granularity level), but can be erased at a second granularity level (e.g., at the block granularity level). That is, page 175 can be the smallest unit of memory (e.g., a set of memory cells) that can be independently programmed or read (e.g., simultaneously programmed or read as part of a single programming or reading operation), and block 170 can be the smallest unit of memory (e.g., a set of memory cells) that can be independently erased (e.g., simultaneously erased as part of a single erase operation). Furthermore, in some cases, NAND memory cells can be erased before they can be rewritten with new data. Therefore, for example, in some cases, the used page 175 may not be updated until the entire block 170 containing page 175 has been erased.

[0036] System 100 may include any number of non-transitory computer-readable media that support technologies for performing write operations. For example, host system 105, memory system controller 115, or memory device 130 (e.g., local controller 135) may include or otherwise have access to one or more non-transitory computer-readable media that store instructions (e.g., firmware) for performing the functions attributed herein to host system 105, memory system controller 115, or memory device 130. For example, such instructions, if executed by host system 105 (e.g., by host system controller 106), memory system controller 115, or memory device 130 (e.g., by local controller 135), may cause host system 105, memory system controller 115, or memory device 130 to perform one or more of the related functions described herein.

[0037] In some cases, memory system 110 may utilize memory system controller 115 to provide a managed memory system, which may include, for example, one or more memory arrays and associated circuitry combined with a local (e.g., on-die or in-package) controller (e.g., local controller 135). An example of a managed memory system is a managed NAND (MNAND) system.

[0038] In some cases, memory system 110 may use a relatively small buffer to categorize data segments associated with sequential write operations. In some cases, in response to receiving a sequential write command from host system 105, memory system 110 may determine a non-linear or interleaved offset for a set of requests for data portions, such as ready-to-transfer (RTT) commands. For example, memory system 110 may determine a first subset of data containing data segments with logical addresses having gaps corresponding to offsets between data segments to be stored in first memory device 130. Subsequently, memory system 110 may transmit a first set of requests for the first subset, store the first subset in a buffer, and program the first subset into first memory device 130. Additionally, memory system 110 may determine a second subset of data containing at least one data segment with logical addresses between data segments of the first subset, using offsets, and may transmit a second set of requests for the second subset, which may be stored in a buffer and subsequently programmed into second memory device 130. In some cases, memory system 110 may reuse the buffer, for example, by storing the second subset in the same set of registers used to store the first subset within the buffer.

[0039] Figure 2 An example of a system 200 is shown, illustrating a technique for performing write operations according to the examples disclosed herein. System 200 may be a reference. Figure 1 An example of system 100 described in the description or its aspects. System 200 may include a memory system 210 configured to store data received from host system 205 and to send data to host system 205 if requested by host system 205 using an access command (e.g., a read command or a write command). System 200 may implement references Figure 1 Aspects of the system 100 described. For example, memory system 210 and host system 205 may be instances of memory system 110 and host system 105, respectively.

[0040] Memory system 210 may include memory device 240 to (e.g., in response to receiving an access command from host system 205) store data transferred between memory system 210 and host system 205, as described herein. Memory device 240 may include references Figure 1 The memory device 240 may include one or more memory devices as described. For example, memory device 240 may include NAND memory, PCM, self-select memory, 3D cross-point, other chalcogenide-based memory, FERAM, MRAM, NOR (e.g., NOR flash) memory, STT-MRAM, CBRAM, RRAM, or OxRAM.

[0041] Memory system 210 may include a memory controller 230 for controlling the transfer of data directly into and out of memory device set 240, for example, for storing data, retrieving data, and determining memory locations where data is to be stored and retrieved. The memory controller 230 may communicate with the memory devices 240 directly or via a bus (not shown) using protocols specific to each type of memory device 240. In some cases, a single memory controller 230 may be used to control multiple memory devices 240 of the same or different types. In some cases, memory system 210 may include multiple memory controllers 230, for example, different memory controllers 230 for each type of memory device 240. In some cases, the memory controller 230 may be implemented as described in reference [reference needed]. Figure 1 Aspects of the local controller 135 described.

[0042] The memory system 210 may additionally include an interface 220 for communicating with the host system 205, and a buffer 225 for temporarily storing data transferred between the host system 205 and the memory device 240. The interface 220, buffer 225, and memory controller 230 can be used to move data between the host system 205 and the memory device 240, for example, as shown by data path 250, and can be collectively referred to as the data path components.

[0043] Using buffer 225 to temporarily store data during transmission allows data to be buffered while commands are being processed, thereby reducing latency between commands and allowing for arbitrary data sizes associated with commands. This also allows for handling command bursts, and buffered data can be stored or transmitted (or both) once the burst stops. Buffer 225 may contain relatively fast memory (e.g., some type of volatile memory such as SRAM or DRAM) or hardware accelerators or both to allow for fast storage and retrieval of data in and out of buffer 225. Buffer 225 may include data path switching components for bidirectional data transfer between buffer 225 and other components.

[0044] Temporary storage of data within buffer 225 refers to the storage of data in buffer 225 during the execution of an access command. That is, after the access command is completed, the associated data may no longer be maintained in buffer 225 (e.g., data may be overwritten for additional access commands). Additionally, buffer 225 may be a non-cached buffer. That is, host system 205 may not read data directly from buffer 225. For example, read commands may be placed in a queue without requiring an address to be matched against an address already in buffer 225 (e.g., no cached address matching or lookup operation is needed).

[0045] The memory system 210 may additionally include a memory system controller 215 for executing commands received from the host system 205 and controlling data path components during data movement. The memory system controller 215 may be a reference... Figure 1 An example of a memory system controller 115 is described. Bus 235 can be used for communication between system components.

[0046] In some cases, one or more queues (e.g., command queue 260, buffer queue 265, and storage queue 270) may be used to control the processing of access commands and the movement of corresponding data. For example, this may be advantageous if the memory system 210 processes more than one access command from the host system 205 in parallel. As examples of possible implementations, command queue 260, buffer queue 265, and storage queue 270 are depicted at interface 220, memory system controller 215, and storage controller 230, respectively. However, if used, the queues may be located anywhere within the memory system 210.

[0047] Data transferred between host system 205 and memory device 240 may take a different path than non-data information (e.g., commands, status information) within memory system 210. For example, system components in memory system 210 may communicate with each other using bus 235, while data may be transferred via data path component using data path 250 instead of bus 235. Memory system controller 215 may control how and whether data is transferred between host system 205 and memory device 240 by communicating with data path component via bus 235 (e.g., using a protocol specific to memory system 210).

[0048] If host system 205 transmits access commands to memory system 210, then interface 220 can receive the commands, for example, according to a protocol (e.g., UFS protocol or eMMC protocol). Therefore, interface 220 can be considered as the front end of memory system 210. After receiving each access command, interface 220 can, for example, transmit the command to memory system controller 215 via bus 235. In some cases, each command can be added to command queue 260 via interface 220 to transmit the command to memory system controller 215.

[0049] The memory system controller 215 may determine that an access command has been received based on (for example, using) communication from interface 220. In some cases, the memory system controller 215 may determine that an access command has been received by retrieving a command from command queue 260. After the command has been retrieved from command queue 260, for example by the memory system controller 215, the command may be removed from the command queue. In some cases, the memory system controller 215 may cause interface 220 to remove the command from command queue 260, for example, via bus 235.

[0050] After confirming that an access command has been received, the memory system controller 215 can execute the access command. For a read command, this may mean obtaining data from the memory device 240 and transferring the data to the host system 205. For a write command, this may mean receiving data from the host system 205 and moving the data to the memory device 240.

[0051] In either case, the memory system controller 215 may use the buffer 225, particularly for temporary storage of data received from or sent to the host system 205. The buffer 225 can be considered as an intermediate part of the memory system 210. In some cases, buffer address management (e.g., pointers to address locations within the buffer 225) may be performed by hardware (e.g., dedicated circuitry) in the interface 220, the buffer 225, or the memory controller 230.

[0052] In order to process a write command received from host system 205, memory system controller 215 may first determine whether buffer 225 has sufficient available space to store the data associated with the command. For example, memory system controller 215 may determine the amount of space within buffer 225 available to store the data associated with the write command, for example via firmware (e.g., controller firmware).

[0053] In some cases, buffer queue 265 can be used to control the flow of commands associated with data stored in buffer 225, including write commands. Buffer queue 265 may contain access commands associated with data currently stored in buffer 225. In some cases, commands in command queue 260 can be moved to buffer queue 265 via memory system controller 215 and can remain in buffer queue 265 while the associated data is stored in buffer 225. In some cases, each command in buffer queue 265 may be associated with an address at buffer 225. That is, a pointer indicating where the data associated with each command is stored in buffer 225 can be maintained. Using buffer queue 265, multiple access commands can be received sequentially from host system 205, and at least some portions of the access commands can be processed in parallel.

[0054] If buffer 225 has sufficient space to store the write data, memory system controller 215 may cause interface 220 to transmit an availability indication (e.g., a "ready to transfer" indication) to host system 205 according to a protocol (e.g., UFS protocol or eMMC protocol). When interface 220 subsequently receives data associated with the write command from host system 205, interface 220 may use data path 250 to transfer the data to buffer 225 for temporary storage. In some cases, interface 220 may obtain the location of the stored data within buffer 225 from buffer 225 or buffer queue 265. Interface 220 may indicate to memory system controller 215, for example, via bus 235 whether the data transfer to buffer 225 has been completed.

[0055] Once written data has been stored in buffer 225 via interface 220, the data can be transferred outside buffer 225 and stored in memory device 240. This can be accomplished using memory controller 230. For example, memory system controller 215 can cause memory controller 230 to retrieve data outside buffer 225 using data path 250 and transfer the data to memory device 240. Memory controller 230 can be considered as the back-end of memory system 210. Memory controller 230 can, for example, indicate to memory system controller 215 via bus 235 that data transfer to memory device 240 has been completed.

[0056] In some cases, memory queue 270 can be used to assist in the transfer of write data. For example, memory system controller 215 can push write commands from buffer queue 265 (e.g., via bus 235) to memory queue 270 for processing. Memory queue 270 may contain entries for each access command. In some instances, memory queue 270 may additionally contain: a buffer pointer (e.g., an address) indicating where in buffer 225 the data associated with the command is stored; and a memory pointer (e.g., an address) indicating the location in memory device 240 associated with the data. In some cases, memory controller 230 can obtain the location within buffer 225 from which data is to be obtained, from buffer 225, buffer queue 265, or memory queue 270. Memory controller 230 can manage the locations within memory device 240 used for storing data (e.g., performing wear leveling, garbage collection, etc.). Entries can be added to memory queue 270, for example, via memory system controller 215. After the data transfer is completed, the entry can be removed from the storage queue 270, for example, by the storage controller 230 or the memory system controller 215.

[0057] In order to process a read command received from host system 205, memory system controller 215 may again first determine whether buffer 225 has sufficient available space to store the data associated with the command. For example, memory system controller 215 may determine the amount of space within buffer 225 available to store the data associated with the read command, for example via firmware (e.g., via controller firmware).

[0058] In some cases, buffer queue 265 can be used to assist buffer storage of data associated with a read command in a manner similar to that described above with reference to the write command. For example, if buffer 225 has sufficient space to store the read data, memory system controller 215 can cause memory controller 230 to retrieve the data associated with the read command from memory device 240 and store the data in buffer 225 for temporary storage using data path 250. After the data transfer to buffer 225 is complete, memory controller 230 can, for example, instruct memory system controller 215 via bus 235.

[0059] In some cases, the storage queue 270 can be used to assist in the transfer of read data. For example, the memory system controller 215 can push a read command to the storage queue 270 for processing. In some cases, the storage controller 230 can obtain the location of data retrieved from the memory device 240 from the buffer 225 or the storage queue 270. In some cases, the storage controller 230 can obtain the location of data stored in the buffer 225 from the buffer queue 265. In some cases, the storage controller 230 can obtain the location of data stored in the buffer 225 from the storage queue 270. In some cases, the memory system controller 215 can move a command processed by the storage queue 270 back to the command queue 260.

[0060] Once data has been stored in buffer 225 by storage controller 230, it can be transferred out of buffer 225 and sent to host system 205. For example, storage system controller 215 can enable interface 220 to retrieve data from buffer 225 using data path 250 and transfer the data to host system 205, for example, according to a protocol (e.g., UFS protocol or eMMC protocol). For example, interface 220 can process commands from command queue 260 and can indicate to storage system controller 215, for example, via bus 235, that the data transfer to host system 205 has been completed.

[0061] The memory system controller 215 can execute received commands in a sequence (e.g., according to the first-in-first-out order of the command queue 260). For each command, the memory system controller 215 can move the data corresponding to the command into and out of the buffer 225, as discussed above. While the data is moved into and stored in the buffer 225, the command can remain in the buffer queue 265. When the processing of a command is complete (e.g., when the data corresponding to the access command has been transferred out of the buffer 225), the command can be removed from the buffer queue 265, for example, via the memory system controller 215. If a command is removed from the buffer queue 265, the address where the data previously associated with the command was stored can be used to store the data associated with the new command.

[0062] The memory system controller 215 may be additionally configured for operations associated with the memory device 240. For example, the memory system controller 215 may perform or manage operations such as wear leveling, garbage collection, error control (e.g., error detection or error correction), encryption, caching, media management, background refresh, health monitoring, and address translation between logical addresses (e.g., LBAs) associated with commands from the host system 205 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 240. That is, the host system 205 may issue commands indicating one or more LBAs, and the memory system controller 215 may recognize one or more physical block addresses indicated by the LBAs. In some cases, one or more consecutive LBAs may correspond to non-consecutive physical block addresses. In some cases, the memory controller 230 may be configured to perform one or more of the above operations in conjunction with or in place of the memory system controller 215. In some cases, the memory system controller 215 may perform the functions of the memory controller 230, and the memory controller 230 may be omitted.

[0063] In some cases, memory system 210 may use buffer 225 to categorize data segments associated with sequential write operations. In some cases, in response to receiving a sequential write command from host system 205, memory system 210 may determine a non-linear or interleaved offset for a set of requests for a portion of the data, such as a Ready to Transfer (RTT) command. For example, memory system 210 may determine a first subset of data containing data segments with logical addresses having gaps corresponding to offsets between data segments to be stored in first memory device 240. Subsequently, memory system 210 may transmit a first set of requests for the first subset, store the first subset in buffer 225, and program the first subset into first memory device 240. Additionally, memory system 210 may determine a second subset of data containing at least one data segment with logical addresses between data segments of the first subset, using offsets, and may transmit a second set of requests for the second subset, which may be stored in buffer 225 and subsequently programmed into second memory device 240. In some cases, memory system 210 can reuse the buffer, for example, by storing the second subset in the same set of registers used to store the first subset.

[0064] Figure 3 An example of a system 300 is shown that supports the technology for performing write operations according to the examples disclosed herein. System 300 may include a memory system 310 configured to perform access operations, such as read or write operations, associated with data from a host system 305, which may be a reference system. Figure 1 and 2 Examples of the corresponding devices described. The host system 305 and memory system 310 can perform sequential access operations, such as sequential read operations or sequential write operations, to access or modify data stored in multiple memory devices 340 (e.g., first memory device 340-a, second memory device 340-b, third memory device 340-c, and fourth memory device 340-d). In some cases, the multiple memory devices 340 may be instances of NAND devices and may contain blocks of memory cells configured to store logic levels corresponding to single or multiple bits, such as single-level cell (SLC) access operations, multi-level cell (MLC) access operations, three-level cell (TLC) access operations, and four-level cell (QLC) access operations. In some cases, sequential access operations may be associated with a continuous (e.g., sequential) range of data having a logical block address (LBA).

[0065] For example, host system 305 can issue sequential read commands for multiple data segments 345 (e.g., first data segment 345-a, second data segment 345-b, third data segment 345-c, and fourth data segment 345-d). In some cases, access commands (e.g., those containing sequential read commands) can be transmitted by host interface 307 of host system 305 and received by interface 320 of memory system 310, which may be a reference interface. Figure 2 An instance of the described interface 220.

[0066] Data segment 345 may contain data associated with a series of consecutive LBAs, such as one or more data pages or other data units or groups. In some cases, multiple data segments 345 may be consecutive across each of the data segments 345. That is, the LBAs of the second data segment 345-b may be sequential with the LBAs of the first data segment 345-a, the LBAs of the third data segment 345-c may be sequential with the LBAs of the second data segment 345-b, and the LBAs of the fourth data segment 345-d may be sequential with the LBAs of the third data segment 345-c.

[0067] In some cases, to improve the speed, bandwidth, or both of sequential read commands, multiple data segments 345 can be stored across multiple memory devices 340 of the memory system 310. For example, a first memory device 340-a may store a first data segment 345-a and a third data segment 345-c, while a second memory device 340-b may store a second data segment 345-b and a fourth data segment 345-d. In response to receiving a sequential read command, interface 320 may (e.g., via processor 315) transmit an indication of the sequential read command to memory controller 330, which may be a reference... Figure 2 An example of a memory controller 230 is described. In some cases, the memory controller 330 may include a channel or path between each of the memory devices 340. Therefore, the memory controller 330 can issue requests for data stored in each of the memory devices 340 in parallel. After receiving a data segment 345, the memory controller 330 may temporarily store the data segment 345 in a buffer 325, and the memory system 310 may subsequently transfer the data segment 345 sequentially to the host system 305, for example, via interface 320. In some cases, the buffer 325 may include a set of segment buffers, each configured to store a data segment. In some instances, the number of segment buffers in the buffer 325 may be less than the number of data segments 345 contained within the plurality of data segments 345. For example, the number of segment buffers may be less than the product of the number of the plurality of memory devices 340 and the number of levels or logical states configured to be stored in the memory cells of the memory devices 340.

[0068] In some cases, memory system 305 can perform sequential write operations to store multiple data segments 345 across memory device 340. As an example, host system 305 can transmit a command to memory system 310 to store multiple data segments 345 (e.g., using host interface 307). In some cases, multiple data segments 345 may initially be stored in host buffer 355 of host system 305. In response to receiving a command from host system 305 to perform a sequential write operation, memory system 310 can generate one or more requests 360 for non-contiguous data segments 445 (e.g., a set of data segments with gaps between LBAs) and transmit them to host system 305.

[0069] In some instances, request 360 may be an instance of an RTT command and may instruct host system 305 to transfer a specific data segment 345 to memory system 310. In some cases, request 360 may include an offset indicating which data segment 345 to transfer. The offset may be an instance of the number of LBAs or the number of data segments and may indicate the starting address of request 360 or a specific data segment 345. In some cases, the offset may correspond to the number of memory devices 340 used to store data. For example, if memory system 310 uses two memory devices 340 to store data, the offset may correspond to two data segments; if memory system 310 uses four memory devices 340 to store data, the offset may correspond to four data segments, and so on.

[0070] For example, memory system 310 may generate a first plurality of requests including a first request and a second request, and transmit the first plurality of requests to host system 305. In some cases, the first request may include an offset indicating a first data segment 345-a, and the second request may include an offset indicating a third data segment 345-c. The offset indicating the third data segment 345-c may depend on the number of memory devices 340. For example, if the number of memory devices 340 is two, the offset may be two segments, and if the number of memory devices 340 is four, the offset may be four segments. In response to receiving the first plurality of requests, host system 305 may transmit the first data segment 345-a and the third data segment 345-c to memory system 310, for example, as part of data transfer 350. Memory system may store the first data segment 345-a and the third data segment 345-c in buffer 325, and subsequently store the first data segment 345-a and the third data segment 345-c in first memory device 340-a. In some cases, a single pass of multiple bit access operations can be used, for example, by writing the first data segment 345-a and the third data segment 345-c to the same set of MLC blocks. In some cases, the number of segment buffers in buffer 325 may correspond to or depend on the number of binary logic states programmable to the memory cells of memory device 340. For example, if memory device 340 contains MLC blocks, the number of segment buffers in buffer 325 may be two (e.g., holding the first data segment 345-a and the third data segment 345-c), or it may contain one or more additional segment buffers. Alternatively, if memory device 340 contains TLC blocks or QLC blocks, the number of segment buffers in buffer 325 may be three or four, respectively.

[0071] In some cases, after transmitting the first plurality of requests, the memory system may generate and transmit a second plurality of requests, including a third and a fourth request. In some cases, the third request may include an offset indicating the second data segment 345-b, and the fourth request may include an offset indicating the fourth data segment 345-d. The memory system may store the second data segment 345-b and the fourth data segment 345-b in a buffer 325. In some cases, a portion of the buffer 325 may be reused in operations that transfer a plurality of segments 445 to the memory device 340. For example, the buffer 325 may contain fewer buffers than the number of segments 445 associated with sequential write operations received from the host system 305 (e.g., where each "buffer" stores one data segment 345). In some cases, the number of buffers may be equal to twice the number of segments used to store in each memory device 340. In this scenario, the memory system 310 can use buffers in a "ping-pong" manner, using a first set of buffers for data segments stored in a first memory device, a second set of buffers for data segments stored in a second memory device, a first set of buffers for data segments stored in a third memory device, and so on (e.g., using one set of buffers at a time to receive data from the host system 305 and using another set of buffers to write data to the memory device). Alternatively, the number of buffers can be less than twice the number of segments stored in each memory device 340. For example, if writing a data segment to the memory device 340 takes less time than receiving a data segment from the host system 305, the memory system 310 can release the buffers before receiving all the data segments of a given memory device, and thus can use a rotating buffer arrangement to reuse one or more buffers in operations associated with the next memory device. Therefore, one or more data segments 345 associated with the second plurality of requests can be stored in the same location of buffer 325 as the location used to store one or more data segments associated with the first plurality of requests, such as a segment buffer of buffer 325 used to store the first data segment 345-a and / or the third data segment 345-c (e.g., at least a portion of buffer 325 can be reused after storing the first data segment 345-a and the third data segment 345-c). For example, data segment 345-b can be stored in the third segment buffer of buffer 325 when data segments 345-a and 345-c are written to memory device 340, and data segment 345-d can be stored in one of the first or second segment buffers of buffer 325 used for data segments 345-a and 345-c. Subsequently, memory system 310 can store the second data segment 345-b and the fourth data segment 345-d in the second memory device 340-b.

[0072] In some instances, memory system 310 may store data associated with the first plurality of requests in the first memory device 340-a while transmitting the second plurality of requests. For example, the second plurality of requests may be transmitted to host system 305 during at least partially overlapping time periods when memory system 310 transmits the first data segment 345-a and the third data segment 345-c from buffer 325 to memory controller 330 and subsequently to the first memory device 340-a.

[0073] It should be noted that although the above example describes the operation of four data segments 345 stored across two memory devices 340 for clarity, any number of data segments 345, memory devices 340, or both can be used. Furthermore, memory devices 340 can include instances of flash memory devices, such as NAND devices, UFS devices, eMMC devices, etc. In such instances, signaling similar to a UFS RTT command can be used to request a specific data segment 345 from the host system 305.

[0074] Figure 4A and 4B Examples of process flow 400 supporting techniques for performing write operations according to the examples disclosed herein are shown. In some instances, process flow 400 may be implemented by aspects of system 300. Process flow 400 may include operations performed by host system 405 and memory system 410, which may be referenced... Figure 3 Examples of host system 305 and memory system 310 are described. For example, memory system 410 may include controller 415, buffer 425, and one or more memory devices 440. In some instances, controller 415 may be or may include components such as interface 320, processor 315, memory controller 330, or combinations thereof. In the following description of process flow 400, operations may be performed in a different order than those shown. For example, specific operations may be omitted from process flow 400, or other operations may be added to process flow 400.

[0075] Process flow 400 may include instances of information and signaling transferred between host system 405 and memory system 410 as part of a sequential access operation, such as a write or read operation. For example, host system 405 may issue a sequential write command to store data into memory system 410. In some cases, host system 405 may temporarily store data in a host buffer at 420. The data may comprise a set of data segments 445, such as a first data segment 445-a, a second data segment 445-b, a third data segment 445-c, and a fourth data segment 445-d, which may be referenced... Figure 3An instance of the corresponding data segment described. Data segment 445 may be stored in the host buffer sequentially (e.g., according to the logical block address associated with the data segment).

[0076] In some instances, process flow 400 may include transmitting a write command for storing data segments 445 in a buffer of host system 405. For example, at 430, host system 405 may transmit a write command to memory system 410 (e.g., to controller 415 of memory system 410). The write command may contain information about the data to be stored in memory system 410, such as an indication of the data size, the size of each data segment 445, the number of data segments 445, an indication of the address range of the data (e.g., LBA), or a combination thereof.

[0077] In some cases, process flow 400 may include an offset for a request set, such as an RTT command set, that identifies data associated with a command transmitted at 430. For example, at 435, controller 415 may use information about the data contained in the command and attributes of memory devices 440, such as the number of memory devices 440 used to store the data, to identify the requested offset. For example, if the memory system uses two memory devices 440 to store the data, the offset may correspond to two data segments 445.

[0078] In some cases, as part of the offset identification, memory system 410 may determine one or more subsets of data segments 445 to be retrieved from host system 405. For example, memory system 410 may determine that a first subset to be retrieved from host system 405 may include a first data segment 445-a and a third data segment 445-c, because the third data segment 445-c may be offset by two from the first data segment 445-a (e.g., the gap or offset between the two data segments may be between the starting logical address of the first data segment 445-a and the starting address of the third data segment 445-c). Additionally, memory system 410 may determine that a second subset to be retrieved from host system 405 may include a second data segment 445-b and a fourth data segment 445-d. In some cases, the second data segment 445-b may contain a logical address between the first data segment 445-a and the third data segment 445-c. For example, the offset for the request of the second data segment 445-b may be smaller than the offset for the request of the third data segment 445-c.

[0079] In some cases, the number of data segments included in a subset may depend on the number of bits that the memory cells of memory device 440 are configured to store. For example, if memory device 440 contains MLC blocks, each subset may contain two data segments 445. Alternatively, if memory device 440 contains TLC blocks, each subset may contain three data segments 445.

[0080] In some instances, memory system 410 may generate a first request set for a first subset of data segment 445. For example, memory system 410 may generate a first request for first data segment 445-a and a second request for third data segment 445-c. In some cases, each request may include an identified offset indicating the corresponding data segment 445. In some cases, memory system 410 may generate additional requests for the first request set (e.g., if memory device 440 contains higher-level blocks such as TLC blocks). Therefore, at 450, the first request set may be transferred, for example, from memory system 410 to host system 405.

[0081] In some cases, process flow 400 may include transmitting a first subset of data segments 445. For example, at 453, host system 405 may transmit a first subset of data (e.g., first data segment 445-a and third data segment 445-c) in response to receiving a first request set from memory system 410. In some instances, at 455, the first subset of data may be temporarily stored in buffer 425. For example, host system 405 may transmit the first subset of data segments 445 serially. Thus, memory system 410 may first receive the first data segment 445-a and store it in a first buffer of buffer 425, and then receive the third data segment 445-c and store it in a second buffer of buffer 425.

[0082] In some cases, process flow 400 may include writing a first subset of data to memory device 440. For example, at 458, memory system 410 may issue a multi-level write command to the first memory device in memory device 440. Thus, at 463, the first memory device may write the first subset of data from buffer 425 to a set of memory cells. In some cases, a single pass may be used to write the first subset of data (e.g., in a single access operation performed by the first memory device, both the first data segment 445-a and the third data segment 445-c may be written to the same set of memory cells, such as an MLC block).

[0083] In some cases, process flow 400 may include transmitting a second set of requests for a second subset of data segment 445. For example, at 460, the memory system may generate the second set of requests and transmit it to the host system 405. In some cases, transmitting the second set of requests and writing the first subset of data segment 445 may be performed at least partially in parallel (e.g., the memory system 410 may retrieve the second subset from the host system 405 during a time period that at least partially overlaps with the time period during which the first subset is written to the first memory device).

[0084] In some cases, process flow 400 may include the transmission of a second subset of data segments 445. For example, at 465, host system 405 may transmit a second subset of data (e.g., second data segment 445-b and fourth data segment 445-d) in response to receiving a second request set from memory system 410. In some instances, memory system 410 may reuse buffer 425 at 468 to temporarily store the second subset. For example, host system 405 may first receive second data segment 445-b and store it in a first segment buffer of buffer 425, and then receive fourth data segment 445-d and store it in a second segment buffer of buffer 425. Alternatively or concurrently, memory system 410 may stream or circulate through a number of segment buffers of buffer 425. For example, the second data segment 445-b can be stored in the third buffer of buffer 425 (e.g., to allow time for the write operation of the first data segment 445-a and the third data segment 445-c to the first memory device), and the fourth data segment can be looped back to be stored in the first buffer of buffer 425.

[0085] In some cases, process flow 400 may include writing a second subset of data to memory device 440. For example, at 470, memory system 410 may issue a multi-level write command to the second memory device in memory device 440. Thus, at 473, the second memory device may write the second subset of data from buffer 425 to a set of memory cells. In some cases, a single-pass write of the second subset of data may be used (e.g., the second data segment 445-b and the fourth data segment 445-d may both be written to the same set of memory cells, such as an MLC block, using a single access operation). Therefore, process flow 400 may allow a reduction in the size of buffer 425, for example, by allowing buffer 425 to be smaller than the total size of multiple data segments 445, while writing data segments 445 to memory device 440 in an interleaved or z-mode (e.g., a mode compatible with sequential reads of consecutive logical address blocks).

[0086] In some cases, the process flow may include sequential read operations to access data written during sequential write operations. In some cases, a sequential read operation for a memory cell storing multiple data bits may sequentially output data segments corresponding to each bit (e.g., a data segment corresponding to the first bit may be output first, then a data segment corresponding to the second bit, and so on). For example, at 475, the host system 405 may transmit a sequential read command to the memory system 410. In response to receiving the sequential read command, the memory system 410 may sequentially retrieve data segments 445 at 478. For example, the memory system 410 may retrieve a first data segment 445-a from a first memory device and may temporarily store the first data segment 445-a in buffer 425 at 480 (e.g., in the first segment buffer of buffer 425). Additionally, the memory system 410 may retrieve a second data segment 445-b from a second memory device and temporarily store the second data segment 445-b in buffer 425 (e.g., in the second segment buffer of buffer 425). Because the first data segment 445-a and the second data segment 445-b are stored in separate memory devices 440 during sequential write operations, the retrieval of the first data segment 445-a and the second data segment 445-b can be performed at least partially in parallel.

[0087] In some cases, after retrieving and storing a first portion of data (e.g., first data segment 445-a and second data segment 445-b), the memory system may transfer the first portion of data to the host system 405 at 485. After retrieving and storing the first portion of data, the memory system may retrieve a second portion of data (e.g., third data segment 445-c and fourth data segment 445-d) and store it in buffer 425. The retrieval and storage of the second portion of data may occur during a time period that at least partially overlaps with the transfer of the first portion of data to the host system 405. The memory system may transfer the second portion of data to the host system 405 after the first portion of data has been transferred. The memory system 410 may continue to retrieve and transfer portions of data until the data associated with the read command has been transferred. Alternatively or additionally, the memory system 410 may retrieve each data segment of data associated with the read request and store it in buffer 425 before transferring the data to the host system.

[0088] Various aspects of process flow 400 may be implemented by a controller and other components. Alternatively, aspects of process flow 400 may be implemented as instructions stored in memory (e.g., firmware stored in memory coupled to host system 405 or memory system 410). For example, when executed by a controller (e.g., interface controller 415), the instructions may cause the controller to perform the operation of process flow 400.

[0089] Figure 5 A block diagram 500 illustrates a memory system 520 that supports techniques for performing write operations according to examples disclosed herein. The memory system 520 may be a reference... Figures 1 to 4B Examples of aspects of the described memory system. Memory system 520 or its various components may be examples of means for performing various aspects of the technology to perform write operations as described herein. For example, memory system 520 may include a receiving component 525, a transferring component 530, a buffering component 535, a storage component 540, a segment identification component 545, or any combination thereof. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

[0090] Receiving component 525 may be configured or otherwise supported to support components for: receiving, at the controller of the memory system and from the host system, a write command associated with a plurality of data segments available at the host system, the memory system comprising a plurality of memory devices. Transmitting component 530 may be configured or otherwise supported to support components for: transmitting to the host system a first plurality of requests for a first subset of the plurality of data segments, wherein the first plurality of requests includes a first request and at least one additional request indicating an offset of the data segment associated with the at least one additional request relative to a previous request in the first plurality of requests, the offset being at least partially based on the number of the plurality of memory devices. In some instances, receiving component 525 may be configured or otherwise supported to support components for: receiving each of the first subset of the plurality of data segments from the host system, at least partially based on transmitting the first plurality of requests. Buffering component 535 may be configured or otherwise supported to support components for: storing the first subset of the plurality of data segments in a buffer at the memory system. Storage component 540 may be configured or otherwise supported to support components for: writing the first subset of the plurality of data segments to a first memory device among the plurality of memory devices.

[0091] In some instances, the transmission component 530 may be configured or otherwise supported to support means for transmitting a second plurality of requests for a second subset of a plurality of data segments to the host system after transmitting a first plurality of requests. In some instances, the receiving component 525 may be configured or otherwise supported to support means for receiving each of the second subset of a plurality of data segments from the host system, at least in part based on the transmission of the second plurality of requests. In some instances, the buffering component 535 may be configured or otherwise supported to store a second subset of a plurality of data segments in a buffer at a memory system. In some instances, the storage component 540 may be configured or otherwise supported to write a second subset of a plurality of data segments into a second memory device among multiple memory devices.

[0092] In some instances, the transmission of a second plurality of requests and the writing of a first subset of a plurality of data segments into a first memory device overlap at least partially in time.

[0093] In some instances, storing a second subset of multiple data segments in a buffer will store at least one data segment of the second subset of multiple data segments in the location of the buffer used to store at least one data segment of the first subset of multiple data segments.

[0094] In some instances, segment identification component 545 may be configured or otherwise support components for identifying a first subset and a second subset of multiple data segments at least in part based on offsets, the first subset comprising a first data segment having a first logical address and a second data segment having a second logical address, and the second subset comprising a third data segment having a third logical address between the first logical address and the second logical address, wherein a first request is made for the first data segment and at least one additional request is made for the second data segment.

[0095] In some instances, receiving component 525 may be configured or otherwise supported to support means for receiving read commands for multiple data segments from a host system. In some instances, receiving component 525 may be configured or otherwise supported to support retrieving a first data segment from a first memory device. In some instances, storage component 540 may be configured or otherwise supported to support retrieving a third data segment from a second memory device, wherein the retrieval of the third data segment at least partially overlaps with the retrieval of the first data segment in time. In some instances, transmission component 530 may be configured or otherwise supported to transmit the first and third data segments to a host system.

[0096] In some instances, the second offset of the second data segment of the second subset is less than the offset of the data segment associated with at least one additional request.

[0097] In some instances, in order to write a first subset of multiple data segments to a first memory device in a plurality of memory devices, storage component 540 may be configured or otherwise support components for transmitting commands to the first memory device for performing multi-level write operations on the first subset of multiple data segments.

[0098] In some instances, the number of segment buffers in a memory system's buffers is less than the product of the number of memory devices and the number of levels of multi-level write operations.

[0099] In some instances, multiple memory devices include flash memory devices.

[0100] In some instances, the first multiple requests contain a Ready to Transmit (RTT) Universal Flash Storage (UFS) command.

[0101] In some instances, the length of a data segment in multiple data segments corresponds to a page in a memory device in multiple memory devices.

[0102] Figure 6 A flowchart illustrating a method 600 that supports performing write operations according to examples disclosed herein is shown. The operation of method 600 can be implemented by a memory system or its components described herein. For example, the operation of method 600 can be provided by reference to... Figures 1 to 5 The described memory system is used for execution. In some instances, the memory system can execute a set of instructions to control the functional elements of the device, thereby performing the described function. Alternatively, the memory system can use dedicated hardware to perform aspects of the described function.

[0103] At 605, the method may include receiving write commands associated with multiple data segments available at the host system from a controller of the memory system, the memory system comprising multiple memory devices. Operation of 605 may be performed according to the examples disclosed herein. In some examples, aspects of operation of 605 may be provided by reference. Figure 5 The described receiving component 525 is used to perform this action.

[0104] At 610, the method may include transmitting to a host system a first plurality of requests for a first subset of a plurality of data segments, wherein the first plurality of requests includes a first request and at least one additional request indicating an offset of the data segment associated with the at least one additional request relative to a previous request in the first plurality of requests, the offset being at least partially based on the number of a plurality of memory devices. Operation of 610 may be performed according to the examples disclosed herein. In some examples, aspects of operation of 610 may be provided by reference to... Figure 5 The described transmission component 530 is used to perform this.

[0105] At 615, the method may include receiving each of a first subset of a plurality of data segments from the host system, at least in part, based on transmitting a first plurality of requests. The operation of 615 can be performed according to the examples disclosed herein. In some instances, aspects of the operation of 615 may be derived from references... Figure 5 The described receiving component 525 is used to perform this action.

[0106] At 620, the method may include storing a first subset of the plurality of data segments in a buffer at the memory system. The operation of 620 can be performed according to the examples disclosed herein. In some instances, aspects of the operation of 620 may be derived from references... Figure 5 The described buffer component 535 is used for execution.

[0107] At 625, the method may include writing a first subset of a plurality of data segments into a first memory device in a plurality of memory devices. The operation of 625 can be performed according to the examples disclosed herein. In some examples, aspects of the operation of 625 may be described by reference. Figure 5 The storage component 540 described is used for execution.

[0108] In some instances, the apparatus described herein may perform one or more methods, such as method 600. The apparatus may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) or any combination thereof for performing aspects of this disclosure:

[0109] Aspect 1: A method, apparatus, or non-transitory computer-readable medium includes operations, features, circuitry, logic, components, or instructions, or any combination thereof, for performing: receiving, at a controller of a memory system and from a host system, a write command associated with a plurality of data segments available at the host system, the memory system comprising a plurality of memory devices; transmitting to the host system a first plurality of requests for a first subset of the plurality of data segments, wherein the first plurality of requests includes a first request and at least one additional request indicating an offset of a data segment associated with the at least one additional request relative to a previous request in the first plurality of requests, the offset being at least partially based on the number of the plurality of memory devices; receiving, at least partially based on transmitting the first plurality of requests, each of the first subset of the plurality of data segments from the host system; storing the first subset of the plurality of data segments in a buffer at the memory system; and writing the first subset of the plurality of data segments into a first memory device among the plurality of memory devices.

[0110] Aspect 2: The method, apparatus, or non-transitory computer-readable medium according to Aspect 1 further comprises operations, features, circuitry, logic, components, or instructions, or any combination thereof, for performing: transmitting to the host system a second plurality of requests for a second subset of the plurality of data segments after transmitting the first plurality of requests; receiving each of the second subset of the plurality of data segments from the host system, at least in part based on the transmission of the second plurality of requests; storing the second subset of the plurality of data segments in the buffer at the memory system; and writing the second subset of the plurality of data segments into a second memory device in the plurality of memory devices.

[0111] Aspect 3: The method, apparatus, or non-transitory computer-readable medium according to aspect 2, wherein the transmission of the second plurality of requests and the writing of the first subset of the plurality of data segments into the first memory device overlap at least partially in time.

[0112] Aspect 4: The method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 2 to 3, wherein storing the second subset of the plurality of data segments in the buffer will store at least one data segment of the second subset of the plurality of data segments in a location of the buffer for storing at least one data segment of the first subset of the plurality of data segments.

[0113] Aspect 5: The method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 2 to 4 further comprises an operation, feature, circuit system, logic, component, or instruction or any combination thereof for performing: identifying a first subset and a second subset of the plurality of data segments at least in part based on the offset, the first subset comprising a first data segment having a first logical address and a second data segment having a second logical address, and the second subset comprising a third data segment having a third logical address between the first logical address and the second logical address, wherein the first request is for the first data segment and the at least one additional request is for the second data segment.

[0114] Aspect 6: The method, apparatus, or non-transitory computer-readable medium according to aspect 5 further comprises operations, features, circuitry, logic, components, or instructions, or any combination thereof, for performing: receiving a read command for the plurality of data segments from the host system; retrieving the first data segment from the first memory device; retrieving the third data segment from the second memory device, wherein the retrieval of the third data segment at least partially overlaps with the retrieval of the first data segment in time; and transmitting the first data segment and the third data segment to the host system.

[0115] Aspect 7: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 2 to 6, wherein the second offset of the second data segment of the second subset is less than the offset of the data segment associated with the at least one additional request.

[0116] Aspect 8: The method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 7, wherein the instructions for writing the first subset of the plurality of data segments to the first memory device of the plurality of memory devices comprise an operation, feature, circuit system, logic, component, or instruction or any combination thereof for performing: transmitting to the first memory device a command for performing a multi-level write operation on the first subset of the plurality of data segments.

[0117] Aspect 9: According to the method, device, or non-transitory computer-readable medium of aspect 8, the number of segment buffers in the buffer of the memory system is less than the product of the number of the plurality of memory devices and the number of levels of the multilevel write operation.

[0118] Aspect 10: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 9, wherein the plurality of memory devices comprises flash memory devices.

[0119] Aspect 11: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 10, wherein the first plurality of requests includes a Ready to Transmit (RTT) Universal Flash Storage (UFS) command.

[0120] Aspect 12: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 11, wherein the length of a data segment in the plurality of data segments corresponds to a page of a memory device in the plurality of memory devices.

[0121] It should be noted that the methods described above describe possible implementations, and the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods described may be combined.

[0122] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bit symbols, or chips that may permeate the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof. Some diagrams may illustrate signaling as a single signal; however, signals may represent a bus of signals, wherein the bus may have various bit widths.

[0123] The terms "electronic connectivity," "conductive contact," "connection," and "coupling" can refer to a relationship between components that supports the flow of electrons between them. Components are considered electronically connected (or electrically contacting, connected, or coupled) to each other if any conductive path exists between them that can support the flow of signals between them at any given time. At any given time, based on (e.g., in response to) the operation of a device containing the connected components, the conductive path between electronically connected (or electrically contacting, connected, or coupled) components can be open or closed. The conductive path between connected components can be a direct conductive path between components, or an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some instances, one or more intermediate components, such as switches or transistors, can be used to interrupt the signal flow between connected components for a period of time.

[0124] The term "coupling" refers to the condition that moves from an open-circuit relationship between components to a closed-circuit relationship. In an open-circuit relationship, signals cannot currently travel between components via a conductive path, while in a closed-circuit relationship, signals can travel between components via a conductive path. If a component, such as a controller, couples other components together, then the component initiates a change that allows signals to flow between other components via conductive paths that were previously not permitted.

[0125] The term "isolation" refers to a relationship between components where signals cannot currently flow between them. Components are isolated from each other if there is an open circuit between them. For example, components separated by a switch positioned between them are isolated from each other when the switch is open. If a controller isolates two components, it achieves the following change: preventing signals from flowing between the components using previously permitted conductive paths.

[0126] The terms “if,” “when,” “based on,” or “at least partially based on” are used interchangeably. In some instances, the terms “if,” “when,” “based on,” or “at least partially based on” are used to describe a connection between conditional actions, conditional processes, or parts of a process.

[0127] The term "in response to" can refer to a condition or action that occurs at least partially (if not completely) as a result of a prior condition or action. For example, a first condition or action may be performed, and a second condition or action may occur at least partially as a result of the occurrence of the prior condition or action (whether directly after the first condition or action or after one or more other intermediate conditions or actions following the first condition or action).

[0128] The devices discussed herein, including memory arrays, can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, and gallium nitride. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemicals including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, either by ion implantation or by any other doping method.

[0129] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include a three-terminal device comprising a source, a drain, and a gate. The terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may include heavily doped, such as degenerate, semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., the majority carriers are electrons), the FET may be called an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), the FET may be called a p-type FET. The channel may be end-capped by an insulating gate oxide. The conductivity of the channel can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "on" or "activated." If a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "off" or "deactivated."

[0130] The description herein, illustrated with reference to the accompanying drawings, describes example configurations and does not represent all instances that can be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description," not "preferred" or "superior to other instances." The detailed description includes specific details that provide an understanding of the described techniques. However, these techniques can be practiced without these specific details. In some cases, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0131] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by a hyphen following the reference numeral and a second numeral used to differentiate between similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of the second reference numeral.

[0132] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored as one or more instructions or code on or transmitted via a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described above can be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions can also be physically located in various locations, including distributed configurations such that portions of the functions are implemented in different physical locations.

[0133] For example, the various illustrative blocks and components described in connection with the disclosure herein may be implemented or executed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device designed to perform the functions described herein, discrete gate or transistor logic, discrete hardware components, or any combination thereof. The general-purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller, or state machine. The processor may be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0134] As used herein, the word "or," as used in the claims, such as in a list of items (e.g., a list of items followed by phrases such as "at least one of" or "one or more of"), indicates a list containing endpoints such that a list of at least one of, for example, A, B, or C, means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Additionally, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, without departing from the scope of this disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should also be interpreted as the phrase "at least partially based on".

[0135] Computer-readable media includes both non-transitory computer-readable storage media and communication media, with communication media encompassing any media that facilitates the transfer of a computer program from one place to another. Non-transitory storage media can be any available media accessible by a general-purpose or special-purpose computer. By way of example, and not limitation, non-transitory computer-readable media may include RAM, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), compressed optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then such coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of media. As used herein, disks and optical discs include CDs, laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, where disks typically copy data magnetically, while optical discs use lasers to copy data optically. Combinations of these are also included within the scope of computer-readable media.

[0136] The description provided herein enables those skilled in the art to make or use this disclosure. Those skilled in the art will appreciate the various modifications that can be made to this disclosure, and that the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus comprising: A controller associated with a memory device, wherein the controller is configured to cause the device to perform the following operations: The system receives write commands associated with multiple data segments available at the host system, which includes multiple memory devices, at the controller of the memory system and from the host system. Transmit to the host system a first plurality of requests for a first subset of the plurality of data segments, wherein the first plurality of requests includes a first request and at least one additional request, the at least one additional request indicating an offset of the data segment associated with the at least one additional request relative to a previous request in the first plurality of requests, the offset being at least in part based on the number of the plurality of memory devices; At least in part based on the transmission of the first plurality of requests, each of the first subset of the plurality of data segments is received from the host system; The first subset of the plurality of data segments is stored in a buffer at the memory system; as well as The first subset of the plurality of data segments is written into the first memory device among the plurality of memory devices.

2. The device of claim 1, wherein the controller is further configured to cause the device to perform the following operations: After transmitting the first plurality of requests, a second plurality of requests for a second subset of the plurality of data segments are transmitted to the host system; At least in part based on the transmission of the second plurality of requests, each of the second subset of the plurality of data segments is received from the host system; The second subset of the plurality of data segments is stored in the buffer at the memory system; as well as The second subset of the plurality of data segments is written into the second memory device of the plurality of memory devices.

3. The device of claim 2, wherein transmitting the second plurality of requests and writing the first subset of the plurality of data segments into the first memory device overlap at least partially in time.

4. The device of claim 2, wherein storing the second subset of the plurality of data segments in the buffer will store at least one data segment of the second subset of the plurality of data segments in a location of the buffer for storing at least one data segment of the first subset of the plurality of data segments.

5. The device of claim 2, wherein the controller is further configured to cause the device to perform the following operations: The first subset and the second subset of the plurality of data segments are identified at least in part based on the offset, the first subset comprising a first data segment having a first logical address and a second data segment having a second logical address, and the second subset comprising a third data segment having a third logical address between the first logical address and the second logical address, wherein the first request is for the first data segment and the at least one additional request is for the second data segment.

6. The device of claim 5, wherein the controller is further configured to cause the device to perform the following operations: Receive read commands for the plurality of data segments from the host system; Retrieve the first data segment from the first memory device; Retrieving the third data segment from the second memory device, wherein the retrieval of the third data segment at least partially overlaps with the retrieval of the first data segment in time; and The first data segment and the third data segment are transmitted to the host system.

7. The device of claim 2, wherein the second offset of the second data segment of the second subset is less than the offset of the data segment associated with the at least one additional request.

8. The device of claim 1, wherein writing the first subset of the plurality of data segments into the first memory device of the plurality of memory devices is configured to cause the device to perform the following operations: A command is transmitted to the first memory device to perform a multi-level write operation on the first subset of the plurality of data segments.

9. The device of claim 8, wherein the number of segment buffers in the buffer of the memory system is less than the product of the number of the plurality of memory devices and the number of levels of the multilevel write operation.

10. The device of claim 1, wherein the plurality of memory devices includes flash memory devices.

11. The device of claim 1, wherein the first plurality of requests includes a prepare to transmit an RTT Universal Flash Storage (UFS) command.

12. The device of claim 1, wherein the length of a data segment in the plurality of data segments corresponds to a page in a memory device in the plurality of memory devices.

13. A non-transitory computer-readable medium storing code, the code comprising instructions executable by a processor to perform the following operations: The system receives write commands associated with multiple data segments available at the host system, which includes multiple memory devices, at the controller of the memory system and from the host system. Transmit to the host system a first plurality of requests for a first subset of the plurality of data segments, wherein the first plurality of requests includes a first request and at least one additional request, the at least one additional request indicating an offset of the data segment associated with the at least one additional request relative to a previous request in the first plurality of requests, the offset being at least in part based on the number of the plurality of memory devices; At least in part based on the transmission of the first plurality of requests, each of the first subset of the plurality of data segments is received from the host system; The first subset of the plurality of data segments is stored in a buffer at the memory system; as well as The first subset of the plurality of data segments is written into the first memory device among the plurality of memory devices.

14. The non-transitory computer-readable medium of claim 13, wherein the instructions are further executable by the processor to perform the following operations: After transmitting the first plurality of requests, a second plurality of requests for a second subset of the plurality of data segments are transmitted to the host system; At least in part based on the transmission of the second plurality of requests, each of the second subset of the plurality of data segments is received from the host system; The second subset of the plurality of data segments is stored in the buffer at the memory system; as well as The second subset of the plurality of data segments is written into the second memory device of the plurality of memory devices.

15. The non-transitory computer-readable medium of claim 14, wherein the transmission of the second plurality of requests and the writing of the first subset of the plurality of data segments into the first memory device overlap at least partially in time.

16. The non-transitory computer-readable medium of claim 14, wherein storing the second subset of the plurality of data segments in the buffer will store at least one data segment of the second subset of the plurality of data segments in a location of the buffer for storing at least one data segment of the first subset of the plurality of data segments.

17. The non-transitory computer-readable medium of claim 14, wherein the instructions are further executable by the processor to perform the following operations: The first subset and the second subset of the plurality of data segments are identified at least in part based on the offset, the first subset comprising a first data segment having a first logical address and a second data segment having a second logical address, and the second subset comprising a third data segment having a third logical address between the first logical address and the second logical address, wherein the first request is for the first data segment and the at least one additional request is for the second data segment.

18. The non-transitory computer-readable medium of claim 17, wherein the instructions are further executable by the processor to perform the following operations: Receive read commands for the plurality of data segments from the host system; Retrieve the first data segment from the first memory device; Retrieving the third data segment from the second memory device, wherein the retrieval of the third data segment at least partially overlaps with the retrieval of the first data segment in time; and The first data segment and the third data segment are transmitted to the host system.

19. The non-transitory computer-readable medium of claim 14, wherein the second offset of the second data segment of the second subset is less than the offset of the data segment associated with the at least one additional request.

20. The non-transitory computer-readable medium of claim 13, wherein the instructions for writing the first subset of the plurality of data segments to the first memory device among the plurality of memory devices are executable by the processor to perform the following operations: A command is transmitted to the first memory device to perform a multi-level write operation on the first subset of the plurality of data segments.

21. The non-transitory computer-readable medium of claim 20, wherein the number of segment buffers in the buffer of the memory system is less than the product of the number of the plurality of memory devices and the number of levels of the multilevel write operation.

22. The non-transitory computer-readable medium of claim 13, wherein the plurality of memory devices includes flash memory devices.

23. The non-transitory computer-readable medium of claim 13, wherein the first plurality of requests includes a prepare to transmit an RTT Universal Flash Storage (UFS) command.

24. The non-transitory computer-readable medium of claim 13, wherein the length of a data segment in the plurality of data segments corresponds to a page in a memory device in the plurality of memory devices.

25. A method comprising: The system receives write commands associated with multiple data segments available at the host system, which includes multiple memory devices, at the controller of the memory system and from the host system. Transmit to the host system a first plurality of requests for a first subset of the plurality of data segments, wherein the first plurality of requests includes a first request and at least one additional request, the at least one additional request indicating an offset of the data segment associated with the at least one additional request relative to a previous request in the first plurality of requests, the offset being at least in part based on the number of the plurality of memory devices; At least in part based on the transmission of the first plurality of requests, each of the first subset of the plurality of data segments is received from the host system; The first subset of the plurality of data segments is stored in a buffer at the memory system; as well as The first subset of the plurality of data segments is written into the first memory device among the plurality of memory devices.

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