Display device and electronic equipment

Abstract

Provided is a display device capable of improving image quality. The display device includes a plurality of pixel blocks in a display region, the pixel blocks including a first circuit and a plurality of second circuits. The first circuit has a function of performing addition operation on a plurality of data supplied from a source driver. The second circuit includes a display element and has a function of performing display in accordance with the data on which the addition operation is performed. One pixel includes one second circuit and a constituent element of the first circuit that is shared. By sharing the first circuit among a plurality of pixels, aperture ratio can be improved.

Description

[0001] This application is a divisional application of the invention patent application with international application number PCT / IB2019 / 053250, international application date of April 19, 2019, application number 201980026665.0 that entered the Chinese national phase, and entitled "Display Device and Electronic Equipment". Technical Field

[0002] One aspect of the present invention relates to a display device.

[0003] Note that one aspect of the present invention is not limited to the aforementioned technical fields. The technical field of one aspect of the invention disclosed in this specification relates to an object, method, or manufacturing method. Furthermore, one aspect of the present invention relates to a process, machine, manufacture, or composition of matter. Therefore, more specifically, examples of the technical field of one aspect of the present invention disclosed in this specification include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, lighting devices, energy storage devices, memory devices, imaging devices, methods of operating these devices, or methods of manufacturing these devices.

[0004] Note that in this specification, etc., a semiconductor device refers to any device capable of operating by utilizing the characteristics of semiconductors. Transistors and semiconductor circuits are one type of semiconductor device. Additionally, storage devices, display devices, imaging devices, and electronic devices sometimes include semiconductor devices. Background Technology

[0005] Techniques for constructing transistors using metal oxides formed on a substrate have attracted attention. For example, Patent Documents 1 and 2 disclose a technique for using transistors using zinc oxide, In-Ga-Zn type oxides as switching elements for pixels in display devices.

[0006] In addition, Patent Document 3 discloses a storage device having a structure that uses transistors with extremely low off-state current in storage cells.

[0007] Furthermore, various improvements and applications have been attempted to improve liquid crystal display devices. For example, Patent Document 4 discloses a transparent display that utilizes field-sequence operation for display.

[0008] [Preliminary Technology Documents]

[0009] [Patent Literature]

[0010] [Patent Document 1] Japanese Patent Application Publication No. 2007-123861

[0011] [Patent Document 1] Japanese Published Patent Application No. 2007- 319 1 1

[0012] [Patent Document 3] Japanese Published Patent Application No. 201 1 -1 19674

[0013] [Patent Document 4] Japanese Published Patent Application No. 2018-21974 SUMMARY

[0014] PROBLEMS TO BE SOLVED BY THE INVENTION

[0015] Display devices have been developed that can display images of 8K4K (pixel count: 7680 x 4320) or higher resolution. Furthermore, the introduction of HDR (high dynamic range) display technology, which improves image quality through luminance adjustment, has been advancing.

[0016] In order to perform clear gradation display, it is desirable to make the range of data potentials that can be supplied to the display element wide. On the other hand, for example, the output voltage of a source driver for a liquid crystal display device is about 15 V, and in the case where a higher voltage is supplied to the display element, a source driver with high output must be used. A source driver with high output has high power consumption, and sometimes a new driver IC has to be developed.

[0017] In addition, in order to display a moving image more smoothly, it is necessary to increase the frame rate, but the more the number of pixels increases, the shorter the horizontal period becomes, so it is difficult to increase the frame rate. By implementing a structure in which the frame rate can be easily increased, the structure can be easily applied to a display device of a field sequential liquid crystal mode or the like.

[0018] Although the above problems need to be addressed, the aperture ratio decreases when the constituent elements of a pixel circuit increase, so it is preferable to configure a pixel circuit using fewer constituent elements.

[0019] Therefore, one of objects of one embodiment of the present application is to provide a display device that can improve image quality. In addition, one of objects of one embodiment of the present application is to provide a display device that can supply a voltage higher than the output voltage of a source driver to a display element. In addition, one of objects of one embodiment of the present application is to provide a display device that can improve the luminance of a displayed image. In addition, one of objects of one embodiment of the present application is to provide a display device that can increase the frame rate. In addition, one of objects of one embodiment of the present application is to provide a display device that can increase the aperture ratio of a pixel.

[0020] Furthermore, one objective of this invention is to provide a low-power display device. Another objective of this invention is to provide a highly reliable display device. Another objective of this invention is to provide a novel display device, etc. Another objective of this invention is to provide a driving method for the aforementioned display device. Another objective of this invention is to provide a novel semiconductor device, etc.

[0021] Note that the description of these objectives does not preclude the existence of other objectives. One aspect of the invention does not require achieving all of the above objectives. Furthermore, objectives other than those described above are obvious from the description, drawings, and claims, and can be extracted from the description, drawings, and claims.

[0022] means of solving technical problems

[0023] One aspect of the present invention relates to a display device capable of improving image quality.

[0024] One aspect of the present invention is a display device comprising multiple pixel blocks. Each pixel block includes a first circuit and multiple second circuits. The first circuit and the second circuits are electrically connected. The first circuit has the function of performing addition operations on first data and second data to generate third data. The second circuit has the function of holding the third data and displaying it according to the third data.

[0025] The first circuit may include a first transistor, a second transistor, and a first capacitor. One of the source and drain of the first transistor may be electrically connected to one electrode of the first capacitor, and the other electrode of the first capacitor may be electrically connected to the other of the source and drain of the second transistor.

[0026] In addition, a third transistor may be included, wherein one of the source and drain of the third transistor may be electrically connected to the other electrode of the first capacitor, and the other of the source and drain of the first transistor may be electrically connected to the other of the source and drain of the second transistor.

[0027] The second circuit may include a third transistor and a third circuit. One of the source and drain of the third transistor may be electrically connected to one of the source and drain of the first transistor, and the other of the source and drain of the third transistor may be electrically connected to the third circuit. The third circuit may include a display element.

[0028] The third circuit can include a fourth transistor, a second capacitor, and a light emitting element used as a display element, one of a source and a drain of the fourth transistor can be electrically connected to the other of the source and the drain of the third transistor, the other of the source and the drain of the fourth transistor can be electrically connected to one electrode of the light emitting element, one electrode of the light emitting element can be electrically connected to one electrode of the second capacitor, and the other electrode of the second capacitor can be electrically connected to the gate of the fourth transistor.

[0029] Further, a fifth transistor can be included, one of a source and a drain of the fifth transistor can be electrically connected to one electrode of the light emitting element, the other of the source and the drain of the fifth transistor can be electrically connected to one of the source and the drain of the fourth transistor, and the other of the source and the drain of the fifth transistor can be electrically connected to one electrode of the second capacitor.

[0030] In addition, the third circuit can include a liquid crystal element as a display element, and one electrode of the liquid crystal element can be electrically connected to one of the source and the drain of the third transistor. Further, a third capacitor can be included, and one electrode of the third capacitor can be electrically connected to one electrode of the liquid crystal element.

[0031] Further, a fourth circuit and a fifth circuit can be included. The fourth circuit can have a function of controlling the first circuit, and the fifth circuit can have a function of controlling the second circuit.

[0032] The pixel block can include a plurality of pixels, and any of the plurality of pixels can include a plurality of constituent elements of the first circuit. The length of the pixel including the plurality of constituent elements of the first circuit in the vertical direction can be greater than that of the other pixels.

[0033] Preferably, the transistor included in the pixel block includes a metal oxide containing In, Zn, and M (M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf) in a channel formation region.

[0034] Effects of Invention

[0035] By using one embodiment of the present application, a display device capable of improving image quality can be provided. In addition, a display device capable of supplying a voltage higher than an output voltage of a source driver to a display element can be provided. In addition, a display device capable of improving the luminance of a displayed image can be provided. In addition, a display device capable of improving the frame rate can be provided. In addition, a display device capable of improving the aperture ratio of a pixel can be provided.

[0036] Furthermore, a low-power display device can be provided. Furthermore, a highly reliable display device can be provided. Furthermore, a novel display device can be provided, etc. Furthermore, a method for operating the aforementioned display device can be provided. Furthermore, a novel semiconductor device, etc., can be provided. Brief description of the attached figures

[0037] [ Figure 1 [Diagram illustrating the display device.]

[0038] [ Figure 2 [A diagram illustrating pixel blocks.]

[0039] [ Figure 3 [Illustration of the circuit selection diagram]

[0040] [ Figure 4 [A diagram illustrating pixel blocks.]

[0041] [ Figure 5 This is a timing diagram illustrating the operation of the pixel block.

[0042] [ Figure 6A and Figure 6B [A diagram illustrating pixel blocks.]

[0043] [ Figure 7 This is a timing diagram illustrating the operation of the pixel block.

[0044] [ Figures 8A to 8D [A diagram illustrating the circuit blocks.]

[0045] [ Figures 9A to 9D [A diagram illustrating the circuit blocks.]

[0046] [ Figures 10A to 10C [A diagram illustrating the circuit blocks.]

[0047] [ Figure 11A and Figure 11B [A diagram illustrating pixel blocks.]

[0048] [ Figure 12 [Diagram illustrating the gate driver]

[0049] [ Figure 13 [Diagram illustrating the gate driver]

[0050] [ Figure 14 [Diagram illustrating the gate driver]

[0051] [ Figure 15A and Figure 15B [Diagram illustrating the gate driver]

[0052] [ Figure 16A and Figure 16B [Diagram illustrating the gate driver]

[0053] [ Figure 17A and Figure 17B ] are diagrams illustrating a gate driver.

[0054] [ Figure 18 ] are diagrams illustrating a structure of a pixel block for simulation.

[0055] [ Figure 19 ] is a timing chart for simulation.

[0056] [ Figure 20A and Figure 20B ] are diagrams illustrating simulation results.

[0057] [ Figure 21 ] is a diagram illustrating a pixel layout.

[0058] [ Figure 22A and Figure 22B ] are diagrams illustrating a pixel layout.

[0059] [ Figure 23 ] is a diagram illustrating estimation results of aperture ratio.

[0060] [ Figures 24A to 24C ] is a diagram illustrating a display device.

[0061] [ Figure 25A and Figure 25B ] are diagrams illustrating a touch panel.

[0062] [ Figure 26A and Figure 26B ] are diagrams illustrating a display device.

[0063] [ Figure 27 ] is a diagram illustrating a display device.

[0064] [ Figure 28A and Figure 28B ] are diagrams illustrating a display device.

[0065] [ Figure 29A and Figure 29B ] are diagrams illustrating a display device.

[0066] [ Figures 30A to 30E ] is a diagram illustrating a display device.

[0067] [ Figures 31A1 to 31C2 ] is a diagram illustrating a transistor.

[0068] [ Figures 32A1 to 32C2 ] is a diagram illustrating a transistor.

[0069] [ Figures 33A1 to 33C2 ] is a diagram illustrating a transistor.

[0070] [ Figures 34A1 to 34C2 ] is a diagram illustrating a transistor.

[0071] [ Figures 35A to 35F ] an explanatory diagram of an electronic device.

[0072] Embodiment

[0073] Embodiments will be described in detail with reference to the accompanying drawings. Note that the present application is not limited to the following description, and it will be readily appreciated by those skilled in the art that the present application can be carried out in various changes and modifications of the embodiments described herein without departing from the spirit and scope of the present application. Therefore, the present application should not be interpreted as being limited to the following description of the embodiments. Note that in structures of the present application described below, the same portions or portions having similar functions are denoted by the same reference numerals throughout the accompanying drawings for describing the embodiments, and repetitive description is omitted. Note that the hatching of the same constituent elements is appropriately omitted or changed in different drawings.

[0074] In addition, even when a circuit diagram shows one element, the element can be formed using a plurality of elements if there is no problem in function. For example, a plurality of transistors used as a switch can be connected in series or in parallel. Further, a capacitor can be divided and arranged at a plurality of positions.

[0075] Further, one conductor has a plurality of functions such as a wiring, an electrode, and a terminal in some cases, and a plurality of names are used for the same element in some cases in this specification. In addition, even when a circuit diagram shows a direct connection between elements, the elements are actually connected through one or a plurality of conductors in some cases, and such a structure is included in the category of the direct connection in this specification.

[0076] (Embodiment 1)

[0077] In this embodiment, a display device of one embodiment of the present application will be described with reference to drawings.

[0078] One embodiment of the present application is a display device including a plurality of pixel blocks in a display region. The pixel block includes a first circuit and a plurality of second circuits electrically connected to the first circuit. The first circuit has a function of performing addition operation on a plurality of data supplied from a source driver. Thus, a voltage higher than an output of the source driver can be generated.

[0079] Further, the second circuit includes a display element and has a function of displaying data on which the addition operation is performed. One pixel includes one second circuit and constituent elements of the shared first circuit. Since the first circuit has more constituent elements (including wirings) and a larger area than the second circuit, the aperture ratio can be improved by sharing the first circuit in a plurality of pixels.

[0080] Figure 1 FIG. 1 is a diagram illustrating a display device of one embodiment of the present application. The display device includes a pixel block 12, a source driver 13, gate drivers 14a and 14b, and a circuit 15. Although an example in which two gate drivers are provided is shown here, one gate driver can be provided.

[0081] A display region is formed of a plurality of pixel blocks 12 arranged regularly. The pixel block 12 includes a circuit 11 and n (n is a natural number of 2 or more) circuits 10. The circuit 11 is electrically connected to each of the circuits 10. The circuit 11 and one of the circuits 10 are used as one pixel. That is, the circuit 11 is commonly used by a plurality of pixels.

[0082] The circuit 10 has a function of adding second data to first data by capacitive coupling to generate third data. The circuit 10 includes a display element and has a function of holding the third data and a function of displaying with the display element in accordance with the third data.

[0083] The circuits 10 included in one pixel block 12 can be arranged in n in the direction in which the source lines extend (the vertical direction). When the components of the circuit 11 are arranged in the occupied region of each pixel, the more the number of the circuits 10, the higher the aperture ratio.

[0084] The more the circuits 10 included in the pixel block 12, the higher the aperture ratio, but in the case where the writing time of image data is taken into account, it is preferable that a plurality of pixel blocks be arranged on each line.

[0085] In a display device with high resolution, writing needs to be performed in a short horizontal period. When the number of the circuits 10 is too large, the capacitance of the wiring in which the circuit 11 and the circuit 10 are connected becomes large, and thus an undesirable phenomenon in which writing cannot be completed in the horizontal period occurs. Thus, the number of the circuits 10 included in the pixel block is preferably appropriately set in accordance with a plurality of conditions such as the aperture ratio, the resolution (the horizontal period), and the capacitance of the wiring in which the circuit 11 and the circuit 10 are connected.

[0086] In the case where the aperture ratio needs to be efficiently increased, n is set to be higher than or equal to 5 and lower than or equal to 100, preferably higher than or equal to 10 and lower than or equal to 50, and more preferably higher than or equal to 20 and lower than or equal to 40, in accordance with the simulation results described later. When n is in this range, it is estimated that the capacitance of the wiring in which the circuit 11 and the circuit 10 are connected is sufficiently small, and thus the influence of the horizontal period can be ignored. Note that when a sufficiently long horizontal period can be ensured, n can be set to be around 100 to 1000.

[0087] Figure 2 A specific example of the pixel block 12 is shown. The pixel block 12 includes the circuit 11 and a plurality of circuits 10 (circuits 10[1] to [n]). Here, a region in which any of the circuits 10[1] to [n] is arranged is a pixel 20[1] to [n].

[0088] Circuit 11 may include transistor 101, transistor 102, and capacitor 104. One of the source and drain terminals of transistor 101 is electrically connected to one electrode of capacitor 104. The other electrode of capacitor 104 is electrically connected to one of the source and drain terminals of transistor 102.

[0089] Circuit 10 may include transistor 103 and circuit block 110. Circuit block 110 may include transistors, capacitors, and display elements, etc. One of the source and drain of transistor 103 is electrically connected to one of the source and drain of transistor 101. The other of the source and drain of transistor 103 is electrically connected to circuit block 110.

[0090] Here, the wiring connecting one of the source and drain of transistor 101, one electrode of capacitor 104, and one of the source and drain of transistor 103 is called node NM. Additionally, the wiring connecting the other of the source and drain of transistor 103 to circuit block 110 is called node NP. Node NP can be in a floating state, and the display elements included in circuit block 110 operate according to the potential of node NP.

[0091] The connections of the constituent elements and various wirings included in circuits 10 and 11 are described. The gate of transistor 101 is electrically connected to wiring 121. The gate of transistor 102 is electrically connected to wiring 122. The gate of transistor 103 is electrically connected to wiring 123. The other of the source and drain of transistor 101 is electrically connected to wiring 125. The other of the source and drain of transistor 102 is electrically connected to wiring 126.

[0092] Wiring 121, 122, 123 (123[1] to [n]) is used as gate lines. For example, wiring 121, 122 is electrically connected to gate driver 14a. Wiring 123 is electrically connected to gate driver 14b. Wiring 125, 126 is used as source lines and is electrically connected to source driver 13 via circuit 15 (see Figure 123). Figure 1 ).

[0093] Circuit 15 may, for example, have Figure 3 The structure is shown. Circuit 15 can be used as a selection circuit and output the potential input from source driver 13 to wiring 125 or wiring 126. Alternatively, the potential "V" can be... ref (e.g., a reference potential such as 0V) is output to wiring 126. This is achieved through signal V... ref _EN, 125_EN, and 126_EN control the transistors connected to each wiring, which can control the output at each potential. Note that circuit 15 is sometimes omitted.

[0094] In the circuit 11, first, the first data (weight: W) is written to the node NM. At this time, "V ref " is supplied to the other electrode of the capacitor 104, and "W-V ref " is held in the capacitor 104. Next, the node NM is made to be in a floating state, and the second data (data: D) is supplied to the other electrode of the capacitor 104, and the potential of the node NM becomes "W-V ref +D" due to the capacitive coupling.

[0095] Here, if "W" = "D", "V ref " = 0 V, and the capacitance of the node NM is sufficiently small, the potential of the node NM becomes "2D" or "2W", and it is possible to output a potential of about twice the output of the source driver 13 to the node NM. Therefore, even if a general-purpose driver IC is used, it is possible to use it for a use requiring a high voltage (for example, a liquid crystal element requiring a high voltage when controlling the gradation, and the like). In addition, it is possible to reduce the voltage supplied from the source driver 13 to about 1 / 2 for driving a general liquid crystal element, a light emitting element, and the like, and thereby it is possible to make the display device low in power consumption.

[0096] As the first data (weight: W), it is also possible to supply correction data. For example, by adding luminance correction data to the image data, it is possible to correct the deviation of the luminance unique to the display device. Further, since it is possible to correct the luminance for each pixel, it is possible to use it for HDR display. In addition, in the case of using a light emitting element as the display element, the display quality is affected by the threshold voltage deviation of the driving transistor, and therefore it is also possible to supply the threshold voltage correction data of this transistor as the first data (weight: W) to improve the display quality. Note that the first data (weight: W) and the second data (data: D) can also be exchanged with each other.

[0097] In one embodiment of the present application, the transistor 103 of the specific circuit 10 is turned on according to the addition operation of the above-described potentials, and the potential of the node NP (= the potential of the node NM) is determined. By sequentially performing such an operation on the circuit 10[1] to the circuit 10[n], the potential of the node NP of each circuit 10 can be determined. That is, it is possible to supply different image data to each pixel.

[0098] The node NM, the node NP are used as storage nodes. By turning on the transistor connected to each node, it is possible to write data to each node. Further, by turning off the transistor, it is possible to hold the data in each node. By using a transistor having an extremely low off-state current as the transistor, it is possible to suppress the leakage current, and thereby it is possible to hold the potential of each node for a long time. The transistor can be, for example, a transistor including a metal oxide in a channel formation region (hereinafter referred to as an OS transistor).

[0099] Specifically, as the transistors 101, 102, and 103, an OS transistor is preferably used. Further, the OS transistor can be used for the constituent elements included in the circuit block 110. In addition, when operation is performed in a range in which the amount of leakage current is allowable, a transistor including Si in a channel formation region (hereinafter referred to as a Si transistor) can be used. Further, the OS transistor and the Si transistor can be used in combination. As the Si transistor, a transistor including amorphous silicon, a transistor including crystalline silicon (typically, low-temperature polysilicon, single crystal silicon), or the like can be given.

[0100] As a semiconductor material for the OS transistor, a metal oxide having an energy gap of 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more can be used. Typically, an oxide semiconductor containing indium, such as a CAAC-OS or a CAC-OS which will be described later, can be used. In the CAAC-OS, atoms constituting a crystal are stable, and the CAAC-OS is suitable for a transistor or the like in which reliability is emphasized. The CAC-OS exhibits high mobility characteristics, and is suitable for a transistor or the like which is driven at high speed.

[0101] Since the semiconductor layer of the OS transistor has a large energy gap, extremely low off-state current characteristics of several yA / μm (current value per channel width of 1 μm) are exhibited. Unlike the Si transistor, the OS transistor has characteristics in which no impact ionization, avalanche breakdown, short channel effect, or the like occurs, and thus a circuit with high reliability can be formed. Further, an unevenness in electrical characteristics due to crystallinity, which is caused by the Si transistor, is less likely to occur in the OS transistor.

[0102] As the semiconductor layer in the OS transistor, for example, a film represented by "In-M-Zn-based oxide" containing indium, zinc, and M (aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium, or hafnium, or the like) can be used.

[0103] When the oxide semiconductor constituting the semiconductor layer is an In-M-Zn-based oxide, the atomic ratio of metal elements of a sputtering target used for forming an In-M-Zn oxide film is preferably In ≥ M and Zn ≥ M. The atomic ratio of metal elements of the sputtering target is preferably In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, or the like. Note that the atomic ratio of the semiconductor layer formed can vary within a range of ±40 % of the atomic ratio of the metal elements of the sputtering target.

[0104] As the semiconductor layer, an oxide semiconductor having a low carrier density is used. For example, an oxide semiconductor having a carrier density of 1 x 10 17 / cm 3 Hereinafter, it is preferable that the carrier density be 1 x 10 15 / cm 3 Hereinafter, it is more preferable that the carrier density be 1 x 10 13 / cm 3 Hereinafter, it is further preferable that the carrier density be 1 x 10 11 / cm 3 Hereinafter, it is still further preferable that the carrier density be less than 1 x 10 10 / cm 3 and be 1 x 10 -9 / cm 3 The above oxide semiconductor is referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. The oxide semiconductor has a low density of defect states and thus can be said to have stable characteristics.

[0105] Note that the present application is not limited to the above description, and a material having a suitable composition can be used depending on the semiconductor characteristics and electrical characteristics (field-effect mobility, threshold voltage, and the like) of a transistor required. In addition, the carrier density, impurity concentration, defect density, atomic ratio of a metal element to oxygen, interatomic distance, density, and the like of the semiconductor layer are preferably set as appropriate so that the semiconductor characteristics of a transistor required are obtained.

[0106] When the oxide semiconductor included in the semiconductor layer contains silicon or carbon, which is one of Group 14 elements, the number of oxygen vacancies increases, which makes the semiconductor layer n-type. Thus, the concentration of silicon or carbon (the concentration measured by secondary ion mass spectrometry) in the semiconductor layer is set to be 2 x 10 18 atoms / cm 3 Hereinafter, it is preferable that the concentration of silicon or carbon be 2 x 10 17 atoms / cm 3 or lower.

[0107] In addition, when an alkali metal or an alkaline earth metal is bonded to an oxide semiconductor, a carrier is sometimes generated, which increases the off-state current of a transistor. Thus, the concentration of an alkali metal or an alkaline earth metal (the concentration measured by secondary ion mass spectrometry) in the semiconductor layer is set to be 1 x 10 18 atoms / cm 3 Hereinafter, it is preferable that the concentration of an alkali metal or an alkaline earth metal be 2 x 10 16 atoms / cm 3 or lower.

[0108] In addition, when the oxide semiconductor that forms the semiconductor layer contains nitrogen, electrons serving as carriers are generated, the carrier density increases, and the transistor tends to have an n-type property. As a result, a transistor using an oxide semiconductor containing nitrogen tends to have a normally-on characteristic. Therefore, the concentration of nitrogen in the semiconductor layer (the concentration measured by secondary ion mass spectrometry) is preferably 5 x 10 18 atoms / cm 3 or less, further preferably 1 x 10 20 atoms / cm 3 or less, and particularly preferably 5 x 10 19 atoms / cm 3 or less.

[0109] In addition, when the oxide semiconductor that forms the semiconductor layer contains hydrogen, hydrogen reacts with oxygen bonded to a metal atom to generate water, and thus an oxygen vacancy is sometimes formed in the oxide semiconductor. In the case where the channel formation region in the oxide semiconductor contains an oxygen vacancy, the transistor tends to have a normally-on characteristic. Furthermore, a defect in which hydrogen enters an oxygen vacancy is sometimes used as a donor to generate an electron serving as a carrier. In addition, part of hydrogen is sometimes bonded to oxygen bonded to a metal atom, and an electron serving as a carrier is generated. Thus, a transistor using an oxide semiconductor containing a large amount of hydrogen tends to have a normally-on characteristic.

[0110] A defect in which hydrogen enters an oxygen vacancy is used as a donor of the oxide semiconductor. However, it is difficult to quantitatively evaluate the defect. Thus, in the oxide semiconductor, evaluation is sometimes performed not in accordance with the donor concentration but in accordance with the carrier concentration. Thus, in this specification and the like, as a parameter of the oxide semiconductor, the carrier concentration in a state where an electric field is not applied is sometimes used instead of the donor concentration. That is, the "carrier concentration" described in this specification and the like can be referred to as the "donor concentration".

[0111] Thus, it is preferable to reduce hydrogen in the oxide semiconductor as much as possible. Specifically, in the oxide semiconductor, the hydrogen concentration measured by secondary ion mass spectrometry (SIMS) is lower than 1 x 10 20 atoms / cm 3 , preferably lower than 1 x 10 19 atoms / cm 3 , more preferably lower than 5 x 10 18 atoms / cm 3 , and further preferably lower than 1 x 10 18 atoms / cm 3 . By using an oxide semiconductor in which impurities such as hydrogen are sufficiently reduced for the channel formation region of a transistor, stable electrical characteristics can be given.

[0112] Further, the semiconductor layer can have, for example, a non-single-crystal structure. The non-single-crystal structure includes, for example, a CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor) having a crystal with a c-axis aligned, a polycrystal structure, a microcrystal structure, or an amorphous structure. In the non-single-crystal structure, the amorphous structure has the highest density of defect states, and the CAAC-OS has the lowest density of defect states.

[0113] The oxide semiconductor film of the amorphous structure has, for example, an atomic arrangement without order and has no crystal component. Alternatively, the oxide film of the amorphous structure is, for example, completely amorphous and has no crystal portion.

[0114] Further, the semiconductor layer can be a mixed film of two or more of a region having an amorphous structure, a region having a microcrystal structure, a region having a polycrystal structure, a region having a CAAC-OS, and a region having a single-crystal structure. The mixed film has, for example, a single-layer structure or a stacked-layer structure including two or more of the above regions.

[0115] One embodiment of a CAC (Cloud-Aligned Composite)-OS of a non-single-crystal semiconductor layer will be described below.

[0116] The CAC-OS refers to a structure in which elements included in an oxide semiconductor are unevenly distributed, for example. The size of a material including elements unevenly distributed is greater than or equal to 0.5 nm and less than or equal to 10 nm, preferably greater than or equal to 1 nm and less than or equal to 2 nm or a size close thereto. Note that in the following, a region in which one or a plurality of metal elements are unevenly distributed in an oxide semiconductor and the region including the metal elements is mixed in a state where the size is greater than or equal to 0.5 nm and less than or equal to 10 nm, preferably greater than or equal to 1 nm and less than or equal to 2 nm or a size close thereto, is referred to as a mosaic or patch-like state.

[0117] The oxide semiconductor preferably contains at least indium. In particular, indium and zinc are preferably contained. In addition to the above, one or more selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium, and the like can be further contained.

[0118] For example, the CAC-OS in an In-Ga-Zn oxide (in the CAC-OS, the In-Ga-Zn oxide can be referred to as CAC-IGZO, in particular) refers to a structure in which a material is divided into an indium oxide (hereinafter referred to as InO X1 (X1 is a real number greater than 0) or an indium zinc oxide (hereinafter referred to as In X2 Zn Y2 O Z2(X2, Y2, and Z2 are real numbers greater than 0) and gallium oxide (hereinafter referred to as GaO X3 (X3 is a real number greater than 0) or gallium zinc oxide (hereinafter referred to as Ga X4 Zn Y4 O Z4 (X4, Y4, and Z4 are real numbers greater than 0) and the like are mixed in a mosaic manner, and the InO X1 or In X2 Zn Y2 O Z2 are uniformly distributed in the film (hereinafter, also referred to as cloudiness).

[0119] In other words, the CAC-OS is a composite oxide semiconductor having a structure in which a region with GaO X3 as a main component and a region with In X2 Zn Y2 O Z2 or InO X1 as a main component are mixed together. In this specification, for example, when the atomic ratio of In to the element M in a first region is higher than the atomic ratio of In to the element M in a second region, the In concentration in the first region is higher than that in the second region.

[0120] Note that IGZO is a general term, and sometimes refers to a compound containing In, Ga, Zn, and O. As a typical example, InGaO3(ZnO) m1 (m1 is a natural number) or In (1+x0) Ga (1-x0) O3(ZnO) m0 (-1 ≤ x0 < 1, and m0 is an arbitrary number) is given.

[0121] The above-described crystalline compound has a single crystal structure, a polycrystal structure, or a CAAC structure. The CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals have c-axis alignment and are connected in the a-b plane in a non-aligned manner.

[0122] On the other hand, the CAC-OS is related to the material composition of an oxide semiconductor. The CAC-OS refers to a structure in which, in a material composition containing In, Ga, Zn, and O, a region with Ga as a main component is observed in a part as a nanoparticle and a region with In as a main component is observed in a part as a nanoparticle, and each of the regions is irregularly dispersed in a mosaic manner. Thus, in the CAC-OS, the crystal structure is a secondary factor.

[0123] The CAC-OS does not include a stacked structure of two or more films having different compositions. For example, a structure including two layers of a film with In as a main component and a film with Ga as a main component is not included.

[0124] Note that a region having GaO X3 as a main component is not always observed. X2 Zn Y2 O Z2 or InO X1 as a main component.

[0125] In the case where CAC-OS includes one or more kinds selected from aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium, instead of gallium, CAC-OS refers to a structure in which a region having a nano-particle-like region in which the metal element is a main component and a region having a nano-particle-like region in which In is a main component are irregularly dispersed in a mosaic pattern.

[0126] CAC-OS can be formed, for example, by a sputtering method under conditions where intentional heating of a substrate is not performed. In the case where CAC-OS is formed by a sputtering method, as a film formation gas, one or more kinds selected from an inert gas (typically, argon), an oxygen gas, and a nitrogen gas can be used. Further, it is more preferable that the flow rate ratio of the oxygen gas in the total flow rate of the film formation gas at the time of film formation be lower, for example, the flow rate ratio of the oxygen gas is set to be 0 % or more and lower than 30 %, preferably 0 % or more and 10 % or less.

[0127] CAC-OS has a characteristic that a clear peak is not observed when measured by an Out-of-plane method, one of X-ray diffraction (XRD) measurement methods, by θ / 2θ scanning. That is, according to X-ray diffraction measurement, it is known that there is no orientation in the a-b plane direction and the c-axis direction in the measurement region.

[0128] Further, in an electron diffraction pattern of CAC-OS obtained by irradiation of an electron beam (also referred to as a nano-beam) having a beam diameter of 1 nm, a ring-shaped region having high brightness (a ring-shaped region) and a plurality of bright spots within the ring-shaped region are observed. Thus, according to the electron diffraction pattern, it is known that the crystal structure of CAC-OS has an nc (nano-crystal) structure having no orientation in the planar direction and the cross-sectional direction.

[0129] Further, for example, in CAC-OS of an In-Ga-Zn oxide, it is confirmed from an EDX mapping image obtained by energy dispersive X-ray spectroscopy (EDX) that a region having GaO X3 as a main component and a region having In X2 Zn Y2O Z2 or InO X1 are mixed.

[0130] The CAC-OS has different properties from the IGZO compound in which metal elements are uniformly distributed. In other words, the CAC-OS has a structure in which regions mainly composed of GaO X3 and the like and regions mainly composed of In X2 Zn Y2 O Z2 or InO X1 are separated from each other and the regions mainly composed of each element are in a mosaic pattern.

[0131] Here, the regions mainly composed of In X2 Zn Y2 O Z2 or InO X1 have higher conductivity than the regions mainly composed of GaO X3 and the like. In other words, when a carrier flows through the regions mainly composed of In X2 Zn Y2 O Z2 or InO X1 , the conductivity of an oxide semiconductor is exhibited. Thus, when the regions mainly composed of In X2 Zn Y2 O Z2 or InO X1 are distributed in an oxide semiconductor in a cloud shape, a high field-effect mobility (μ) can be achieved.

[0132] On the other hand, the regions mainly composed of GaO X3 and the like have higher insulating properties than the regions mainly composed of In X2 Zn Y2 O Z2 or InO X1 . In other words, when the regions mainly composed of GaO X3 and the like are distributed in an oxide semiconductor, a leakage current can be suppressed and good switching operation can be achieved.

[0133] Thus, when the CAC-OS is used for a semiconductor element, a high on-state current (I X3 ) and a high field-effect mobility (μ) can be achieved by a complementary action of the insulating properties of GaO X2 and the like and the conductivity of In Y2 Zn Z2 O X1 or InO on .

[0134] Further, the semiconductor element using the CAC-OS has high reliability. Therefore, the CAC-OS is suitable for a material constituting various semiconductor devices.

[0135] Note that, Figure 2 The structure in which the circuit 11 is provided in the pixel 20[1] is shown, but the circuit 11 can be provided in another pixel. Further, as shown in Figure 4 , the constituent elements of the circuit 11 can be provided in a plurality of regions in a dispersed manner.

[0136] For example, the transistor 101 can be provided in the pixel 20[1], the transistor 102 can be provided in the pixel 20[2], and the divided capacitor 104 can be provided in the pixel 20[n-1] and the pixel 20[n]. In this way, by providing the constituent elements of the circuit 11 in a dispersed manner, the number and the area occupied by the constituent elements such as the transistors and the capacitors provided in each pixel can be reduced, and thus the aperture ratio can be improved.

[0137] Note that, although not shown in Figure 4 , there can be a pixel in which the constituent elements of the circuit 11 are not provided. Further, there can be a plurality of the constituent elements provided in one pixel. Further, the capacitor can be provided in one pixel without being divided. Further, the number of the capacitors divided can be increased and the divided capacitors can be provided in three or more pixels.

[0138] Next, the operation method of the pixel block 12 shown in Figure 5 will be described with reference to the timing chart shown in Figure 2 or Figure 4 . Note that, in the following description, a high potential is denoted as "H" and a low potential is denoted as "L". Further, the weight supplied to the pixel 20[1] is denoted as "W[1]", the image data is denoted as "D[1]", the weight supplied to the pixel 20[2] is denoted as "W[2]", the image data is denoted as "D[2]", the weight supplied to the pixel 20[n-1] is denoted as "W[n-1]", the image data is denoted as "D[n-1]", the weight supplied to the pixel 20[n] is denoted as "W[n]", and the image data is denoted as "D[n]". As "V ref ", for example, 0 V, a GND potential, or a specific reference potential can be used.

[0139] Note that, here, detailed changes caused by the structure of the circuit, the operation timing, or the like are not taken into account in the distribution of the potential, the coupling, or the loss. The change in the potential caused by the capacitive coupling using the capacitor depends on the capacity ratio of the capacitor and the load connected to the capacitor, but for the sake of convenience of the description, it is assumed that the capacitance value of the circuit block 110 is sufficiently small.

[0140] First, the write operation of "W[1]" in the pixel 20[1] will be described.

[0141] At time Tl, "W[l]" is supplied to the wiring 125, and "V ref " is supplied to the wiring 126, and the potentials of the wirings 121, 122, 123[l] are made "H", whereby the transistor 102 is turned on, and the potential of the other electrode of the capacitor 104 is made "V ref ". This operation is a reset operation for the following addition operation (capacitive coupling operation).

[0142] In addition, the transistors 101, 103 are turned on, and the potential of the wiring 125 is written to the node NP[l]. This operation is a weight write operation, and the potential of the node NP[l] is made "W[l]".

[0143] At time T2, the potentials of the wirings 121, 122 are made "L", and the potential of the wiring 123[l] is made "H", whereby the transistors 101, 102 are not turned on. At this time, the node NP[l] holds "W[l]". Further, the capacitor 104 holds "W[l]-V ref ". Up to this point is the write operation of "W[l]" in the pixel 20[l].

[0144] Next, the addition operation of "D[l]" in the pixel 20[l] will be described.

[0145] At time T3, "D[l]" is supplied to the wiring 126, and the potential of the wiring 121 is made "L", and the potentials of the wirings 122, 123[l] are made "H", whereby the transistors 102, 103 are turned on. At this time, the potential of the other electrode of the capacitor 104 is made "D[l]", and "D[l]" is added to the potential of the node NP[l] due to capacitive coupling. This operation is an addition operation, and the potential of the node NP[l] is made "W[l]-V ref +D[l]". At this time, if "V ref "=0, the potential of the node NP[l] is made "W[l]+D[l]". The potential of the node NP[l] is supplied to the display element and display is performed.

[0146] At time T4, when the potentials of the wirings 121, 122, 123[l] are made "L", the transistor 103 is not turned on, and the potential of the node NP[l] is held, and display continues until the operation of the next frame. The above is the operation explanation of the pixel 20[l].

[0147] Next, the write operation of "W[2]" in the pixel 20[2] will be described.

[0148] At time T5, "W[2]" is supplied to the wiring 125, and "V ref", the potential of the wiring 121, 122, 123[2] is "H", whereby the transistor 102 is turned on, and the potential of the other electrode of the capacitor 104 is "V ref ".

[0149] In addition, the transistors 101, 103 are turned on, and the potential of the wiring 125 is written to the node NP[2]. This operation is a weight writing operation, and the potential of the node NP[2] is "W[2]".

[0150] At time T6, the potential of the wiring 121, 122 is made "L", and the potential of the wiring 123[2] is made "H", whereby the transistors 101, 102 are not turned on. At this time, the node NP[2] holds "W[2]". In addition, the capacitor 104 holds "W[2]-V ref ". Up to this point is the writing operation of "W[2]" in the pixel 20[2].

[0151] Next, the addition operation of "D[2]" in the pixel 20[2] will be described.

[0152] At time T7, "D[2]" is supplied to the wiring 126, the potential of the wiring 121 is made "L", and the potential of the wiring 122, 123[1] is made "H", whereby the transistors 102, 103 are turned on. At this time, the potential of the other electrode of the capacitor 104 is "D[2]", and "D[2]" is added to the potential of the node NP[1] due to capacitive coupling. This operation is an addition operation, and the potential of the node NP[1] is "W[2]-V ref +D[2]". At this time, if "V ref "=0, the potential of the node NP[2] is "W[2]+D[2]". The potential of the node NP[2] is supplied to the display element and displayed.

[0153] At time T8, when the potential of the wiring 121, 122, 123[2] is "L", the transistor 103 is not turned on, and the potential of the node NP[2] is held, and the display continues until the operation of the next frame. The above is the operation explanation of the pixel 20[2].

[0154] The potential of the node NP[2] is supplied to the display element and displayed. The above is the operation explanation of the pixel 20[2]. By causing the pixel 20[n-1] to perform the same operation at times T9 to T12, display corresponding to "W[n-1]+D[n-1]" can be performed in the pixel 20[n-1]. Further, by causing the pixel 20[n] to perform the same operation at times T13 to T16, display corresponding to "W[n]+D[n]" can be performed in the pixel 20[n].

[0155] By the above-described manner, the pixel block 12 can be operated.

[0156] Circuit 11 can also have Figure 6A The structure shown. Figure 6A The circuit 11 shown is Figure 2 or Figure 4 The difference in circuit 11 shown is that it includes transistor 105 and a source line.

[0157] The gate of transistor 105 is electrically connected to wiring 122. One of the source and drain of transistor 105 is electrically connected to the other electrode of capacitor 104. The other of the source and drain of transistor 105 is connected to a capacitor capable of supplying "V". ref The wiring is electrically connected to the source and drain of transistor 101 and the source and drain of transistor 102.

[0158] exist Figure 2 or Figure 4 In the structure of circuit 11 shown, data (D) and "V" are supplied alternately from wiring 126. ref ",exist Figure 6A In the structure of circuit 11 shown, "V" is supplied through a dedicated path. ref Therefore, weights (W) and data (D) can be supplied from wiring 125 in a switchable manner. Thus, one of the source lines can be reduced.

[0159] Reference Figure 7 The timing diagram shown illustrates that in Figure 2 or Figure 4 The pixel block 12 shown uses Figure 6A The circuit shown in Figure 11 is in operation.

[0160] At time T1, "W"[1] is supplied to wiring 125, making the potential of wirings 121 and 123[1] "H". As a result, transistor 105 is turned on, and the potential of the other electrode of capacitor 104 is "V". ref This function is used to reset the subsequent addition operation (capacitive coupling operation).

[0161] In addition, transistors 101 and 103 are turned on, and the potential of wiring 125 is written to node NP[1]. This operation is a weight writing operation, and the potential of node NP[1] is "W[1]".

[0162] At time T2, the potential of wiring 121 is set to "L" and the potential of wiring 123[1] is set to "H", and transistors 101 and 105 are not turned on. At this time, node NP[1] remains "W[1]". In addition, capacitor 104 remains "W[1]-V". ref "Up to this point, the writing of "W[1]" in pixel 20[1] has been completed.

[0163] At time T3, "D[1]" is supplied to the wiring 125, the potential of the wiring 121 is "L", the potentials of the wirings 122, 123[1] are "H", whereby the transistors 102, 103 are turned on. At this time, the potential of the other electrode of the capacitor 104 is "D[1]", and "D[1]" is added to the potential of the node NP[1] due to the capacitive coupling. This operation is an addition operation, and the potential of the node NP[1] is "W[1] - V ref +D[1]". At this time, if "V ref "=0, the potential of the node NP[1] is "W[1]+D[1]". The potential of the node NP[1] is supplied to the display element and display is performed.

[0164] At time T4, when the potentials of the wirings 121, 122, 123[1] are "L", the transistor 103 is not turned on, and the potential of the node NP[1] is held until the operation of the next frame and display is continued. The above is a description of the operation of the pixel 20[1].

[0165] By performing the same operation on the pixel 20[2] at times T5 to T8, display corresponding to "W[2]+D[2]" can be performed in the pixel 20[2]. Further, by performing the same operation on the pixel 20[n-1] at times T9 to T12, display corresponding to "W[n-1]+D[n-1]" can be performed in the pixel 20[n-1]. Further, by performing the same operation on the pixel 20[n] at times T13 to T16, display corresponding to "W[n]+D[n]" can be performed in the pixel 20[n].

[0166] The circuit 11 can also have the structure shown in Fig. 10. Figure 6B The circuit 11 shown in Fig. 10 differs from the circuit 11 shown in Fig. 1 in that the transistor 106 and the capacitor 107 are included. Figure 6B The circuit 11 shown in Fig. 10 differs from the circuit 11 shown in Fig. 1 in that the transistor 106 and the capacitor 107 are included. Figure 2 The circuit 11 shown in Fig. 10 differs from the circuit 11 shown in Fig. 1 in that the transistor 106 and the capacitor 107 are included. Figure 4 The circuit 11 shown in Fig. 10 differs from the circuit 11 shown in Fig. 1 in that the transistor 106 and the capacitor 107 are included.

[0167] One electrode of the capacitor 107 is electrically connected to the node NM. The other electrode of the capacitor 107 is electrically connected to one of the source and drain of the transistor 106. The gate of the transistor 106 is electrically connected to the wiring 127 which is used as a gate line. The other of the source and drain of the transistor 106 is electrically connected to the wiring 128 which is used as a source line.

[0168] Figure 6BThe circuit 11 shown includes two capacitors connected in parallel to the node NM, and various operations can be performed. For example, image correction can be performed by writing correction data for the threshold voltage of the drive transistor of the light emitting element to one of the capacitors and writing brightness correction data to the other capacitor. In addition, in an operation using a liquid crystal element, by using different capacitors in accordance with the polarity of the signal corresponding to the inversion operation, respectively, the polarity of the charge accumulated in both electrodes of the capacitor can be made constant. Therefore, the amount of charge supplied at the time of the inversion operation can be reduced, and the power consumption of the display device can be suppressed.

[0169] Figures 8A to 8C is an example of a structure that can be used for the circuit block 110 and that includes a light emitting element as a display element.

[0170] Figure 8A The structure shown includes a transistor 111, a capacitor 113, and a light emitting element 114. One of the source and drain of the transistor 111 is electrically connected to one electrode of the light emitting element 114. One electrode of the light emitting element 114 is electrically connected to one electrode of the capacitor 113. The other electrode of the capacitor 113 is electrically connected to the gate of the transistor 111. The gate of the transistor 111 is electrically connected to the node NP.

[0171] The other of the source and drain of the transistor 111 is electrically connected to a wiring 128. The other electrode of the light emitting element 114 is electrically connected to a wiring 129. The wirings 128, 129 have a function of supplying a power supply. For example, the wiring 128 can supply a high potential power supply. In addition, the wiring 129 can supply a low potential power supply.

[0172] In Figure 8A In the structure shown, current flows through the light emitting element 114 when the potential of the node NM is higher than the threshold voltage of the transistor 111. Due to this, sometimes the light emitting element 114 starts to emit light when the weight (W) is written to the node NP, resulting in a limitation in the use of the structure.

[0173] In addition, as Figure 8B shown, one electrode of the light emitting element 114 can be electrically connected to the wiring 128, and the other electrode of the light emitting element 114 can be electrically connected to the other of the source and drain of the transistor 111. This structure can also be used for other circuit blocks 110 that include the light emitting element 114.

[0174] Figure 8C is an example of a structure that can be used for the circuit block 110 and that includes a light emitting element as a display element. Figure 8AThe structure of the additional transistor 112 is described. One of the source and drain of transistor 112 is electrically connected to one of the source and drain of transistor 111. The other of the source and drain of transistor 112 is electrically connected to the light-emitting element 114. The gate of transistor 112 is electrically connected to wiring 127. Wiring 127 may function as a signal line to control the conduction of transistor 112.

[0175] In this structure, current flows through the light-emitting element 114 when the potential of node NP is above the threshold voltage of transistor 111 and transistor 112 is turned on. Therefore, the light-emitting element 114 can start emitting light at any timing after the addition of weights (W) and data (D).

[0176] Figure 8D Yes Figure 8C The structure of the additional transistor 115 is described. One of the source and drain of transistor 115 is electrically connected to one of the source and drain of transistor 111. The other of the source and drain of transistor 115 is electrically connected to wiring 131. The gate of transistor 115 is electrically connected to wiring 132. Wiring 132 may function as a signal line to control the conduction of transistor 115.

[0177] Wiring 131 can be electrically connected to a supply source of a specific potential, such as a reference potential. The writing of image data can also be stabilized by supplying a specific potential to one of the source and drain of transistor 111 from wiring 131.

[0178] Furthermore, wiring 131 can be connected to circuit 120 and can function as a monitoring line. Circuit 120 can have one or more of the following functions: a supply source for the specific potential, the ability to obtain the electrical characteristics of transistor 111, and the ability to generate correction data.

[0179] Figures 9A to 9D This is an example of a structure that can be used in circuit block 110 and include a liquid crystal element as a display element.

[0180] Figure 9A The structure shown includes a capacitor 116 and a liquid crystal element 117. One electrode of the liquid crystal element 117 is electrically connected to one electrode of the capacitor 116. One electrode of the capacitor 116 is electrically connected to the node NP.

[0181] The other electrode of capacitor 116 is electrically connected to wiring 133. The other electrode of liquid crystal element 117 is electrically connected to wiring 134. Wiring 133 and 134 have the function of supplying power. For example, wiring 133 and 134 can supply reference potentials such as GND and 0V or any potential.

[0182] Alternatively, it can be like Figure 9BThe capacitor 116 is omitted as illustrated. As described above, an OS transistor can be used as the transistor connected to the node NP. Since the leakage current of the OS transistor is extremely small, display can be maintained for a long time even if the capacitor 116 used as a holding capacitor is omitted. Further, the structure is not limited to that of the transistor, and in the case where the display period is shortened by high-speed operation using a field sequential driving method or the like, omission of the capacitor 116 is also effective. By omitting the capacitor 116, the aperture ratio can be improved. In addition, the transmittance of the pixel can be improved.

[0183] In Figure 9A and Figure 9B the structure, the operation of the liquid crystal element 117 is started when the potential of the node NP is set to be higher than the operation threshold value of the liquid crystal element 117. Thus, display operation can be started when the weight is written to the node NP, which can limit the use of the structure. Note that in a transmissive liquid crystal display device, for example, by turning off the back light until the addition operation of the weight (W) and the data (D) is completed, the display can be suppressed from being seen even if unnecessary display operation is performed.

[0184] Figure 9C is a structure in which the transistor 118 is added to the structure of Figure 9A . One of the source and drain of the transistor 118 is electrically connected to one of the electrodes of the capacitor 116. The other of the source and drain of the transistor 118 is electrically connected to the node NP. The gate of the transistor 118 is electrically connected to the wiring 130. The wiring 130 can have a function of a signal line which controls the conduction of the transistor 118.

[0185] In this structure, the liquid crystal element 117 is applied with the potential of the node NP while the transistor 118 is in conduction. Thus, the operation of the liquid crystal element can be started at an arbitrary timing after the addition operation of the weight (W) and the data (D).

[0186] Further, since the potential supplied to the capacitor 116 and the liquid crystal element 117 is continuously held in a state where the transistor 118 is not in conduction, it is preferable to reset the potential supplied to the capacitor 116 and the liquid crystal element 117 before rewriting the image data. In this reset, for example, a reset potential is supplied to the source line (e.g., the wirings 125, 126, and the like) connected to the pixel, and the transistor 101 and the transistor 118 are simultaneously made to be in conduction.

[0187] Figure 9D is a structure in which the transistor 119 is added to the structure of Figure 9C . One of the source and drain of the transistor 119 is electrically connected to one of the electrodes of the liquid crystal element 117. The other of the source and drain of the transistor 119 is electrically connected to the wiring 131. The gate of the transistor 119 is electrically connected to the wiring 132. The wiring 132 can have a function of a signal line which controls the conduction of the transistor 119.

[0188] The circuit 120 electrically connected to wiring 131 is as described above. Figure 8C Similarly, as described above, it can also have the function of resetting the potential supplied to capacitor 116 and liquid crystal element 117.

[0189] Figures 10A to 10C Show Figure 6A The middle part is used to supply "V" ref Specific examples of wiring using the "". For example... Figure 10A As shown, when using a light-emitting element as a display element, wiring 128 can be used to supply "V" ref The wiring of “V”. Because “V” ref "Preferred voltages are 0V, GND, or low voltage, so wiring 128 also has the function of supplying at least one of these voltages. Additionally, 'V' can be supplied to wiring 128 when data is written to node NP." ref ", and supplies a high-potential power supply to wiring 128 when the light-emitting element 114 emits light. Additionally, such as Figure 10B As shown, the wiring 129 supplying low potential can be used as a supply for "V". ref The wiring.

[0190] like Figure 10C As shown, when a liquid crystal element is used as a display element, wiring 133 can be used to supply "V" ref The wiring can be either 134 or 144. Note that the supply of "V" can be configured regardless of the type of display component. ref "Dedicated public cabling".

[0191] Furthermore, in one aspect of the invention, such as Figure 11A , Figure 11B As shown, the transistors included in pixel block 12 can also be configured with a back gate. Figure 11A The diagram shows a structure in which the back gate and front gate are electrically connected, which has the effect of improving the on-state current. Figure 11B The diagram shows a structure in which the back gate is electrically connected to wiring 135, which can supply a constant potential and control the threshold voltage of the transistor.

[0192] In addition, such as Figure 4 As shown in the timing diagram, the gate signal "H" is input to circuit 10 in a shifted manner at certain intervals. On the other hand, during the operation of each circuit 10, the gate signal "H" or "L" is input to circuit 11. This operation is repeated as many times as the number of circuits 10 included in the pixel block 12.

[0193] Therefore, as Figure 1As shown, the gate driver 14a of the control circuit 11 and the gate driver 14b of the control circuit 10 are preferably provided. By providing the gate drivers of the control circuits 10 and 11 respectively, the number of PWC (Pulse Width Control) signals required for operation can be made smaller than the number of circuits 10 included in the pixel block 12.

[0194] For example, Figure 12 is a view showing input and output signals of the gate drivers 14a and 14b. Here, the number of rows of pixels is 1280, and the number of pixels (circuits 10) included in the pixel block 12 is 4.

[0195] The signals input to the gate driver 14a can be SPL (a start pulse signal for the gate driver 14a), CLK[1:4]L (a clock signal for the gate driver 14a), PWC1, PWC2 (pulse width control signals for the gate signals), and the signals can be output to the gate lines GL1[1] to GL1

[320] and GL2[1] to GL2

[320] . Here, GL1 corresponds to the wiring 125, and GL2 corresponds to the wiring 126. Further, 320 coincides with the number of pixel blocks 12 provided in the vertical direction.

[0196] The signals input to the gate driver 14b can be SPR (a start pulse signal for the gate driver 14b), CLK[1:4]R (a clock signal for the gate driver 14b), and the signals can be output to the gate lines GL3[1] to GL3

[1280] . Here, GL3 corresponds to the wiring 123. Further, 1280 coincides with the number of pixels 20 provided in the vertical direction.

[0197] Figure 13 is an example of a block diagram of the gate driver 14a. The gate driver 14a includes a shift register circuit composed of a plurality of set-reset flip-flops and a buffer circuit (BuF). One stage of the shift register circuit is denoted by "SR", and a dummy stage is denoted by "DUM". RES is a reset signal, and by inputting "H", the outputs of the shift register circuit can be all set to "L".

[0198] The "BuF" includes an AND circuit, and can output signals to the gate lines (GL1 and / or GL2) using the output signal (SROUT signal) of the "SR", the PWC1 signal, and the PWC2 signal.

[0199] The "SR" can have, for example, Figure 15A the block diagram shown in Figure 15BThe structure of the circuit diagram shown. Here, LIN indicates a shift signal input from the preceding stage "SR", FO indicates an output signal that controls the transistor included in "Buf", and RIN indicates a reset signal input from the succeeding stage "SR". Note that the input clock signal can be, for example, a combination of CLK[1]L and CLK[3]L or a combination of CLK[2]L and CLK[4]L.

[0200] The buffer circuit (BuF) can have Figure 16A the block diagram shown, and Figure 16B The structure of the circuit diagram shown. Here, FN indicates a signal (FO) input from "SR", and LN indicates a signal (SROUT) input from "SR".

[0201] Figure 14 One example of a block diagram of the gate driver 14b is shown. The gate driver 14b includes a shift register circuit composed of a plurality of set-reset flip-flops. The stage of the shift register circuit is indicated by "SR", and the dummy stage is indicated by "DUM". The "SR" can have, for example, Figure 17A the block diagram shown, and Figure 17B The structure of the circuit diagram shown.

[0202] Next, the simulation results regarding the pixel block 12 are described. Figure 18 The structure of the pixel block 12 used for simulation is shown. Figure 19 A timing chart used for simulation is shown. The number of pixels included in the pixel block 12 is 4, and the circuit block 110 has Figure 9A The structure shown (liquid crystal element and capacitor). The voltage change of the node NP at the time when each pixel is sequentially operated is simulated.

[0203] The parameters used for simulation are as follows: the transistor size is L / W = 4 μm / 4 μm (transistors included in the pixel block 12); the capacitance value of the capacitor Cl is 500 fF; the capacitance value of the capacitor Cs is 100 fF; the capacitance value of the liquid crystal element Clc is 100 fF; the common electrodes VCOM and TCOM are 0 V. Further, as the voltage applied to the gate of the transistor, "H" is set to +15 V and "L" is set to -10 V. In addition, as the circuit simulation software, SPICE is used. Here, Figure 18 The parasitic capacitance of the wiring PL shown is not included in the parameters.

[0204] Figure 19 is a timing chart used for simulation. Here, the weights (W[1] to [4]) and the data (D[1] to [4]) are both 5 V. "V ref " is 0 V.

[0205] Figure 20AAnalog results when the weights (W[1] to [4]) and the data (D[1] to [4]) are all 5V and "V ref " is 0V are shown. The horizontal axis indicates time, and the vertical axis indicates the voltage of the node NP. In each node NP, it is confirmed that the weights (W) and the data (D) are added according to the capacitance ratio.

[0206] Figure 20B Analog results when the weight (W[1]) and the data (D[2]) are 5V, the weight (W[2]) and the data (D[2]) are 2.5V, the weight (W[3]) and the data (D[3]) are -2.5V, the weight (W[4]) and the data (D[4]) are -5V, and "V ref " is 0V are shown. In each node NP, it is confirmed that the weights (W) and the data (D) are added according to the capacitance ratio. In addition, because the addition operation can be performed regardless of the polarity of the weights and the data within the same pixel block 12, gate line inversion driving can be performed.

[0207] Thus, it is confirmed that the pixel block 12 of one embodiment of the present application can normally perform the addition operation of the weights (W) and the data (D) within a range not affected by the parasitic capacitance of the wiring PL.

[0208] Next, analog results regarding the pixel layout are described. Figure 21 The basic structure is Figure 18 the pixel block 12 shown in FIG. 8, Figure 21 One example of the layout of three pixels in the vertical direction is shown for the mth column and the (m+1)th column.

[0209] In the layout shown in Figure 21 , the constituent elements up to the pixel electrode PE corresponding to the node NP are shown and Cs is omitted. A bottom-gate type (with a back gate) transistor is shown as one example of a transistor.

[0210] The transistors Trl, Tr2 are included in the first row of pixels of the pixel block 12. Thus, as the number of transistors included in each row, the first row is three transistors Trl, Tr2, Tr3, and one transistor Tr3 after the second row. Note that the size of the transistors Trl, Tr2 is assumed to be L / W = 4 μm / 30 μm, and the size of the transistor Tr3 is assumed to be L / W = 4 μm / 10 μm. The pixel pitch is assumed to be about 136 μm (the pixel pitch of the transistors of the first row and the transistors after the second row is different).

[0211] A conductive layer manufactured in the same process as the gate wiring and a conductive layer manufactured in the same process as the source wiring are used as a pair of electrodes for C1. These two conductive layers are arranged parallel to the source lines SL1 and SL2, and each pixel has an overlapping region separated by an insulating layer (e.g., a gate insulating film). That is, each pixel contains a capacitor. Because these capacitors are connected in parallel, they are equivalent to a large capacitor.

[0212] In other words, by segmenting and configuring capacitor C1, the aperture ratio and transmittance of the pixels can be improved. Note that it is preferable to use the connection wiring BR, which is a bridging gate wiring, to make electrical connections between conductive layers constituting the capacitor. For example, the connection wiring BR can be manufactured using the same process as the source wiring.

[0213] Here, because the first row of pixels contains transistors Tr1 and Tr2 and their driving gate lines, it has a greater number of constituent elements compared to pixels in other rows. For example... Figure 22A As shown in Type 1, when the vertical length of all pixels is unified to A, pixel electrode PE1 becomes smaller than pixel electrodes PE2 and PE3. Therefore, sometimes the display of the first column is perceived as a dark line.

[0214] Therefore, as Figure 22B As shown in Type 2, the vertical length of all pixel electrodes can be unified to B, making the vertical length of the first row of pixels greater than that of the pixels in the second row and beyond. Alternatively, the vertical length of each pixel can be adjusted so that pixel electrode PE1 is greater than pixel electrodes PE2 and PE3. By employing this structure, the first row of the display can be suppressed from being perceived as a dark line.

[0215] Figure 23 The diagram shows an estimated aperture ratio when using a type 1 or type 2 pixel block as shown in Figure 22 as a display area. The aperture ratio shown here is (area of ​​all pixel electrodes within the pixel block) / (area of ​​the pixel block). In the estimation, the number of pixels included in the pixel block ranges from 1 to 4000. It is assumed that the pixels of type 1 are all square pixels with a side length of 136 μm. In type 2, when the number of pixels is 1, the pixel is a square pixel with a side length of 136 μm; when the number of pixels is 2 or more, the vertical length is adjusted so that the pixel electrodes have the same size. For comparison with type 1, the vertical length of the pixel block is the same as when using square pixels with a side length of 136 μm.

[0216] like Figure 23As shown, both Type 1 and Type 2 have a tendency that the aperture ratio sharply increases as the number of pixels in the pixel block reaches about 10, and the aperture ratio reaches 81% when the number of pixels is about 20. Thereafter, the aperture ratio slowly increases, and the aperture ratio approaches 82% when the number of pixels is 100. Thus, in the case where the aperture ratio is valued, it is preferable that the number of pixels in the pixel block be as large as possible. However, when the effective effect on the pixel layout is taken into consideration, it is preferable that the number of pixels in the pixel block be about 5 to 100, more preferably about 10 to 50, and further preferably about 20 to 40.

[0217] According to the simulation results above, the effect of one embodiment of the present application can be confirmed.

[0218] This embodiment mode can be implemented in combination with the structures described in other embodiment modes and the like as appropriate.

[0219] (Embodiment 2)

[0220] This embodiment mode describes a structure example of a display device using a liquid crystal element and a structure example of a display device using a light emitting element. Note that the components, operation, and functions of the display device described in Embodiment 1 are omitted in this embodiment mode.

[0221] Figures 24A to 24C A structure of a display device which can use one embodiment of the present application is shown.

[0222] In Figure 24A , a sealant 4005 is provided so as to surround a display portion 215 provided over a first substrate 4001, and the display portion 215 is sealed with the sealant 4005 and a second substrate 4006.

[0223] The pixel block 12 described in Embodiment 1 or the like can be provided in the display portion 215. Note that a scan line driver circuit described below corresponds to a gate driver, and a signal line driver circuit corresponds to a source driver.

[0224] In Figure 24A , the scan line driver circuit 221a, the signal line driver circuit 231a, the signal line driver circuit 232a, and the common line driver circuit 241a each include a plurality of integrated circuits 4042 provided over a printed board 4041. The integrated circuits 4042 are formed of a single-crystal semiconductor or a polycrystal semiconductor. The common line driver circuit 241a has a function of supplying a prescribed potential to the wires 128, 129, 132, 133, and 135 described in Embodiment 1 or the like.

[0225] Various signals and potentials are supplied to the scan line driver circuit 221a, the common line driver circuit 241a, the signal line driver circuit 231a, and the signal line driver circuit 232a through FPCs 4018.

[0226] The integrated circuits 4042 included in the scan line driver circuit 221a and the common line driver circuit 241a have a function of supplying a selection signal to the display portion 215. The integrated circuits 4042 included in the signal line driver circuit 231a and the signal line driver circuit 232a have a function of supplying image data to the display portion 215. The integrated circuits 4042 are mounted in a region different from a region surrounded by the sealant 4005 on the first substrate 4001.

[0227] Note that there is no particular limitation on a connection method of the integrated circuits 4042, and a wire bonding method, a COG (Chip On Glass) method, a TCP (Tape Carrier Package) method, a COF (Chip On Film) method, or the like can be used.

[0228] Figure 24B An example in which the integrated circuits 4042 included in the signal line driver circuit 231a and the signal line driver circuit 232a are mounted by the COG method is illustrated. In addition, by forming part or all of a driver circuit on a substrate on which the display portion 215 is formed, a system-on-panel can be formed.

[0229] Figure 24B An example in which the scan line driver circuit 221a and the common line driver circuit 241a are formed on a substrate on which the display portion 215 is formed is illustrated. By simultaneously forming a driver circuit and a pixel circuit in the display portion 215, the number of components can be reduced. Thus, the productivity can be improved.

[0230] In addition, in Figure 24B , the sealant 4005 is provided so as to surround the display portion 215, the scan line driver circuit 221a, and the common line driver circuit 241a provided over the first substrate 4001. The second substrate 4006 is provided over the display portion 215, the scan line driver circuit 221a, and the common line driver circuit 241a. Thus, the display portion 215, the scan line driver circuit 221a, and the common line driver circuit 241a are sealed together with a display element by the first substrate 4001, the sealant 4005, and the second substrate 4006.

[0231] Although in Figure 24BAnother example in which the signal line driver circuits 231a and 231b are formed separately and mounted to the first substrate 4001 is illustrated in FIG. 1A, but one embodiment of the present application is not limited to this structure. The signal line driver circuits can be formed separately and mounted, or part of the signal line driver circuits or part of the scan line driver circuits can be formed separately and mounted. In addition, as illustrated in FIG. 1B, the signal line driver circuits 231a and 231b can be formed on a substrate on which the display portion 215 is formed. Figure 24C

[0232] Further, a display device at times includes a panel in which a display element is in a sealed state and a module in which an IC or the like including a controller is mounted.

[0233] In addition, the display portion and the scan line driver circuit provided over the first substrate include a plurality of transistors. As the transistors, the transistors described in the above embodiment can be used.

[0234] The structures of the transistors included in the peripheral driver circuit and the transistors included in the pixel circuit of the display portion can be the same or different. The transistors included in the peripheral driver circuit can all have the same structure or a plurality of structures can be combined. Similarly, the transistors included in the pixel circuit can all have the same structure or a plurality of structures can be combined.

[0235] In addition, an input device 4200 can be provided over the second substrate 4006. The structure of the display device illustrated in FIG. 1C can be used as a touch panel. Figures 24A to 24C

[0236] The sensing element (also referred to as a sensor element) included in the touch panel of one embodiment of the present application is not particularly limited. Various sensors capable of detecting the approach or contact of a detection object such as a finger or a stylus can be used as the sensing element.

[0237] As a mode of the sensor, for example, various modes such as an electrostatic capacity method, a resistance film method, a surface acoustic wave method, an infrared method, an optical method, and a pressure-sensitive method can be used.

[0238] In this embodiment, a touch panel including a sensing element of the electrostatic capacity method is described as an example.

[0239] As the electrostatic capacity method, a surface type electrostatic capacity method, a projection type electrostatic capacity method, or the like can be used. As the projection type electrostatic capacity method, a self-capacitance method, a mutual-capacitance method, or the like can be used. The mutual-capacitance method is preferable because multi-point sensing can be performed at the same time.

[0240] ​​The touch panel of one embodiment of the present application can employ various structures, such as a structure in which a separately manufactured display device and a sensing element are attached, a structure in which an electrode or the like that constitutes a sensing element is provided in one or both of a substrate that supports a display element and an opposing substrate, and the like.

[0241] Figure 25A and Figure 25B An example of a touch panel is shown. Figure 25A is a perspective view of a touch panel 4210. Figure 25B is a perspective view of an input device 4200. Note that only typical constituent elements are shown for clarity.

[0242] The touch panel 4210 has a structure in which a separately manufactured display device and a sensing element are attached.

[0243] The touch panel 4210 includes an input device 4200 and a display device which are provided to overlap with each other.

[0244] The input device 4200 includes a substrate 4263, an electrode 4227, an electrode 4228, a plurality of wirings 4237, a plurality of wirings 4238, and a plurality of wirings 4239. For example, the electrode 4227 can be electrically connected to the wiring 4237 or the wiring 4239. The electrode 4228 can be electrically connected to the wiring 4239. An FPC 4272b can be electrically connected to the plurality of wirings 4237 and the plurality of wirings 4238, respectively. The FPC 4272b can be provided with an IC 4273b.

[0245] Alternatively, a touch sensor can be provided between the first substrate 4001 and the second substrate 4006 of the display device. When a touch sensor is provided between the first substrate 4001 and the second substrate 4006, an optical touch sensor using a photoelectric conversion element can be used in addition to an electrostatic capacity touch sensor.

[0246] Figure 26A and Figure 26B is a cross-sectional view along the dot-dash line N1-N2 in Figure 24B . Figure 26A and Figure 26B The display device illustrated in FIGS. 1A and 1B includes an electrode 4015 electrically connected to a terminal of an FPC 4018 by an anisotropic conductive layer 4019. Note that in Figure 26A and Figure 26B In FIGS. 4A and 4B, the electrode 4015 is electrically connected to the wiring 4014 formed in an opening in the insulating layer 4112, the insulating layer 4111, and the insulating layer 4110.

[0247] The electrode 4015 is formed using the same conductive layer as the first electrode layer 4030, and the wiring 4014 is formed using the same conductive layer as the source and drain electrodes of the transistor 4010 and the transistor 4011.

[0248] In addition, the display portion 215 and the scan line driver circuit 221a provided over the first substrate 4001 include a plurality of transistors, in Figure 26A and Figure 26B In FIGS. 4A and 4B, a transistor 4010 in the display portion 215 and a transistor 4011 in the scan line driver circuit 221a are illustrated. Although Figure 26A and Figure 26B In FIGS. 4A and 4B, a transistor 4010 in the display portion 215 and a transistor 4011 in the scan line driver circuit 221a are illustrated. Although

[0249] In FIGS. 4A and 4B, a transistor 4010 in the display portion 215 and a transistor 4011 in the scan line driver circuit 221a are illustrated. Although Figure 26B and Figure 26A In FIGS. 4A and 4B, a transistor 4010 in the display portion 215 and a transistor 4011 in the scan line driver circuit 221a are illustrated. Although Figure 26B In FIGS. 4A and 4B, a transistor 4010 in the display portion 215 and a transistor 4011 in the scan line driver circuit 221a are illustrated. Although

[0250] In addition, the transistor 4010 and the transistor 4011 are provided over the insulating layer 4102. Further, the transistor 4010 and the transistor 4011 include an electrode 4017 formed over the insulating layer 4111. The electrode 4017 can be used as a back gate electrode.

[0251] In addition, Figure 26A and Figure 26A The display device illustrated in FIGS. 4A and 4B includes a capacitor 4020. The capacitor 4020 includes an electrode 4021 formed in the same step as a gate electrode of the transistor 4010 and an electrode formed in the same step as a source electrode and a drain electrode. Each of the electrodes overlaps with the other with the insulating layer 4103 interposed therebetween.

[0252] In general, the capacity of a capacitor provided in a pixel portion of a display device is set so that the capacitor can hold electric charge for a specified period, taking into account the leakage current of a transistor provided in the pixel portion or the like. The capacity of the capacitor can be set taking into account the off-state current of the transistor or the like.

[0253] The transistor 4010 provided in the display portion 215 is electrically connected to a display element. Figure 26A is an example of a liquid crystal display device in which a liquid crystal element is used as a display element. In Figure 26A In FIGS. 4A and 4B, a transistor 4010 in the display portion 215 and a transistor 4011 in the scan line driver circuit 221a are illustrated. Although

[0254] As the liquid crystal element 4013, a liquid crystal element using various modes can be used. For example, a liquid crystal element using a VA (Vertical Alignment) mode, a TN (Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an ASM (Axially Symmetric Aligned Micro-cell) mode, an OCB (Optically Compensated Bend) mode, an FLC (Ferroelectric Liquid Crystal) mode, an AFLC (Anti-Ferroelectric Liquid Crystal) mode, an ECB (Electrically Controlled Birefringence) mode, a VA-IPS (Vertical Alignment In-Plane-Switching) mode, a guest-host mode, or the like can be used.

[0255] In addition, a normally black liquid crystal display device, such as a transmissive liquid crystal display device using a vertical alignment (VA) mode, can be used for the liquid crystal display device shown in this embodiment. As the vertical alignment mode, a MVA (Multi-Domain Vertical Alignment) mode, a PVA (Patterned Vertical Alignment) mode, an ASV (Advanced Super View) mode, or the like can be used.

[0256] A liquid crystal element is an element that controls transmission or non-transmission of light by using an optical modulation effect of liquid crystal. The optical modulation effect of liquid crystal is controlled by an electric field (a horizontal electric field, a vertical electric field, or a tilted direction electric field) applied to the liquid crystal. As the liquid crystal used for the liquid crystal element, a thermotropic liquid crystal, a low-molecular liquid crystal, a high-molecular liquid crystal, a high-molecular dispersion type liquid crystal (PDLC: Polymer Dispersed Liquid Crystal), a ferroelectric liquid crystal, an anti-ferroelectric liquid crystal, or the like can be used. These liquid crystal materials exhibit a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, or the like depending on conditions.

[0257] Although FIG. 26 illustrates an example of a liquid crystal display device including a liquid crystal element having a vertical electric field mode, a liquid crystal display device including a liquid crystal element having a horizontal electric field mode can be used for one embodiment of the present application. In the case of employing a horizontal electric field mode, a liquid crystal exhibiting a blue phase for which an alignment film is unnecessary can be used. A blue phase is one of the phases of liquid crystals, which appears just before the cholesteric phase changes into the isotropic phase upon heating and cooling of cholesteric liquid crystals. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition in which a specific substance is mixed at 5 wt% or more is used for the liquid crystal layer 4008 in order to expand the temperature range. Since the liquid crystal composition including a liquid crystal exhibiting a blue phase and a specific substance has a high response speed and has optical isotropy, the liquid crystal composition is preferably used. Further, the liquid crystal composition including a liquid crystal exhibiting a blue phase and a specific substance does not require an alignment process and has a small viewing angle dependence. In addition, since an alignment film does not need to be provided, rubbing treatment is not necessary, and thus electrostatic breakdown due to the rubbing treatment can be prevented and defects and damage of the liquid crystal display device in the manufacturing process can be reduced.

[0258] The spacer 4035 is a columnar spacer obtained by etching an insulating layer selectively, and is provided to control the distance (cell gap) between the first electrode layer 4030 and the second electrode layer 4031. Note that a spherical spacer can also be used.

[0259] In addition, as necessary, an optical member (optical substrate) such as a black matrix (light-blocking layer), a coloring layer (color filter), a polarizing member, a phase difference member, an anti-reflection member, or the like can be provided as appropriate. For example, circular polarization using a polarizing substrate and a phase difference substrate can be used. In addition, as a light source, a backlight or a side light or the like can be used. As the above-described backlight or side light, a Micro-LED or the like can be used.

[0260] In Figure 26B In the display device illustrated in FIG. 26, a light-blocking layer 4132, a coloring layer 4131, and an insulating layer 4133 are provided between the substrate 4006 and the second electrode layer 4031.

[0261] As a material that can be used for the light-blocking layer, carbon black, titanium black, a metal, a composite oxide of a metal oxide or a solid solution including a plurality of metal oxides, or the like can be given. The light-blocking layer can be a film including a resin material or a thin film including an inorganic material such as a metal. Alternatively, a stacked film of a film including a material of a coloring layer can be used for the light-blocking layer. For example, a stacked structure of a film including a material of a coloring layer for transmitting light of a certain color and a film including a material of a coloring layer for transmitting light of another color can be employed. By making the material of the coloring layer and the material of the light-blocking layer the same, in addition to the use of the same equipment, process simplification can be achieved, and is thus preferable.

[0262] As a material that can be used for the colored layer, a metal material, a resin material, a resin material containing a pigment or a dye, or the like can be given. The light-blocking layer and the colored layer can be formed using, for example, an inkjet method or the like.

[0263] In addition, Figure 26B and Figure 27 The display device illustrated in FIG. 41A includes an insulating layer 4111 and an insulating layer 4104. As the insulating layer 4111 and the insulating layer 4104, an insulating layer through which impurity elements are unlikely to penetrate is used. By sandwiching the semiconductor layer of the transistor with the insulating layer 4111 and the insulating layer 4104, entry of impurities from the outside can be prevented.

[0264] Further, as a display element included in a display device, a light-emitting element can be used. As the light-emitting element, an EL element utilizing electroluminescence, for example, can be used. An EL element has a layer containing a light-emitting organic compound (also referred to as EL layer) between a pair of electrodes. When voltage is applied across the pair of electrodes, holes injected from the electrode on the anode side and electrons injected from the electrode on the cathode side are recombined, and thus the light-emitting substance included in the EL layer emits light.

[0265] An EL element is classified into, on the basis of whether light-emitting materials are organic compounds or inorganic compounds, an organic EL element in which light-emitting materials are organic compounds and an inorganic EL element in which light-emitting materials are inorganic compounds.

[0266] In an organic EL element, by application of voltage, electrons are injected from one electrode into the EL layer, and holes are injected from the other electrode into the EL layer. By recombination of these carriers (electrons and holes), a light-emitting organic compound forms an excited state, and thus emits light when returning to a ground state from the excited state. Due to this mechanism, such a light-emitting element is called a current-excitation light-emitting element.

[0267] The EL layer can include, in addition to a light-emitting compound, a substance having a high hole- injecting property, a substance having a high hole-transport property, a hole-blocking material, a substance having a high electron-transport property, a substance having a high electron-injecting property, or a substance having a bipolar property (a substance having both a high hole-transport property and a high electron-transport property), or the like.

[0268] The EL layer can be formed by a method such as an evaporation method (including a vacuum evaporation method), a transfer method, a printing method, an inkjet method, or a coating method.

[0269] Inorganic EL elements are classified, depending on their element structures, into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements. A dispersion-type inorganic EL element includes a light-emitting layer in which particles of a light-emitting material are dispersed in a binder, and its light-emitting mechanism is donor-acceptor recombination-type light emission utilizing a donor level and an acceptor level. A thin-film-type inorganic EL element is a structure in which a light-emitting layer is sandwiched between dielectric layers, and the dielectric layers sandwiching the light-emitting layer are sandwiched between electrodes, and its light-emitting mechanism is localized-type light emission utilizing an inner-shell electron transition of a metal ion. Note that an organic EL element is described here as a light-emitting element.

[0270] At least one of a pair of electrodes of the light-emitting element is made to be transparent in order to extract light emission. A transistor and a light-emitting element are formed over a substrate, and a top emission structure in which light emission is extracted from a surface on the opposite side to the substrate, a bottom emission structure in which light emission is extracted from a surface on the substrate side, and a dual emission structure in which light emission is extracted from both surfaces can be employed as the light-emitting element.

[0271] Figure 27 This is an example of a light-emitting display device (also referred to as "EL display device") in which a light-emitting element is used as a display element. The light-emitting element 4513 used as a display element is electrically connected to the transistor 4010 provided in the display portion 215. Although the light-emitting element 4513 has a stacked structure of a first electrode layer 4030, a light-emitting layer 4511, and a second electrode layer 4031, the structure is not limited thereto. The structure of the light-emitting element 4513 can be changed as appropriate depending on the direction in which light is extracted from the light-emitting element 4513, and the like.

[0272] The partition wall 4510 is formed using an organic insulating material or an inorganic insulating material. It is particularly preferable to use a photosensitive resin material, form an opening portion in the first electrode layer 4030, and form a side surface of the opening portion into an inclined surface having a continuous curvature.

[0273] The light-emitting layer 4511 can be formed using one layer or a stacked layer of a plurality of layers.

[0274] The light-emitting color of the light-emitting element 4513 can be white, red, green, blue, cyan, magenta, yellow, or the like depending on a material of the light-emitting layer 4511.

[0275] As a method of realizing color display, there are a method of combining a light emitting element 4513 whose emission color is white and a colored layer, and a method of providing a light emitting element 4513 whose emission color is different for each pixel. The former method is higher in productivity than the latter method. On the other hand, in the latter method, a light emitting layer 4511 needs to be formed for each pixel, so it is lower in productivity than the former method. However, in the latter method, a light emission color whose color purity is higher than that of the former method can be obtained. By providing the light emitting element 4513 with a microcavity structure in the latter method, the color purity can be further improved.

[0276] The light emitting layer 4511 can also contain an inorganic compound such as a quantum dot. For example, by using a quantum dot for the light emitting layer, it can also be used as a light emitting material.

[0277] In order to prevent oxygen, hydrogen, moisture, carbon dioxide, and the like from intruding into the light emitting element 4513, a protective layer can also be formed on the second electrode layer 4031 and the partition wall 4510. As the protective layer, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum oxynitride, DLC (Diamond Like Carbon), or the like can be formed. Further, a filler 4514 is provided in a space sealed by the first substrate 4001, the second substrate 4006, and the sealing agent 4005 and is sealed. In this way, in order not to be exposed to external gas, it is preferable to use a protective film (adhesive film, ultraviolet-cured resin film, or the like) that is high in airtightness and less in outgassing, a cover material, for packaging (encapsulation).

[0278] As the filler 4514, in addition to an inert gas such as nitrogen or argon, an ultraviolet-cured resin or a heat-cured resin can also be used, and for example, PVC (polyvinyl chloride), an acrylic resin, polyimide, an epoxy resin, a silicone resin, PVB (polyvinyl butyral), or EVA (ethylene-vinyl acetate), or the like can be used. The filler 4514 can also contain a desiccant.

[0279] As the sealing agent 4005, a glass material such as a glass powder or a resin material that is cured at room temperature such as a two-liquid mixed type resin, a photocurable resin, a heat-cured resin, or the like can be used. The sealing agent 4005 can also contain a desiccant.

[0280] In addition, as needed, an optical film such as a polarizing plate or a circularly polarizing plate (including an elliptically polarizing plate), a phase difference plate (λ / 4 plate, λ / 2 plate), a color filter, or the like can also be appropriately provided on the light emission surface of the light emitting element. Further, an antireflection film can also be provided on the polarizing plate or the circularly polarizing plate. For example, an anti-glare treatment that is a treatment of reducing reflected glare by diffusing reflected light using the unevenness of the surface can be performed.

[0281] By incorporating a microcavity structure into the light-emitting element, it is possible to extract light with high color purity. Furthermore, by combining the microcavity structure with color filters, reflected glare can be prevented, thereby improving image visibility.

[0282] Regarding the first electrode layer and the second electrode layer (also known as the pixel electrode layer, common electrode layer, counter electrode layer, etc.) that apply voltage to the display element, their light transmittance and reflectivity can be selected according to the direction of light extraction, the location of the electrode layer, and the pattern structure of the electrode layer.

[0283] As the first electrode layer 4030 and the second electrode layer 4031, transparent conductive materials such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide with added silicon oxide can be used.

[0284] Furthermore, the first electrode layer 4030 and the second electrode layer 4031 may be formed from one or more of the following metals, alloys, and nitrides: tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), cobalt (Co), nickel (Ni), titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), and silver (Ag).

[0285] Furthermore, the first electrode layer 4030 and the second electrode layer 4031 can be formed using a conductive composition containing a conductive polymer (also known as a conductive polymer). As the conductive polymer, so-called π-electron conjugated conductive polymers can be used. Examples include polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives, or copolymers or derivatives thereof composed of two or more of aniline, pyrrole, and thiophene.

[0286] Furthermore, since transistors are easily damaged by static electricity, etc., it is preferable to provide a protection circuit to protect the drive circuit. The protection circuit is preferably constructed using non-linear components.

[0287] Note that, as Figure 26A As shown, a stacked structure in which transistors and capacitors include overlapping regions in the height direction can also be used. For example, by arranging transistors 4011 and 4022, which form the driving circuit in an overlapping manner, a narrow bezel display device can be realized. Furthermore, by arranging transistors 4010, 4023, capacitors 4020, etc., that form the pixel circuit in a manner that partially includes overlapping regions, the aperture ratio and resolution can be improved. In addition, in Figure 26B The middle shows the Figure 28A The liquid crystal display device shown is an example of using a multilayer structure, but this structure can also be applied to... Figure 28B The EL display device shown.

[0288] Further, in the pixel circuit, a light-transmitting conductive film having high light transmittance to visible light is used as an electrode and a wiring, and the light transmittance in the pixel can be increased, so that the aperture ratio can be substantially increased. Further, since the semiconductor layer also has light transmittance when an OS transistor is used, the aperture ratio is further increased. This is also effective when a transistor or the like does not employ a stacked structure.

[0289] Further, a display device can be configured by combining a liquid crystal display device and a light-emitting device.

[0290] The light-emitting device is provided on the side opposite to the display surface or on the end portion of the display surface. The light-emitting device has a function of supplying light to the display element. The light-emitting device is called a backlight.

[0291] Here, the light-emitting device can include a plate-shaped or film-shaped light guide portion (also referred to as a light guide plate), and a plurality of light-emitting elements which emit light of different colors. By providing the light-emitting elements near the side surface of the light guide portion, light can be emitted from the side surface of the light guide portion. The light guide portion includes a mechanism for changing the light path (also referred to as a light extraction mechanism), and thus the light-emitting device can uniformly irradiate light to the pixel portion of the display panel. Alternatively, a structure in which the light-emitting device is provided directly below the pixel without the light guide portion can be employed.

[0292] The light-emitting device preferably includes light-emitting elements of three colors of red (R), green (G), and blue (B). Further, a light-emitting element of white (W) can be included. As the light-emitting elements, light-emitting diodes (LEDs) are preferably used.

[0293] Further, the light-emitting element is preferably a light-emitting element having extremely high color purity in which the full width at half maximum (FWHM) of an emission spectrum is 50 nm or less, preferably 40 nm or less, more preferably 30 nm or less, and still more preferably 20 nm or less. Note that the smaller the full width at half maximum of the emission spectrum, the better, and for example, can be 1 nm or more. Thus, when color display is performed, display with high color reproducibility can be performed.

[0294] Further, the light-emitting element of red is preferably an element in which the peak wavelength of an emission spectrum is in a range of 625 nm or more and 650 nm or less. Further, the light-emitting element of green is preferably an element in which the peak wavelength of an emission spectrum is in a range of 515 nm or more and 540 nm or less. The light-emitting element of blue is preferably an element in which the peak wavelength of an emission spectrum is in a range of 445 nm or more and 470 nm or less.

[0295] The display device drives the pixels in synchronization with the emission of the light emitting elements of the three colors in sequence, and performs color display by the successive-adding color mixing method. This driving method can also be referred to as a field sequential driving method.

[0296] The field sequential driving method can display a bright color image. In addition, a smooth moving image can be displayed. Furthermore, by using the above-described driving method, since it is not necessary to constitute one pixel by a plurality of sub-pixels of different colors, the effective reflection area (also referred to as effective display area, aperture ratio) of one pixel can be enlarged, and bright display can be performed. Moreover, since it is not necessary to provide a color filter in the pixel, the transmittance of the pixel can be improved, and brighter display can be performed. In addition, the manufacturing process can be simplified, and thus the manufacturing cost can be reduced.

[0297] Figure 28A 、 Figure 28B FIG. 1 is an example of a cross-sectional view of a display device capable of field sequential driving. A backlight unit capable of emitting light of RGB colors is provided on the substrate 4001 side of the display device. Note that in the field sequential driving method, since the color is displayed by time division of the emission of light of RGB colors, a color filter is not necessary.

[0298] Figure 28B The backlight unit 4340a illustrated in FIG. 4A has a structure in which a plurality of light emitting elements 4342 are provided under the pixel with a diffusion plate 4352 interposed therebetween. The diffusion plate 4352 has a function of diffusing light emitted from the light emitting elements 4342 to the substrate 4001 side to make the luminance in the display portion surface uniform. A polarizing plate can also be provided as necessary between the light emitting elements 4342 and the diffusion plate 4352. In addition, the diffusion plate 4352 can not be provided if not necessary. Further, the light shielding layer 4132 can also be omitted.

[0299] The backlight unit 4340a can realize bright display since a larger number of light emitting elements 4342 can be mounted. In addition, a light guide plate is not necessary, and there is an advantage that the light of the light emitting elements 4342 is not easily lost in efficiency. Note that a lens 4344 for light diffusion can also be provided in the light emitting elements 4342 as necessary.

[0300] Figure 29A The backlight unit 4340b illustrated in FIG. 4B has a structure in which a light guide plate 4341 is provided under the pixel with the diffusion plate 4352 interposed therebetween. A plurality of light emitting elements 4342 are provided at the end portion of the light guide plate 4341. The light guide plate 4341 has a concave-convex shape on the side opposite to the diffusion plate 4352, and can scatter the guided light with the concave-convex shape to be emitted in the direction of the diffusion plate 4352.

[0301] The light emitting elements 4342 can be fixed to a printed circuit board 4347. Note that in the case of the backlight unit 4340b, the light emitting elements 4342 can be fixed to the light guide plate 4341. Figure 28AThe light emitting elements 4342 of each color of RGB are arranged in the depth direction, and the light emitting elements 4342 of each color of RGB overlap each other as illustrated in FIG. 43. Further, a reflective layer 4348 that reflects visible light can be provided on the side of the light guide plate 4341 opposite the light emitting elements 4342.

[0302] The backlight unit 4340b can be low cost and thin because the number of light emitting elements 4342 can be reduced.

[0303] A light scattering liquid crystal element can also be used as the liquid crystal element. A composite material including a liquid crystal and a polymer is preferably used as the light scattering liquid crystal element. For example, a polymer dispersion type liquid crystal element can be used. Alternatively, a polymer network type liquid crystal (PNLC) element can be used.

[0304] The light scattering liquid crystal element has a structure in which a liquid crystal portion is provided in a three-dimensional network structure of a resin portion sandwiched between a pair of electrodes. As a material for the liquid crystal portion, for example, a nematic liquid crystal can be used. Further, a photocurable resin can be used as the resin portion. The photocurable resin can use, for example, a monofunctional monomer such as an acrylate or a methacrylate; a multifunctional monomer such as a diacrylate, a triacrylate, a dimethacrylate, or a trimethacrylate; or a polymerizable compound that is a mixture of the above.

[0305] The light scattering liquid crystal element displays by transmitting or scattering light using anisotropy of the refractive index of the liquid crystal material. Further, the resin portion can also have anisotropy of the refractive index. When the liquid crystal molecules are aligned in a certain direction according to a voltage applied to the light scattering liquid crystal element, a direction in which a difference in the refractive index between the liquid crystal portion and the resin portion becomes small is generated, and light incident along the direction is transmitted without being scattered in the liquid crystal portion. Thus, the light scattering liquid crystal element appears to be in a transparent state from the direction. On the other hand, when the liquid crystal molecules are randomly aligned according to the applied voltage, the difference in the refractive index between the liquid crystal portion and the resin portion does not change much, and thus the incident light is scattered in the liquid crystal portion. Thus, the light scattering liquid crystal element becomes an opaque state regardless of the viewing direction.

[0306] Figure 28A is a structure in which the liquid crystal element 4013 of the display device of Figure 29B is replaced with a light scattering liquid crystal element 4016. The light scattering liquid crystal element 4016 includes a composite layer 4009 having a liquid crystal portion and a resin portion, and electrode layers 4030 and 4031. The constituent elements of the field sequential driving are the same as those of Figure 28B , and an alignment film and a polarizing plate are not needed when the light scattering liquid crystal element 4016 is used. Note that the shape of the spacer 4035 is spherical, but can be columnar.

[0307] Figure 28B The display device shown in FIG. 34 is modified as shown in FIG. 35. Figures 30A to 30E The liquid crystal element 4013 of the display device shown in FIG. 34 is replaced with a light scattering type liquid crystal element 4016. Figure 29B The structure shown in FIG. 35 is preferably a structure which operates in a mode of transmitting light when no voltage is applied to the light scattering type liquid crystal element 4016 and scattering light when a voltage is applied. By employing this structure, a transparent display device can be obtained in a normal state (non-display state). At this time, color display can be performed when operating in the scattering light mode.

[0308] Figures 30A to 30E The display device shown in FIG. 34 is modified as shown in FIG. 35. Figure 29B Note that in FIG. 35, only the components of part of the display device shown in FIG. 34 are shown and other components are omitted. Figure 30A Figure 30B

[0309] Figure 30C A structure in which the substrate 4001 is used as a light guide plate is shown. A concave-convex shape can be provided on the outer side surface of the substrate 4001. In this structure, a light guide plate need not be separately provided, so the manufacturing cost can be reduced. Furthermore, since light attenuation due to the light guide plate does not occur, light emitted from the light emitting element 4342 can be efficiently utilized.

[0310] Figure 30D A structure in which light is incident from the vicinity of the end of the composite layer 4009 is shown. By utilizing total reflection at the interface between the composite layer 4009 and the substrate 4006 and the interface between the composite layer 4009 and the substrate 4001, light can be emitted from the light scattering type liquid crystal element to the outside. As the resin portion of the composite layer 4009, a material having a larger refractive index than the substrate 4001 and the substrate 4006 is used.

[0311] Note that the light emitting element 4342 is not provided only on one side of the display device, but can be provided on both opposite sides as shown in FIG. 36. Figure 30E Further, it can be provided on three sides or four sides. By providing the light emitting element 4342 on a plurality of sides, light attenuation can be compensated for, and a large-area display element can be corresponded to.

[0312] Figure 29B A structure in which light emitted from the light emitting element 4342 is guided to the display device through a mirror 4345 is shown. With this structure, since light can be easily guided to the display device from a certain angle, total reflection light can be efficiently obtained.

[0313] Figures 30A to 30E ​​The structure in which the composite layer 4009 is stacked over the layer 4003 and the layer 4004 is shown. One of the layer 4003 and the layer 4004 is a support such as a glass substrate, and the other can be formed of an inorganic film, a cover film or a thin film of an organic resin, or the like. As the resin portion of the composite layer 4009, a material having a larger refractive index than the layer 4004 is used. Further, as the layer 4004, a material having a larger refractive index than the layer 4003 is used.

[0314] A first interface is formed between the composite layer 4009 and the layer 4004, and a second interface is formed between the layer 4004 and the layer 4003. With this structure, light which does not totally reflect at the first interface and passes through is totally reflected at the second interface, and can return to the composite layer 4009. Thus, light emitted from the light emitting element 4342 can be efficiently utilized.

[0315] Note that, Figure 31A1 and Figure 31A1 The structures of the above embodiments can be combined with each other.

[0316] The present embodiment can be implemented in combination with the structures described in other embodiments and the like.

[0317] (Embodiment 3)

[0318] In this embodiment, an example of a transistor which can be used instead of each of the transistors described in the above embodiments is described with reference to drawings.

[0319] A display device of one embodiment of the present application can be manufactured using a transistor of various modes such as a bottom-gate transistor or a top-gate transistor. Thus, it is possible to easily replace a semiconductor layer material or a transistor structure used in correspondence with an existing production line.

[0320] [Bottom-gate transistor]

[0321] Figure 31A2 A cross-sectional view of a channel protective transistor 810 which is one of bottom-gate transistors is shown. In the channel protective transistor 810, a channel region is formed in a semiconductor layer 742. Figure 31B1 In the channel protective transistor 810, the transistor 810 is formed over a substrate 771. Further, the transistor 810 includes an electrode 746 over the substrate 771 with an insulating layer 772 interposed therebetween. Further, the semiconductor layer 742 is included over the electrode 746 with an insulating layer 726 interposed therebetween. The electrode 746 can be used as a gate electrode. The insulating layer 726 can be used as a gate insulating layer.

[0322] Further, the insulating layer 741 is included over the channel formation region of the semiconductor layer 742. Further, the electrode 744a and the electrode 744b are included over the insulating layer 726 so as to be in contact with part of the semiconductor layer 742. The electrode 744a can be used as one of a source electrode and a drain electrode. The electrode 744b can be used as the other of the source electrode and the drain electrode. Part of the electrode 744a and part of the electrode 744b are formed over the insulating layer 741.

[0323] The insulating layer 741 can be used as a channel protective layer. By providing the insulating layer 741 over the channel formation region, the semiconductor layer 742 can be prevented from being exposed at the time of formation of the electrode 744a and the electrode 744b. Thus, the channel formation region of the semiconductor layer 742 can be prevented from being etched at the time of formation of the electrode 744a and the electrode 744b. According to one embodiment of the present application, a transistor with excellent electric characteristics can be implemented.

[0324] Further, the transistor 810 includes the insulating layer 728 over the electrode 744a, the electrode 744b, and the insulating layer 741, and includes the insulating layer 729 over the insulating layer 728.

[0325] When an oxide semiconductor is used for the semiconductor layer 742, a material capable of extracting oxygen from part of the semiconductor layer 742 to generate an oxygen vacancy is preferably used for at least a portion of the electrode 744a and the electrode 744b which is in contact with the semiconductor layer 742. The carrier concentration of a region in the semiconductor layer 742 where an oxygen vacancy is generated is increased, the region is n-type and becomes an n-type region (n + layer). Thus, the region can be used as a source region or a drain region. When an oxide semiconductor is used for the semiconductor layer 742, as one example of a material capable of extracting oxygen from the semiconductor layer 742 to generate an oxygen vacancy, tungsten, titanium, or the like can be given.

[0326] By forming a source region and a drain region in the semiconductor layer 742, the contact resistance of the electrode 744a and the electrode 744b to the semiconductor layer 742 can be reduced. Thus, the electric characteristics of the transistor such as field-effect mobility and threshold voltage can be excellent.

[0327] When a semiconductor such as silicon is used for the semiconductor layer 742, a layer used as an n-type semiconductor or a p-type semiconductor is preferably provided between the semiconductor layer 742 and the electrode 744a and between the semiconductor layer 742 and the electrode 744b. The layer used as an n-type semiconductor or a p-type semiconductor can be used as a source region or a drain region of the transistor.

[0328] The insulating layer 729 is preferably formed using a material having a function of preventing or reducing diffusion of impurities from the outside into the transistor. Further, the insulating layer 729 can be omitted as necessary.

[0329] Figure 31A1The transistor 811 is different from the transistor 810 in that the electrode 723 serving as a back gate electrode is included over the insulating layer 729. The electrode 723 can be formed using the same material and method as the electrode 746.

[0330] In general, a back gate electrode is formed using a conductive layer and is provided so that a channel formation region of a semiconductor layer is interposed between the gate electrode and the back gate electrode. Thus, the back gate electrode can have the same function as the gate electrode. The potential of the back gate electrode can be the same as that of the gate electrode, or can be a ground potential (GND potential) or an arbitrary potential. In addition, by independently changing the potential of the back gate electrode without being linked to the gate electrode, the threshold voltage of the transistor can be changed.

[0331] The electrode 746 and the electrode 723 can each be used as a gate electrode. Thus, the insulating layer 726, the insulating layer 728, and the insulating layer 729 can each be used as a gate insulating layer. In addition, the electrode 723 can be provided between the insulating layer 728 and the insulating layer 729.

[0332] Note that when one of the electrode 746 and the electrode 723 is referred to as a "gate electrode", the other is referred to as a "back gate electrode". For example, in the transistor 811, when the electrode 723 is referred to as a "gate electrode", the electrode 746 is referred to as a "back gate electrode". In addition, when the electrode 723 is used as a "gate electrode", the transistor 811 is one of top-gate transistors. Furthermore, one of the electrode 746 and the electrode 723 is sometimes referred to as a "first gate electrode", and the other is sometimes referred to as a "second gate electrode".

[0333] By providing the electrode 746 and the electrode 723 with the semiconductor layer 742 interposed therebetween and setting the potentials of the electrode 746 and the electrode 723 to be the same, a region through which a carrier in the semiconductor layer 742 flows is more expanded in a film thickness direction, so that the amount of movement of the carrier increases. As a result, the on-state current of the transistor 811 increases, and the field-effect mobility is also increased.

[0334] Thus, the transistor 811 is a transistor with a large on-state current relative to the size. That is, the size of the transistor 811 can be reduced relative to the on-state current required. According to one embodiment of the present application, the size of a transistor can be reduced. Thus, according to one embodiment of the present application, a semiconductor device with high integration can be achieved.

[0335] In addition, since the gate electrode and the back gate electrode are formed using a conductive layer, the gate electrode and the back gate electrode have a function of preventing an electric field generated outside the transistor from affecting the semiconductor layer in which a channel is formed (particularly, an electric field shielding function against static electricity or the like). In addition, when the back gate electrode is formed to be larger than the semiconductor layer so that the semiconductor layer is covered with the back gate electrode, the electric field shielding function can be improved.

[0336] In addition, by forming the back gate electrode using a conductive film having light blocking properties, light can be prevented from entering the semiconductor layer from the back gate electrode side. Thus, light degradation of the semiconductor layer can be prevented, and deterioration of the threshold voltage and the like of the transistor can be prevented.

[0337] According to one embodiment of the present application, a transistor with high reliability can be provided. In addition, a semiconductor device with high reliability can be provided.

[0338] Figure 31B2 is a cross-sectional view of a channel-etching transistor 825, which is one of the bottom-gate transistors. The transistor 825 has substantially the same structure as the transistor 810, with the exception that the electrode 744a and the electrode 744b are formed without using the insulating layer 729. Thus, part of the semiconductor layer 742 exposed when the electrode 744a and the electrode 744b are formed is etched. On the other hand, since the insulating layer 729 is not provided, the productivity of the transistor can be improved. Figure 31C1

[0339] Figure 31C2 The transistor 821 illustrated in FIG. 8B differs from the transistor 820 in that the electrode 723 which can be used as a back gate electrode is included over the insulating layer 729.

[0340] By providing the insulating layer 729, exposure of the semiconductor layer 742 caused when the electrode 744a and the electrode 744b are formed can be prevented. Thus, the semiconductor layer 742 can be prevented from being thinned when the electrode 744a and the electrode 744b are formed.

[0341] In addition, the distance between the electrode 744a and the electrode 746 and the distance between the electrode 744b and the electrode 746 are longer in the transistors 820 and 821 than in the transistors 810 and 811. Thus, the parasitic capacitance generated between the electrode 744a and the electrode 746 can be reduced. Furthermore, the parasitic capacitance generated between the electrode 744b and the electrode 746 can be reduced. According to one embodiment of the present application, a transistor with favorable electrical characteristics can be provided.

[0342] Figures 32A1 to 32C2 is a cross-sectional view of a channel-etching transistor 825, which is one of the bottom-gate transistors. The transistor 825 has substantially the same structure as the transistor 810, with the exception that the electrode 744a and the electrode 744b are formed without using the insulating layer 729. Thus, part of the semiconductor layer 742 exposed when the electrode 744a and the electrode 744b are formed is etched. On the other hand, since the insulating layer 729 is not provided, the productivity of the transistor can be improved.​

[0343] Figure 32B2 The transistor 825 shown differs from the transistor 820 in that the electrode 723 serving as a back gate electrode is provided over the insulating layer 729.

[0344] Figure 32C2 is a cross-sectional view taken along the channel width direction of the transistors 810, 811, 820, 821, 825, and 826.

[0345] In the structure shown in FIG. 8B, the gate electrode and the back gate electrode are connected to each other, whereby the potentials of the gate electrode and the back gate electrode are the same. Further, the semiconductor layer 742 is sandwiched between the gate electrode and the back gate electrode. Figure 33A1 and Figure 33A2 In the structure shown in FIG. 8B, the gate electrode and the back gate electrode are connected to each other, whereby the potentials of the gate electrode and the back gate electrode are the same. Further, the semiconductor layer 742 is sandwiched between the gate electrode and the back gate electrode.

[0346] In the channel width direction, the lengths of the gate electrode and the back gate electrode are larger than that of the semiconductor layer 742, and the semiconductor layer 742 is entirely sandwiched by the gate electrode or the back gate electrode with the insulating layers 726, 741, 728, and 729 therebetween.

[0347] By employing this structure, the semiconductor layer 742 included in the transistor can be surrounded by the electric field of the gate electrode and the back gate electrode.

[0348] The device structure of a transistor in which the semiconductor layer 742 forming a channel formation region is surrounded by the electric field of the gate electrode and the back gate electrode, like the transistor 821 or the transistor 826, can be referred to as a Surrounded channel (S-channel) structure.

[0349] By employing the S-channel structure, the semiconductor layer 742 can be effectively subjected to an electric field for inducing a channel formation by one or both of the gate electrode and the back gate electrode, whereby the current drivability of the transistor is improved, and thus a higher on-state current characteristic can be obtained. Further, since the on-state current can be increased, the transistor can be miniaturized. Further, by employing the S-channel structure, the mechanical strength of the transistor can be improved.

[0350] [Top-gate transistor]

[0351] Figure 33B1 The transistor 842 shown is one of top-gate transistors. The transistor 842 differs from the transistor 830 and the transistor 840 in that the electrode 744a and the electrode 744b are formed after the insulating layer 729 is formed. The electrode 744a and the electrode 744b are electrically connected to the semiconductor layer 742 in openings formed in the insulating layer 728 and the insulating layer 729.

[0352] In addition, a portion of the insulating layer 726 not overlapping with the electrode 746 is removed, and impurities 755 are introduced into the semiconductor layer 742 with the electrode 746 and the remaining insulating layer 726 as masks, whereby an impurity region can be formed in the semiconductor layer 742 in a self-alignment manner. The transistor 842 includes a region where the insulating layer 726 extends beyond the end portion of the electrode 746. The impurity concentration of the region of the semiconductor layer 742 into which the impurities 755 are introduced through the insulating layer 726 is lower than that of the region of the semiconductor layer 742 into which the impurities 755 are not introduced through the insulating layer 726. An LDD (Lightly Doped Drain) region is formed in the region of the semiconductor layer 742 not overlapping with the electrode 746.

[0353] Figure 33B2 The transistor 843 illustrated in FIG. 8A is different from the transistor 842 in that it includes the electrode 723. The transistor 843 includes the electrode 723 formed over the substrate 771. The electrode 723 has a region overlapping with the semiconductor layer 742 with the insulating layer 772 interposed therebetween. The electrode 723 can be used as a back gate electrode.

[0354] In addition, as in the transistors 844 and 845 illustrated in FIGS. 8B and 8C, the insulating layer 726 can be completely removed in the region not overlapping with the electrode 746. In addition, as in the transistors 846 and 847 illustrated in FIGS. 8D and 8E, the insulating layer 726 can not be removed. Figure 33C1 Figure 33C2 In addition, as in the transistors 844 and 845 illustrated in FIGS. 8B and 8C, the insulating layer 726 can be completely removed in the region not overlapping with the electrode 746. In addition, as in the transistors 846 and 847 illustrated in FIGS. 8D and 8E, the insulating layer 726 can not be removed. Figures 34A1 to 34C2 Figure 35A In addition, as in the transistors 844 and 845 illustrated in FIGS. 8B and 8C, the insulating layer 726 can be completely removed in the region not overlapping with the electrode 746. In addition, as in the transistors 846 and 847 illustrated in FIGS. 8D and 8E, the insulating layer 726 can not be removed.

[0355] In the transistors 842 to 847, the impurities 755 can be introduced into the semiconductor layer 742 with the electrode 746 as a mask after the formation of the electrode 746, whereby an impurity region can be formed in the semiconductor layer 742 in a self-alignment manner. According to one embodiment of the present application, a transistor with excellent electrical characteristics can be implemented. In addition, according to one embodiment of the present application, a semiconductor device with high integration can be implemented.

[0356] Figure 35B FIG. 9A is a cross-sectional view of the channel width direction of the transistors 842, 843, 844, 845, 846, and 847.

[0357] The transistors 843, 845, and 847 have the S-channel structure described above. However, the transistors 843, 845, and 847 are not necessarily provided with the S-channel structure.

[0358] This embodiment mode can be implemented in appropriate combination with the structures described in other embodiment modes and the like.

[0359] (Embodiment 4) ​​

[0360] As electronic devices to which one embodiment of the present application can be applied, a display device, a personal computer, an image storage device and an image reproduction device provided with a recording medium, a mobile phone, a game machine including a portable game machine, a portable data terminal, an electronic book reader, a camera such as a video camera or a digital camera, a goggle-type display (head-mounted display), a navigation system, an audio reproduction device (a car audio system, a digital audio player, or the like), a copier, a facsimile machine, a printer, a multifunction printer, an automatic teller machine (ATM), and a vending machine can be given. FIG. 35 illustrates specific examples of these electronic devices.

[0361] Figure 35C is a digital camera including a housing 961, a shutter button 962, a microphone 963, a speaker 967, a display portion 965, an operation key 966, a zoom button 968, a lens 969, and the like. With the use of one embodiment of the display device of the present application for the display portion 965, display of various images can be performed.

[0362] Figure 35D is a digital sign including a large display portion 922. For example, it is installed to the side surface of a column 921. With the use of one embodiment of the display device of the present application for the display portion 922, display with high display quality can be performed.

[0363] Figure 35E is an example of a mobile phone including a housing 951, a display portion 952, an operation button 953, an external connection port 954, a speaker 955, a microphone 956, a camera 957, and the like. The mobile phone includes a touch sensor in the display portion 952. All operations such as making a call or inputting text can be performed by touching the display portion 952 with a finger or a stylus. In addition, the housing 901 and the display portion 952 have flexibility and can be used by being bent as illustrated. With the use of one embodiment of the display device of the present application for the display portion 952, display of various images can be performed.

[0364] Figure 35F is a video camera including a first housing 901, a second housing 902, a display portion 903, an operation key 904, a lens 905, a connection portion 906, a speaker 907, and the like. The operation key 904 and the lens 905 are provided in the first housing 901, and the display portion 903 is provided in the second housing 902. With the use of one embodiment of the display device of the present application for the display portion 903, display of various images can be performed.

[0365] ​is a television set including a housing 971, a display portion 973, an operation key 974, a speaker 975, a communication terminal 976, and a photosensor 977. The display portion 973 is provided with a touch sensor, and input operation can be performed. By using the display device of one embodiment of the present application for the display portion 973, display of various images can be performed.

[0366] ​ is a portable data terminal including a housing 911, a display portion 912, a speaker 913, and a camera 919. Data can be inputted or outputted by a touch panel function of the display portion 912. By using the display device of one embodiment of the present application for the display portion 912, display of various images can be performed.

[0367] This embodiment mode can be implemented in combination with the structures described in other embodiment modes and the like as appropriate.

[0368] [Explanation of Symbols]

[0369] 10: circuit, 11: circuit, 12: pixel block, 13: source driver, 14a: gate driver, 14b: gate driver, 15: circuit, 20: pixel, 101: transistor, 102: transistor, 103: transistor, 104: capacitor, 105: transistor, 106: transistor, 107: capacitor, 110: circuit block, 111: transistor, 112: transistor, 113: capacitor, 114: light-emitting element, 115: transistor, 116: capacitor, 117: liquid crystal element, 118: transistor, 119: transistor, 120: circuit, 121: wiring, 122: wiring, 123: wiring, 125: wiring, 126: wiring, 127: wiring, 128: wiring, 129: wiring, 130: wiring, 131: wiring, 132: wiring, 133: wiring, 134: wiring, 135: wiring, 215: display portion, 221a: scan line driver circuit, 231a: signal line driver circuit, 232a: signal line driver circuit, 241a: common line driver circuit, 723: electrode, 726: insulating layer, 728: insulating layer, 729: insulating layer, 741: insulating layer, 742: semiconductor layer, 744a: electrode, 744b: electrode, 746: electrode, 755: impurity, 771: substrate, 772: insulating layer, 810: transistor, 811: transistor, 820: transistor, 821: transistor, 825: transistor, 826: transistor, 830: transistor, 840: transistor, 842: transistor, 843: transistor, 844: transistor, 845: transistor, 846: transistor, 847: transistor, 901: housing, 902: housing, 903: display portion, 904: operation key, 905: lens, 906: connection portion, 907: speaker, 911: housing, 912: display portion, 913: speaker, 919: camera, 921: column, 922: display portion, 951: housing, 952: display portion, 953: operation button, 954: external connection terminal, 955: speaker, 956: microphone, 957: camera, 961: housing, 962: shutter button, 963: microphone, 965: display portion, 966: operation key, 967: speaker, 968: zoom button, 969: lens, 971: housing, 973: display portion, 974: operation key, 975: speaker, 976: communication connection terminal, 977: photosensor, 4001: substrate, 4003: layer, 4004: layer, 4005: sealing agent, 4006: substrate, 4008: liquid crystal layer, 4009: composite layer, 4010: transistor, 4011: transistor, 4013: liquid crystal element, 4014: wiring, 4015: electrode, 4016: light-scattering liquid crystal element, 4017: electrode, 4018: FPC, 4019: anisotropic conductive layer, 4020: capacitor,4021: electrode, 4022: transistor, 4023: transistor, 4030: electrode layer, 4031: electrode layer, 4032: insulating layer, 4033: insulating layer, 4035: spacer, 4041: printed circuit board, 4042: integrated circuit, 4102: insulating layer, 4103: insulating layer, 4104: insulating layer, 4110: insulating layer, 4111: insulating layer, 4112: insulating layer, 4131: colored layer, 4132: light-blocking layer, 4133: insulating layer, 4200: input device, 4210: touch panel, 4227: electrode, 4228: electrode, 4237: wiring, 4238: wiring, 4239: wiring, 4263: substrate, 4272b: FPC, 4273b: IC, 4340a: backlight unit, 4340b: backlight unit, 4341: light guide plate, 4342: light-emitting element, 4344: lens, 4345: mirror, 4347: printed circuit board, 4348: reflective layer, 4352: diffusion plate, 4510: partition wall, 4511: light-emitting layer, 4513: light-emitting element, 4514: filler.

Claims

1. A display device comprising a plurality of pixel blocks, wherein each of the plurality of pixel blocks comprises a first circuit and a plurality of second circuits, each of the plurality of second circuits comprises a display element, the first circuit is electrically connected to the plurality of second circuits, the plurality of second circuits are arranged in a direction in which a source line extends, each of the plurality of pixel blocks comprises a plurality of pixels, the first circuit is shared by the plurality of pixels, the plurality of second circuits are respectively provided in the plurality of pixels, a first pixel of the plurality of pixels comprises a plurality of components of the first circuit and one of the plurality of second circuits, and in the direction in which the source line extends, a length of the first pixel is greater than a length of another pixel of the plurality of pixels.

2. The display device according to claim 1, wherein the first circuit comprises a first transistor, a second transistor, and a first capacitor, one of a source and a drain of the first transistor is electrically connected to a first electrode of the first capacitor, a second electrode of the first capacitor is electrically connected to one of a source and a drain of the second transistor, a gate of the first transistor is electrically connected to a first gate line, and a gate of the second transistor is electrically connected to a second gate line.

3. The display device according to claim 2, further comprising a third transistor, wherein one of a source and a drain of the third transistor is electrically connected to the first electrode of the first capacitor, the other of the source and the drain of the first transistor and the other of the source and the drain of the second transistor are electrically connected to a source driver, and a gate of the third transistor is electrically connected to a third gate line.

4. The display device according to claim 3, wherein each of the plurality of second circuits comprises the third transistor and a third circuit comprising the display element, one of the source and the drain of the third transistor is electrically connected to one of the source and the drain of the first transistor, and the other of the source and the drain of the third transistor is electrically connected to the third circuit.

5. The display device according to claim 4, wherein the display element comprises a light-emitting element, the third circuit further comprises a fourth transistor and a second capacitor, a gate of the fourth transistor is electrically connected to the other of the source and the drain of the third transistor, one of a source and a drain of the fourth transistor is electrically connected to a first electrode of the light-emitting element, the first electrode of the light-emitting element is electrically connected to a first electrode of the second capacitor, and a second electrode of the second capacitor is electrically connected to the gate of the fourth transistor.

6. The display device according to claim 5, further comprising a fifth transistor, wherein one of a source and a drain of the fifth transistor is electrically connected to the first electrode of the light-emitting element, the other of the source and the drain of the fifth transistor is electrically connected to one of the source and the drain of the fourth transistor, and the other of the source and the drain of the fifth transistor is electrically connected to the gate of the fourth transistor. and the other of the source and the drain of the fifth transistor is electrically connected to the first electrode of the second capacitor.

7. The display device according to claim 4, wherein the display element includes a liquid crystal element, and one of the source and the drain of the third transistor is electrically connected to the first electrode of the liquid crystal element.

8. The display device according to claim 7, further comprising a third capacitor, wherein a first electrode of the third capacitor is electrically connected to the first electrode of the liquid crystal element.

9. The display device according to claim 2, wherein at least one of the first transistor and the second transistor includes a metal oxide in a channel formation region, and the metal oxide includes In, Zn, and M, and M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf.

10. The display device according to any one of claims 1 to 9, further comprising a fourth circuit and a fifth circuit, wherein the fourth circuit is configured to control the first circuit, and the fifth circuit is configured to control the plurality of second circuits.

11. A display device comprising: a source driver; a first circuit to which data from the source driver is input; a second circuit electrically connected to the first circuit; and a third circuit electrically connected to the first circuit, wherein the second circuit and the third circuit are arranged in a direction in which a source line extends, the first circuit includes a first transistor, a second transistor, and a first capacitor, one of a source and a drain of the first transistor is electrically connected to a first electrode of the first capacitor, the other of the source and the drain of the first transistor is electrically connected to the source driver, one of a source and a drain of the second transistor is electrically connected to a second electrode of the first capacitor, the second circuit includes a third transistor and a first display element, the third circuit includes a fourth transistor and a second display element, and one of a source and a drain of the third transistor and one of a source and a drain of the fourth transistor are electrically connected to one of the source and the drain of the first transistor.

12. A display device comprising: a source driver; a first circuit to which data from the source driver is input; a second circuit electrically connected to the first circuit, the second circuit including a first display element; and a third circuit electrically connected to the first circuit, the third circuit including a second display element, wherein the first circuit includes a first transistor, a second transistor, and a first capacitor, one of a source and a drain of the first transistor is electrically connected to a first electrode of the first capacitor, the other of the source and the drain of the first transistor is electrically connected to the source driver, one of a source and a drain of the second transistor is electrically connected to a second electrode of the first capacitor, the second circuit further includes a third transistor electrically connected to the first display element, the third circuit further includes a fourth transistor electrically connected to the second display element, and one of a source and a drain of the third transistor and one of a source and a drain of the fourth transistor are electrically connected to one of the source and the drain of the first transistor.

13. The display device according to claim 11 or 12, wherein each of the third transistor and the fourth transistor includes a metal oxide in a channel formation region, and the metal oxide includes In, Zn, and M, and M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf.

14. The display device according to claim 11 or 12, wherein at least one of the first transistor and the second transistor includes a metal oxide in a channel formation region, and the metal oxide includes In, Zn, and M, and M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf.

15. The display device according to claim 11 or 12, wherein each of the first display element and the second display element includes a light-emitting element.

16. The display device according to claim 11 or 12, wherein each of the first display element and the second display element includes a liquid crystal element.

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