Semiconductor device based on encapsulated graphene nanoribbons and method of making the same

Abstract

This invention provides a semiconductor device based on encapsulated graphene nanoribbons and its fabrication method. The semiconductor device includes: a substrate, encapsulated graphene nanoribbons located thereon, and corresponding metal electrodes. The encapsulated graphene nanoribbons includes: an insulating encapsulation with atomic-level flatness, the insulating encapsulation being formed by at least two atomic layers stacked in parallel, with adjacent atomic layers bonded by van der Waals forces; at least one longitudinal section extending along the thickness direction of the insulating encapsulation; and at least one graphene nanoribbon, which breaks through the van der Waals forces of any two adjacent atomic layers exposed on the longitudinal section and embeds itself between the two atomic layers. The graphene nanoribbons used in this semiconductor device are encapsulated in an insulating encapsulation with atomic-level flatness, isolating them from the external environment, thus giving them properties close to those of intrinsic nanoribbons, resulting in high-quality, high-performance carbon-based electronic devices. Furthermore, the fabrication method is simple, low-cost, and can be mass-produced.

Description

Technical Field

[0001] This invention relates to the field of nanomaterial electronic device technology, and in particular to semiconductor devices based on encapsulated graphene nanoribbons and their fabrication methods. Background Technology

[0002] In recent years, graphene nanoribbons, as a one-dimensional material, have attracted widespread attention. The unique band structure of graphene nanoribbons endows them with distinctive electrical, magnetic, and optical properties. Graphene nanoribbons show great promise for applications in field-effect transistors, gas sensors, photodetectors, and energy storage.

[0003] Graphene nanoribbons possess tunable band gaps and ultra-high carrier mobility, making them ideal materials for fabricating various electronic devices. However, traditional graphene nanoribbons are generally fabricated on the surface of various substrates, and surface-based graphene nanoribbons are susceptible to problems such as molecular adsorption and organic liquid contamination, resulting in generally poor performance of devices based on surface nanoribbons. Therefore, it is essential to propose a semiconductor device based on encapsulated graphene nanoribbon materials to improve the performance of electronic devices. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a semiconductor device based on encapsulated graphene nanoribbons and a method for preparing the same, in order to solve the problems of poor performance of semiconductor devices based on graphene nanoribbons prepared on the substrate surface in the prior art.

[0005] To achieve the above and other related objectives, the present invention provides a semiconductor device based on encapsulated graphene nanoribbons, the semiconductor device comprising: a substrate, encapsulated graphene nanoribbons located on the substrate, and corresponding metal electrodes;

[0006] The substrate includes a semiconductor layer and an insulating layer located on the surface of the semiconductor layer;

[0007] The encapsulated graphene nanoribbons include:

[0008] An insulating package located on the insulating layer of the substrate and having atomic-level flatness, the insulating package being formed by at least two atomic layers stacked in parallel in sequence, and adjacent atomic layers being bonded together by van der Waals forces;

[0009] At least one longitudinal section is formed by the insulating package extending from the surface of the insulating package along the thickness direction of the insulating package for one or more atomic layers;

[0010] At least one graphene nanoribbon breaks through the van der Waals forces of any two adjacent atomic layers exposed on the longitudinal section and embeds itself between the two atomic layers, and is encapsulated by the insulating encapsulation body, wherein the boundary shape of the graphene nanoribbon is serrated.

[0011] Optionally, the insulating layer is a silicon oxide insulating layer; the semiconductor layer is a silicon semiconductor layer; and the insulating package is a hexagonal boron nitride insulating package.

[0012] Optionally, the semiconductor device further includes: a source metal electrode and a drain metal electrode; the source metal electrode and the drain metal electrode extend from the surface of the insulating package into its interior and are in contact with the cross-section of the same graphene nanoribbon.

[0013] Optionally, the semiconductor device further includes: a first metal electrode and a second metal electrode; the first metal electrode extends from the surface of the insulating package toward its interior and is in contact with the cross-section of the first graphene nanoribbon; the second metal electrode extends from the surface of the insulating package toward its interior and is in contact with the cross-section of the second graphene nanoribbon; the first graphene nanoribbon and the second graphene nanoribbon are located between different atomic layers in the insulating package and intersect in space.

[0014] Optionally, the semiconductor device further includes a source metal electrode and a drain metal electrode; the source metal electrode and the drain metal electrode are disposed on the surface of the insulating package and are located directly above the same graphene nanoribbon.

[0015] Optionally, the semiconductor device further includes: a source metal electrode, a drain metal electrode, and a one-dimensional semiconductor material strip; the source metal electrode and the drain metal electrode are disposed on the surface of the insulating package and are located directly above the same graphene nanoribbon; the one-dimensional semiconductor material strip is disposed on the surface of the insulating package and is located between and in contact with the source metal electrode and the drain metal electrode.

[0016] The present invention also provides a method for fabricating a semiconductor device based on encapsulated graphene nanoribbons, for fabricating the semiconductor device based on encapsulated graphene nanoribbons as described above, the method comprising the following steps:

[0017] A substrate is provided, the substrate including a semiconductor layer and an insulating layer located on the surface of the semiconductor layer;

[0018] Encapsulated graphene nanoribbons are formed on the surface of the insulating layer of the substrate;

[0019] Metal electrodes are formed on or inside the encapsulated graphene nanoribbons;

[0020] The method for forming the encapsulated graphene nanoribbons includes:

[0021] An insulating package with atomic-level flatness is provided, the insulating package being formed by stacking at least two atomic layers in parallel, adjacent atomic layers being bonded by van der Waals forces, and at least one longitudinal section being formed on the insulating package, the longitudinal section extending from the surface of the insulating package along the thickness direction of the insulating package.

[0022] Nanocatalyst particles are formed on the surface of the insulating package and the longitudinal section surface, and the nanocatalyst particles are bonded to the surface of the insulating package and the longitudinal section surface.

[0023] Growth process: The insulating encapsulation containing the nano-catalyst particles is subjected to chemical vapor deposition to form a carbon product layer on the surface of the insulating encapsulation and graphene nanoribbons inside the insulating encapsulation. The graphene nanoribbons break through the van der Waals forces of any two adjacent atomic layers exposed on the longitudinal section and embed themselves between the two atomic layers, and are encapsulated by the insulating encapsulation. The reaction gas introduced is a carbon source gas, and the growth temperature is 600℃~1000℃.

[0024] Cooling process: After growth is complete, the carbon source gas is turned off, and the material is cooled to room temperature under the protection of the protective gas before being removed.

[0025] Etching process: The carbon product layer formed on the surface of the insulating package during the growth process is removed, thereby forming the graphene nanoribbons only inside the insulating package.

[0026] Optionally, the preparation method further includes the step of preparing a source metal electrode and a drain metal electrode, wherein the source metal electrode and the drain metal electrode extend from the surface of the insulating package into its interior and are in contact with the cross-section of the same graphene nanoribbon.

[0027] Furthermore, the method for fabricating the source metal electrode and the drain metal electrode includes:

[0028] A photoresist layer is coated on the surface of the substrate on which the encapsulated graphene nanoribbons are formed, and the photoresist layer is patterned to form a patterned photoresist layer.

[0029] Based on the patterned photoresist layer, the encapsulated graphene nanoribbon is etched to expose the cross-section of the same graphene nanoribbon, thereby obtaining etched trenches.

[0030] The etched trenches are filled with a metallic material that extends above the surface of the etched trenches to obtain the source metal electrode and the drain metal electrode.

[0031] Optionally, the preparation method further includes the steps of preparing a first metal electrode and a second metal electrode, wherein the first metal electrode extends from the surface of the insulating package toward its interior and is in contact with the cross-section of the first graphene nanoribbon, and the second metal electrode extends from the surface of the insulating package toward its interior and is in contact with the cross-section of the second graphene nanoribbon, wherein the first graphene nanoribbon and the second graphene nanoribbon are located between different atomic layers in the insulating package and intersect in space.

[0032] Furthermore, the method for preparing the first metal electrode and the second metal electrode includes:

[0033] A photoresist layer is coated on the surface of the substrate on which the encapsulated graphene nanoribbons are formed, and the photoresist layer is patterned to form a patterned photoresist layer.

[0034] Based on the patterned photoresist layer, the encapsulated graphene nanoribbons are etched to expose the cross-sections of the first and second graphene nanoribbons, which are located between different atomic layers and spatially intersecting in the insulating package, to obtain etched trenches.

[0035] The etched trenches are filled with a metallic material that extends above the surface of the etched trenches to obtain the first metal electrode and the second metal electrode.

[0036] Furthermore, the photoresist layer is exposed using an electron beam exposure method to obtain the patterned photoresist layer.

[0037] As described above, the semiconductor device based on encapsulated graphene nanoribbons and its fabrication method of the present invention encapsulate the semiconductor material layer graphene nanoribbons in an insulating package with atomic-level flatness, isolating it from the external environment. This allows the graphene nanoribbons to possess physical properties close to those of intrinsic nanoribbons. Furthermore, the graphene nanoribbons can be effectively protected during the fabrication process of the semiconductor device, effectively avoiding problems such as molecular adsorption and organic liquid contamination during the process. This results in high-quality, high-performance carbon-based electronic devices. Carbon-based electronic devices are characterized by low contact barriers, high mobility, and excellent conductivity. In addition, the fabrication method is simple, low-cost, and can be mass-produced, thus possessing significant industrialization value. Attached Figure Description

[0038] Figure 1 The diagram shows a cross-sectional structure of a semiconductor device based on encapsulated graphene nanoribbons, as shown in the first example of Embodiment 1 of the present invention.

[0039] Figure 2The diagram shows a three-dimensional structure of a semiconductor device based on encapsulated graphene nanoribbons, as shown in the second example of Embodiment 1 of the present invention.

[0040] Figure 3 The image shown is a scanning electron microscope image of a semiconductor device based on encapsulated graphene nanoribbons, as shown in the second example of Embodiment 1 of the present invention.

[0041] Figure 4 The diagram shows a cross-sectional structure of a semiconductor device based on encapsulated graphene nanoribbons, as shown in the third example of Embodiment 1 of the present invention.

[0042] Figure 5 The diagram shown is a cross-sectional view of a semiconductor device based on encapsulated graphene nanoribbons, as illustrated in the fourth example of Embodiment 1 of the present invention.

[0043] Figures 6 to 10 The diagram shows the cross-sectional structure of each step in the fabrication method of the semiconductor device based on encapsulated graphene nanoribbons according to Embodiment 2 of the present invention.

[0044] Figures 11 to 13 The images shown are scanning electron microscope (SEM) images of each step in the fabrication method of a semiconductor device based on encapsulated graphene nanoribbons, which is shown in Experimental Example 1 of Embodiment 2 of the present invention.

[0045] Component designation explanation

[0046] 10 base

[0047] 100 Semiconductor Layer

[0048] 101 Insulation Layer

[0049] 20-packed graphene nanoribbons

[0050] 200 Insulating Encapsulation

[0051] 201 Graphene Nanoribbons

[0052] 202 First Graphene Nanoribbon

[0053] 203 Second Graphene Nanoribbon

[0054] 300 source metal electrode

[0055] 301 Drain Metal Electrode

[0056] 302 First Metal Electrode

[0057] 303 Second Metal Electrode

[0058] 304 one-dimensional semiconductor material strip

[0059] 305 photoresist layer

[0060] 306 Patterned photoresist layer

[0061] 307 Etched Grooves

[0062] 308 metallic material layer

[0063] 309 Positioning Marker Detailed Implementation

[0064] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0065] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0066] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for the device in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or there may be one or more layers in between. The phrase “between” as used herein includes both endpoint values.

[0067] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0068] Please see Figures 1 to 13 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0069] Example 1

[0070] like Figures 1 to 5 As shown, this embodiment provides a semiconductor device based on encapsulated graphene nanoribbons. The semiconductor device includes: a substrate 10, an encapsulated graphene nanoribbon 20 located on the substrate 10, and corresponding metal electrodes.

[0071] The substrate 10 includes a semiconductor layer 100 and an insulating layer 101 located on the surface of the semiconductor layer 100;

[0072] The encapsulated graphene nanoribbons 20 include:

[0073] An insulating package 200 located on the insulating layer 101 of the substrate 10 and having atomic-level flatness, the insulating package 200 being formed by at least two atomic layers stacked in parallel in sequence, and adjacent atomic layers being bonded together by van der Waals forces;

[0074] At least one longitudinal section is formed of the insulating package 200 extending from the surface of the insulating package 200 along the thickness direction of the insulating package 200 for one or more atomic layer thicknesses;

[0075] At least one graphene nanoribbon 201 breaks through the van der Waals forces of any two adjacent atomic layers exposed on the longitudinal section and is embedded between the two atomic layers, and is encapsulated by the insulating encapsulator 200, wherein the boundary shape of the graphene nanoribbon 201 is serrated.

[0076] In the semiconductor device based on encapsulated graphene nanoribbons in this embodiment, the semiconductor material layer graphene nanoribbons is encapsulated in an insulating package with atomic-level flatness, isolating it from the external environment. This allows the graphene nanoribbons to have physical properties close to those of intrinsic nanoribbons. Furthermore, the graphene nanoribbons can be effectively protected during the fabrication process of the semiconductor device, effectively avoiding problems such as molecular adsorption and organic liquid contamination during the process. This results in high-quality, high-performance carbon-based electronic devices, which have the characteristics of low contact barrier, high mobility, and excellent conductivity.

[0077] As an example, in the encapsulated graphene nanoribbons, all the graphene nanoribbons 201 are located between the same two atomic layers, or at least two graphene nanoribbons 201 are located between different two atomic layers. That is, it is not limited whether all the graphene nanoribbons 201 in the insulating encapsulation 200 have the same horizontal height; they can all be located between the same two atomic layers or between different two atomic layers. In other words, the graphene nanoribbons 201 can be without atomic layers between them, or they can be separated by one or more atomic layers.

[0078] As an example, the insulating layer 101 is a silicon oxide insulating layer; the semiconductor layer 100 is a silicon semiconductor layer; and the insulating package 200 is a hexagonal boron nitride insulating package.

[0079] As an example, the longitudinal section can be a longitudinal section naturally formed on the outer periphery of the insulating package 200 in the thickness direction; or it can be a longitudinal section formed by etching the insulating package 200 along its thickness direction. The specific configuration depends on actual needs.

[0080] like Figure 1 As shown in the illustration, as a specific example, the semiconductor device further includes a source metal electrode 300 and a drain metal electrode 301. The source metal electrode 300 and the drain metal electrode 301 extend from the surface of the insulating package 200 into its interior and are in contact with the cross-section of the same graphene nanoribbon 201. Thus, the semiconductor device is formed as a field-effect transistor device based on a single graphene nanoribbon. Since the graphene nanoribbon 201 is a one-dimensional structure, its cross-section can be understood as a zero-dimensional point. Therefore, the contact method between the source metal electrode 300 and the drain metal electrode 301 electrically connected to it can be understood as a zero-dimensional contact. By optimizing each fabrication step, the insulating package can achieve clean contact points between the metal electrodes and the nanoribbon with a small potential barrier, thereby effectively improving the performance of the field-effect transistor device.

[0081] like Figure 2 and Figure 3 As shown, as another specific example, the semiconductor device further includes: a first metal electrode 302 and a second metal electrode 303 (e.g., ...). Figure 3 (As shown); the first metal electrode 302 extends from the surface of the insulating package 200 toward its interior and contacts the cross-section of the first graphene nanoribbon 202; the second metal electrode 303 extends from the surface of the insulating package 200 toward its interior and contacts the cross-section of the second graphene nanoribbon 203; the first graphene nanoribbon 202 and the second graphene nanoribbon 203 are located between different atomic layers in the insulating package 200 and intersect in space (e.g. Figure 2 (As shown). Thus, the semiconductor device is formed as a tunneling device based on two intersecting graphene nanoribbons. When a voltage is applied to the two ends of the first metal electrode 302 and the second metal electrode 303, current tunneling will occur at the intersection of the two intersecting graphene nanoribbons.

[0082] It should be noted that the first graphene nanoribbon 202 and the second graphene nanoribbon 203 are located between different two-dimensional encapsulation material layers in the insulating encapsulation body 200 and intersect in space. This means that the first graphene nanoribbon 202 and the second graphene nanoribbon 203 are located at different thickness positions along the thickness direction in the insulating encapsulation body 200, and are isolated from each other by the insulating encapsulation body 200. In addition, the first graphene nanoribbon 202 and the second graphene nanoribbon 203 are not parallel, and they intersect when projected in the horizontal direction.

[0083] like Figure 4 As shown, as another specific example, the semiconductor device further includes a source metal electrode 300 and a drain metal electrode 301; the source metal electrode 300 and the drain metal electrode 301 are disposed on the surface of the insulating package 200 and located directly above the same graphene nanoribbon 201. Thus, the semiconductor device is formed as a tunneling device based on a single graphene nanoribbon. When a voltage is applied across the source metal electrode 300 and the drain metal electrode 301, current flows from one of the metal electrodes, tunnels through the insulating package 200 as the tunneling medium to the graphene nanoribbon, flows through the graphene nanoribbon, and then tunnels again through the insulating package 200 as the tunneling medium to the other metal electrode.

[0084] like Figure 5 As shown, as another specific example, the semiconductor device further includes: a source metal electrode 300, a drain metal electrode 301, and a one-dimensional semiconductor material strip 304; the source metal electrode 300 and the drain metal electrode 301 are disposed on the surface of the insulating package 200 and are located directly above the same graphene nanoribbon 201; the one-dimensional semiconductor material strip 304 is disposed on the surface of the insulating package 200 and is located between and in contact with the source metal electrode 300 and the drain metal electrode 301. In use, the one-dimensional semiconductor material strip 304 serves as a test channel, the semiconductor layer 100 serves as a control electrode, and the graphene nanoribbon 201 is kept floating as a floating electrode. When the source metal electrode 300 is suspended and the drain metal electrode 301 is grounded, a bias voltage V relative to the drain metal electrode 301 is applied to the semiconductor layer 100. g After a forward bias is applied, a certain concentration of charge carriers (such as electrons) will be induced in the one-dimensional semiconductor material strip 304 between the source metal electrode 300 and the drain metal electrode 301. A portion of these charge carriers will tunnel through the insulating encapsulation layer 200 to the encapsulated graphene nanoribbon 201. The charge carriers stored in the graphene nanoribbon 201 will shield part of the electric field from the control electrode, causing the turn-on voltage V of the one-dimensional semiconductor material strip 304 between the source metal electrode 300 and the drain metal electrode 301 to decrease. sdThe presence or absence of stored charge in the graphene nanoribbons 201 within the insulating package can affect the turn-on voltage of the test channel, thus distinguishing between the '0' and '1' states. Since the charge within the graphene nanoribbons 201 in the insulating package can be stored long-term, this semiconductor device can be configured as a floating-gate memory device.

[0085] Example 2

[0086] This embodiment provides a method for fabricating a semiconductor device based on encapsulated graphene nanoribbons. This method can be used to fabricate the semiconductor device based on encapsulated graphene nanoribbons described in Embodiment 1 above. The effect of the semiconductor device based on encapsulated graphene nanoribbons obtained by this method can be found in Embodiment 1 above, and will not be repeated hereafter. The fabrication method includes the following steps:

[0087] A substrate is provided, the substrate including a semiconductor layer and an insulating layer located on the surface of the semiconductor layer;

[0088] Encapsulated graphene nanoribbons are formed on the surface of the insulating layer of the substrate;

[0089] Metal electrodes are formed on or inside the encapsulated graphene nanoribbons;

[0090] The method for forming the encapsulated graphene nanoribbons includes:

[0091] An insulating package with atomic-level flatness is provided, the insulating package being formed by stacking at least two atomic layers in parallel, adjacent atomic layers being bonded by van der Waals forces, and at least one longitudinal section being formed on the insulating package, the longitudinal section extending from the surface of the insulating package along the thickness direction of the insulating package.

[0092] Nanocatalyst particles are formed on the surface of the insulating package and the longitudinal section surface, and the nanocatalyst particles are bonded to the surface of the insulating package and the longitudinal section surface.

[0093] Growth process: The insulating encapsulation containing the nano-catalyst particles is subjected to chemical vapor deposition to form a carbon product layer on the surface of the insulating encapsulation and graphene nanoribbons inside the insulating encapsulation. The graphene nanoribbons break through the van der Waals forces of any two adjacent atomic layers exposed on the longitudinal section and embed themselves between the two atomic layers, and are encapsulated by the insulating encapsulation. The reaction gas introduced is a carbon source gas, and the growth temperature is 600℃~1000℃.

[0094] Cooling process: After growth is complete, the carbon source gas is turned off, and the material is cooled to room temperature under the protection of the protective gas before being removed.

[0095] Etching process: The carbon product layer formed on the surface of the insulating package during the growth process is removed, thereby forming the graphene nanoribbons only inside the insulating package.

[0096] The formation mechanism of graphene nanoribbons in the semiconductor device fabrication method based on encapsulation of this embodiment is as follows: First, the nanocatalyst particles are bonded to the surface of the longitudinal section. During the growth process, at a growth temperature of 600℃~1000℃, the carbon source gas is cracked and releases carbon atoms and carbon-containing free radicals with the assistance of the nanocatalyst particles. When the carbon content in the nanocatalyst particles at the surface of the longitudinal section reaches a certain supersaturation, carbon will precipitate and nucleate from the nanocatalyst particles, break through the van der Waals forces between two adjacent atomic layers and intercalate into the atomically flat insulating encapsulation body, thereby growing a layer embedded between the atomic layers of the insulating encapsulation body, i.e., between the two-dimensional encapsulation material layers. Finally, the carbon product layer formed on the surface of the insulating encapsulation body is removed. The graphene nanoribbons prepared by this method are embedded inside the insulating encapsulation and are not exposed on the surface of the insulating encapsulation. This gives the graphene nanoribbons properties close to those of intrinsic nanoribbons. At the same time, the edge structure of the graphene nanoribbons is regular. In addition, the preparation method is simple, low in cost, and can be mass-produced, thus having good industrialization value.

[0097] like Figure 1 As shown, as an example, the method for fabricating the semiconductor device based on encapsulated graphene nanoribbons further includes the step of fabricating a source metal electrode 300 and a drain metal electrode 301, wherein the source metal electrode 300 and the drain metal electrode 301 extend from the surface of the insulating encapsulation 200 into its interior and are in contact with the cross-section of the same graphene nanoribbon 201. Figures 6 to 10 As shown, preferably, the method for preparing the source metal electrode 300 and the drain metal electrode 301 includes: as follows Figure 6 and Figure 7 As shown, firstly, a photoresist layer 305 is coated on the surface of the substrate 10 on which the encapsulated graphene nanoribbons 20 are formed; as Figure 8 As shown, the photoresist layer 305 is then patterned to form a patterned photoresist layer 306. For example, electron beam lithography can be used to expose the photoresist layer 305 to obtain the patterned photoresist layer 306. The window formed in the patterned photoresist layer 306 is located above the same graphene nanoribbon 201, so that the cross-section of the graphene nanoribbon 201 can be exposed after subsequent etching of the insulating package 200; for example... Figure 9 As shown, next, the encapsulated graphene nanoribbons 20 are etched based on the patterned photoresist layer 306 to expose the cross-section of the same graphene nanoribbon 201, thereby obtaining an etched trench 307; as Figure 10As shown, a metal material layer 308 is then formed on the surface of the structure obtained above. This metal material layer 308 fills the etched trenches 307 and is also deposited on the surface of the patterned photoresist layer 306; as Figure 1 As shown, finally, the patterned photoresist layer 306 and the metal material layer 308 on its surface are removed, so that the remaining metal material layer 308 is formed as the source metal electrode 300 and the drain metal electrode 301.

[0098] like Figure 2 and Figure 3 As shown, as an example, the method for fabricating the semiconductor device based on encapsulated graphene nanoribbons further includes the steps of fabricating a first metal electrode 302 and a second metal electrode 303, wherein the first metal electrode 302 extends from the surface of the insulating encapsulation 200 toward its interior and is in contact with the cross-section of the first graphene nanoribbon 202, and the second metal electrode 303 extends from the surface of the insulating encapsulation 200 toward its interior and is in contact with the cross-section of the second graphene nanoribbon 203, wherein the first graphene nanoribbon 202 and the second graphene nanoribbon 203 are located between different atomic layers in the insulating encapsulation 200 and intersect in space. Preferably, the method for fabricating the first metal electrode 302 and the second metal electrode 303 includes: firstly, coating a photoresist layer on the surface of the substrate 10 on which the encapsulated graphene nanoribbons 20 are formed; then, patterning the photoresist layer to form a patterned photoresist layer, for example, by exposing the photoresist layer using an electron beam lithography method to obtain the patterned photoresist layer, wherein the window formed in the patterned photoresist layer is located above two intersecting graphene nanoribbons to facilitate subsequent processing of the insulating encapsulation 2. After etching, the cross-sections of the two intersecting graphene nanoribbons are exposed; then, the encapsulated graphene nanoribbons 20 are etched based on the patterned photoresist layer to expose the cross-sections of the first and second graphene nanoribbons, which are located between different atomic layers and spatially intersecting within the insulating package, thus obtaining etching trenches; next, a metal material layer is formed on the surface of the obtained structure, which fills the etching trenches and is also formed on the surface of the patterned photoresist layer 306; as Figure 3 As shown, finally, the patterned photoresist layer and the metal material layer on its surface are removed, thereby the remaining metal material layer is formed as the first metal electrode 302 and the second metal electrode 303.

[0099] The following specific experimental examples further illustrate the fabrication method of the encapsulated graphene nanoribbon semiconductor device of this embodiment.

[0100] Experimental Example 1

[0101] 1) Take a silicon wafer with a silicon oxide layer of 285nm thickness, i.e. substrate 10, cut it into 1cm×1cm pieces, cleave hexagonal boron nitride (hBN), evaporate the catalyst and grow ultra-long graphene nanoribbons encapsulated between the hexagonal boron nitride layers in a tube furnace, i.e. encapsulated graphene nanoribbon 20.

[0102] 2) The above sample was placed in a plasma cleaner and the carbon nanotubes grown on the sample surface were oxidized in an O2 environment to obtain clearer images of atomic interlayer graphene nanoribbons in a scanning electron microscope. The parameters selected were: gas flow rate 5 sccm, power 30W, and time 30s.

[0103] 3) Use a scanning electron microscope to photograph interatomic graphene nanoribbons and screen for graphene nanoribbons suitable for use as field-effect transistors.

[0104] 4) Spin-coat a layer of polymethyl methacrylate (PMMA) onto the silicon wafer surface where the sample is located at a speed of 4000 rpm for 30 seconds.

[0105] 5) Denature the PMMA in 3-4 cross-shaped patterns around the sample using electron beam lithography, and wash away the denatured PMMA with developer. These denatured PMMA serve as positioning marks 309 for subsequent overlay. Figure 11 As shown.

[0106] 6) Using the positioning mark 309, two areas in the middle section of the target graphene nanoribbon are selected to draw the source and drain metal electrode patterns. The PMMA is then patterned again using electron beam exposure with overlay marks. The denatured PMMA is washed away with developer to expose the underlying hexagonal boron nitride and silicon wafer. Figure 12 As shown.

[0107] 7) The above samples were fed into a reactive ion etching (RIE) machine. The first etching conditions were: CHF3 flow rate of 40 sccm and O2 flow rate of 6 sccm, pressure maintained at approximately 11 Pa, RF power of 45 W, etching time of 7 min, sample stage height z = 10 mm, and sample stage temperature of 15 °C. Under these CHF3 and O2 etching conditions, the silicon oxide layer was slightly damaged.

[0108] Another etching condition: First, the residual organic liquid layer on the sample surface is etched using CHF3 and O2. The etching conditions are basically the same as the first etching condition, except that the etching time is set to 10-20 seconds to fully expose the hexagonal boron nitride. Then, SF6 with a flow rate of 80 sccm, a pressure of approximately 12 Pa, an RF power of 35 W, and an etching time of 1 minute are introduced. It is important to note that the etching time needs to be adjusted flexibly according to different samples to avoid completely etching through the hexagonal boron nitride. Otherwise, some hexagonal boron nitride will also be etched along the direction parallel to the silicon wafer, leading to poor contact between the subsequent graphene nanoribbons and the metal electrodes. The sample stage height is set to z = 10 mm, and the sample stage temperature is 15 °C. Under this SF6 etching condition, the silicon oxide layer is basically undamaged.

[0109] 8) As soon as possible, send the etched sample into the evaporation coating chamber to deposit 3nm Cr and 100nm Au. The total thickness of the metal must exceed the height of hexagonal boron nitride.

[0110] Alternatively, a thicker layer of Cr, such as 60 nm Cr and 40 nm Au, can be deposited to ensure contact between the graphene nanoribbons and Cr. Or, a Cr / Pd / Au metallic structure can be deposited.

[0111] 9) First, prepare acetone and heat it on a heating stage at 80℃~100℃ for a period of time to raise the internal temperature of the acetone. Then, immerse the sample after metal deposition in hot acetone for about 1 hour. If the gold film on the sample surface has not yet fallen off, use a pipette to gently blow off the metal film on the surface. Afterward, quickly transfer the sample with the metal film detached to an isopropanol solution to wash away the residual acetone. Then, place the sample in fresh acetone or N-methylpyrrolidone for about 15 minutes to further wash away the residual organic matter on the sample surface. Immediately afterwards, wash away the residual acetone on the sample surface in fresh isopropanol solution. Finally, use a nitrogen gun to blow away the isopropanol liquid on the surface of the silicon wafer. This yields the following result: Figure 1 The field-effect transistor device based on a single graphene nanoribbon, and its corresponding scanning electron micrograph, are shown in the following image. Figure 13 As shown, the bright white line between the source metal electrode 300 and the drain metal electrode 301 is the graphene nanoribbon 201 encapsulated in the interlayer of hexagonal boron nitride.

[0112] Experimental Example 2

[0113] This experimental example is basically the same as Experiment 1, except that in step 3), the atomic-layer graphene nanoribbons are imaged using a scanning electron microscope, and two spatially intersecting graphene nanoribbons are selected. The prepared semiconductor device uses metal electrodes on different graphene nanoribbons as the first and second metal electrodes, thereby forming a tunneling device based on two intersecting graphene nanoribbons, such as... Figure 3 The image shown is a scanning electron microscope image.

[0114] Experimental Example 3

[0115] 1) Take a silicon wafer with a silicon oxide layer of 285nm thickness, i.e. substrate 10, cut it into 1cm×1cm pieces, cleave hexagonal boron nitride (hBN), evaporate the catalyst and grow ultra-long graphene nanoribbons encapsulated between the hexagonal boron nitride layers in a tube furnace, i.e. encapsulated graphene nanoribbon 20.

[0116] 2) The above sample was placed in a plasma cleaner and the carbon nanotubes grown on the sample surface were oxidized in an O2 environment to obtain clearer images of atomic interlayer graphene nanoribbons in the scanning electron microscope. The parameters selected were: gas flow rate 5 sccm, power 30W, and time 30s.

[0117] 3) Use scanning electron microscopy to image atomically interlayer graphene nanoribbons and screen for graphene nanoribbons suitable for tunneling devices based on single graphene nanoribbons.

[0118] 4) Spin-coat a layer of polymethyl methacrylate (PMMA) onto the silicon wafer surface where the sample is located at a speed of 4000 rpm for a total spin-coating time of 30 s.

[0119] 5) Denature the PMMA in 3-4 cross patterns around the sample using electron beam lithography, and wash away the denatured PMMA with developer as positioning marks 309 for subsequent overlay.

[0120] 6) Using the positioning mark 309, two areas in the middle section of the target graphene nanoribbon are selected to draw the electrode patterns of the source metal electrode and the drain metal electrode. The PMMA is then patterned again using electron beam exposure with overlay marks. The denatured PMMA is washed away with developer to expose the hexagonal boron nitride and silicon wafer underneath.

[0121] 7) The obtained sample is sent into the evaporation coating chamber and 3nm Cr and 100nm Au are deposited. The total thickness of the metal must exceed the height of hexagonal boron nitride.

[0122] 8) First, prepare acetone and heat it on a heating stage at 80℃~100℃ for a period of time to raise the internal temperature of the acetone; then immerse the sample after metal deposition in hot acetone for about 1 hour. If the gold film on the sample surface has not yet fallen off, use a pipette to gently blow off the metal film on the surface; then quickly transfer the sample with the metal film detached to isopropanol solution to wash away the residual acetone; then place the sample in fresh acetone or N-methylpyrrolidone for about 15 minutes to further wash away the residual organic matter on the sample surface; immediately afterward, wash away the residual acetone on the sample surface in fresh isopropanol; finally, use a nitrogen gun to blow away the isopropanol liquid on the silicon wafer surface. This yields the following result: Figure 4 A tunneling device based on a single graphene nanoribbon.

[0123] In summary, this invention provides a semiconductor device based on encapsulated graphene nanoribbons and its fabrication method. The semiconductor device uses graphene nanoribbons as the semiconductor material layer, encapsulated in an insulating package with atomically flatness, isolating it from the external environment. This allows the graphene nanoribbons to possess properties close to those of intrinsic nanoribbons. Furthermore, the graphene nanoribbons are effectively protected during the fabrication process, avoiding problems such as molecular adsorption and organic liquid contamination. This results in a high-quality, high-performance carbon-based electronic device. Carbon-based electronic devices exhibit low contact barriers, high mobility, and excellent conductivity. In addition, the fabrication method is simple, low-cost, and can be mass-produced, possessing significant industrialization value. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and has high industrial applicability.

[0124] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A packaged graphene nanoribbon-based semiconductor device, comprising: The semiconductor device includes: a substrate, encapsulated graphene nanoribbons located on the substrate, and corresponding metal electrodes; The substrate includes a semiconductor layer and an insulating layer located on the surface of the semiconductor layer; The encapsulated graphene nanoribbons include: An insulating package located on the insulating layer of the substrate and having atomic-level flatness, the insulating package being formed by at least two atomic layers stacked in parallel in sequence, and adjacent atomic layers being bonded together by van der Waals forces; At least one longitudinal section is formed by the insulating package extending from the surface of the insulating package along the thickness direction of the insulating package for one or more atomic layers; At least one graphene nanoribbon breaks through the van der Waals forces of any two adjacent atomic layers exposed on the longitudinal section and is embedded between the two atomic layers, and is encapsulated by the insulating encapsulation body, wherein the boundary shape of the graphene nanoribbon is serrated. The semiconductor device further includes: a first metal electrode and a second metal electrode; the first metal electrode extends from the surface of the insulating package toward its interior and is in contact with the cross-section of the first graphene nanoribbon; the second metal electrode extends from the surface of the insulating package toward its interior and is in contact with the cross-section of the second graphene nanoribbon; the first graphene nanoribbon and the second graphene nanoribbon are located between different atomic layers in the insulating package and intersect in space; or, The semiconductor device further includes: a source metal electrode, a drain metal electrode, and a one-dimensional semiconductor material strip; the source metal electrode and the drain metal electrode are disposed on the surface of the insulating package and are located directly above the same graphene nanoribbon; the one-dimensional semiconductor material strip is disposed on the surface of the insulating package and is located between and in contact with the source metal electrode and the drain metal electrode.

2. The packaged graphene nanoribbon-based semiconductor device of claim 1, wherein: The insulating layer is a silicon oxide insulating layer; the semiconductor layer is a silicon semiconductor layer; and the insulating package is a hexagonal boron nitride insulating package.

3. The semiconductor device based on encapsulated graphene nanoribbons according to claim 1, characterized in that, The semiconductor device further includes a source metal electrode and a drain metal electrode; the source metal electrode and the drain metal electrode extend from the surface of the insulating package into its interior and are in contact with the cross-section of the same graphene nanoribbon.

4. The packaged graphene nanoribbon-based semiconductor device of claim 1, wherein, The semiconductor device further includes a source metal electrode and a drain metal electrode; the source metal electrode and the drain metal electrode are disposed on the surface of the insulating package and are located directly above the same graphene nanoribbon.

5. A method for fabricating a semiconductor device based on encapsulated graphene nanoribbons as described in claim 1, characterized in that, The preparation method includes the following steps: A substrate is provided, the substrate including a semiconductor layer and an insulating layer located on the surface of the semiconductor layer; Encapsulated graphene nanoribbons are formed on the surface of the insulating layer of the substrate; Metal electrodes are formed on or inside the encapsulated graphene nanoribbons; The method for forming the encapsulated graphene nanoribbons includes: An insulating package with atomic-level flatness is provided, the insulating package being formed by stacking at least two atomic layers in parallel, adjacent atomic layers being bonded by van der Waals forces, and at least one longitudinal section being formed on the insulating package, the longitudinal section extending from the surface of the insulating package along the thickness direction of the insulating package. Nanocatalyst particles are formed on the surface of the insulating package and the longitudinal section surface, and the nanocatalyst particles are bonded to the surface of the insulating package and the longitudinal section surface. Growth process: The insulating encapsulation containing the nano-catalyst particles is subjected to chemical vapor deposition to form a carbon product layer on the surface of the insulating encapsulation and graphene nanoribbons inside the insulating encapsulation. The graphene nanoribbons break through the van der Waals forces of any two adjacent atomic layers exposed on the longitudinal section and embed themselves between the two atomic layers, and are encapsulated by the insulating encapsulation. The reaction gas introduced is a carbon source gas, and the growth temperature is 600℃~1000℃. Cooling process: After growth is complete, the carbon source gas is turned off, and the material is cooled to room temperature under the protection of the protective gas before being removed. Etching process: The carbon product layer formed on the surface of the insulating package during the growth process is removed, thereby forming the graphene nanoribbons only inside the insulating package.

6. The method for fabricating a semiconductor device based on encapsulated graphene nanoribbons according to claim 5, characterized in that, The preparation method further includes the step of preparing a source metal electrode and a drain metal electrode, wherein the source metal electrode and the drain metal electrode extend from the surface of the insulating package into its interior and are in contact with the cross-section of the same graphene nanoribbon.

7. The method for fabricating a semiconductor device based on encapsulated graphene nanoribbons according to claim 6, characterized in that, The method for preparing the source metal electrode and the drain metal electrode includes: A photoresist layer is coated on the surface of the substrate on which the encapsulated graphene nanoribbons are formed, and the photoresist layer is patterned to form a patterned photoresist layer. Based on the patterned photoresist layer, the encapsulated graphene nanoribbon is etched to expose the cross-section of the same graphene nanoribbon, thereby obtaining etched trenches. The etched trenches are filled with a metallic material that extends above the surface of the etched trenches to obtain the source metal electrode and the drain metal electrode.

8. The method for fabricating a semiconductor device based on encapsulated graphene nanoribbons according to claim 5, characterized in that, The preparation method further includes the steps of preparing a first metal electrode and a second metal electrode, wherein the first metal electrode extends from the surface of the insulating package toward its interior and is in contact with the cross section of the first graphene nanoribbon, and the second metal electrode extends from the surface of the insulating package toward its interior and is in contact with the cross section of the second graphene nanoribbon, wherein the first graphene nanoribbon and the second graphene nanoribbon are located between different atomic layers in the insulating package and intersect in space.

9. The method for fabricating a semiconductor device based on encapsulated graphene nanoribbons according to claim 8, characterized in that, The method for preparing the first metal electrode and the second metal electrode includes: A photoresist layer is coated on the surface of the substrate on which the encapsulated graphene nanoribbons are formed, and the photoresist layer is patterned to form a patterned photoresist layer. Based on the patterned photoresist layer, the encapsulated graphene nanoribbons are etched to expose the cross-sections of the first and second graphene nanoribbons, which are located between different atomic layers and spatially intersecting in the insulating package, to obtain etched trenches. The etched trenches are filled with a metallic material that extends above the surface of the etched trenches to obtain the first metal electrode and the second metal electrode.

10. The method of claim 7 or 9, wherein the method further comprises: The photoresist layer is exposed using an electron beam exposure method to obtain the patterned photoresist layer.

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