Dual core breakdown protection inductor topology

Abstract

A breakdown protection circuit includes: a first switch connected to a positive bus and connected to a first central node via a first electrical path; a second switch connected to a negative bus and connected to the first central node via a second electrical path; a detour third electrical path connecting the first central node to a first load output; a first magnetic core surrounding the first electrical path and the detour third electrical path; a second magnetic core surrounding the second electrical path and the detour third electrical path, wherein the polarity of one of the first electrical path and the second electrical path is consistent with the polarity of the detour third electrical path within a corresponding one of the first magnetic core and the second magnetic core, and the polarity of the other of the first electrical path and the second electrical path is opposite to the polarity of the detour third electrical path within a corresponding one of the first magnetic core and the second magnetic core.

Description

Technical Field

[0001] This disclosure generally relates to breakdown current fault protection circuits for circuits exposed to breakdown current spikes. Background Technology

[0002] Circuits (such as those used in satellites and spacecraft) encompass a wide range of power requirements. DC-to-AC conversion, DC-to-DC conversion, and many other standard power system implementations involve bridging circuits, such as H-bridge circuits, utilizing multiple transistors arranged in series, which are alternately switched on to provide the appropriate power conversion. Exposure to certain conditions more prevalent in space applications can cause undesirable closure of one or more switches within a circuit. When a closed switch causes the positive terminal to connect in series with the negative terminal, a short circuit occurs, and a rapid increase in current is generated. This condition is known as a breakdown event.

[0003] In some cases, a rapid increase in current can cause the current passing through switches or other electronic devices to exceed their rated current levels, potentially damaging or destroying the devices. Furthermore, due to the rate at which current rises during a breakdown event, existing reactive (i.e., active only after the event is detected) protection systems may be too slow to provide adequate protection during some events. Summary of the Invention

[0004] In one exemplary embodiment, a breakdown protection circuit includes: a first switch connected to a positive bus and connected to a first central node via a first electrical path; a second switch connected to a negative bus and connected to the first central node via a second electrical path; a detour third electrical path connecting the first central node to a first load output; a first magnetic core surrounding the first electrical path and the detour third electrical path; a second magnetic core surrounding the second electrical path and the detour third electrical path, wherein the polarity of one of the first electrical path and the second electrical path is consistent with the polarity of the detour third electrical path within a corresponding one of the first magnetic core and the second magnetic core, and the polarity of the other of the first electrical path and the second electrical path is opposite to the polarity of the detour third electrical path within a corresponding one of the first magnetic core and the second magnetic core.

[0005] Another example of the breakdown protection circuit described above further includes: a third switch connected to the positive bus and connected to the second center node via a fourth electrical path; a fourth switch connected to the negative bus and connected to the second center node via a fifth electrical path; a detour sixth electrical path connecting the second center node to a second load output; a first magnetic core surrounding the fourth electrical path and the detour sixth electrical path; a second magnetic core surrounding the fifth electrical path and the detour sixth electrical path, wherein the polarity of one of the fourth and fifth electrical paths is the same as the polarity of the detour sixth electrical path within a corresponding one of the first and second magnetic cores, and the polarity of the other of the fourth and fifth electrical paths is opposite to the polarity of the detour sixth electrical path within a corresponding one of the first and second magnetic cores.

[0006] In another example of any of the breakdown protection circuits described above, the polarity of the first electrical path is the same as the polarity of the detour third electrical path in the first magnetic core, and the polarity of the fourth electrical path is opposite to the polarity of the detour sixth electrical path in the first magnetic core.

[0007] In another example of any of the breakdown protection circuits described above, the polarity of the second electrical path is opposite to that of the detour third electrical path in the second magnetic core, and the polarity of the fifth electrical path is consistent with that of the detour sixth electrical path in the second magnetic core.

[0008] In another example of any of the breakdown protection circuits described above, the first, second, third, and fourth switches are connected as an H-bridge topology.

[0009] In another example of any of the breakdown protection circuits described above, the circuit is characterized by the absence of a zero-volt switching (ZVS) inductor.

[0010] In another example of any of the breakdown protection circuits described above, at least one of the first and second switches includes a voltage spike buffer.

[0011] In another example of any of the breakdown protection circuits described above, at least one of the first and second switches lacks a voltage spike buffer.

[0012] In another example of any of the breakdown protection circuits described above, each of the first switch and the second switch is a field-effect transistor (FET).

[0013] In another example of any of the breakdown protection circuits described above, the first switch and the second switch are arranged in a half-bridge topology.

[0014] An exemplary method for mitigating breakdown events includes: connecting a first switch to a central node via a first electrical path; connecting a second switch to the central node via a second electrical path; connecting the central node to a load via a detour third electrical path; passing the first electrical path and the detour third electrical path through a first magnetic core; passing the second electrical path and the detour third electrical path through a second magnetic core, wherein the first electrical path coincides with the detour third electrical path within the first magnetic core, and the polarity of the second electrical path is opposite to that of the detour third electrical path within the second magnetic core.

[0015] Another example of the method for mitigating breakdown events described above further includes: connecting a third switch to a second center node via a fourth electrical path; connecting a fourth switch to the second center node via a fifth electrical path; connecting the second center node to the load via a detour sixth electrical path; passing the fourth electrical path and the detour sixth electrical path through the first magnetic core; passing the fifth electrical path and the detour sixth electrical path through the second magnetic core, wherein the polarity of the fourth electrical path is opposite to the polarity of the detour sixth electrical path within the first magnetic core, and wherein the polarity of the fifth electrical path is consistent with the detour sixth electrical path within the second magnetic core.

[0016] In another example of any of the methods described above for mitigating breakdown events, the first switch and the second switch are field-effect transistors.

[0017] Another example of any of the methods described above for mitigating breakdown events further includes using the body diode of each of the first and second switches to buffer the zero-voltage switching voltage.

[0018] These and other features of the invention can be best understood from the following description and drawings, which are briefly described below. Attached Figure Description

[0019] Figure 1 illustrates an exemplary prior art H-bridge switch circuit topology.

[0020] Figure 2 An exemplary dual-core breakdown-protected inductor H-bridge rectifier topology is schematically illustrated.

[0021] Figure 3 An exemplary dual-core breakdown-protected half-bridge rectifier topology is schematically illustrated. Detailed Implementation

[0022] Figure 1 schematically illustrates an exemplary H-bridge topology 10 according to an existing circuit design. The H-bridge 10 includes four transistors 22, 24, 26, and 28, having a first set of two transistors 22 and 24 arranged in series, and a second set of two transistors 26 and 28 arranged in series. An inductor 30 is connected across nodes 40 and 42, which connect to each set of transistors 22, 24, 26, and 28. The inductor 30 creates an electromagnetic connection to a transformer 50, and a controller 60 controls the operation of the transistors 22, 24, 26, and 28 to prevent two transistors in any set from closing simultaneously. The positive and negative terminals of each set of transistors 22, 24, 26, and 28 are connected to the positive and negative terminals of the corresponding DC bus. The controller 60 operates according to known H-bridge control principles to supply power to a power distribution system. The inductor 30 also operates as a zero-voltage switching (ZVS) inductor and mitigates breakdown events.

[0023] During normal operation, transistors 22, 24, 26, and 28 are alternately switched by controller 60 to provide the correct power output across 40 and 42. Due to the semiconductor construction of the transistors, exposure to radiation or electromagnetic pulses may overshoot the control signal input and force transistors 22, 24, 26, and 28 into a closed (or, alternatively, a breakdown) state. A short circuit occurs when all two transistors 22, 24 or 26, 28, or both sets of transistors simultaneously are in the closed state, directly connecting the positive and negative terminals. A short circuit results in a rapid current ramp (di / dt) of high current levels that can burn out the connected circuitry or the transistors 22, 24, 26, and 28 themselves, leading to an irreversible failure state.

[0024] Most ground applications are not expected to be exposed to the types of hazards that could lead to the failure states described above. However, space applications, such as satellites, space stations, and similar systems, are exposed to radiation spikes that could lead to the failure states described above for the duration of the radiation spikes. Similarly, ground applications expected to be exposed to a significant amount of radiation or electromagnetic pulses may experience the same or similar failure states. In both cases, when the transistor in the H-bridge is exposed to an event, the transistor may be forced to close (break down) until the event has completely passed.

[0025] Continuing to refer to the general H-bridge configuration in Figure 1, where similar reference numerals indicate similar elements, Figure 2 The illustration schematically depicts an H-bridge configuration 100, including a dual-core breakdown protection inductor arrangement configured to protect against the failure states described above. Like the conventional H-bridge 10, Figure 2The H-bridge 100 includes two sets of transistors 122, 124, 126, and 128, each set being arranged in series and connected to corresponding center node pairs 140 and 142 via electrical paths 182, 184, 186, and 188. Each of the sets of transistors 122, 124 and 126, 128 connects a positive terminal to a negative terminal. The zero-voltage switching inductor 30 connecting nodes 140 and 142 in the prior art is omitted (in...). Figure 2 (The image shown is omitted in the dashed line diagram) and is replaced by a pair of magnetic cores 132, 134 arranged in a double-pass protection configuration. The directional arrows shown indicate exemplary instantaneous current flow during normal operation.

[0026] Each of nodes 140, 142 is connected to a terminal of load 190 via a corresponding detour electrical path 170, 172. As used herein, an electrical path refers to any combination of wires, circuit traces, or other current paths that connect an electrical component to a minimum or negligible impedance. Each detour electrical path 170, 172 is wound around a dual magnetic core 132, 134 such that as electrical path 170, 172 passes through one of cores 132, 134, the polarity of electrical path 170, 172 is the same as that of the corresponding transistors 122, 124, 126, 128, and as electrical path 170, 172 passes through the other of cores 132, 134, the polarity of electrical path 170, 172 is opposite to that of the corresponding transistors 122, 124, 126, 128. As used herein, same polarity means that the expected direction of current flow matches, and opposite polarity means that the expected direction of current flow is opposite.

[0027] Electrical paths 170 and 172 are configured such that in each of cores 132 and 134, one electrical path 170 and 172 is polarity matched with the corresponding electrical paths 182, 184, 186, and 188, and the polarity of one electrical path 170 and 172 is opposite to that of the corresponding electrical paths 182, 184, 186, and 188. During normal operation, this configuration causes most of the flux from cores 132 and 134 to be canceled out, allowing cores 132 and 134 to operate in place of the zero-voltage switching inductor 130 of the conventional H-bridge 10 (see Figure 1). Normal operation involves repeated switching of transistors 122, 124, 126, and 128, with each switching resulting in a negative voltage spike. In some examples, the body diode 180 is sufficiently sized and combined with the uncancelled flux to suppress the negative voltage spikes caused by switching without requiring additional circuitry. In an alternative example, a negative voltage spike is expected to exceed the capability of the transistor body diode 180, and a voltage buffer circuit is included. The voltage buffer circuit can be any available voltage buffer circuit capable of handling the expected magnitude of voltage spikes that occur due to switching, and can be connected to any known buffer configuration.

[0028] When a radiation event or any other event occurs that causes all transistors 122, 124, 126, and 128 to operate in the closed (breakdown) state, each of the positive nodes is directly connected to the corresponding negative node, and all current flows through cores 132 and 134 in the same direction from positive to negative. The consistent polarity of the current flow for the duration of the breakdown event generates a consistent flux in cores 132 and 134, and there is no flux cancellation. Thus, the inductance of lines 170 and 172 through cores 132 and 134 limits the rate at which current can increase. This limited current increase allows the transistors, and any electrical components connected to the positive and negative terminals, to survive the breakdown event until a controller or other protection system shuts off all transistors 122, 124, 126, and 128. After the breakdown event has completed, the controller or other protection system can reset transistors 122, 124, 126, and 128, thereby allowing transistors 122, 124, 126, and 128 to return to standard operation. In the event of a sufficiently short-lived breakdown, transistors 122, 124, 126, and 128 can immediately return to standard operation without requiring a reset of the protection circuitry.

[0029] Continue to refer to Figures 1 and 2, Figure 3 This illustration schematically depicts the application of a dual-core breakdown-protected inductor configuration to a half-bridge configuration 200. Those skilled in the art will appreciate that the teachings contained herein can be extrapolated to three-phase bridges and any other similar circuits. The half-bridge configuration 200 includes two transistors 222, 224, arranged in series and connected to a center node 240 via a first electrical path 282 and a second electrical path 284. Node 240 is connected to ground via a detour electrical path 270 passing through cores 230, 232 in the opposite direction. As in the H-bridge 100 example, the current flow through cores 230, 232 disables most, but not all, of the inductance due to flux, as well as the remaining inductance, replacing the inductor in a conventional half-bridge that would connect node 240 to ground 241.

[0030] Although the above descriptions of h-bridge and half-bridge topologies utilizing transistor switching elements are provided, the above descriptions of... Figure 2 and 3 The illustrated and described dual-core breakdown inductor configuration can be extended to any switching arrangement subject to potential damage breakdown events, including but not limited to motor drivers, other semiconductor switch types and / or other types of field-effect transistors (FETs).

[0031] It should be further understood that any of the concepts described above can be used alone or in combination with any or all of the other concepts described above. Although embodiments of the invention have been disclosed, those skilled in the art will recognize that certain modifications will fall within the scope of the invention. For this reason, the appended claims should be studied to determine the true scope and content of the invention.

Claims

1. A breakdown protection circuit, comprising: A first switch is connected to the positive bus and connected to the first central node via a first electrical path; The second switch is connected to the negative bus and connected to the first central node via a second electrical path; By taking a detour through a third electrical path, the first central node is connected to the first load output; The first magnetic core, the first electrical path and the detour third electrical path pass through the first magnetic core; as well as The second magnetic core, the second electrical path and the detour third electrical path pass through the second magnetic core; The polarity of one of the first electrical path and the second electrical path is consistent with the polarity of the detour third electrical path within the corresponding one of the first magnetic core and the second magnetic core, and the polarity of the other of the first electrical path and the second electrical path is opposite to the polarity of the detour third electrical path within the corresponding one of the first magnetic core and the second magnetic core. Consistent polarity means that the expected direction of current flow matches, and opposite polarity means that the expected direction of current flow is opposite.

2. The breakdown protection circuit as described in claim 1, further comprising: The third switch is connected to the positive bus and connected to the second central node via a fourth electrical path; A fourth switch is connected to the negative bus and to the second central node via a fifth electrical path; By taking a detour through the sixth electrical path, the second center node is connected to the second load output; The first magnetic core, the fourth electrical path and the detour sixth electrical path pass through the first magnetic core; as well as The second magnetic core, the fifth electrical path and the detour sixth electrical path pass through the second magnetic core; The polarity of one of the fourth and fifth electrical paths is consistent with the polarity of the detour sixth electrical path within the corresponding one of the first and second magnetic cores, and the polarity of the other of the fourth and fifth electrical paths is opposite to the polarity of the detour sixth electrical path within the corresponding one of the first and second magnetic cores.

3. The breakdown protection circuit as claimed in claim 2, wherein the polarity of the first electrical path is consistent with the polarity of the detour third electrical path in the first magnetic core, and the polarity of the fourth electrical path is opposite to the polarity of the detour sixth electrical path in the first magnetic core.

4. The breakdown protection circuit as claimed in claim 3, wherein the polarity of the second electrical path is opposite to the polarity of the detour third electrical path in the second magnetic core, and wherein the polarity of the fifth electrical path is consistent with the polarity of the detour sixth electrical path in the second magnetic core.

5. The breakdown protection circuit as claimed in claim 2, wherein the first, second, third and fourth switches are connected as an H-bridge topology.

6. The breakdown protection circuit of claim 1, wherein the circuit is characterized by the absence of a zero-volt switching (ZVS) inductor.

7. The breakdown protection circuit of claim 1, wherein at least one of the first and second switches includes a voltage spike buffer.

8. The breakdown protection circuit of claim 1, wherein at least one of the first and second switches lacks a voltage spike buffer.

9. The breakdown protection circuit of claim 1, wherein each of the first switch and the second switch is a field-effect transistor (FET).

10. The breakdown protection circuit of claim 1, wherein the first switch and the second switch are arranged in a half-bridge topology.

11. A method for mitigating breakdown events, comprising: A first switch is connected to a central node via a first electrical path, and a second switch is connected to the central node via a second electrical path; The central node is connected to the load via a detour third electrical path; The first electrical path and the detour third electrical path pass through the first magnetic core; The second electrical path and the detour third electrical path pass through the second magnetic core; and The polarity of the first electrical path is the same as the polarity of the detour third electrical path within the first magnetic core, and the polarity of the second electrical path is opposite to the polarity of the detour third electrical path within the second magnetic core. The same polarity means that the expected direction of current flow is matched, and the opposite polarity means that the expected direction of current flow is opposite.

12. The method of claim 11, further comprising: The third switch is connected to the second central node via the fourth electrical path, and the fourth switch is connected to the second central node via the fifth electrical path; The second central node is connected to the load via a detour sixth electrical path; The fourth electrical path and the detour sixth electrical path are made to pass through the first magnetic core; The fifth electrical path and the detour sixth electrical path pass through the second magnetic core; and The polarity of the fourth electrical path is opposite to that of the detour sixth electrical path within the first magnetic core, and the polarity of the fifth electrical path is the same as that of the detour sixth electrical path within the second magnetic core.

13. The method of claim 11, wherein the first switch and the second switch are field-effect transistors.

14. The method of claim 11, further comprising: The body diode of each of the first and second switches is used to buffer the zero-voltage switching voltage.

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