A method for transmitting and receiving spaceborne frequency-agile radar based on FPGA

Abstract

A method for transmitting and receiving spaceborne frequency-agile radar based on FPGA includes: first, determining the parameters of the broadband linear frequency modulated (LFM) signal to be generated; then, determining the processing clock rate of the DAC chip and the sampling rate of the ADC chip; based on the processing clock rate of the DAC chip and the processing capability of the FPGA chip, determining the number of LFM signal channels and clock rate to be processed in parallel by the FPGA in real time, and determining the angle quantization bits for real-time calculation by the FPGA. Then, by mathematically modeling the LFM signal, finding characteristic solutions, and using multi-level accumulation and decomposition of fixed characteristic values ​​for quantization and storage, the hardware limitations of the FPGA are overcome, realizing the calculation of power multiplication, and implementing the transmission and reception counting of arbitrary frequency-agile LFM signals in engineering. Applying this method, the bandwidth, duration, and center frequency of the signal are not restricted, and it can be uploaded in real time without the need for external waveform memory, reducing the timing risk of FPGA programming and improving the reliability of the design.

Description

Technical Field

[0001] This invention relates to a method for transmitting and receiving spaceborne frequency-agile radar based on FPGA, belonging to the field of spaceborne tracking radar signal processing technology. Background Technology

[0002] Frequency-agile radar is a type of pulse radar. The transceiver system designed in this paper transmits a pulsed linear frequency-modulated signal with a frequency-agile frequency response (FFM) configuration. This means the signal bandwidth and center frequency can be arbitrarily varied in real time, supporting both regular and random variations. This frequency-agile transceiver design achieves the most efficient and optimal anti-jamming capability among radar algorithms. Based on measured data, this design increases the detection range by 30% compared to traditional fixed-frequency radars with similar parameters.

[0003] This frequency-agile transceiver design features an instantaneously variable center frequency and signal bandwidth. It primarily enables the transmission and reception of frequency-agile radar signals, with a sampling rate of 200MHz and variable pulse width. The digital processing unit is highly integrated, including three AD converters and one DA converter. The main processing FPGA handles the down-conversion processing for transmission and reception, while the DSP provides timing control for the frequency agile signal. Summary of the Invention

[0004] The technical problem solved by this invention is to overcome the shortcomings of the prior art and provide a method for transmitting and receiving spaceborne frequency-agile radar based on FPGA. The method uses variable frequency word accumulation to generate frequency-agile transmit and receive waveforms and uses multi-stage filters to replace single high-order filters for digital filtering.

[0005] The technical solution of this invention is: a method for transmitting and receiving spaceborne frequency-agile radar based on FPGA, comprising:

[0006] 1) Determine the signal parameters of the linear frequency modulated signal to be transmitted, including the DAC chip sampling rate, the duration and bandwidth of the linear frequency modulated signal, the number of parallel interfaces of the DAC, and the quantization bit width;

[0007] 2) Based on the parameters, the real-time phase calculation of the transmitted signal is divided into two parts, namely K / f, which can be stored as a constant. s 2 And the remainder, which is computed in real time in the FPGA;

[0008] 3) Calculate the phase word of the transmitted linear frequency modulated signal in real time based on the center frequency above, and calculate the corresponding sin value based on the phase word and output it to the DAC chip;

[0009] 4) Determine the parameters for receiving down-conversion based on the center frequency of the received signal and the sampling rate of the ADC chip;

[0010] 5) Calculate the real-time phase accumulation word required for real-time digital down-conversion, which consists of two parts: one part is a fixed quantized 1 / f. s The remainder consists of multiplication operations calculated in real time.

[0011] 6) Calculate the real-time phase word of the received digital down-conversion based on the center frequency word of the current input signal, and calculate the real-time sin and cos values ​​required for down-conversion.

[0012] Furthermore, real-time calculation methods for transmit and receive angle values ​​include:

[0013] Calculate the phase accumulation word for a single parallel channel;

[0014] Then calculate the angle value for signal reception and processing.

[0015] Furthermore, the parallel single-channel phase accumulation includes:

[0016] phase(t)=phase(t-1)+delt_phase_A+delt_phase_B+delt_phase_C

[0017] delt_phase_A = 2 p *f i / f s

[0018] delt_phase_B = 2 p+4 *(2*N+18)*K / f s 2

[0019] delt_phase_C = 2 p+5 *K / f s 2

[0020] Where phase(t) is the frequency phase word at time t, delt_phase_A is the accumulated frequency word of the split A part, delt_phase_B is the accumulated frequency word of the split B part, delt_phase_C is the accumulated frequency word of the split C part, and f i f is the center frequency of the transmitted signal. s denoted as DAC sampling rate, p as quantization bit width, N as number of parallel transmit channels, and K as the modulation frequency of the transmitted linear frequency modulated signal.

[0021] Furthermore, the calculation of the angle value for signal reception processing includes:

[0022] delt(f) = 2πf i (t+1)-2π·f i t = 2π·f i / f s

[0023] phase(t) = phase(t-1) + delt(f)

[0024] Where delt(f) is the accumulated frequency word, t is the current sampling time, and f i f is the center frequency of the received signal. s Let be the ADC sampling frequency, and phase(t) be the frequency word at time t.

[0025] Furthermore, the calculated real-time sine and cosine values ​​are input into the Cordic IP core for angle calculation.

[0026] Furthermore, the parameters of the broadband linear frequency modulated signal include center frequency, time width, bandwidth, and duty cycle.

[0027] An FPGA-based spaceborne frequency-agile radar transmitting and receiving system includes:

[0028] The first module determines the signal parameters of the linear frequency modulated signal to be transmitted, including the DAC chip sampling rate, the duration of the linear frequency modulated signal, the bandwidth, the number of parallel interfaces of the DAC, and the quantization bit width.

[0029] The second module, based on the parameters, divides the real-time phase calculation of the transmitted signal into two parts, namely K / f, which can be stored as a constant. s 2 And the remainder, which is computed in real time in the FPGA;

[0030] The third module calculates the phase word of the transmitted linear frequency modulated signal in real time based on the center frequency above, and calculates the corresponding sin value based on the phase word and outputs it to the DAC chip.

[0031] The fourth module determines the parameters for receiving down-conversion based on the center frequency of the received signal and the sampling rate of the ADC chip.

[0032] The fifth module calculates the real-time phase accumulation word required for real-time digital down-conversion, which is divided into two parts: one part is a fixed quantized 1 / f. s The remainder consists of multiplication operations calculated in real time.

[0033] The sixth module calculates the real-time phase word of the received digital down-conversion based on the center frequency word of the current input signal, and generates the real-time sin and cos values ​​required for down-conversion.

[0034] Furthermore, real-time calculation methods for transmit and receive angle values ​​include:

[0035] Calculate the phase accumulation word for a single parallel channel;

[0036] Then calculate the angle value for signal reception and processing;

[0037] The parallel single-channel phase accumulation includes:

[0038] phase(t)=phase(t-1)+delt_phase_A+delt_phase_B+delt_phase_C

[0039] delt_phase_A = 2 p *f i / f s

[0040] delt_phase_B = 2 p+4 *(2*N+18)*K / f s 2

[0041] delt_phase_C = 2 p+5 *K / f s 2

[0042] Where phase(t) is the frequency phase word at time t, delt_phase_A is the accumulated frequency word of the split A part, delt_phase_B is the accumulated frequency word of the split B part, delt_phase_C is the accumulated frequency word of the split C part, and f i f is the center frequency of the transmitted signal. s Where p is the DAC sampling rate, N is the quantization bit width, K is the number of parallel transmission channels, and K is the modulation frequency of the transmitted linear frequency modulated signal.

[0043] Furthermore, the calculation of the angle value for signal reception processing includes:

[0044] delt(f) = 2πf i (t+1)-2π·f i t = 2π·f i / f s

[0045] phase(t) = phase(t-1) + delt(f)

[0046] Where delt(f) is the accumulated frequency word, t is the current sampling time, and f i f is the center frequency of the received signal. sLet be the ADC sampling frequency, and phase(t) be the frequency word at time t;

[0047] Furthermore, the calculated real-time sine and cosine values ​​are input into the Cordic IP core for angle calculation.

[0048] Furthermore, the parameters of the broadband linear frequency modulated signal include center frequency, time width, bandwidth, and duty cycle.

[0049] A computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the FPGA-based spaceborne frequency-agile radar transmission and reception method.

[0050] An FPGA-based spaceborne frequency-agile radar transmitting and receiving device includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the steps of the FPGA-based spaceborne frequency-agile radar transmitting and receiving method.

[0051] The advantages of this invention compared to the prior art are:

[0052] This invention overcomes the hardware limitations of FPGAs by mathematically modeling linear frequency modulated signals, finding characteristic solutions, and using multi-level accumulation and quantization storage of fixed characteristic values. It achieves power multiplication calculations and, in engineering applications, realizes the generation of frequency-agile signals and digital down-conversion of frequency-agile signals, enabling real-time frequency-agile transmission and reception of on-orbit radar. Simultaneously, experiments were conducted on a multi-core DSP-TMS320C6678+Xilinx V7 XC7VX690T hardware platform. Test results show a significant improvement in the search, detection, and tracking capabilities of this frequency-agile radar. This improved search efficiency solves the problems of weak target characteristics, large target resolution differences, and difficulty in stable real-time tracking in orbit for spaceborne radars, thus broadening its applicability. Attached Figure Description

[0053] Figure 1 This is a flowchart of the real-time processing method of the present invention;

[0054] Figure 2 This is a hardware implementation block diagram in an embodiment of the present invention;

[0055] Figure 3 This is a block diagram of the digital down-conversion implementation in an embodiment of the present invention. Detailed Implementation

[0056] To better understand the above technical solutions, the technical solutions of this application will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the embodiments of this application and the specific features in the embodiments are detailed descriptions of the technical solutions of this application, rather than limitations on the technical solutions of this application. In the absence of conflict, the embodiments of this application and the technical features in the embodiments can be combined with each other.

[0057] The following description, in conjunction with the accompanying drawings, provides a more detailed explanation of an FPGA-based spaceborne frequency-agile radar transmission and reception method provided in this application. Specific implementation methods may include (e.g.) Figures 1-3 As shown):

[0058] (1) Determine the required broadband linear frequency modulation signal parameters, including center frequency, time width, bandwidth, and duty cycle;

[0059] (2) Determine the number of channels and clock rate of the FPGA for real-time parallel processing of broadband linear frequency modulation signals based on the processing clock rate of the DAC and ADC chips and the processing capability of the FPGA chip; determine the number of angle quantization bits for real-time calculation of the FPGA based on the accuracy requirements of the broadband linear frequency modulation signals.

[0060] (3) Calculate the real-time angle required for each broadband linear frequency modulation signal and digital down-conversion mixing using the FPGA adder.

[0061] (4) Calculate the sine and cosine values ​​of the real-time angle of each broadband linear frequency modulation signal;

[0062] The sampling rate of ADC and DAC chips needs to satisfy the sampling theorem and be able to adapt to the processing capabilities of the main processing FPGA.

[0063] In step (3), the real-time transmission and reception angle values ​​are calculated as follows:

[0064] The formula for calculating the angle of signal transmission is as follows:

[0065] The formula for calculating the phase accumulation of a parallel single-channel circuit is as follows:

[0066] phase(t)=phase(t-1)+delt_phase_A+delt_phase_B+delt_phase_C;

[0067] delt_phase_A = 2 p *f i / f s ;

[0068] delt_phase_B = 2 p+4 *(2*N+18)*K / fs 2 ;

[0069] delt_phase_C = 2 p+5 *K / f s 2 ;

[0070] The formula for calculating the angle value in signal reception processing is as follows:

[0071] delt(f) = 2πf i (t+1)-2π·f if ·t=2π·f i

[0072] phase(t) = phase(t-1) + delt(f)

[0073] In step (4), the real-time sine and cosine values ​​are calculated by inputting the real-time phase values ​​calculated in step (3) into the Cordic IP core for angle calculation.

[0074] The solution provided in the embodiments of this application specifically includes:

[0075] 1) Frequency-short transmission realization

[0076] The formula for the pulsed frequency-agile transmit signal generated by the system is as follows:

[0077] y = cos(2πf) i t+πKt 2 )

[0078] θ=2πf i t+πKt 2 ,t=[0,τ)

[0079] Where f i This indicates the starting frequency of the broadband linear frequency modulated signal. B represents the modulation frequency of the linear frequency modulated signal, B represents the signal bandwidth, and T represents the time width.

[0080] This design uses 16 parallel channels.

[0081] The FPGA processes 16 data channels in real time in parallel. Following a sampling period T equal to 16 times that of the DAC chip, the data is decimated, quantized, and the input angle value of each signal is calculated in real time.

[0082] Route 1:

[0083] Δθ1(m)=θ(16m)-θ(16*m-16)=16f a T2 p +16 2 KT2 2 p-1 +16 2 (m-1)KT 2 2 p

[0084] Δθ1(m+1)=θ(16*m+8)-θ(16*m)=16f a T2 p +16 2 KT 2 2 p-1 +16 2 mKT 2 2 p

[0085] The difference between the two angular changes:

[0086] Δθ1(m+1)-Δθ1(m)=16 2 KT 2 2 p

[0087] Route 2:

[0088] Δθ2(m)=θ(16*m+1)-θ(16*m-15)=16f a T2 p +(16+2)*16KT 2 2 p-1 +16 2 (m-1)KT 2 2 p

[0089] Δθ2(m+1)=θ(16*m+17)-θ(16*m+1)=16f a T2 p +(16+2)*16*KT 2 2 p-1 +16 2 *mKT 2 2 p

[0090] The difference between two adjacent changes in angle:

[0091] Δθ2(m+1)-Δθ2(m)=16 2 *KT 2 2 p

[0092] …

[0093] Route 16:

[0094] Δθ i(m)=θ(16*m+16-1)-θ(16m-1)=16f a T2 p +(14+2i)*16*KT 2 2 p-1 +16 2 *(m-1)KT 2 2 p

[0095] Δθ i (m+1)=θ(16*m+32-1)-θ(16*m+16-1)=16*f a T2 p +(16+16-2)16*KT 2 2 p-1 +16 2 *mKT 2 2 p

[0096] The difference between two adjacent changes in angle:

[0097] Δθ i (m+1)-Δθ i (m)=16 2 *KT 2 2 p

[0098] Therefore, after analysis, a two-stage accumulation method can be used to calculate the real-time angle. The accumulation calculation requires calculating three phase accumulation factors, namely delt_phase_A, delt_phase_B, and delt_phase_C.

[0099] ΔT=1 / f s N represents the Nth path.

[0100] The formula for calculating the phase accumulation of a parallel single-channel circuit is as follows:

[0101] phase(t)=phase(t-1)+delt_phase_A+delt_phase_B+delt_phase_C;

[0102] delt_phase_A = 2 p *f i / f s ;

[0103] delt_phase_B = 2 p+4 *(2*N+18)*K / f s 2 ;

[0104] delt_phase_C = 2 p+5 *K / f s 2 ;

[0105] Since the DAC sampling rate is fixed, therefore 2 P *1 / f s The calculation and quantization can be performed locally. The quantized value is defined as a constant U, and K is the frequency modulation, which is the real-time calculation part. Calculated by FPGA division IP_CORE, 2 P *f i / f s The calculation is implemented using a multiplication kernel, represented as U*f. i .

[0106] Finally, the real-time phase words of N=16 paths are input into the Cordic core for cosine calculation. The output result is truncated to a 10-bit quantized value and then output to the DAC chip. The timing control changes the input frequency word f. i And at K, the instantaneous phase of the current frequency is recalculated, thereby enabling the frequency agile switching function of the transmission frequency.

[0107] Implementation of agile digital downconversion

[0108] Unlike traditional DDC engineering implementations, frequency-agile DDC input signal center frequency is variable, and the center frequency between different pulses is also changing. Real-time mixing frequency calculation is required. To reduce multiplier resource usage, the mixing generation module uses addition instead of multiplication to generate the frequency phase word. This is then implemented through a CORDIC IP core in the FPGA. Real-time input signal frequency words are needed to calculate the corresponding sin and cosine values ​​within the FPGA. The calculation is performed by addition within the period of the current frequency word, that is:

[0109] delt(f) = 2πf i (t+1)-2π·f if ·t=2π·f i

[0110] The input center frequency is used as the accumulated frequency word for frequency word accumulation to obtain a real-time continuous agile frequency mixing waveform. The current pulse center frequency of the entire system is calculated by the DSP and transmitted to the FPGA for frequency and phase calculation through the high-speed GPIO interface.

[0111] The calculation of delt(f) is performed using a multiplication kernel, which shares the same parameter U with the frequency agile transmission calculation.

[0112] The instantaneous phase input to the cordic calculation is:

[0113] phase(t) = phase(t-1) + delt(f)

[0114] After the instantaneous phase calculation is completed, the Cordic_IP core calculates and outputs the real-time mixing waveform. The specific engineering implementation is as follows: Figure 3 As shown.

[0115] The instantaneous phase word of the frequency-agile transmit and receive inputs is set to a normalized value for calculation.

[0116] This application provides a computer-readable storage medium storing computer instructions that, when executed on a computer, cause the computer to perform... Figure 1 The method described.

[0117] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product implemented on one or more computer-usable storage media (including, but not limited to, disk storage and optical storage) containing computer-usable program code.

[0118] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0119] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0120] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0121] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0122] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

[0123] The contents not described in detail in this specification are common knowledge to those skilled in the art.

Claims

1. A method for transmitting and receiving of a satellite-borne agile frequency radar based on FPGA, characterized in that, Comprise: 1) determine the signal parameters of the linear frequency modulation signal to be transmitted, including the DAC chip sampling rate, the linear frequency modulation signal time width, the bandwidth, the number of DAC parallel interfaces and the quantization bit width; 2) According to the parameters, the real-time phase calculation of the transmitting signal is divided into two parts, which are the constant part that can be stored as and the remaining part that is calculated in real time in the FPGA. 3) real-time calculation of the phase word of the transmitted linear frequency modulation signal according to the center frequency of the transmitted signal, and calculation of the corresponding sin value output to the DAC chip according to the phase word; 4) determining the parameters of the received down-conversion according to the center frequency of the received signal and the sampling rate of the ADC chip; 5) Calculate the real-time phase accumulation word needed for real-time digital down conversion, which is divided into two parts, one part is the fixed quantized and the other part is the multiplication part calculated in real time. 6) calculating the real-time phase word of the received digital down-conversion according to the center frequency word of the current input signal, and generating the real-time sin and cos values required for down-conversion for calculation; The real-time transmission and reception angle value calculation method comprises: Calculating the phase accumulation word of the parallel single channel; Then calculating the angle value of the signal reception processing; The phase accumulation of the parallel single channel comprises: wherein, is is the frequency phase word at the moment, is the accumulated frequency word of the A part after splitting, is the accumulated frequency word of the B part after splitting, is the accumulated frequency word of the C part after splitting, is the center frequency of the transmitted signal, is the DAC sampling rate, is the quantization bit width, is the number of transmitting parallel paths, is the frequency modulation rate of the transmitted chirp signal.

2. The transmitting and receiving method of a spaceborne agile frequency radar based on FPGA according to claim 1, wherein, The calculation of the angle value of the signal reception processing comprises: wherein, is the accumulated frequency word, is the current sampling instant, is the center frequency of the received signal, is the ADC sampling frequency, is the frequency word at the instant.

3. The transmitting and receiving method of a spaceborne agile frequency radar based on FPGA according to claim 1, characterized in that, The calculation of the real-time sine and cosine values is to input the calculated real-time phase value into the Cordic IP core for angle calculation.

4. The transmitting and receiving method of a spaceborne agile frequency radar based on FPGA according to claim 1, characterized in that, The wideband linear frequency modulation signal parameters include center frequency, time width, bandwidth and duty cycle.

5. A FPGA-based space-borne agile frequency radar transmit and receive system, characterized in that, Comprise: The first module determines the signal parameters of the linear frequency modulation signal to be transmitted, including the DAC chip sampling rate, the linear frequency modulation signal time width, the bandwidth, the number of DAC parallel interfaces and the quantization bit width; The second module divides the real-time phase calculation of the transmitted signal into two parts according to the parameters, which are respectively a constant part that can be stored, and a remaining part that is calculated in real time in the FPGA; The third module calculates the phase word of the transmitted linear frequency modulation signal in real time according to the center frequency of the transmitted signal, and calculates the corresponding sin value output to the DAC chip according to the phase word; The fourth module determines the parameters of the received down-conversion according to the center frequency of the received signal and the sampling rate of the ADC chip; The fifth module calculates the real-time phase accumulation word needed by real-time digital down conversion, which is divided into two parts, one part is the fixed quantized and the other part is the multiplication part calculated in real time. The sixth module calculates the real-time phase word of the received digital down-conversion according to the center frequency word of the current input signal, and generates the real-time sin and cos values required for down-conversion for calculation; The real-time transmission and reception angle value calculation method comprises: Calculating the phase accumulation word of the parallel single channel; Then calculating the angle value of the signal reception processing; The phase accumulation of the parallel single channel comprises: wherein, is is the frequency phase word at the moment, is the accumulated frequency word of the A part after splitting, is the accumulated frequency word of the B part after splitting, is the accumulated frequency word of the C part after splitting, is the center frequency of the transmitted signal, is the DAC sampling rate, is the quantization bit width, is the number of transmitting parallel paths, is the frequency modulation rate of the transmitted chirp signal.

6. The system of claim 5, wherein, The calculation of the angle value of the signal reception processing comprises: wherein, is the accumulated frequency word, is the current sampling instant, is the center frequency of the received signal, is the ADC sampling frequency, is the frequency word at the instant. The calculation of the real-time sine and cosine values is to input the calculated real-time phase value into the Cordic IP core for angle calculation; The wideband linear frequency modulation signal parameters include center frequency, time width, bandwidth and duty cycle.

7. A computer-readable storage medium storing a computer program, the computer program comprising instructions that, when executed by a computer, cause the computer to perform the method of any one of claims 1-6. The computer program is executed by the processor to realize the steps of the method of any one of claims 1-4.

8. A FPGA-based satellite-borne frequency-agile radar transmitting and receiving device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: The processor executes the computer program to realize the steps of the method of any one of claims 1-4.

Images