High signal-to-noise ratio solid-state imaging device
By adopting SOI structure and deep trench isolation technology in CMOS image sensors, the surface and channel orientation of pixels are optimized, and the problems of high power consumption and low readout speed in CMOS image sensors are solved, achieving high-speed operation and high performance Pixel structure.
Patent Information
- Application Number
- CN202080106976.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2020-11-19
- Publication Date
- 2024-12-20
- Estimated Expiration
- 2040-11-19
AI Technical Summary
In CMOS image sensors, the increase in the number of pixels leads to high power consumption and low readout speed. The prior art has failed to effectively solve the contradiction between the substrate characteristics of photodiodes and transistors in pixels, resulting in the inability to obtain enhanced characteristics of image sensors. .
Using an insulator semiconductor (SOI) structure, by setting an insulator layer between the substrate and the SOI layer, the surface and channel orientation of the pixel is optimized, and combined with the deep trench isolation structure, the independent characteristics of the photodiode and the transistor in the pixel are ensured. Achieve high-speed operation and low noise.
It realizes high-speed operation and high-performance pixel structure, reduces power consumption and readout noise, and improves the performance and sensitivity of the image sensor.
Smart Images
Figure CN116648922B_ABST
Abstract
Description
Technical Field
[0001] The present application relates to a solid-state image sensor, an imaging device and an electronic device. More specifically, the present application relates to a pixel structure with enhanced performance. Background Art
[0002] The number of pixels in CMOS image sensors (CIS) has increased due to the demand for high-resolution images. However, CIS chips have the disadvantages of high power consumption and low readout speed.
[0003] The pixels of the CIS chip include a photodiode for converting an impact electromagnetic wave into a pixel charge and storing the charge, and a transistor readout portion within the pixel for controlling the storage and readout of the converted pixel charge. Such a CIS is usually made of a body substrate. However, for example, it is proposed to manufacture a CIS from a semiconductor-on-insulator (SOI) substrate to achieve low power consumption and high-speed readout. For example, a CIS manufactured from an SOI substrate is proposed in U.S. Pat. No. 6,838,301. SOI devices can improve the performance of short channel devices. For example, compared with body devices, low power consumption, high-speed operation and latch-up prevention can be achieved.
[0004] Fig.21 An example of a conventional pixel 101 of a CIS manufactured using an SOI process is shown. The SOI substrate 132 includes a base substrate 102, a thin film SOI layer 104, and an insulating layer (buried oxide layer) 106 interposed therebetween.
[0005] The base substrate 102 includes a photodiode 108 that generates and stores pixel charges by photoelectric conversion in response to incident electromagnetic waves. For example, the base substrate 102 may be formed of an epitaxial layer to improve the dark current characteristics of the photodiode 108. For example, when the base substrate 102 includes a p-type doped Si material, the photodiode 108 may be an n-type doped n-well region disposed in the base substrate 102.
[0006] The base substrate 102 further includes a well contact 110 coupled to the photodiode 108 for electrical isolation from other photodiodes and fixing the potential of the photodiode; a floating diffusion region 112 to which the pixel charge stored in the photodiode 108 is transferred; and a transfer gate 114 including a channel region having a source terminal coupled to the photodiode 108 and a drain terminal coupled to the floating diffusion region 112, and controlling the transfer of the pixel charge from the photodiode 108 to the floating diffusion region 112 in response to an applied voltage. The well contact 110, the floating diffusion region 112, and the transfer gate 114 may be disposed in a region of the base substrate 102, on a surface side in contact with the insulating layer 106 or on a side of the SOI layer 104, wherein the insulating layer 106 and the SOI layer 104 have been removed. For example, if the photodiode 108 is an n-type well, the well contact 110 may be a p+ doped region, and the floating diffusion region 112 may be an n+ doped region. If the photodiode 108 is a p-type well, the well contact 110 may be an n+ doped region, and the floating diffusion region 112 may be a p+ doped region. The transfer gate 114 may include: a channel region having a source terminal coupled to the photodiode 108 and a drain terminal coupled to the floating diffusion region 112; and an electrode disposed on a gate insulating film located on a surface of the channel region and made of a conductive material. When a voltage is applied to the transfer gate 114, the pixel charge generated in the photodiode 108 is transferred to the floating diffusion region 112 through the transfer gate 114.
[0007] The pixel charges transferred to the floating diffusion region 112 are read out by an in-pixel transistor readout portion provided on the SOI layer 104 .
[0008] Alternatively, the photodiode can have a configuration called a single photon avalanche diode (SPAD). A pixel with such a photodiode includes a high electric field region in the pixel. The electrons and holes generated by repeated photoelectron conversion are accelerated by the high electric field to collide with atoms in the pixel and generate more electrons and holes, and finally an electron avalanche amplification that generates a large number of electrons and holes occurs. Therefore, even if the intensity of the incident electromagnetic wave is small, SPAD can generate a large amount of pixel charge, so it can help to achieve high sensitivity of imaging and high accuracy of distance measurement using image sensors.
[0009] Photodiodes must have low dark current and high optical properties, while in-pixel transistors must operate at high speed, low readout noise, and low power consumption. Therefore, the preferred properties of the substrates for photodiodes and in-pixel transistors are different from each other.
[0010] Therefore, when a CIS is manufactured from a bulk silicon substrate and an SOI substrate having the same characteristics as the SOI layer, a CIS having enhanced characteristics cannot be obtained. In order to improve the characteristics of a CIS, it is necessary to use an SOI substrate having bulk silicon and an SOI layer having different characteristics.
[0011] However, for example, US Pat. No. 6,838,301, which discloses a pixel including an in-pixel transistor and a photodiode, does not indicate that the photodiode and the in-pixel transistor require different substrate characteristics, and thus the technical problems discussed above are not even recognized. Summary of the invention
[0012] Problems that this application needs to solve
[0013] The present application provides an image sensor, including a pixel structure that achieves high-speed operation and has enhanced performance, for solving the above-mentioned technical problems.
[0014] Means of solving the problem
[0015] An implementation of the present application provides an image sensor, wherein the image sensor includes a plurality of pixels arranged in an array.
[0016] The pixel has a semiconductor-on-insulator (SOI) structure, wherein the SOI structure includes a base substrate, an SOI layer, and an insulating layer inserted between the base substrate and the SOI layer.
[0017] Wherein, the base substrate comprises:
[0018] a photodiode that generates pixel charge in response to incident electromagnetic waves;
[0019] a well contact coupled to the photodiodes for providing electrical isolation between the photodiodes and fixing the potential of the photodiodes;
[0020] a floating diffusion region that temporarily stores pixel charge transferred from the photodiode during readout; a transfer gate that includes a channel region having a source terminal coupled to the photodiode and a drain terminal coupled to the floating diffusion region and controls the transfer of the pixel charge from the photodiode to the floating diffusion region in response to an applied voltage,
[0021] wherein the SOI layer includes an intra-pixel transistor readout portion, the intra-pixel transistor readout portion includes a plurality of transistors for performing readout and amplification of the pixel charge from the floating diffusion region and for performing reset of the floating diffusion region,
[0022] The SOI layer includes a predefined surface orientation and a predefined channel orientation, and the predefined channel orientation is parallel to the direction of the channel of the transistor.
[0023] wherein the base substrate comprises a predefined surface orientation and a predefined channel orientation, the predefined channel orientation being a direction of the channel of the transistor parallel to the SOI layer,
[0024] The surface orientation and / or the channel orientation of the SOI layer are / is different from the surface orientation and / or the channel orientation of the base substrate.
[0025] According to an implementation of the present application, the surface orientation of the SOI layer may be in the (100) direction, and the channel orientation of the SOI layer may be <100> direction.
[0026] According to an implementation of the present application, the surface orientation of the base substrate may be (100) direction, and the channel orientation of the base substrate may be <110> direction.
[0027] According to an implementation of the present application, the surface orientation of the base substrate may be (110) direction, and the channel orientation of the base substrate may be <110> direction.
[0028] According to an implementation of the present application, the transistor of the in-pixel transistor readout portion disposed on the SOI layer may have a PMOS structure.
[0029] According to an implementation of the present application, the surface orientation of the SOI layer may be in the (100) direction, and the channel orientation of the SOI layer may be <110> direction.
[0030] According to an implementation of the present application, the surface orientation of the base substrate may be (100) direction, and the channel orientation of the base substrate may be <100> direction.
[0031] According to an implementation of the present application, the surface orientation of the base substrate may be (110) direction, and the channel orientation of the base substrate may be <110> direction.
[0032] According to an implementation of the present application, the transistor of the in-pixel transistor readout portion disposed on the SOI layer may have an NMOS structure.
[0033] According to an implementation of the present application, the base substrate may include a deep trench isolation (DTI) structure, wherein the DTI structure is arranged to surround the photodiode and provide insulation from adjacent pixels.
[0034] The DTI structure may be composed of a groove filled with an insulating material, or the sidewall of the groove may be covered with a DTI insulating layer, and the groove may be filled with a conductive material isolated from the base substrate by the DTI insulating layer,
[0035] The surface orientation of the sidewall of the groove may be in a (100) direction.
[0036] According to an implementation of the present application, the surface orientation of the base substrate may be offset at a predefined angle relative to the surface orientation of the SOI layer.
[0037] According to an implementation of the present application, the offset angle may be less than or equal to 7 degrees.
[0038] According to an implementation of the present application, the insulating layer may include a first insulating layer, a second insulating layer, and an additional semiconductor layer inserted between the first insulating layer and the second insulating layer.
[0039] According to an implementation of the present application, the insulating layer may include a first insulating layer to a third insulating layer stacked together.
[0040] The first insulating layer and the third insulating layer may be composed of the same material.
[0041] A material constituting the second insulating layer may be different from materials constituting the first insulating layer and the third insulating layer.
[0042] According to an implementation of the present application, the first insulating layer and the third insulating layer may be made of SiO 2 Layer composition,
[0043] The second insulating layer may be made of Si 3 N 4 Layer composition.
[0044] According to an implementation of the present application, the insulating layer may include a stack of a first insulating layer, a conductive layer, and a second insulating layer.
[0045] According to an implementation of the present application, the first insulating layer and the second insulating layer may be SiO 2 layer,
[0046] The conductive layer may be a tungsten layer.
[0047] Another implementation of the present application provides a camera for a mobile phone, a digital camera, a web camera, a surveillance camera, a video camera, a camera for a vehicle and / or transportation equipment, a medical camera or a machine vision camera, characterized in that it includes an image sensor according to any one of the implementations of the present application.
[0048] Another implementation of the present application provides a method for manufacturing an image sensor according to any one of the implementations of the present application, comprising the following steps:
[0049] The SOI layer is bonded to a base substrate via an insulating layer to obtain an SOI substrate, wherein the SOI layer comprises a predefined surface orientation and / or a predefined channel orientation, the predefined channel orientation being a direction parallel to a channel of a transistor to be formed, wherein the base substrate comprises a predefined surface orientation and / or a predefined channel orientation, the predefined channel orientation being parallel to the channel of the transistor to be formed on the SOI layer, the predefined surface orientation and / or the predefined channel orientation being different from the surface orientation of the SOI layer and / or the channel orientation of the SOI layer,
[0050] forming a photodiode in the base substrate,
[0051] Predefined areas of the SOI layer and the insulating layer are removed to expose the base substrate, and a well contact, a floating diffusion region and a transfer gate are formed on the exposed base substrate, and an in-pixel transistor readout portion including a source follower transistor and a reset transistor is formed on the SOI layer.
[0052] Effects of this application
[0053] The implementation of the present application can provide an image sensor having a pixel structure that realizes high-speed operation and provides high performance. BRIEF DESCRIPTION OF THE DRAWINGS
[0054] Figure 1 A block diagram of an image sensor device provided by one embodiment of the present application is shown.
[0055] Figure 2 A cross-sectional view of a pixel provided by one embodiment of the present application is shown.
[0056] Figure 3 A circuit diagram of a pixel provided by an embodiment of the present application is shown.
[0057] Figure 4 A plan view of an SOI substrate provided by one embodiment of the present application is shown.
[0058] Figure 5A cross-sectional view of a pixel provided by the present application is shown, wherein the pixel is formed in Figure 4 The SOI substrate is shown.
[0059] Figure 6 A plan view of an SOI substrate provided by one embodiment of the present application is shown.
[0060] Figure 7 A cross-sectional view of a pixel provided by the present application is shown, wherein the pixel is formed in Figure 6 The SOI substrate is shown.
[0061] Figure 8 A plan view of an SOI substrate provided by one embodiment of the present application is shown.
[0062] Fig. 9 A cross-sectional view of a pixel provided by the present application is shown, wherein the pixel is formed in Figure 8 The SOI substrate is shown.
[0063] Fig.10 Shows Figure 8 and Fig. 9 A plan view of a base substrate of a SOI substrate is shown.
[0064] Fig.11 A plan view of an SOI substrate provided by one embodiment of the present application is shown.
[0065] Fig.12 A cross-sectional view of a pixel provided by the present application is shown, wherein the pixel is formed in Fig.11 The SOI substrate is shown.
[0066] Fig.13 A perspective view of an SOI substrate provided by one embodiment of the present application is shown.
[0067] Fig.14A A step of a method for manufacturing a pixel provided by an embodiment of the present application is shown.
[0068] Fig. 14B A step of a method for manufacturing a pixel provided by an embodiment of the present application is shown.
[0069] Fig. 14C A step of a method for manufacturing a pixel provided by an embodiment of the present application is shown.
[0070] Fig.14D A step of a method for manufacturing a pixel provided by an embodiment of the present application is shown.
[0071] Fig.15 A cross-sectional view of a pixel provided by one embodiment of the present application is shown.
[0072] Fig.16 A cross-sectional view of a pixel provided by one embodiment of the present application is shown.
[0073] Fig.17 A cross-sectional view of a pixel provided by one embodiment of the present application is shown.
[0074] Fig.18 A partial cross-sectional view of an image sensor combined with pixels provided by one embodiment of the present application is shown.
[0075] Fig.19 A block diagram of an imaging system provided by an embodiment of the present application is shown.
[0076] Fig. 20 An example of application of a camera system provided by an embodiment of the present application is shown.
[0077] Fig.21 A cross-sectional view of a conventional image sensor is shown. DETAILED DESCRIPTION
[0078] Figure 1 A block diagram of an image sensor 201 provided by an embodiment of the present application is shown. The image sensor 201 includes a pixel array 209 . The pixel array 209 has pixels 1 arranged in an array. Figure 2 A cross-sectional view of a pixel 1 provided in accordance with an embodiment of the present application is shown. Figure 3 A circuit diagram of a pixel 1 provided in accordance with an embodiment of the present application is shown.
[0079] The image sensor 201 may include: a pixel array 209 having pixels 1 arranged in an array; a control circuit 205 for controlling each pixel of the pixel array 209; a read circuit 210 for reading out a signal from each pixel; and a signal processing circuit 206 for processing the signal read out by the read circuit 210.
[0080] The pixel 1 has a semiconductor-on-insulator (SOI) structure consisting of a base substrate 2, an SOI layer 4, and an insulating layer 6 inserted between the base substrate 2 and the SOI layer 4. The base substrate 2 and the SOI layer 4 may be composed of Si, SiGe, Ge, III-V semiconductors, or any other photosensitive material. "Photosensitive material" refers to a material that generates electrons and holes (hereinafter referred to as "pixel charges") in response to incident electromagnetic waves.
[0081] The base substrate 2 includes a photodiode 8 that generates and stores pixel charges in response to incident electromagnetic waves. For example, if the base substrate 2 is composed of a p-doped Si material, the photodiode 8 may be an n-doped n-well region disposed in the base substrate 2 .
[0082] The base substrate 2 further includes: a well contact 10 coupled to the photodiode 8 for electrical separation between the photodiodes and fixing the potential of the photodiode; a floating diffusion region 12 for reading out the pixel charge generated by photoelectric conversion and stored in the photodiode 8; and a transfer gate 14 including a channel region having a source terminal coupled to the photodiode 8 and a drain terminal coupled to the floating diffusion region 12, the transfer gate 14 controlling the transfer of the pixel charge from the photodiode 8 to the floating diffusion region 12 in response to an applied voltage. The well contact 10, the floating diffusion region 12 and the transfer gate 14 can be arranged in a region on the surface of the base substrate 2 contacting the insulating layer 6 or in a region on the SOI side of the base substrate 2, wherein the insulating layer 6 and the SOI layer 4 have been removed. For example, if the photodiode 8 is of n-type, the well contact 10 can be a p+ doped region and the floating diffusion region 12 can be an n+ doped region. If the photodiode 8 is of p-type, the well contact 10 can be an n+ doped region and the floating diffusion region 12 can be a p+ doped region. Next, the case of the n-type photodiode 8 is discussed. The transfer gate 14 includes an electrode made of a conductive material and disposed on a gate insulating film located on the surface of the channel region. When a voltage is applied to the transfer gate 14, the pixel charge generated in the photodiode 8 is transferred to the floating diffusion region 12 through the transfer gate 14.
[0083] If the pixel charge generated in the photodiode 8 of the array of pixels 1 leaks from the photodiode 8 to other parts such as adjacent pixels, the pixel charge to be stored may be reduced. If the pixel charge flows into the photodiode 8 from the photodiode of the adjacent pixel, the pixel charge to be stored may increase. Regardless of the incident electromagnetic wave, the charge flowing into the photodiode 8 and flowing out of the photodiode 8 is called crosstalk. When crosstalk occurs, the amount of pixel charge no longer corresponds to the amount of electromagnetic waves that hit the photodiode 8. Therefore, crosstalk is a source of noise, thereby preventing accurate measurement of the amount of incident electromagnetic waves. In order to suppress crosstalk, the base substrate 2 also includes a deep trench isolation (DTI) structure 16, which is arranged so that the DTI structure 16 surrounds the photodiode 8, and preferably, the depth of the DTI structure can be equal to the thickness of the base substrate 2. In this case, each photodiode is completely electrically isolated from the adjacent photodiode. The DTI structure 16 can be a groove filled with an insulating material and arranged on the base substrate 2, or a p-doped region (not shown) can be provided instead of the DTI structure, etc. The DTI structure 16 can prevent pixel charges from leaking from the photodiode 8 and from flowing into the photodiode 8 to reduce crosstalk.
[0084] The SOI layer 4 includes an intra-pixel transistor readout portion, which includes a plurality of transistors that read out and amplify pixel charges from the floating diffusion region 12 and perform a reset operation of the floating diffusion region 12. For example, the intra-pixel transistor readout portion may include a source follower transistor 18, a reset transistor 20, and a row select transistor 24. The transistors in the intra-pixel transistor readout portion may be isolated from each other by a shallow trench isolation (STI) structure. The source follower transistor 18 includes a drain 26, a source 28, and a gate 30. The gate 30 of the source follower transistor 18 is coupled to the floating diffusion region 12, and the drain 26 is coupled to the device voltage 22. The source 28 of the source follower transistor 18 is coupled to the drain of the row select transistor 24. The drain of the reset transistor 20 is coupled to the device voltage 22, and the source of the reset transistor 20 is coupled to the floating diffusion region 12.
[0085] The in-pixel transistor readout portion having such a configuration can read out the change in the voltage applied to the gate 30 of the source follower transistor 18, in other words, the change in the potential of the floating diffusion area 12 as the output voltage Vout at the source of the source follower transistor 18. The source follower transistor 18 and / or the additional transistor can also amplify the output of the source follower transistor 18. Before reading out the amount of electromagnetic waves striking the photodiode 8, a reset voltage is applied to the gate electrode of the reset transistor 20 to reset the potential of the floating diffusion area 12 by the device voltage 22. In this step, the potential of the floating diffusion area 12 is recorded as a reference voltage. Then, the reset voltage is turned off, and a voltage is applied to the transfer gate 14 to transfer the pixel charge from the photodiode 8 to the floating diffusion area 12. For example, if the pixel charge is an electron, the potential of the floating diffusion area 12 drops compared to the reset state. Therefore, the output voltage Vout also drops. When the pixel charge is transferred to the floating diffusion area 12, the amount of pixel charge and the amount of electromagnetic waves striking the photodiode 8 are determined by performing correlated double sampling using the reference voltage and the output voltage.
[0086] In the present embodiment, an example is described in which pixel charges respectively stored in all pixels 1 included in the array are sequentially read out using row selection transistors, and the data is read out as a frame consisting of all pixels 1 in the array. However, alternatively, an image sensor that operates in a method called "event-driven type" instead of reading out data as a frame can be implemented by using the pixels 1 of the present embodiment. The event-driven image sensor can output data at any time in response to changes in the intensity of electromagnetic waves incident on the pixels in an asynchronous manner. Specifically, for example, if the pixel charge generated by the electromagnetic wave incident on the photodiode and stored in the photodiode exceeds a predefined threshold, the event of the electromagnetic wave intensity exceeding the threshold or the data of the electromagnetic wave intensity can be output with the coordinates and timing information of the pixel.
[0087] The transistor readout portion within the pixel requires high-speed operation, low noise, and low power consumption. Therefore, the source follower transistor 18 and the reset transistor 20 are preferably configured to make the charge mobility as high as possible. In order to improve the mobility, for example, the channel orientation of the transistor, in other words, the orientation along the channel from the source to the drain is preferably a specific crystal axis orientation in the SOI layer with high charge mobility.
[0088] The pixel charge from the photodiode 8 to the floating diffusion area 12 is also preferably transferred at a high speed. Therefore, the orientation from the photodiode 8 to the floating diffusion area 12 is also preferably oriented along a specific crystal axis having a high charge mobility in the base substrate. On the other hand, as described above, in order to prevent the pixel charge from flowing into or leaking from the photodiode 8 and to prevent crosstalk, the normal of the side of the DTI structure 16 surrounding the photodiode 8 is preferably oriented along a specific crystal axis of the base substrate having a low interface energy level density. In other words, since the characteristics required for the photodiode 8 are different from the characteristics required for the in-pixel transistor readout portion, the surface orientation and / or channel orientation of the SOI layer is preferably different from the surface orientation of the base substrate and / or the orientation of the base substrate parallel to the channel orientation of the SOI layer (hereinafter referred to as "the channel orientation of the base substrate" to simplify the description, although the transistor included in the in-pixel transistor readout portion is not formed on the base substrate).
[0089] Figures 4 to 12 Exemplary embodiments of preferred combinations of surface orientation / channel orientation of the SOI layer and surface orientation / channel orientation of the base substrate are shown. However, it should be understood that various combinations of orientations can be achieved in addition to the combinations shown below, and such combinations can include various advantages.
[0090] Figure 4 A plan view of an embodiment of an SOI substrate 32 is shown, and when the transistor 24 having a drain 26, a source 28, and a gate 30 in the in-pixel transistor readout portion (e.g., a source follower transistor 18 and / or a reset transistor 20) disposed on the SOI layer 4 has a PMOS structure, the SOI substrate 32 includes a preferred surface orientation / channel orientation of the SOI layer 4 and a preferred surface orientation / channel orientation of the base substrate 2. It should be noted that, for ease of understanding, the positions of the SOI layer 4, the insulating layer 6, and the base substrate 2 are shown moved relative to each other. In addition, only one transistor 18 is shown in an enlarged manner. Here, a circular mark with a dot in the center indicates that the direction of the arrow is perpendicular to the paper and comes out of the paper. The same applies to the subsequent drawings. Figure 5 Shows the formation of Figure 4 A cross-sectional view of an embodiment of a pixel 1 on an SOI substrate 32 is shown.
[0091] exist Figure 4 and Figure 5 In the embodiment, the surface orientation of the SOI layer 4, in other words, the orientation along the surface normal direction of the SOI layer 4 is preferably in the (100) direction, and the channel orientation of the SOI layer 4 parallel to the channel orientation from the drain 26 to the source 28 of the transistor 24 is preferably <100> In addition, the surface orientation of the base substrate 2 is preferably (100) and the channel orientation of the base substrate 2 is preferably <110> If the surface orientation and channel orientation of the PMOS structure are (100) and <100> direction, the channel of the transistor has the highest hole mobility. Therefore, the surface orientation and <100> The PMOS structure transistor 24 with a channel orientation in the φ2 direction has the advantages of high-speed operation and suppressed flicker noise and random telegraph signal noise due to the high hole mobility of the channel.
[0092] Figure 6 A plan view of an embodiment of an SOI substrate 32 is shown, in which the SOI substrate 32 has a preferred surface orientation / channel orientation of the SOI layer 4 and a preferred surface orientation / channel orientation of the base substrate 2 when the transistor 24 including the drain 26, the source 28 and the gate 30 in the in-pixel transistor readout portion (e.g., the source follower transistor 18 and / or the reset transistor 20) disposed on the SOI layer 4 includes a PMOS structure. Figure 7 Shows the formation of Figure 6 A cross-sectional view of an embodiment of a pixel 1 on a SOI layer 4 is shown.
[0093] exist Figure 6 and Figure 7 In the example, the surface orientation and channel orientation of the SOI layer 4 are (100) and <100> Direction, similar to Figure 4 and Figure 5 The SOI substrate 32 is shown. Therefore, as described above, the transistor 24 including the PMOS structure has the advantages of high-speed operation and suppressed flicker noise and random telegraph noise due to the high hole mobility of the channel.
[0094] like Figure 7 As shown, the surface orientation and channel orientation of the base substrate 2 are (110) and <110> Direction, and Figure 4 and Figure 5The situation shown is different. A groove filled with an insulating material is formed on the base substrate 2 and constitutes a DTI structure 16 surrounding the photodiode 8 of the pixel 1, having a side orientation in the (100) direction. The side of the groove having a surface orientation in the (100) direction is characterized by a low interface energy level density of charges. Charges captured on the side of the groove of the DTI structure 16 may flow into the photodiode 8, which may generate a dark current source. Therefore, when the side of the groove of the DTI structure 16 has a surface orientation in the (100) direction and has a low interface energy level density, there is an advantage in suppressing the dark current caused by charges flowing from the side of the groove to the photodiode 8.
[0095] When manufacturing the photodiode 8, for example, it is necessary to manufacture an n-well region in the base substrate 2 by doping. Therefore, an ion implantation process is performed. In particular, the surface of the silicon substrate having a surface orientation in the (110) direction provides a high ion channeling effect in the ion implantation process. Since the ions incident on the surface having a surface orientation in the (110) direction collide along the direction of the sparse arrangement of atoms constituting the silicon crystal, the probability of the ions colliding with the atoms of the silicon crystal is reduced. Therefore, the ions can approach a deeper position than the position expected based on the energy of the ion beam and the stopping power of the silicon crystal. If the surface orientation of the base substrate 2 is thus Figure 6 and Figure 7 In the (110) direction shown, a photodiode 8 having a deep shape in the depth direction (thickness direction) of the base substrate 2 can be formed. Such a photodiode 8 has a larger volume and therefore has an increased full well capacity, which is the capacity for storing pixel charges generated by incident electromagnetic waves. Therefore, an image sensor with high sensitivity can be provided.
[0096] Figure 8 A plan view of an embodiment of an SOI substrate 32 is shown, in which the SOI substrate 32 includes a preferred surface orientation / channel orientation of the SOI layer 4 and a preferred surface orientation / channel orientation of the base substrate 2 when the transistor 24 including the drain 26, the source 28 and the gate 30 in the in-pixel transistor readout portion (e.g., the source follower transistor 18 and / or the reset transistor 20) disposed on the SOI layer 4 has an NMOS structure. Fig. 9 Shows the formation of Figure 8 A cross-sectional view of an embodiment of a pixel 1 on a SOI layer 4 is shown. Fig.10 Shown include Figure 8 and Fig. 9 A plan view of the base substrate 2 of the pixel 1 is shown.
[0097] exist Figure 8 and Fig. 9 In the embodiment, the surface orientation and channel orientation of the SOI layer 4 are preferably (100) and (200) directions, respectively. <110> Direction, different from Figure 4and Figure 5 The SOI substrate 32 is shown. If the surface orientation and channel orientation in the NMOS structure are (100) and <110> direction, the channel of the transistor has the highest electron mobility. Therefore, the surface orientation having a (100) direction and <110> The transistor 24 having an NMOS structure with a channel orientation in the direction has the advantages of high-speed operation and suppressed flicker noise and random telegraph signal noise due to high electron mobility in the channel.
[0098] The surface orientation and channel orientation of the base substrate 2 are (100) and <100> In particular, when the pixel charge generated in the photodiode 8 is transferred to the floating diffusion region 12 by, for example Fig.10 This configuration is advantageous when the four photodiodes 81 to 84 shown are shared. Fig.10 As shown, four photodiodes 81 to 84 are coupled to the floating diffusion region 12 through transfer gates 141 to 144, respectively. For example, the transfer paths of pixel charges from the photodiodes 81, 82, 83, and 84 to the floating diffusion region 12 formed on the base substrate 2 are respectively located at the base substrate 2 having the highest electron mobility. <110> Therefore, the transfer speed of the pixel charges from the photodiodes 81, 82, 83 and 84 to the floating diffusion area 12 can be increased, thereby providing high-speed operation of the pixel 1.
[0099] Fig.11 A plan view of an embodiment of an SOI substrate 32 is shown, in which the SOI substrate 32 includes a preferred surface orientation / channel orientation of the SOI layer 4 and a preferred surface orientation / channel orientation of the base substrate 2 when the transistor 24 including the drain 26, the source 28 and the gate 30 in the in-pixel transistor readout portion (e.g., the source follower transistor 18 and / or the reset transistor 20) disposed on the SOI layer 4 has an NMOS structure. Fig.12 Shows the formation of Fig.11 A cross-sectional view of an embodiment of a pixel 1 on a SOI layer 4 is shown.
[0100] exist Fig.11 and Fig.12 In the example, the surface orientation and channel orientation of the SOI layer 4 are (100) and <110> Direction, similar to Figure 8 and Fig. 9 The SOI substrate 32 is shown. Therefore, as described above, the transistor 24 having the NMOS structure has the advantages of high-speed operation and suppressed flicker noise and random telegraph signal noise due to the high electron mobility of the channel of the transistor 24.
[0101] exist Fig.11 and Fig.12In the embodiment, the surface orientation and channel orientation of the base substrate 2 are (110) and <110> Direction, similar to Figure 6 and Figure 7 The SOI substrate 32 is shown. Therefore, as shown in FIG. Figure 7 As described above, the groove formed on the base substrate 2 and constituting the DTI structure 16 surrounding the photodiode 8 has a side wall having a surface orientation in the (100) direction, in which the charge interface energy level density is low. Therefore, there is an advantage of suppressing dark current generated by charge leakage from the groove side wall of the DTI structure 16 to the photodiode 8.
[0102] exist Fig.11 and Fig.12 In the embodiment, when the photodiode 8 is formed, the base substrate 2 provides a high ion channeling effect during the ion implantation process, so that a photodiode having a deep shape in the depth direction (thickness direction) of the base substrate 2 can be manufactured. Since such a photodiode 8 has an increased full well capacity, which is a capacity for storing pixel charges generated by incident electromagnetic waves, an image sensor with high sensitivity can be obtained.
[0103] The characteristics required for the photodiode, the PMOS transistor, and the NMOS transistor are different from each other. Therefore, as described above, the surface orientation and channel orientation of the base substrate 2 in which the photodiode is formed, the surface orientation and channel orientation of the SOI layer 4 on which the PMOS transistor is formed, and the surface orientation and channel orientation of the SOI layer 4 on which the NMOS transistor is formed are preferably selected according to the characteristics required for the photodiode, the PMOS transistor, and the NMOS transistor, respectively. As a result, the surface orientation and / or channel orientation of the base substrate 2 is different from the surface orientation and / or channel orientation of the SOI layer 4.
[0104] Figures 4 to 12 An example is shown in which the surface orientation / channel orientation of the SOI layer 4 of the SOI substrate 32 on which the pixel 1 is formed is significantly different from the surface orientation / channel orientation of the base substrate 2. On the other hand, Fig.13 A perspective view of an SOI substrate 32 is shown in which the normal direction of the base substrate 2 deviates from the surface orientation of the SOI layer 4 at a predefined angle. Fig.13In the example shown, when the surface orientation of the SOI layer 4 is in the (100) direction, the (100) direction of the base substrate 2 deviates from the normal direction 34 at a predefined angle α (e.g., 2 degrees, 4 degrees, or 7 degrees). When the surface orientation is the same as the crystal axis direction (e.g., the (100) direction), ion channeling may occur during the ion implantation process for forming the photodiode 8. As described above, although the ion channeling may be beneficial for forming a deep photodiode, the depth distribution of the ions may be broadened, and it may be difficult to accurately dope ions at a predefined depth. However, if the normal direction of the surface of the base substrate 2 deviates from the normal direction 34 at a predefined small angle (e.g., 2 degrees, 4 degrees, or 7 degrees), the ion channeling may occur during the ion implantation process for forming the photodiode 8. Fig.13 If the crystal axis deviates from the (100) direction by 2 degrees, 4 degrees or 7 degrees as shown, the ion channeling effect can be reduced and ions can be accurately doped at a predefined depth.
[0105] refer to Figures 14A to 14D A method for producing such a pixel 1 is described. Figures 14A to 14D A method for manufacturing a pixel 1 to be formed on an SOI substrate 32 is shown, wherein the SOI layer 4 has a surface orientation in the (100) direction and <100> direction, and wherein the base substrate 2 has a surface orientation in the (100) direction and <110> The channel orientation of the direction, such as Figure 4 and Figure 5 However, it is obvious to those skilled in the art that this manufacturing method can be similarly applied to other combinations of surface orientations and channel orientations described herein or not shown but obvious to those skilled in the art.
[0106] exist Fig.14A In the present invention, the SOI substrate 32 is obtained by: having a surface orientation with a (100) direction and <110> The surface of the p-type base substrate 2 has a channel orientation in a (100) direction and / or has a surface orientation in a (100) direction and <100> An oxide layer is formed on the surface of the SOI layer 4 having a channel orientation in the direction; the above items are bonded; and they are polished to a predefined thickness. The oxide layer constitutes the insulating layer 6. In addition to selecting the surface orientation and channel orientation of the base substrate 2 and the SOI layer 4, the method of providing the SOI substrate 32 is known to those skilled in the art.
[0107] Then, in Fig. 14B In the embodiment, the photodiode 8 is formed by performing n-type doping from the side of the base substrate 2 by a method known to those skilled in the art.
[0108] Then, in Fig. 14CIn the embodiment, predefined areas of the SOI layer 4 and the insulating layer 6 are removed by methods known to those skilled in the art to expose the base substrate 2. A well contact 10, a floating diffusion region 12, a transfer gate 14, and an in-pixel transistor readout portion including a source follower transistor 18, a reset transistor 20, and a row select transistor 24 are formed on the exposed base substrate 2 by methods known to those skilled in the art.
[0109] Then, in Fig.14D In the embodiment of the present invention, a groove constituting a DTI structure 16 is formed on a base substrate 2 so that the groove surrounds a photodiode 8 to obtain a pixel 1. The groove can be formed by a known method, such as reactive ion etching (RIE) or deep reactive ion etching (Deep-RIE). The groove can be filled with an insulating material. Alternatively, a pixel separation structure can be formed by forming a p-type doped region instead of the DTI structure 16.
[0110] Figures 15 to 17 Examples of the pixels 1 formed on the SOI substrate 32 having various configurations are shown.
[0111] exist Fig.15 In the pixel 1 shown, the insulating layer 6 includes a first insulating layer 61, a second insulating layer 62, and an additional semiconductor layer 63 inserted between the first insulating layer 61 and the second insulating layer 62. For example, the pixel 1 having such a configuration allows additional elements such as transistors to be formed on the additional semiconductor layer 63 to embody the three-dimensional structure of the transistor readout portion within the pixel, thereby reducing the area. In addition, the semiconductor layer 63 can be used as an electrical shield to enhance the electrical separation between the transistor readout portion within the pixel formed on the SOI layer and the photodiode formed on the base substrate.
[0112] exist Fig.16 In the pixel 1 shown, the insulating layer 6 includes a first insulating layer 61, a second insulating layer 62, and a third insulating layer 63 inserted between the first insulating layer 61 and the second insulating layer 62. The first insulating layer 61 and the second insulating layer 62 are made of the same material (e.g., SiO 2 The third insulating layer 63 is made of a material different from the materials forming the first insulating layer 61 and the second insulating layer 62, such as Si 3 N 4 The pixel 1 having such a configuration can actively utilize the fixed charge of the third insulating layer 64 to reduce the operating voltage of the in-pixel transistor readout portion of the SOI layer and reduce the dark current generated from the interface between the semiconductor material of the base substrate and the insulating layer 61.
[0113] exist Fig.17In the pixel 1 shown, the insulating layer 6 includes a first insulating layer 61, a second insulating layer 62, and a conductive layer 65 inserted between the first insulating layer 61 and the second insulating layer 62 and made of, for example, a tungsten layer. Since such a conductive layer 65 can have reflectivity, for example, the conductive layer 65 can reflect electromagnetic waves that are incident from one side of the base substrate 2 and transmitted without being absorbed by the photodiode 8, and generate pixel charges that return to the photodiode 8, and the conductive layer 65 can improve the sensitivity of the pixel 1.
[0114] Fig.18 FIG. 2 shows a partial cross-sectional view of an image sensor 201 combined with a pixel 1 provided in some embodiments of the present application. The image sensor 201 may have a logic circuit substrate 212, and the logic circuit substrate 212 includes Figure 1 The control circuit 205, readout circuit 210, signal processing circuit 206, etc. shown are provided, for example, by copper-copper bonding or any other substrate bonding technology. The logic circuit substrate 212 can be provided on one side of the in-pixel transistor readout portion of the pixel 1 through the interlayer insulating film 214, and can be connected to the in-pixel transistor readout portion through the metal interconnect wiring 216. The color filter 203 and the microlens 202 can be provided on one side of the photodiode 8.
[0115] Fig.19 A block diagram of such an image sensor 201 is shown. Electromagnetic waves 220 strike pixels 1 of an image sensor array 209 through microlenses 202 and color filters 203. Control circuitry 205 may control the image sensor array 209. Signals from the image sensor array 209 may be processed by signal processing circuitry 206, and, for example, image data mapping the intensity of the electromagnetic waves at each pixel position may be generated. The image data may be displayed on a monitor 207 and / or stored in a memory 208.
[0116] Fig. 20 An example of the technology of applying the image sensor 201 of the present application is shown. For example, the image sensor 201 can be applied to a wide variety of fields, such as sports equipment such as wearable cameras, medical equipment such as endoscopes, cosmetic equipment, vehicles or transportation equipment such as trucks, mobile phones, game consoles, entertainment equipment such as digital cameras and video cameras, agricultural fields such as farmland monitoring cameras, home appliances such as televisions and refrigerators, and security fields such as surveillance cameras, network cameras, and machine vision cameras.
[0117] Although the embodiments of the present application are described illustratively, it will be easily understood by those skilled in the art that various modifications and changes may be adopted without departing from the spirit and scope of the present application.
[0118] Reference numerals
[0119] 1, 101: pixels;
[0120] 2. 102: base substrate;
[0121] 4. 104: SOI layer;
[0122] 6. 106: insulation layer;
[0123] 8, 81, 82, 83, 84 and 108: photodiodes;
[0124] 10, 110: well contacts;
[0125] 12, 112: floating diffusion area;
[0126] 14, 141, 142, 143, 144, 114: transfer gate;
[0127] 16: Deep trench isolation (DTI) structure;
[0128] 18: Source follower transistor;
[0129] 20: reset transistor;
[0130] 22: Device voltage;
[0131] 24: row selection transistor;
[0132] 26: drain;
[0133] 28: source;
[0134] 30: gate;
[0135] 32: SOI substrate;
[0136] 34: normal direction of the base substrate;
[0137] 61: first insulating layer;
[0138] 62: second insulating layer;
[0139] 63: additional semiconductor layer;
[0140] 64: third insulating layer;
[0141] 65: conductive layer;
[0142] 201: Image sensor;
[0143] 202: microlens;
[0144] 203: Color filter;
[0145] 205: control circuit;
[0146] 206: signal processing circuit;
[0147] 207: monitor;
[0148] 208: Memory
[0149] 209: image sensor array;
[0150] 210: Readout circuit.
Claims
1. An image sensor, characterized in that: comprising a plurality of pixels arranged in an array, The pixel has a semiconductor-on-insulator (SOI) structure, wherein the SOI structure includes a base substrate, an SOI layer, and an insulating layer inserted between the base substrate and the SOI layer. Wherein, the base substrate comprises: a photodiode that generates pixel charge in response to incident electromagnetic waves; a well contact coupled to the photodiodes for providing electrical isolation between the photodiodes and fixing the potential of the photodiodes; a floating diffusion region temporarily storing pixel charge transferred from the photodiode during readout; a transfer gate including a channel region having a source terminal coupled to the photodiode and a drain terminal coupled to the floating diffusion region and controlling the transfer of the pixel charge from the photodiode to the floating diffusion region in response to an applied voltage, wherein the SOI layer includes an intra-pixel transistor readout portion, the intra-pixel transistor readout portion includes a plurality of transistors for performing readout and amplification of the pixel charge from the floating diffusion region and for performing reset of the floating diffusion region, The SOI layer includes a predefined surface orientation and a predefined channel orientation, and the predefined channel orientation is parallel to the direction of the channel of the transistor. wherein the base substrate comprises a predefined surface orientation and a predefined channel orientation, the predefined channel orientation being a direction of the channel of the transistor parallel to the SOI layer, The surface orientation and / or the channel orientation of the SOI layer are / is different from the surface orientation and / or the channel orientation of the base substrate.
2. The image sensor according to claim 1, characterized in that The surface orientation of the SOI layer is (100) direction, and the channel orientation of the SOI layer is <100> direction.
3. The image sensor according to claim 2, characterized in that The surface orientation of the base substrate is (100) direction, and the channel orientation of the base substrate is <110> direction.
4. The image sensor according to claim 2, characterized in that: The surface orientation of the base substrate is (110) direction, and the channel orientation of the base substrate is <110> direction.
5. The image sensor according to any one of claims 2 to 4, characterized in that: The transistor of the in-pixel transistor readout portion disposed on the SOI layer has a PMOS structure.
6. The image sensor according to claim 1, characterized in that: The surface orientation of the SOI layer is (100) direction, and the channel orientation of the SOI layer is <110> direction.
7. The image sensor according to claim 6, characterized in that: The surface orientation of the base substrate is (100) direction, and the channel orientation of the base substrate is <100> direction.
8. The image sensor according to claim 6, characterized in that: The surface orientation of the base substrate is (110) direction, and the channel orientation of the base substrate is <110> direction.
9. The image sensor according to any one of claims 6 to 8, characterized in that: The transistor of the in-pixel transistor readout portion disposed on the SOI layer has an NMOS structure.
10. The image sensor according to claim 4 or 8, characterized in that: The base substrate includes a deep trench isolation (DTI) structure, the DTI structure being arranged to surround the photodiode and provide insulation from adjacent pixels, The DTI structure is composed of a groove filled with an insulating material, or the sidewall of the groove is covered with a DTI insulating layer, and the groove is filled with a conductive material isolated from the base substrate by the DTI insulating layer. Wherein, the surface orientation of the side wall of the groove is (100) direction.
11. The image sensor according to claim 1, characterized in that: The surface orientation of the base substrate is offset at a predefined angle relative to the surface orientation of the SOI layer.
12. The image sensor according to claim 11, characterized in that The offset angle is less than or equal to 7 degrees.
13. The image sensor according to any one of claims 1-4, 6-8, 11, and 12, characterized in that: The insulating layer includes a first insulating layer, a second insulating layer, and an additional semiconductor layer interposed between the first insulating layer and the second insulating layer.
14. The image sensor according to any one of claims 1-4, 6-8, 11, and 12, characterized in that: The insulating layer comprises a first insulating layer, a second insulating layer and a third insulating layer which are stacked, Wherein, the first insulating layer and the third insulating layer are composed of the same material, The material constituting the second insulating layer is different from the materials constituting the first insulating layer and the third insulating layer.
15. The image sensor according to claim 14, characterized in that: The first insulating layer and the third insulating layer are composed of SiO2 layers, Wherein, the second insulating layer is composed of a Si3N4 layer.
16. The image sensor according to any one of claims 1-4, 6-8, 11, and 12, characterized in that: The insulating layer includes a stack of a first insulating layer, a conductive layer, and a second insulating layer.
17. The image sensor according to claim 16, characterized in that: The first insulating layer and the second insulating layer are SiO2 layers, Wherein, the conductive layer is a tungsten layer.
18. A camera for a mobile phone, a digital camera, a web camera, a surveillance camera, a video camera, a camera for a vehicle and / or transport equipment, a medical camera or a machine vision camera, characterized in that: Comprising an image sensor according to any one of claims 1 to 17.
19. A method for manufacturing an image sensor according to any one of claims 1 to 17, characterized in that: The following steps are involved: The SOI layer is bonded to a base substrate via an insulating layer to obtain an SOI substrate, wherein the SOI layer comprises a predefined surface orientation and / or a predefined channel orientation, the predefined channel orientation being a direction parallel to a channel of a transistor to be formed, wherein the base substrate comprises a predefined surface orientation and / or a predefined channel orientation, the predefined channel orientation being parallel to the channel of the transistor to be formed on the SOI layer, the predefined surface orientation and / or the predefined channel orientation being different from the surface orientation of the SOI layer and / or the channel orientation of the SOI layer, forming a photodiode in the base substrate, Predefined areas of the SOI layer and the insulating layer are removed to expose the base substrate, and a well contact, a floating diffusion region and a transfer gate are formed on the exposed base substrate, and an in-pixel transistor readout portion including a source follower transistor and a reset transistor is formed on the SOI layer.