A memory device having a TFET

Abstract

This application provides a memory and electronic device incorporating a tunneling field-effect transistor (TFET), relating to the field of semiconductor technology. This memory can improve operating efficiency and reduce operating voltage and power consumption. The memory includes a substrate with a first doped region and a second doped region having the same doping type. A memory cell is located on the substrate. Each memory cell includes not only a storage portion but also a gate transistor and a TFET located on either side of the storage portion. The storage portion and the TFET share a common control gate. Thus, the memory is erased using a hot hole injection (HHI) erasure method. Furthermore, under the control of the TFET, the erase voltage can be reduced, thus lowering the memory's power consumption.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly to a non-volatile memory having a tunneling field-effect transistor and an electronic device containing the non-volatile memory. Background Technology

[0002] Flash memory is a type of non-volatile memory, meaning that data is not lost when power is off. In particular, embedded flash (EFlash) has become a standard feature of microcontroller units (MCUs) because it greatly simplifies the supply chain of MCU-related products, reduces costs, simplifies applications, and also improves the performance and reliability of MCUs.

[0003] Figure 1a and Figure 1b These are cross-sectional views of two different flash memory structures. Figure 1a The diagram shown is a structural diagram of a memory cell in a floating gate (FG) flash memory. Figure 1b The diagram shown is a structural diagram of a storage cell in a charge trapping (CT) flash memory.

[0004] Combination Figure 1a The memory cell in the FG flash mainly includes a tunnel oxide layer 03, a floating gate (FG) layer 04, an oxide-nitride-oxide (ONO) layer 05 and a control gate (CG) layer 3 stacked sequentially on the substrate 1. Furthermore, a first doped region 11 for forming the source electrode and a second doped region 12 for forming the drain electrode are formed in the substrate 1.

[0005] Figure 1b The storage units in the CT flash shown are Figure 1a Compared to the storage cells in the FG flash shown, the CTflash storage cell has two fewer structural layers: the floating gate layer 04 and the tunnel oxide layer 03. In addition, the differences also include: the charge trapping layer 06 is made of an insulating material with high charge trapping density (generally silicon nitride, Si3N4), that is, it stores charge through the insulating material. In contrast, in the FG flash, the floating gate layer 04 is made of a conductive material (such as doped polysilicon), that is, it stores charge through the conductive material.

[0006] CT flash has several advantages over FG flash. For example, in FG flash, because charge is stored through conductive materials, the requirements for the oxide layer (including the tunnel oxide layer 03) located below the floating gate layer 04 are very stringent. For instance, when the oxide layer thins or ages due to excessive erase / write cycles, electrons stored in the floating gate layer 04 can easily escape, affecting storage performance. However, in CT flash, the charge trapping layer 06 is made of a high-charge-trapping density insulating material, making it difficult for electrons to escape once trapped. Therefore, CT flash... Figure 1a and Figure 1b As can be seen, a relatively thick tunnel oxide layer 03 is located below the floating gate layer 04 in the FG flash. Furthermore, to prevent trapped electrons from escaping, the thickness of the floating gate layer 04 is also greater than the thickness of the charge trapping layer 06. This increases the overall height of the memory cell. For example, at the 45nm process node, the height of an FG flash cell may be about 90nm higher than that of a CT flash cell. From a process perspective, CT flash, with its thinner gate material, is easier to implement than FG flash. From a memory integration perspective, CT flash has a higher integration density than FG flash. Consequently, the application range of CT flash is becoming increasingly wider.

[0007] However, for Figure 1a The FG flash structure shown, and Figure 1b The CT Flash structure shown uses Fowler-Nordheim tunneling (FN tunneling) as its erasure principle. This erasure method has low efficiency, which limits the performance improvement of these two memory structures. Summary of the Invention

[0008] This application provides a memory with a tunneling field-effect transistor and an electronic device containing the memory. The main purpose is to provide a memory that can improve operating efficiency and reduce operating voltage and power consumption.

[0009] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0010] In a first aspect, this application provides a memory, which is a non-volatile memory, comprising a substrate made of semiconductor material, such as a P-type semiconductor substrate, wherein a first doped region and a second doped region of the same doping type are formed on the surface of the semiconductor substrate by doping, for example, both the first doped region and the second doped region are N-type, a channel region is formed in the region of the semiconductor substrate located between the first doped region and the second doped region, and a memory cell is disposed on the substrate, the memory cell comprising a storage portion, a tunneling field-effect transistor and a gate transistor.

[0011] The substrate has a charge storage layer that is insulated from the substrate. This charge storage layer can be a charge trapping layer. A first control gate that is insulated from the charge storage layer is disposed on the charge storage layer. A second control gate that is insulated from the first doped region is disposed on the first doped region. A third control gate that is insulated from the second doped region is disposed on the second doped region.

[0012] The storage section includes a channel region, a charge storage layer, and a first control gate; the tunneling field-effect transistor includes a first doped region, a channel region, and a second control gate; the gate transistor includes a second doped region, a channel region, and a third control gate; and the first control gate and the second control gate are integrally formed, so that the storage section and the tunneling field-effect transistor are a common-gate structure.

[0013] Structurally, the control gate in the memory provided in this application includes not only the first control gate, but also the second control gate and the third control gate, thus forming a memory cell as described above that includes not only the storage part, but also the gate transistor and the tunneling field effect transistor (TFET), and the storage part and the TFET adopt a common gate structure.

[0014] Compared to existing memories, the memory provided in this application achieves high programming and erasing efficiency while also reducing operating voltage and power consumption. The erasing process of this memory will be used as an example below for illustration.

[0015] During the erasure process, a voltage greater than a threshold is applied to the first and second control gates, which are integrally molded structures, and a suitable positive voltage is applied to the first doped region. Band-to-band tunneling occurs at the interface between the first doped region and the substrate. Hot holes in the channel region are injected into the charge storage layer and neutralize the electrons stored in the charge storage layer, thus achieving erasure. This erasure method is called hot hole injection (HHI) erasure, which has a relatively high erasure efficiency.

[0016] During the erasure process described above, the voltages applied to the integrated first and second control gates, as well as the voltage applied to the first doped region, are lower than existing voltages. This is because band-to-band tunneling at the interface between the first doped region and the substrate is achieved jointly under the control of the second control gate of the TFET and the voltage applied to the first doped region. In other words, the generation of hot holes is achieved under the combined control of these two parts, which significantly reduces the voltage applied to the first control gate and the first doped region. This lowers the erasure operating voltage and thus reduces power consumption.

[0017] In one possible implementation of the first aspect, the third control gate and the first control gate are integrally formed, so that the gate transistor, the storage section, and the tunneling field-effect transistor are common-controlled gate structures.

[0018] In other words, not only do the storage section and the TFET share a common gate, but the gate selector and the storage section also share a common gate.

[0019] During programming, this memory employs source-side injection (SSI) and channel hot electron (CHE) injection mechanisms to inject generated hot electrons into the charge storage layer. Specifically, a voltage greater than a threshold is applied to the interconnected control gates, a zero voltage is applied to the first doped region, and an appropriate positive voltage is applied to the second doped region. Under these conditions, an inversion channel is formed in the region of the select transistor near the first doped region. The strong electric field between the first and second doped regions generates a large number of electron-hole pairs, and the generated hot electrons are injected into the charge storage layer. Unlike existing technologies, the voltage applied to the control gate is appropriate, avoiding the need for a large positive high voltage (PHV) as in existing technologies. Consequently, this application can also reduce programming power consumption.

[0020] Furthermore, during the writing process of the memory in this application, the generated hot electrons are injected more uniformly into the charge storage layer. The electrons stored in the charge storage layer are more evenly distributed, which can reduce local damage to the material, such as reducing damage to the charge storage layer or reducing damage to the dielectric material located between the charge storage layer and the substrate.

[0021] In addition, since the first control gate, the second control gate, and the third control gate are integrally formed, only one connection port is needed to apply voltage to the control gate, which includes all three parts. Compared with the existing four-terminal memory, one connection port can be reduced, thereby simplifying the winding structure of the memory.

[0022] In one possible implementation of the first aspect, the charge storage layer includes a charge trapping layer.

[0023] In other words, the charge storage layer uses a charge trapping layer made of insulating material. When a charge trapping layer is used as a charge storage layer, once electrons enter the trap, they are difficult to escape. It is not very sensitive to the insulating materials used for the insulating charge trapping layer and the substrate, as well as the insulating materials used for the insulating charge trapping layer and the first control gate. This allows the insulating material to be made thinner, thereby reducing the overall size of the memory and improving the integration density.

[0024] In one possible implementation of the first aspect, the material of the charge storage layer includes silicon nitride.

[0025] In one possible implementation of the first aspect, the surface of the second control gate that is away from the substrate is disposed close to the substrate relative to the surface of the first control gate that is away from the substrate.

[0026] This can be understood as follows: the surface of the second control gate furthest from the substrate is not flush with the surface of the first control gate furthest from the substrate, but rather closer to the substrate than the first control gate. This makes it easier to implement from a manufacturing process perspective.

[0027] In one possible implementation of the first aspect, the surface of the third control gate that is away from the substrate is disposed close to the substrate relative to the surface of the first control gate that is away from the substrate.

[0028] The surface of the third control gate furthest from the substrate is not flush with the surface of the first control gate furthest from the substrate, but is closer to the substrate than the first control gate. Similarly, this is easier to implement from a fabrication perspective.

[0029] In one possible implementation of the first aspect, the surface of the second control gate away from the substrate is flush with the surface of the third control gate away from the substrate.

[0030] In a possible implementation of the first aspect, the memory further includes bit lines and source lines; the source lines are disposed above and electrically connected to the first doped region; the bit lines are disposed above and electrically connected to the second doped region; wherein the second control gate is insulated from the source lines; and the third control gate is insulated from the bit lines.

[0031] Since the second control gate is located above the first doped region, it is necessary to insulate the second control gate from the source line in order to avoid electrical connection between the second control gate and the source line.

[0032] Furthermore, since the third control gate is located above the second doped region, it is necessary to insulate the third control gate from the bit line in order to avoid electrical connection between the third control gate and the bit line. For example, a dielectric material can be placed between the two mutually insulated structures.

[0033] In one possible implementation of the first aspect, the third control gate and the first control gate are integrally formed; the memory also includes word lines; the first control gate is electrically connected to the word lines.

[0034] In a possible implementation of the first aspect, the memory further includes an insulating layer; wherein the charge storage layer is isolated from the substrate by the insulating layer; the first control gate, the second control gate, and the third control gate are all isolated from the charge storage layer by the insulating layer; the second control gate and the substrate, and the third control gate and the substrate are also isolated from each other by the insulating layer.

[0035] In one possible implementation of the first aspect, the memory includes a plurality of memory cells arranged in an array along an orthogonal first direction and a second direction; the first control gates of the plurality of memory cells arranged along the first direction are interconnected; the first doped regions of the plurality of memory cells arranged along the second direction are interconnected; and the second doped regions of the plurality of memory cells arranged along the second direction are interconnected.

[0036] In one possible implementation of the first aspect, the substrate is a P-type substrate, and both the first doped region and the second doped region are N-type doped regions; during the programming process of the memory, the first control gate is used to receive a first programming positive voltage, the first doped region is used to receive a second programming positive voltage, and the second doped region is used to ground, wherein the first programming positive voltage is less than the second programming positive voltage.

[0037] Compared to existing applications where both the first and second programming positive voltages are greater than 4V, this application significantly reduces programming power consumption.

[0038] In a possible implementation of the first aspect, further, the first programming positive voltage is less than 4V.

[0039] In a possible implementation of the first aspect, further, the second programming positive voltage is less than 4V.

[0040] In one possible implementation of the first aspect, the substrate is a P-type substrate, and both the first doped region and the second doped region are N-type doped regions; during the erasure process of the memory, the first control gate is used to receive a first erase negative voltage, the first doped region is used to receive a second erase positive voltage, and the second doped region is used to ground, wherein the absolute value of the first erase negative voltage is less than the second erase positive voltage.

[0041] Compared to existing cases where the absolute value of the first erase negative voltage is greater than 4V and the second erase positive voltage is greater than 4V, this application will also significantly reduce erase power consumption.

[0042] In one possible implementation of the first aspect, further, the absolute value of the first erase negative voltage is less than 4V.

[0043] In a possible implementation of the first aspect, further, the second erase positive voltage is less than 4V.

[0044] Secondly, this application also provides a processor, including a processing circuit and a memory as described in any implementation of the first aspect above, wherein the processing circuit is electrically connected to the memory.

[0045] The electronic device provided in this application includes a memory in any implementation of the first aspect. Therefore, the electronic device provided in this application and the memory of the above-described technical solution can solve the same technical problem and achieve the same expected effect.

[0046] Thirdly, this application also provides an electronic device, including a circuit board and a memory in any implementation of the first aspect above, or a processor in the implementation of the second aspect, wherein the memory and the processor are disposed on the circuit board and electrically connected to the circuit board.

[0047] The electronic device provided in this application includes a memory or processor of any implementation of the first aspect. Therefore, the electronic device provided in this application can solve the same technical problem and achieve the same expected effect as the memory and processor of the above technical solution. Attached Figure Description

[0048] Figure 1a This is a cross-sectional view of a partial structure of an existing FG flash.

[0049] Figure 1b This is a cross-sectional view of a partial structure of a CT flash in the prior art;

[0050] Figure 2 An exploded view of a portion of the structure of an electronic device;

[0051] Figure 3 This is a partial structural diagram of an electronic device;

[0052] Figure 4a This is a schematic diagram of one configuration of the memory according to an embodiment of this application;

[0053] Figure 4b This is a schematic diagram of another form of the memory according to an embodiment of this application;

[0054] Figure 4c This is a schematic diagram of another form of the memory according to an embodiment of this application;

[0055] Figure 5 This is a schematic diagram showing the connection relationship between a memory, a driver, and a decoder.

[0056] Figure 6This is a cross-sectional view of a partial structure of a gate-type CT flash;

[0057] Figure 7a for Figure 6 A schematic diagram of the programming principle of the gate-divided CT flash structure shown.

[0058] Figure 7b for Figure 6 A schematic diagram of the erasure principle of the gate-divided CT flash structure shown;

[0059] Figure 8 This is a cross-sectional view of a partial structure of a memory provided in an embodiment of this application;

[0060] Figure 9a for Figure 8 The diagram shows the programming principle of the memory.

[0061] Figure 9b for Figure 8 The diagram shows the erase principle of the memory.

[0062] Figure 10 A cross-sectional view of a partial structure of another memory provided in an embodiment of this application;

[0063] Figure 11 A cross-sectional view of a partial structure of another memory provided in an embodiment of this application;

[0064] Figure 12a for Figure 11 The diagram shows the programming principle of the memory.

[0065] Figure 12b for Figure 11 The diagram shows the erase principle of the memory.

[0066] Figure 13 This is a cross-sectional view of a portion of the memory structure provided in an embodiment of this application;

[0067] Figure 14 This is a partial structural diagram of the memory array provided in an embodiment of this application.

[0068] Figure label:

[0069] 11-Mid-frame; 110-Border; 111-Carrier plate; 12-Back cover; 13-Display; 01-Circuit board; 02-Chip; 021-First chip; 022-Second chip; 03-Tunnel oxide layer; 04-Floating gate layer; 05-Oxide-nitride-oxide layer; 06-Charge capture layer; 07-Memory gate layer;

[0070] 1-Substrate; 11-First doped region; 12-Second doped region; 2-Charge storage layer; 3-Control gate layer; 31-First control gate; 32-Second control gate; 33-Third control gate; 4-Insulating layer; 5-Electrode connection layer; 61-Storage section; 62-Tunneling field-effect transistor; 63-Gate transistor; 71-First section; 72-Second section; 73-Third section. Detailed Implementation

[0071] Before introducing the embodiments involved in this application, the technical terms involved in this application will be explained in detail as follows.

[0072] Hot electrons (HE): These are high-energy electrons that are generated when the electric field in the channel is very strong due to avalanche breakdown.

[0073] Channel hot electron (CHE) injection, also known as channel avalanche injection, is a phenomenon in which some high-energy hot electrons in the channel are injected into the gate oxide layer. When the electric field in the channel is very strong, the hot electrons multiply due to channel avalanche breakdown. If the energy accumulated between two collisions is sufficient to overcome the potential barrier between Si and the gate oxide layer, these hot electrons may be injected into the gate oxide layer. This type of injection is called CHE injection.

[0074] Band-to-band tunneling (BTBT): When a PN junction is reverse biased, electrons can tunnel from the valence band of the P region to the conduction band of the N region when some unoccupied energy states in the N-region conduction band have the same energy as some electron-occupied energy states in the P-region valence band and the barrier region is very narrow.

[0075] Hot hole (HH): A hole with high energy.

[0076] Hot hole injection (HHI) injection: This is a phenomenon in which some high-energy hot holes in the channel are injected into the gate oxide layer.

[0077] The embodiments provided in this application are described below with reference to the accompanying drawings.

[0078] This application provides an electronic device. This electronic device may include a mobile phone, tablet computer, smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) devices, augmented reality (AR) devices, and may also be a home appliance, an automobile, an artificial intelligence device, or a server, data center, etc. This application does not impose any special limitations on the specific form of the described electronic device.

[0079] Taking any of the above electronic devices, such as a mobile phone, as an example, Figure 2 As shown, the electronic device may include a mid-frame 11, a rear shell 12, and a display screen 13. The mid-frame 11 includes a support plate 110 for supporting the display screen 13 and a frame 111 surrounding the support plate 110. The rear shell 12 is connected to the mid-frame 11 and can prevent external moisture and dust from affecting the performance of the internal structure of the electronic device (e.g., preventing the circuit board supported on the support plate 110 and the electronic components supported on the circuit board).

[0080] Combination Figure 3 The aforementioned electronic device may also include a controller 110, a memory 120, a universal serial bus (USB) interface 130, a charging management module 140, a power management module 141, an antenna 1, an antenna 2, a mobile communication module 150, a wireless communication module 160, etc.

[0081] Understandable, Figure 2 and Figure 3 The structure shown does not constitute a specific limitation on the electronic device. In other embodiments of this application, the electronic device may include a... Figure 2 and Figure 3 More or fewer parts, or combining some parts, or separating some parts.

[0082] Controller 110 may include one or more processing units, such as application processors (APs), modem controllers, graphics processing units (GPUs), image signal processors (ISPs), video codecs, digital signal processors (DSPs), baseband controllers, or neural network processing units (NPUs). These different processing units may be independent devices or integrated into one or more controllers.

[0083] In some embodiments, controller 110 may include one or more interfaces. Interfaces may include an inter-integrated circuit (I2C) interface, an inter-integrated circuit sound (I2S) interface, a pulse code modulation (PCM) interface, a universal asynchronous receiver / transmitter (UART) interface, a mobile industry processor interface (MIPI), a general-purpose input / output (GPIO) interface, a subscriber identity module (SIM) interface, and / or a universal serial bus (USB) interface 130, etc.

[0084] The USB port 130 can specifically be a Mini USB port, a Micro USB port, a USB Type-C port, etc. The USB port 130 can be used to connect a charger to charge electronic devices, or to transfer data between electronic devices and peripheral devices. It can also be used to connect headphones for audio playback.

[0085] The charging management module 140 is used to receive charging input from the charger. The charger can be a wireless charger or a wired charger.

[0086] The power management module 141 receives input from the charging management module 140 and supplies power to the controller 110, memory 120, etc. In some other embodiments, the power management module 141 may also be located in the controller 110. In other embodiments, the power management module 141 and the charging management module 140 may also be located in the same device.

[0087] The wireless communication function of the electronic device can be realized through antenna 1, antenna 2, mobile communication module 150, wireless communication module 160, modem controller and baseband controller, etc.

[0088] Antenna 1 and antenna 2 are used to transmit and receive electromagnetic wave signals. Each antenna in the electronic device can be used to cover one or more communication frequency bands. Different antennas can also be reused to improve antenna utilization. For example, antenna 1 can be reused as a diversity antenna for a wireless local area network. In some other embodiments, the antennas can be used in conjunction with a tuning switch.

[0089] The mobile communication module 150 can provide solutions for wireless communication applications in electronic devices, including 2G / 3G / 4G / 5G. The mobile communication module 150 may include at least one filter, switch, power amplifier, low-noise amplifier (LNA), etc. The mobile communication module 150 can receive electromagnetic waves via antenna 1, and perform filtering, amplification, and other processing on the received electromagnetic waves before transmitting them to a modem controller for demodulation. The mobile communication module 150 can also amplify the signal modulated by the modem controller and convert it into electromagnetic waves for radiation via antenna 1.

[0090] The wireless communication module 160 can provide solutions for wireless communication applications in electronic devices, including wireless local area networks (WLANs) (such as wireless fidelity (Wi-Fi) networks), Bluetooth (BT), global navigation satellite system (GNSS), frequency modulation (FM), near field communication (NFC), and infrared (IR) technologies. The wireless communication module 160 can be one or more devices integrating at least one communication processing module. The wireless communication module 160 receives electromagnetic waves via antenna 2, performs frequency modulation and filtering of the electromagnetic wave signals, and sends the processed signal to controller 110. The wireless communication module 160 can also receive signals to be transmitted from controller 110, perform frequency modulation and amplification, and convert them into electromagnetic waves for radiation via antenna 2.

[0091] In some embodiments, antenna 1 of the electronic device is electrically connected to mobile communication module 150, and antenna 2 is electrically connected to wireless communication module 160, enabling the electronic device to communicate with networks and other devices via wireless communication technology. The wireless communication technology may include Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), etc.

[0092] The memory 120 can be used to store computer executable program code, which includes instructions. The controller 110 performs various functional applications and data processing of the electronic device by executing the instructions stored in the memory 120 and / or the instructions stored in the memory disposed in the controller.

[0093] Based on this, the aforementioned electronic device may also include a circuit board, such as a printed circuit board (PCB). The controller 110, memory 120, etc., can be mounted on the circuit board, and the controller 110 and memory 120 are electrically connected to the circuit board.

[0094] The different forms of memory in electronic devices are described below with reference to the accompanying drawings.

[0095] Figure 4a The diagram illustrates one configuration of the memory, where a first chip 021 and a second chip 022 are stacked and packaged on a PCB 01. One of the chips, 021 and 022, serves as a controller, and the other as memory, such as flash memory. The first chip 021 and the second chip 022 are interconnected via through-silicon vias (TSVs) and redistribution layers (RDLs). Figure 4a In this system, since the controller and memory are two independent chips, the memory can be called a stand-alone memory.

[0096] Figure 4bThe diagram illustrates another form of memory. After being packaged separately, the first chip 021 and the second chip 022 can be connected to PCB 01 via electrical connection structures, such as a ball grid array (BGA). In this configuration, one chip (021) and the other chip (022) serve as a controller, while the other is the memory. Electrical connection between the controller and the memory can be achieved through metal traces laid on PCB 01. Figure 4a Similarly, since the controller and memory are two independent chips, the memory can be called a stand-alone memory.

[0097] Figure 4c This illustrates another form of memory, integrating the memory and controller into the same chip 02; therefore, this memory can be called embedded memory. For example, as... Figure 4c The controller and memory are integrated into the same chip. The controller can generate control signals, which can be read, write, and erase control signals to control the read, write, and erase operations of data in the memory.

[0098] Figure 5 A connection diagram of a memory, driver, and decoder is provided. The memory comprises multiple memory cells arranged in an array along a first direction (X) and a second direction (Y) to form a memory array. The memory cells arranged along the X direction are connected to the same word line (WL), and the memory cells arranged along the Y direction are connected to the same bit line (BL). Furthermore, the driver is electrically connected to the memory, and the decoder is electrically connected to the driver. The decoder decodes the address of the accessed memory cell, and the driver uses the logic level transmitted by the decoder to drive the memory cells in the memory array to perform read and write operations.

[0099] The aforementioned memory can be a non-volatile flash memory structure, such as an FG flash structure or a CT flash structure.

[0100] Figure 6 A cross-sectional view of a memory cell in a split-gate (SG) CT flash structure is given, consisting of... Figure 6As can be seen, the gate-type CT flash includes a substrate 1, a first doped region 11 (also known as the drain) and a second doped region 12 (also known as the source) formed in the substrate 1, as well as a control gate layer 3, a charge trapping layer 06 and a memory gate (MG) layer 07 formed on the substrate 1. The control gate layer 3 is insulated from the substrate 1. In addition, the charge trapping layer 06 is insulated from both the substrate 1 and the control gate layer 3. The memory gate layer 07 is located on the charge trapping layer 06 and is also insulated from both the charge trapping layer 06 and the control gate layer 3.

[0101] Figure 7a It shows Figure 6 The diagram illustrates the programming (also known as writing) process of the gate-divided CT flash. Figure 7b The erase process of this gate CT flash is shown.

[0102] Continue as Figure 7a and Figure 7b As shown, the source formed by doping is electrically connected to the source line (SL), the drain formed by doping is electrically connected to the bit line (BL), the control gate layer 3 is electrically connected to WL, and the memory gate layer 07 is electrically connected to another signal line.

[0103] besides, Figure 7a and Figure 7b The programming and erasing principles shown are illustrated using a P-type substrate and N-type source and drain as an example.

[0104] exist Figure 7a The programming process shown employs source-side injection (SSI) and channel hot electron (CHE) injection mechanisms (also known as hot carrier injection) to inject hot electrons into the charge trapping layer 06. Simply put, as... Figure 7a When a low voltage is applied to the supply line BL, a positive high voltage (PHV) is applied to the source line SL, a low positive voltage is applied to the word line WL, and a positive high voltage is applied to the memory gate layer 07, a large number of electron-hole pairs are generated in the channel region between the source and drain under the influence of the strong electric field between the source and drain. The generated hot electrons, as they flow towards the source, are subjected to a large transverse electric field (such as...) between the memory gate layer 07 and the control gate layer 3. Figure 7a The electric field E1), and at the same time, a large longitudinal electric field (such as) is generated between the memory gate layer 07 and the substrate 1. Figure 7aThe electric field E2), and then, when the hot electrons drift from the drain to between the memory gate layer 07 and the control gate layer 3, they will be subjected to the combined electric field E of electric fields E1 and E2, and will be affected by the electric field E. Figure 7a The electric field force F shown will be injected into the charge trapping layer 06 and remain there, thus achieving programming. Such programming can be called SSI programming.

[0105] However, by Figure 7a It can be seen that the injection sites of hot electrons are relatively concentrated, such as... Figure 7a The dashed box in the magnified partial view shows the approximate location of the hot electron injection. As can be seen from the magnified view, the injection location is basically near the control gate layer 3 of the charge trapping layer 06. This programming method causes significant localized damage to the material. For example, it results in substantial losses in the portion of the oxide layer between the charge trapping layer 06 and the substrate 1 near the control gate layer 3, and in the portion of the charge trapping layer 06 near the control gate layer 3. This reduces the number of programming cycles for the device and affects its lifespan. Furthermore, in... Figure 7a During the programming process of the structure shown, a large positive voltage needs to be applied to the source line SL to generate a large number of electron-hole pairs in the channel region between the source and drain. A large positive voltage also needs to be applied to the memory gate layer 07 to inject hot electrons into the charge trapping layer 06. For example, a voltage of 4V to 10V may need to be applied to the source line SL, and a voltage of 4V to 10V also needs to be applied to the memory gate layer 07. As a result, the power consumption of the device is relatively large during programming.

[0106] exist Figure 7b In the erase process shown, a positive high voltage is applied to the source line SL, a negative high voltage (NHV) is applied to the memory gate layer 07, a 0V voltage is applied to the word line WL, and a working voltage Vdd is applied to the bit line BL. This causes the PN junction formed between the source end and the P-type substrate (or P-well) to be reverse biased, resulting in band-to-band tunneling (BTBT), whereby valence band electrons in the P-well tunnel to the source end, leaving a large number of holes in the P-well. Under the influence of the high electric field generated by the negative high voltage applied to the memory gate layer 07, the holes are pulled into the charge trapping layer 06 to neutralize the electrons, thus achieving erasure. This type of erasure can be called hot hole injection (HHI) erasure.

[0107] exist Figure 7bDuring the erasure process of the structure shown, a positive high voltage needs to be applied to the source line SL to achieve band tunneling and leave a large number of holes in the P-well. At the same time, a large negative high voltage also needs to be applied to the memory gate layer 07 to generate a large electric field so that the hot holes can be pulled into the charge trapping layer 06. This results in a large voltage applied to the source line SL and the memory gate layer 07. For example, a voltage of 4V to 10V needs to be applied to the source line SL, and a voltage of -4V to -10V needs to be applied to the memory gate layer 07. As a result, the power consumption of the device during erasure is also relatively large.

[0108] besides, Figure 7a and Figure 7b The CT flash using grid-splitting technology shown has four ports (e.g., Figure 7b As shown in the diagram (ports A1 to A4), this results in a large number of connection ports and more complex wiring, which also affects the improvement of the memory's integration density.

[0109] It should be noted that the positive high voltage (PHV) involved in this application is approximately greater than 4V, and the absolute value of the negative high voltage (NHV) is approximately greater than 4V.

[0110] Figure 8 This is a cross-sectional view of a partial structure of a flash memory according to this application. Figure 8 Only one of the multiple storage units in the flash structure is shown, by Figure 8 As can be seen, the flash structure includes a storage section 61 for storing charge, a gate transistor 63, and a tunneling field-effect transistor (TFET) 62. The storage section 61 and the TFET 62 share a control gate, that is, the storage section 61 and the TFET 62 adopt a common gate structure. The storage section 61 and the gate transistor 63 do not share a control gate, that is, the storage section 61 and the gate transistor 63 adopt a separate gate structure.

[0111] Combination Figure 8 The structure of flash memory will be further explained, such as... Figure 8The flash structure includes a substrate 1 made of semiconductor material, such as a P-type semiconductor substrate. The substrate 1 has a first doped region 11 and a second doped region 12 with the same doping type formed by a doping process. For example, the first doped region 11 and the second doped region 12 can both be N-type. One of the first doped regions 11 and the second doped region 12 forms the source, and the other doped region forms the drain. A channel region is formed in the region of the substrate 1 located between the first doped region 11 and the second doped region 12.

[0112] Of course, the semiconductor substrate 1 can be N-type, and the first doped region 11 and the second doped region 12 can both be P-type.

[0113] Continue to combine Figure 8 The flash structure also includes a charge storage layer 2, a first control gate 31 and a second control gate 32, which are integrally formed structures.

[0114] The first control gate 31 is formed on the side of the charge storage layer 2 away from the substrate 1, that is, above the charge storage layer 2, and the second control gate 32 is located above the first doped region 11. In a specific process, the first control gate 31 and the second control gate 32 can be fabricated in a single process. For example, polysilicon material is deposited on the charge storage layer 2, so that polysilicon is deposited on the surface of the charge storage layer 2 and polysilicon is also deposited on the surface of the first doped region 11, thus forming an integral first control gate 31 and second control gate 32.

[0115] In addition, the first control gate 31 is insulated from the charge storage layer 2, the second control gate 32 is insulated from the charge storage layer 2, and the second control gate 32 is also insulated from the first doped region 11. For example, an insulating layer 4 can be provided between the first control gate 31 and the charge storage layer 2, and an insulating layer 4 can also be provided between the second control gate and the charge storage layer 2, and between the second control gate and the first doped region 11.

[0116] Combined Figure 8 The flash structure also includes a third control gate 33, which is formed on the second doped region 12 and is insulated from the second doped region 12.

[0117] The second control gate 32 is located on the first doped region 11, meaning that at least a portion of the orthogonal projection of the first control gate 32 onto the substrate 1 lies within the boundary of the first doped region 11. The third control gate 33 is located on the second doped region 12, meaning that at least a portion of the orthogonal projection of the second control gate 33 onto the substrate 1 lies within the boundary of the second doped region 11. Figure 8The dashed box in the figure shows the approximate locations of the storage section 61, TFET 62, and gate transistor 63.

[0118] like Figure 8 The storage portion 61, outlined by the dashed line, includes a channel region and a charge storage layer 2, as well as a first control gate 31.

[0119] For example Figure 8 The TFET62 outlined in the dashed box includes: a first doped region 11, a channel region, and a second control gate 32.

[0120] For example Figure 8 The gate 63 outlined in the dashed box includes: a second doped region 12, a channel region, and a second control gate 32.

[0121] This can be understood as, combined with Figure 8 The channel region includes a first part 71, a second part 72, and a third part 73. The first part 71 is close to the first doped region 11, the second part 72 is close to the second doped region 12, and the third part 73 is located between the first part 71 and the second part 72. It should be noted that the first part 71 and the third part 73 may partially overlap, and the second part 72 and the third part 73 may also partially overlap.

[0122] In this configuration, the channel region of TFET 62 can be the first part 71, the channel region of the storage section 61 can be the third part 73, and the channel region of the turn-on transistor 63 can be the second part 72. The following is a combination of... Figure 9a and Figure 9b Explain each Figure 8 The programming and erasing principles of the flash structure shown. Figure 9a It shows Figure 8 The programming process of the flash structure shown is as follows: Figure 9b It shows Figure 8 The erase process of the flash structure shown is illustrated. Furthermore, the programming and erasing principles are explained using the example of a P-type substrate 1 and an N-type first doped region 11 and a second doped region 12.

[0123] Combination Figure 9a During the programming process of this flash structure, SSI programming is still used. It can be understood as follows: when a 0V voltage is applied to the bit line BL connected to the second doped region 12 (which can be called the drain), a positive high voltage is applied to the source line SL connected to the first doped region 11 (which can be called the source), a positive low voltage is applied to the word line WL connected to the second CG layer, and a positive high voltage is applied to the first control gate 31, a large number of electron-hole pairs are generated in the channel region between the source and drain under the action of the strong electric field between the source and drain. The generated hot electrons are injected into the charge storage layer 2 (such as the charge capture layer) and stay there during the process of flowing to the source, thus realizing programming.

[0124] Combination Figure 9b During the erase process of this flash structure, the bit line BL is grounded, and a voltage close to 0V is applied to the word line WL. It is only necessary to apply a voltage greater than the threshold to the first control gate layer 31, and apply a suitable positive voltage (relative to) the source line SL. Figure 7b (If the voltage applied to SL is much smaller), band tunneling will occur at the interface between the first doped region 11 and the substrate 1. Hot holes are injected into the charge storage layer 2 and neutralized with electrons stored in the charge storage layer 2, thus achieving erasure.

[0125] exist Figure 9b During the erase process shown, because this application has a TFET62, under the control of the TFET62, compared to Figure 7b This will reduce the voltage applied to the source line SL and the first control gate 31, thereby reducing the erase power consumption.

[0126] The reason for reducing erase power consumption can be understood as follows: When a voltage is applied to the first control gate 31, the connected first control gate 31 and second control gate 32 can perform two functions. The first function is to allow valence band electrons in the substrate 1 to tunnel to the first doped region 11. In other words, since the TFET 62 and the storage portion 61 share the control gate layer, when a voltage is applied to the first control gate 31, the second control gate 32 of the TFET 62 will also have a voltage. Under this voltage, band-to-band tunneling will occur at the interface between the first doped region 11 and the substrate 1. That is, valence band electrons from the P-well of the substrate tunnel to the first doped region 11, leaving a large number of hot holes in the P-well. The second function is to pull the hot holes left by band-to-band tunneling in the substrate 1 into the charge storage layer 2 to neutralize the hot electrons in the charge storage layer 2, thus achieving erasure.

[0127] Furthermore, under the voltage of the source line SL, band tunneling will also occur at the interface between the first doped region 11 and the substrate 1, leaving a large number of hot holes in the P-well.

[0128] From the above combination Figure 9b During the erasure process, the generation of a large number of holes in the P-well is based on the action of two voltages: the voltage of the second control gate 2 of the TFET and the voltage of the source line SL. In this way, compared to... Figure 7b In the erase process shown, when the amount of hot holes generated is comparable, the source voltage SL can be lower. The voltage applied by the first control gate 31 only needs to be greater than the threshold voltage, thereby reducing the erase power consumption.

[0129] Figure 8 , Figure 9a and Figure 9bA schematic diagram of the structure of the first control gate 31 and the second control gate 32 is given. Figure 8 In the first control gate 31, the surface away from the substrate 1 is flush with the surface of the second control gate 32, which is also away from the substrate 1.

[0130] Figure 10 Another structural schematic diagram of the first control gate 31 and the second control gate 32 is given. Figure 10 In this configuration, the surface of the first control gate 31 that is away from the substrate 1 is not flush with the surface of the second control gate 32 that is away from the substrate 1. That is, the surface of the second control gate 32 that is away from the substrate 1 is closer to the substrate 1 than the surface of the first control gate 31 that is away from the substrate 1.

[0131] In the above Figure 8 , Figure 9a , Figure 9b and Figure 10 In the flash memory cell shown, the third control gate 33 and the first control gate 31 of the select transistor are separated by an insulating layer, which is a split-gate structure. Figure 11 A cross-sectional view of a partial structure of another flash memory architecture is given. Figure 11 Only one storage unit in the memory is shown.

[0132] Figure 11 The storage unit shown, and the above Figure 10 The memory cells shown are similar in that they also include a memory portion 61, a gate transistor 63, and a TFET 62 formed on the substrate 1. The difference is that the gate transistor 63 shares a control gate with the memory portion 61 and the TFET 62, that is, the first control gate 31, the second control gate 32, and the third control gate 33 are integrated into one structure.

[0133] From a structural perspective, Figure 11 and Figure 10 In comparison, because the selector 63 shares the control gate layer with the storage section 61 and the TFET 62, one connection terminal can be reduced, i.e., as shown below. Figure 11 As shown, the first doped region 12 is connected to port C1, the control gate containing the first control gate 31, the second control gate 32 and the third control gate 33 is connected to port C2, and the first doped region 11 is connected to port C3, that is, it has three connection ports.

[0134] However, as Figure 10 As shown, the first doped region 12 is connected to port B1, the third control gate, which serves as the control gate for the selector, is connected to port B2, the control gate containing the first control gate 31 and the second control gate 32 is connected to port B3, and the first doped region 11 is connected to port B4, thus having four connection ports. Therefore, Figure 11 Compared to the structure shown Figure 10 The structure shown can reduce one connection port, thereby simplifying the wiring of the entire memory. Figure 11 The flash structure shown can be called a gateless 3-transistor device, where the 3 transistors refer to the gate transistor 63, the storage section 61, and the TFET 62.

[0135] The following is combined Figure 12a and Figure 12b Explain each Figure 11 The programming and erasing principles of the memory are shown. Figure 12a It shows Figure 11 The programming process of the flash structure shown is as follows: Figure 12b It shows Figure 11 The erase process of the flash structure shown is illustrated. Furthermore, the programming and erasing principle is explained using the example of a P-type substrate 1 and an N-type first doped region 11 and a second doped region 12.

[0136] Combination Figure 12a During the programming process of this flash structure, SSI programming is still used. This can be understood as follows: a voltage at least greater than the threshold is applied to the first control gate 31; the second doped region 12 (which can be the drain) is grounded; and an appropriate positive voltage (less than the source) is applied to the first doped region 11 (which can be the source). Figure 7b The voltage applied to the second doped region, under which condition, an inversion channel is formed in the region of the channel region near the second doped region 12. Figure 12a (The approximate location of the inversion channel is shown). A large number of electron-hole pairs are generated by the strong electric field between the first doped region 11 and the second doped region 12. The generated hot electrons are injected into the charge storage layer 2 and stay there as they flow towards the source, thus achieving programming.

[0137] and Figure 7a The difference in programming methods shown is that the voltage applied to the first control gate 31 only needs to be greater than the threshold voltage, such as 1.3V, unlike... Figure 7a The diagram shows that a large positive voltage, such as 4V to 10V, needs to be applied to the memory gate layer 07. Furthermore, the voltage applied to the first doped region 11 is significantly smaller. Figure 7a The voltage applied to the first doped region 11 shown is, for example, Figure 12a A voltage of 2.5V is applied to the first doped region 11, however, Figure 7a The process requires applying a voltage of 4V to 10V to the SL, thereby reducing programming power consumption.

[0138] Furthermore, as provided in this embodiment... Figure 12aDuring programming, the voltage applied to the first control gate 31 is less than 4V, the voltage applied to the first doped region 11 is also less than 4V, and the voltage applied to the first control gate 31 is less than the voltage applied to the first doped region 11.

[0139] Also, in Figure 12a In this configuration, since the third control gate 33 of the gate 63 and the first control gate 31 of the storage section 61 are integrated, compared to... Figure 7a The programming process shown is in Figure 12a During the programming process shown, when hot electrons drift toward the first doped region 11, they are only subjected to a longitudinal electric field (such as...). Figure 12a The electric field E), and will not be affected by it. Figure 7a The transverse electric field, in this case, such as Figure 12a As shown, during the drift process, the hot electrons are uniformly injected into the charge storage layer 2 along the longitudinal field strength, without any... Figure 7a The phenomenon shown is that electron injection sites are concentrated, therefore, in Figure 12a The programming process shown will significantly reduce the phenomenon of local damage to the material, thereby increasing the number of times the device can be programmed and extending its service life.

[0140] Combination Figure 12b During the erase process, the second doped region 12 is grounded, a negative voltage (greater than the threshold voltage) is applied to the first control gate 31, and a suitable positive voltage (relative to the threshold voltage) is applied to the first doped region 11. Figure 7b (If the voltage applied to SL is much smaller), band tunneling will occur at the interface between the first doped region 11 and the substrate 1. Hot holes are injected into the charge storage layer 2 and neutralized with electrons stored in the charge storage layer 2, thus achieving erasure.

[0141] for Figure 12b The structure shown reduces the voltage applied to the first control gate 31 and the voltage applied to the first doped region 11 during the erasure process, and the reasons for these reductions are as follows: Figure 9b The reasons for reducing erase power consumption are basically the same and will not be repeated here. In short, the reduction in erase power consumption is achieved by introducing TFET62 and having TFET62 and the memory section 61 share a common gate.

[0142] The following are provided in this embodiment: Figure 12b In the erase process shown, the absolute value of the negative voltage applied to the first control gate 31 is less than 4V, the positive voltage applied to the first doped region 11 is less than 4V, and the absolute value of the voltage applied to the first control gate 31 is less than the voltage applied to the first doped region 11. Based on the above... Figure 11 The description of the flash structure shown, and combined with Figure 12a and Figure 12b The description of the programming and erasing principles of this flash structure reveals that it is a gateless structure. By reducing the number of gates, high programming and erasing efficiencies can be achieved. In addition, it reduces operating voltage, power consumption, and the number of ports, simplifying the winding of the memory.

[0143] Furthermore, in some alternative implementation methods, such as Figure 11 , Figure 12a and Figure 12b As shown, the surface of the third control gate 33 that is away from the substrate 1 is positioned closer to the substrate 1 than the surface of the first control gate 31 that is away from the substrate 1. The surface of the third control gate 33 that is away from the substrate 1 can be flush with the surface of the second control gate 32 that is away from the substrate 1.

[0144] In some alternative embodiments, the surface of the third control gate 33 away from the substrate 1 is flush with the surface of the first control gate 31 away from the substrate 1. Alternatively, the surface of the third control gate 33 away from the substrate 1 may be flush with the surface of the second control gate 32 away from the substrate 1.

[0145] In the flash structure described in this application, the charge storage layer 2 can be a charge trapping layer, for example, made of silicon nitride. In this case, since a charge trapping layer made of insulating material is used as the charge storage layer, once electrons enter and become trapped, they are difficult to escape. Figure 12b The material used for the insulating charge storage layer 2 and the substrate 1, as well as the insulating layer between the insulating charge storage layer 2 and the first control gate 31, is not very sensitive, which allows the insulating layer 4 to be designed to be thinner, thereby reducing the size of the entire flash structure and improving the integration of the memory.

[0146] In other embodiments, the charge storage layer 2 may be a floating gate layer, for example, a floating gate layer made of polysilicon.

[0147] Flash structures fabricated using charge trapping layers have a wider operating temperature range compared to flash structures fabricated using floating gate layers. For example, the operating temperature range of a flash structure fabricated using charge trapping layers is -40℃ to +150℃, while that of a flash structure fabricated using floating gate layers is -40℃ to +125℃.

[0148] In the memory structures described above, the first control gate 31, the second control gate 32, and the third control gate 33 can be made of poly-Si (p-Si, polycrystalline silicon). The insulating layer 4 can be made of one or more of the following insulating materials: SiO2 (silicon dioxide), Al2O3 (alumina), HfO2 (hafnium dioxide), ZrO2 (zirconia), TiO2 (titanium dioxide), Y2O3 (yttrium oxide), and Si3N4 (silicon nitride).

[0149] Figure 13 A cross-sectional view of a partial structure of a flash memory is provided. In addition to a substrate 1, a first doped region 11 and a second doped region 12 formed in the substrate 1, a charge storage layer 2, a first control gate 31, a second control gate 32 and a third control gate 33, the flash memory structure also includes BL and SL, and an electrode connection layer 5 formed on the control gate. The electrode connection layer 5, BL and SL are all made of conductive material, and the electrode connection layer 5 is electrically connected to the word line WL. In addition, BL is formed on the second doped region 12 and electrically connected to the second doped region 12, and SL is formed on the first doped region 11 and electrically connected to the first doped region 11.

[0150] Continue to combine Figure 13 The first doped region 11 and the second doped region 12 have highly doped regions, and BL and SL are both formed on the highly doped regions. For example, in Figure 12, the first doped region 11 and the second doped region 12 are both N-type doped structures. Therefore, SL is formed on the N-type highly doped region of the first doped region 11, and BL is formed on the N-type highly doped region of the second doped region 12.

[0151] In this way, the second control gate 32, which is the TFET, has a gap with SL, meaning it cannot contact SL. Similarly, the third control gate 33, which is the selector, has a gap with BL, meaning it cannot contact BL.

[0152] Therefore, as Figure 13 As shown, the side of the second control gate 32 near SL is filled with an insulating layer 4 between it and SL, and the side of the third control gate 33 near BL is filled with an insulating layer 4 between it and BL.

[0153] Figure 14 A partial structure of a flash memory array is presented, comprising multiple memory cells, multiple WL (Write-Only) modules, multiple BL (Blade-Only) modules, and multiple SL (Single-Only) modules. The memory cells can adopt the aforementioned... Figure 13 The diagram shows a three-tube structure without a grid.

[0154] Among them, multiple BLs and multiple SLs are arranged along the first direction X, and multiple WLs are arranged along the second direction Y. The first direction X is perpendicular to the second direction Y. In addition, multiple storage cells arranged along the first direction X share a WL, and multiple storage cells arranged along the second direction Y share a BL and a SL. Figure 13 This application provides only one exemplary structure for the deployment of multiple WL, multiple BL, multiple SL, and multiple storage units; it is not limited to this type of configuration. Figure 14 The layout shown can also be other layout methods.

[0155] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0156] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A memory, characterized in that, include: Substrate; as well as At least one memory cell, said at least one memory cell being formed on said substrate, each of said memory cells comprising: The storage component includes: The channel region is located between the first doped region and the second doped region, which are formed in the substrate and have the same doping type. A charge storage layer is disposed on the substrate and is insulated from the substrate; A first control gate is disposed on the side of the charge storage layer away from the substrate and is insulated from the charge storage layer; Tunneling field-effect transistors include: The first doped region; The trench area; The second control gate is disposed on the first doped region and is insulated from the first doped region. The second control gate and the first control gate are integrally formed. The gate transistor includes: The second doped region; The trench area; A third control gate is disposed on the second doped region and is insulated from the second doped region.

2. The memory according to claim 1, characterized in that, The third control gate and the first control gate are integrally formed.

3. The memory according to claim 1 or 2, characterized in that, The charge storage layer includes a charge trapping layer.

4. The memory according to claim 1 or 2, characterized in that, The surface of the second control gate that is away from the substrate is disposed close to the substrate relative to the surface of the first control gate that is away from the substrate.

5. The memory according to claim 3, characterized in that, The surface of the second control gate that is away from the substrate is disposed close to the substrate relative to the surface of the first control gate that is away from the substrate.

6. The memory according to claim 1 or 2, characterized in that, The surface of the third control gate that is away from the substrate is disposed close to the substrate relative to the surface of the first control gate that is away from the substrate.

7. The memory according to claim 3, characterized in that, The surface of the third control gate that is away from the substrate is disposed close to the substrate relative to the surface of the first control gate that is away from the substrate.

8. The memory according to claim 1 or 2, characterized in that, The surface of the second control gate away from the substrate is flush with the surface of the third control gate away from the substrate.

9. The memory according to claim 1 or 2, characterized in that, The memory also includes bit lines and source lines; The source line is disposed on the side of the first doped region away from the substrate and is electrically connected to the first doped region; The bit line is disposed on the side of the second doped region away from the substrate and is electrically connected to the second doped region; The second control gate is insulated from the source line; The third control gate is insulated from the bit line.

10. The memory according to claim 1 or 2, characterized in that, The third control gate and the first control gate are integrally molded structures; The memory also includes word lines; The first control gate is electrically connected to the word line.

11. The memory according to claim 1 or 2, characterized in that, The memory includes a plurality of memory cells, which are arranged in an array along an orthogonal first and second direction; The first control gates of the plurality of storage cells arranged along the first direction are interconnected; The first doped regions of the plurality of memory cells arranged along the second direction are interconnected; The second doped regions of the plurality of memory cells arranged along the second direction are interconnected.

12. The memory according to claim 2, characterized in that, The substrate is a P-type substrate, and both the first doped region and the second doped region are N-type doped regions. During the programming process of the memory, the first control gate is used to receive a first programming positive voltage, the first doped region is used to receive a second programming positive voltage, and the second doped region is used to ground, wherein the first programming positive voltage is less than the second programming positive voltage.

13. The memory according to claim 12, characterized in that, The first programming positive voltage is less than 4V.

14. The memory according to claim 12 or 13, characterized in that, The second programming positive voltage is less than 4V.

15. The memory according to claim 2, characterized in that, The substrate is a P-type substrate, and both the first doped region and the second doped region are N-type doped regions. During the erasure process of the memory, the first control gate is used to receive a first erase negative voltage, the first doped region is used to receive a second erase positive voltage, and the second doped region is used to ground, wherein the absolute value of the first erase negative voltage is less than the second erase positive voltage.

16. The memory according to claim 15, characterized in that, The absolute value of the first erase negative voltage is less than 4V.

17. The memory according to claim 16, characterized in that, The second erase positive voltage is less than 4V.

18. A processor, characterized in that, include: The memory as described in any one of claims 1 to 17; A processing circuit, which is electrically connected to the memory.

19. An electronic device, characterized in that, include: Circuit board; The memory as described in any one of claims 1 to 17, or the processor as described in claim 18; The memory and the processor are mounted on the circuit board and electrically connected to the circuit board.

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