Power control circuit and power IC

Abstract

This application provides a power control circuit and a power IC, relating to the field of power control. The power control circuit includes a pulse counter and a target voltage generation module. The input terminal of the pulse counter is connected to dual control signals, and the output terminal of the pulse counter is connected to the target voltage generation module, used to generate a pulse count result based on the pulse count of the two pulse signals generated by the dual control signals. The target voltage generation module is used to generate different target voltages based on the pulse count result. Using the power control circuit provided in this application, the output voltage of the power IC can be controlled by dual control signals; effectively reducing the pulse signal control time and improving the voltage response speed.

Description

Technical Field

[0001] This application relates to the field of power control, and more specifically, to a power control circuit and a power IC. Background Technology

[0002] AMOLED (Active Matrix Organic Light-Emitting Diode) is an active matrix organic light-emitting diode display technology, an advanced technology used to manufacture high-quality color displays. AMOLED display technology is widely used in electronic products such as smartphones, tablets, and televisions.

[0003] The main components of an AMOLED display are the screen, driver IC, and driver FPC (Flexible Printed Circuit Board). An AMOLED display module typically requires five voltage inputs: VCI (Display IC Analog Voltage), VDDI (Display IC Digital Voltage), ELVDD (Screen Anode Voltage), ELVSS (Screen Cathode Voltage), and AVDD (Screen Analog Voltage). To control pixel brightness, contrast, and color, the values ​​of ELVDD and ELVSS need to be controlled; AVDD supplies power to the analog circuitry within the display module and can also be adjusted as needed.

[0004] Currently, all existing control methods for the three voltage types AVDD, ELVDD, and ELVSS suffer from long pulse times. Longer pulse times mean slower voltage changes and an inability to quickly respond to changes in the input signal. Summary of the Invention

[0005] The purpose of this application is to provide a power control circuit and a power IC. By inputting dual control signals to a pulse counter, the pulse counter counts the pulses generated by the dual control signals and generates a corresponding pulse count result. Furthermore, the target voltage generation module of this power control circuit generates the required target voltage based on the pulse count result. Using the power control circuit provided in this application, the output voltage of the power IC can be controlled through dual control signals, effectively reducing the pulse signal control time and improving the voltage response speed.

[0006] In a first aspect, embodiments of this application provide a power control circuit, which includes: a pulse counter and a target voltage generation module; the input terminal of the pulse counter is connected to dual control signals, the output terminal of the pulse counter is connected to the target voltage generation module, and is used to generate a pulse counting result based on the pulse count of the two pulse signals generated by the dual control signals; the target voltage generation module is used to generate different target voltages based on the pulse counting result.

[0007] In the above implementation process, the power control circuit provided in this application provides dual control signals to a pulse counter. The pulse counter counts the pulses generated by the dual control signals and generates corresponding pulse counting results. Furthermore, the target voltage generation module of the power control circuit generates the required target voltage based on the pulse counting results. The use of dual control signals can greatly reduce the pulse control duration in the process of generating a single-pulse control signal, such as using AVDD, ELVDD, and ELVSS voltages, thereby improving the voltage response speed and reducing the problem of interference caused by long-term pulse signals.

[0008] Optionally, in this embodiment, the target voltage generation module includes: a first voltage generation submodule having a first voltage divider unit, a pulse width modulation unit, and a voltage boost / buck control unit; the input terminal of the first voltage divider unit is connected to the output terminal of a pulse counter, the output terminal of the first voltage divider unit is connected to the input terminal of the pulse width modulation unit, and is used to generate a first target signal based on the pulse counting result; the output terminal of the pulse width modulation unit is connected to the input terminal of the voltage boost / buck control unit, and is used to adjust the duty cycle of the first target signal; the voltage boost / buck control unit is used to generate a first target voltage based on the first target signal after adjusting the duty cycle.

[0009] In the above implementation process, the first voltage generation submodule of the power control circuit provided in this application embodiment includes a first voltage divider unit, a pulse width modulation unit, and a voltage rise and fall control unit; respectively, it realizes the functions of voltage division, pulse width modulation, and voltage rise and fall regulation, and finally generates different voltage values ​​according to different needs, so as to achieve stable and accurate output voltage.

[0010] Optionally, in this embodiment of the application, the target voltage generation module further includes: a second voltage generation submodule and a third voltage generation submodule; the second voltage generation submodule is used to generate a second target voltage, and the third voltage generation submodule is used to generate a third target voltage; wherein, the first target voltage, the second target voltage and the third target voltage include the screen anode voltage, the screen cathode voltage and the screen simulated voltage.

[0011] In the above implementation process, the target voltage generation module of the power control circuit provided in this application embodiment includes three sub-modules, namely a first voltage generation sub-module, a second voltage generation sub-module, and a third voltage generation sub-module. Through the cooperation of the first voltage generation sub-module, the second voltage generation sub-module, and the third voltage generation sub-module, the three voltages AVDD, ELVDD, and ELVSS required to light up the AMOLED screen can be generated respectively. Furthermore, since these three voltages are controlled by two control signals, the time of the control pulse action can be shortened, and the voltage response speed can be improved.

[0012] Optionally, in this embodiment, the pulse counter includes: a first pulse counter and a second pulse counter; the dual control signals include: a first pulse control signal and a second pulse control signal; the first pulse control signal is connected to the clock input terminal of the first pulse counter; the second pulse control signal is connected to the clock input terminal of the second pulse counter; the first pulse control signal and the second pulse control signal are respectively used to provide clock signals for the first pulse counter and the second pulse counter.

[0013] In the above implementation process, the pulse counter includes a first pulse counter and a second pulse counter. The inputs of the first pulse counter and the second pulse counter are a first pulse control signal and a second pulse control signal, respectively. Thus, the first pulse control signal and the second pulse control signal simultaneously control the circuit to generate the required three voltages AVDD, ELVDD and ELVSS, which greatly shortens the pulse time.

[0014] Optionally, in this embodiment, the first pulse counter includes a plurality of first sub-counters, and the second pulse counter includes a plurality of second sub-counters; the output terminals of the pulse counters include odd output terminals and even output terminals; wherein, the odd output terminals include the output terminals of a plurality of first sub-counters, and the even output terminals include the output terminals of a plurality of second sub-counters; the even output terminals are connected to the odd output terminals through an inverter and an AND gate, so that the even output terminals and the odd output terminals are not simultaneously at a high level.

[0015] In the above implementation process, both the first pulse counter and the second pulse counter are composed of multiple sub-counters; the output terminal of the first pulse counter is the odd output terminal, and the output terminal of the second pulse counter is the even output terminal. There are inverters and AND gates between the counting output terminal and the even output terminal to ensure that the even output terminal and the odd output terminal are not high level at the same time; at the same time, it can also control the small phase difference between the first pulse signal and the second pulse signal to avoid unstable generation level or noise problems.

[0016] Optionally, in this embodiment, the first n outputs of the pulse counter are connected to the input of the first voltage generation submodule, and the first voltage generation submodule generates a first target signal based on the counting results of the first n outputs of the pulse counter; the (n+1)th to the mth outputs of the pulse counter are connected to the input of the second voltage generation submodule, and the second voltage generation submodule generates a second target signal based on the counting results of the (n+1)th to the mth outputs of the pulse counter; the (m+1)th to the last output of the pulse counter are connected to the input of the third voltage generation submodule, and the third voltage generation submodule generates a third target signal based on the counting results of the (m+1)th to the last output of the pulse counter; wherein, m > n > 1, the second target signal includes an intermediate signal for generating the second target voltage, and the third target signal includes an intermediate signal for generating the third target voltage.

[0017] In the above implementation process, under the pulse signals generated by the first pulse control signal and the second pulse control signal, the first target signal, the second target signal and the third target signal corresponding to the first target voltage, the second target voltage and the third target voltage are controlled simultaneously; that is, the power control circuit provided in this application embodiment controls the generation of three target voltages simultaneously through two pulse control signals, thereby shortening the voltage response time.

[0018] Optionally, in this embodiment, the pulse width modulation unit includes: a comparator and a flip-flop; the input of the comparator is connected to a first voltage divider unit and a first clock signal source, and is used to generate a duty cycle adjustment signal according to a first target signal and a clock signal; wherein, the first clock signal source generates a triangular wave signal; the input of the flip-flop is connected to the output of the comparator and a second clock signal source, and is used to generate a target PWM signal according to the duty cycle adjustment signal and the second clock signal source, so as to realize the logic control of the duty cycle adjustment signal; wherein, the second clock signal source generates a square wave signal.

[0019] In the above implementation process, after the pulse counter counts, the embodiment of this application generates a corresponding voltage divider based on the counting result; furthermore, pulse width modulation is performed; the comparator and flip-flop are used in combination to achieve precise pulse width control. The comparator is used to compare the input signal with the reference signal to determine the high or low level of the output, while the flip-flop is used to control the duration of the output signal. By appropriately adjusting the threshold of the comparator and the parameters of the flip-flop, the width of the output pulse can be precisely controlled.

[0020] Optionally, in this embodiment, the voltage boost / buck control unit includes an inverter, a first operational amplifier, a second operational amplifier, a first field-effect transistor (FET), and a second FET; the input of the first operational amplifier is connected to the output of a flip-flop, and the output of the first operational amplifier is connected to the gate of the first FET; the input of the inverter is connected to the output of the flip-flop, and the output of the inverter is connected to the input of the second operational amplifier; the output of the second operational amplifier is connected to the gate of the second FET; the drain of the first FET is connected to the source of the second FET; wherein, the first and second operational amplifiers are used to adjust and amplify the target PWM signal; the first and second FETs are used to turn on or off according to the adjusted and amplified target PWM signal.

[0021] In the above implementation process, the first operational amplifier and the second operational amplifier adjust and amplify the target PWM signal, and the first field-effect transistor and the second field-effect transistor are turned on or off according to the adjusted and amplified target PWM signal. The operational amplifier can filter out noise, smooth the signal, and provide a stable output, which helps to ensure the quality and stability of the output signal and reduce instability caused by interference or fluctuations.

[0022] Optionally, in this embodiment, the voltage boost / buck control unit further includes an inductor; the inductor is connected to the drain of the first field-effect transistor and the source of the second field-effect transistor, and the drain of the second field-effect transistor is the output terminal of the voltage boost / buck control unit; wherein, the inductor is used to store electrical energy.

[0023] In the above implementation process, the power control circuit provided in this application embodiment is composed of an inverter, a first operational amplifier, a second operational amplifier, a first field-effect transistor, a second field-effect transistor, and an inductor to form a gate control. Since MOSFETs have advantages such as low on-resistance, high switching speed, and good temperature characteristics, the power control circuit provided in this application embodiment has the characteristics of simplicity, high efficiency, and stability.

[0024] Secondly, embodiments of this application provide a power supply IC, which includes the power control circuit of any one of the first aspects of this application.

[0025] In the above implementation process, the power supply IC provided in the embodiments of this application can efficiently generate the required stable voltage; such as the three voltages AVDD, ELVDD and ELVSS required by the AMOLED screen in the embodiments of this application, the response speed and voltage stability of AVDD, ELVDD and ELVSS voltages are improved. Attached Figure Description

[0026] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 A diagram of the control elements corresponding to the first control method provided by the prior art;

[0028] Figure 2 A diagram of the control elements corresponding to the second control method provided by the prior art;

[0029] Figure 3 A schematic diagram of a power control circuit provided in an embodiment of this application;

[0030] Figure 4 A circuit diagram of the first voltage generation submodule provided in the embodiments of this application;

[0031] Figure 5 A circuit diagram of the power control circuit provided in the embodiments of this application;

[0032] Figure 6 A circuit diagram of a pulse counter provided in an embodiment of this application;

[0033] Figure 7 A pulse diagram provided for an embodiment of this application;

[0034] Figure 8 A circuit diagram of the voltage generation submodule provided in the embodiments of this application;

[0035] Figure 9 The pulse timing diagram provided for the embodiments of this application.

[0036] Icons: Power control circuit - 100; First pulse control signal - SWIRE1; Second pulse control signal - SWIRE2; Pulse counter - 110; First pulse counter - 111; First sub-counter - 1111; Second pulse counter - 112; Second sub-counter - 1121; Target voltage generation module - 120; First voltage generation sub-module - 121; First voltage divider unit - 1211; Pulse width modulation unit - 1212; Comparator - 12121; Flip-flop - 12122; Voltage boost / buck control unit - 1213; Inverter - A; First operational amplifier - OP1; Second operational amplifier - OP2; First field-effect transistor - T1; Second field-effect transistor - T2; Inductor - L; Second voltage generation sub-module - 122; Third voltage generation sub-module - 123. Detailed Implementation

[0037] The technical solutions of the embodiments of this application will now be described with reference to the accompanying drawings. For example, the flowcharts and block diagrams in the drawings illustrate the architecture, functions, and operations of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagram may represent a module, program segment, or part of code, which contains one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and combinations of blocks in the block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or can be implemented using a combination of dedicated hardware and computer instructions. In addition, the functional modules in the various embodiments of the present invention may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0038] AMOLED (Active Matrix Organic Light-Emitting Diode) is an active matrix organic light-emitting diode display technology, an advanced technology used to manufacture high-quality color displays. A power management IC (PMIC) is an integrated circuit used to manage and control the power supply and power management functions of a power system. It mainly includes various power management functions such as switching power supplies, linear regulators, DC-DC buck-boost converters, protection circuits, and charging management circuits.

[0039] AMOLED display modules typically require five voltage inputs to operate normally: VCI, VDDI, ELVDD, ELVSS, and AVDD. To control pixel brightness, contrast, and color, the values ​​of ELVDD and ELVSS need to be adjusted; AVDD supplies power to the analog circuitry within the display module and can also be adjusted as needed.

[0040] During the research process, the applicant discovered that there are currently two control methods for generating ELVDD, ELVSS, and AVDD.

[0041] The first method involves outputting one SWIRE signal to the control chip and another as an enable signal; please refer to the following for details. Figure 1 , Figure 1The control element diagram corresponding to the first control method provided by the prior art; such as Figure 1 As shown, under the action of the enable signal, the SWIRE starts outputting pulses. To generate three voltages—ELVDD, ELVSS, and AVDD—different pulse control signals are required; however, this method can only generate pulses through one control signal, resulting in excessively long pulse durations. Actual wide voltage range requirements lead to more edge variations, inevitably increasing the number of pulses, typically reaching 60-70 pulses for common voltages. As the demand for wide voltage range increases, the number of pulses will continue to grow. This increase in pulse number causes longer pulse durations, resulting in slower response times to voltage changes. Furthermore, long pulses are more susceptible to interference, easily leading to incorrect voltage settings.

[0042] The second method uses one pin as ASWIRE and the other pin as ESWIRE; please refer to the following for details. Figure 2 , Figure 2 The control element diagram corresponding to the first control method provided by the prior art; such as Figure 2 As shown, ASWIRE controls the output and change of the AVDD voltage, and ESWIRE controls the output and change of the ELVDD and ELVSS voltages. Therefore, the control of the AVDD, ELVDD, and ELVSS voltages becomes a two-way control. Although the AVDD voltage is controlled by an independent voltage change on another pin, which reduces the overall SWIRE signal length, the voltage change still suffers from slow response, and the long pulse is susceptible to interference, leading to incorrect voltage settings.

[0043] Based on this, this solution provides a power control circuit and a power IC. The power control circuit generates AVDD, ELVDD, and ELVSS voltages under the action of a control signal to drive an AMOLED display. The power control circuit provided in this application, without adding pins, controls the output voltage of the power control circuit by inputting a dual-pulse signal, thereby further reducing the pulse control signal duration and improving the problem of voltage not responding quickly to changes. It also reduces the susceptibility to interference caused by long-duration pulse signals.

[0044] Please refer to Figure 3 , Figure 3 This is a schematic diagram of a power control circuit provided in an embodiment of this application; the power control circuit provided in an embodiment of this application includes a pulse counter 110 and a target voltage generation module 120.

[0045] The input terminal of the pulse counter 110 is connected to the dual control signals, and the output terminal of the pulse counter 110 is connected to the target voltage generation module 120. It is used to generate a pulse counting result based on the number of pulses of the two pulse signals generated by the dual control signals.

[0046] The dual control signals can be understood as two identical control signals connected to the two input ports of the pulse counter 110. Furthermore, the dual control signals can generate corresponding counting results based on the number of pulses corresponding to the two generated pulse signals.

[0047] The target voltage generation module 120 is used to generate different target voltages based on the pulse counting results.

[0048] It should be noted that the target voltage generation module 120 provided in this application embodiment can generate different target voltages based on the pulse counting results in the following ways: using a frequency divider to divide the pulse counting results of the counter, using a latch or trigger 12122 to capture and store the pulse counting results of the counter, using a digital comparator 12121 to compare the pulse counting results of the counter with a preset threshold, or using a digital-to-analog converter to use the pulse counting results of the counter as the input of a DAC to convert it into a corresponding analog voltage.

[0049] pass Figure 3 As can be seen, the power control circuit provided in this application embodiment inputs dual control signals to the pulse counter 110, which counts the pulses generated by the dual control signals and generates corresponding pulse counting results. Furthermore, the target voltage generation module 120 of this power control circuit generates the required target voltage based on the pulse counting results. The use of dual control signals can greatly reduce the pulse control time during the generation of AVDD, ELVDD, and ELVSS voltages, improving the voltage response speed and reducing the problem of susceptibility to interference from long-duration pulse signals.

[0050] Please refer to Figure 4 , Figure 4 The circuit structure diagram of the first voltage generation submodule 121 provided in the embodiment of this application; in an optional embodiment of this application, the target voltage generation module 120 includes: a first voltage generation submodule 121 having a first voltage divider unit 1211, a pulse width modulation unit 1212 and a voltage boost / blow control unit 1213.

[0051] The input terminal of the first voltage divider unit 1211 is connected to the output terminal of the pulse counter 110, and the output terminal of the first voltage divider unit 1211 is connected to the input terminal of the pulse width modulation unit 1212.

[0052] In this embodiment, the first voltage divider unit 1211 is used to generate a first target signal based on the pulse counting result. It should be noted that the pulse counting result obtained by counting the pulses through the pulse counter 110 is a digitally represented counting result, which is usually a binary digital code. In order to obtain the corresponding voltage, a DAC can be used to convert the digital code into the corresponding analog voltage value.

[0053] The output of the pulse width modulation unit 1212 is connected to the input of the voltage boost / buck control unit 1213 and is used to adjust the duty cycle of the first target signal. For example, pulse width modulation (PWM) technology can typically be used for duty cycle adjustment.

[0054] The voltage boost / buck control unit 1213 is used to generate a first target voltage based on a first target signal after adjusting the duty cycle. That is, the voltage boost / buck control unit 1213 boosts or bucks the first target voltage after adjusting the duty cycle to obtain the final first target voltage.

[0055] pass Figure 4 As can be seen, the first voltage generation submodule 121 of the power control circuit provided in this application embodiment includes a first voltage divider unit 1211, a pulse width modulation unit 1212 and a voltage rise and fall control unit 1213; respectively realize the functions of voltage division, pulse width modulation and voltage rise and fall regulation, and finally generate different voltage values ​​according to different needs to achieve stable and accurate output voltage.

[0056] Please refer to Figure 5 , Figure 5 The circuit diagram of the power control circuit provided in the embodiment of this application; in an optional embodiment of this application, the target voltage generation module 120 further includes: a second voltage generation submodule 122 and a third voltage generation submodule 123.

[0057] The second voltage generation submodule 122 is used to generate the second target voltage, and the third voltage generation submodule 123 is used to generate the third target voltage.

[0058] It should be noted that the first target voltage, the second target voltage, and the third target voltage include the anode voltage of the screen, the cathode voltage of the screen, and the simulated voltage of the screen. For example, as shown... Figure 5 The first target voltage shown is the ELVDD voltage, the second target voltage is the AVDD voltage, and the third target voltage is the ELVSS voltage; however, Figure 5 For example only, the first target voltage can also be the AVDD voltage or the ELVSS voltage; the second target voltage can also be the ELVDD voltage or the ELVSS voltage; and the third target voltage can also be the AVDD voltage or the ELVDD voltage.

[0059] pass Figure 5 As can be seen, the target voltage generation module 120 of the power control circuit provided in this application embodiment includes three sub-modules, namely a first voltage generation sub-module 121, a second voltage generation sub-module 122, and a third voltage generation sub-module 123. Through the cooperation of the first voltage generation sub-module 121, the second voltage generation sub-module 122, and the third voltage generation sub-module 123, the three voltages AVDD, ELVDD, and ELVSS required to light up the AMOLED screen can be generated respectively. Furthermore, since these three voltages are controlled by two control signals, the time of the control pulse can be shortened, and the voltage response speed can be improved.

[0060] Please refer to Figure 6 , Figure 6 The circuit diagram of the pulse counter 110 provided in the embodiments of this application is shown. In an optional embodiment of this application, the pulse counter 110 includes: a first pulse counter 111 and a second pulse counter 112.

[0061] The dual control signals include: a first pulse control signal and a second pulse control signal.

[0062] like Figure 6 As shown, the first pulse control signal is SWIRE1, and the second pulse control signal is SWIRE2; the row of counters input to SWIRE1 is the first pulse counter 111, and the row of counters input to SWIRE2 is the second pulse counter 112.

[0063] exist Figure 6 In this circuit, the first pulse control signal is connected to the clock input terminal of the first pulse counter 111, and the second pulse control signal is connected to the clock input terminal of the second pulse counter 112.

[0064] The first pulse control signal and the second pulse control signal are used to provide clock signals for the first pulse counter 111 and the second pulse counter 112, respectively. That is, using SWIRE1 as the clock signal for the first pulse counter 111 and SWIRE2 as the clock signal for the second pulse counter 112, the first pulse counter 111 and the second pulse counter 112 are updated simultaneously under the action of the same clock pulse, which can ensure the stability of the counters.

[0065] pass Figure 6It can be seen that the pulse counter 110 includes a first pulse counter 111 and a second pulse counter 112. The inputs of the first pulse counter 111 and the second pulse counter 112 are the first pulse control signal and the second pulse control signal, respectively. Thus, the first pulse control signal and the second pulse control signal simultaneously control the circuit to generate the required three voltages AVDD, ELVDD and ELVSS, which greatly shortens the pulse time.

[0066] Please continue reading. Figure 6 In an optional embodiment of this application, the first pulse counter 111 includes a plurality of first sub-counters 1111, and the second pulse counter 112 includes a plurality of second sub-counters 1121.

[0067] The output terminals of the pulse counter 110 include odd output terminals and even output terminals; it should be noted that the odd output terminals include the output terminals of multiple first sub-counters 1111, and the even output terminals include the output terminals of multiple second sub-counters 1121.

[0068] like Figure 6 As shown, the output terminals of the multiple first sub-counters 1111 are line1, line3, line5...line73, i.e., odd-numbered output terminals; the output terminals of the multiple second sub-counters 1121 are line2, line4, line6...line72, i.e., even-numbered output terminals; the output terminals of the first sub-counters and the output terminals of the second sub-counters 1121 together constitute the output terminals line1, line2, line3, line4...line73 of the pulse counter 110 in this embodiment of the application.

[0069] The even-numbered output is connected to the odd-numbered output via inverter A and an AND gate, so that the even-numbered output and the odd-numbered output are not both high at the same time.

[0070] pass Figure 6 It can be seen that the even-numbered outputs are connected to the odd-numbered outputs through inverter A and an AND gate, making the states of all odd-numbered outputs related to the states of the even-numbered outputs, and the states of the even-numbered outputs also related to the odd-numbered outputs. Figure 6 Taking the first sub-counter 1111 corresponding to SWIRE1 and the first sub-counter 1121 corresponding to SWIRE2 as an example, the data input terminal Di is input to 1. When SWIRE1 outputs 1 pulse and SWIRE2 does not output, line1 should be high level 1, and all other output terminals except line1 should be 0. Figure 6 The circuit structure in the diagram can be represented by a truth table as shown in Table 1:

[0071] Table 1

[0072] SWIRE1 SWIRE2 Di Line 1 Line 2 Line 3 Line 4 ...... Linen 1 0 1 1 0 0 0 0 1 1 1 0 1 0 0 0 2 1 1 0 0 1 0 0 2 2 1 0 0 0 1 0 ...... ...... 1 ...... ...... ...... ...... ...... ......

[0073] It should be noted that, under normal circumstances, the phases of the SWIRE1 and SWIRE2 control signals are aligned; however, in practical applications, for the stability of the SWIRE1 and SWIRE2 decoding circuits, there may be a certain degree of misalignment between SWIRE1 and SWIRE2.

[0074] Please refer to Figure 7 , Figure 7 This is a pulse diagram provided for an embodiment of this application. Generally, SWIRE1 and SWIRE2 can be identical (both amplitude and phase are identical), or they can have a certain phase difference. By creating a phase difference, each control signal can be switched at different times, reducing the possibility of interference. In some scenarios, it is necessary to ensure that two control signals operate synchronously within the same clock cycle, but perfect alignment may introduce timing delays or conflicts. Appropriate misalignment can provide an appropriate time interval while maintaining synchronization to meet timing requirements.

[0075] pass Figure 6 It can be seen that the first pulse counter 111 and the second pulse counter 112 are both composed of multiple sub-counters; the output terminal of the first pulse counter 111 is the odd output terminal, and the output terminal of the second pulse counter 112 is the even output terminal. There is an inverter A and an AND gate between the counting output terminal and the even output terminal to ensure that the even output terminal and the odd output terminal are not high level at the same time; at the same time, it can also control the small phase difference between the first pulse signal and the second pulse signal to reduce the generation level instability or noise problems.

[0076] Please continue reading. Figure 6 Please refer to the following: Figure 8 , Figure 8 A circuit diagram of the voltage generation submodule provided in the embodiments of this application; as follows: Figure 8 As shown, the first n outputs of the pulse counter 110 are connected to the input of the first voltage generation submodule 121, and the first voltage generation submodule 121 generates the first target signal based on the counting results of the first n outputs of the pulse counter 110.

[0077] The (n+1)th to (m)th output terminals of the pulse counter 110 are connected to the input terminals of the second voltage generation submodule 122, and the second voltage generation submodule 122 generates the second target signal based on the counting results of the (n+1)th to (m)th output terminals of the pulse counter 110.

[0078] The (m+1)th to the last output of the pulse counter 110 is connected to the input of the third voltage generation submodule 123, and the third voltage generation submodule 123 generates the third target signal based on the counting results of the (m+1)th to the last output of the pulse counter 110.

[0079] like Figure 6 As shown, Figure 6 Lines 1-58 correspond to the first counting result, lines 59-69 correspond to the second counting result, and lines 70-73 correspond to the third counting result. The first counting result, the second technical result, and the third technical result can be converted into the first target signal, the second target signal, and the third target signal.

[0080] It should be noted that m > n > 1, the second target signal includes the intermediate signal for generating the second target voltage, and the third target signal includes the intermediate signal for generating the third target voltage.

[0081] Therefore, it can be seen that under the pulse signals generated by the first pulse control signal and the second pulse control signal, the first target signal, the second target signal and the third target signal corresponding to the first target voltage, the second target voltage and the third target voltage are controlled simultaneously; that is, the power control circuit provided in this application embodiment controls the generation of three target voltages simultaneously through two pulse control signals, thereby shortening the voltage response time.

[0082] Please continue reading. Figure 4 In an optional embodiment of this application, the pulse width modulation unit 1212 includes: a comparator 12121 and a trigger 12122;

[0083] The input of comparator 12121 is connected to the first voltage divider unit 1211 and the first clock signal source, and is used to generate a duty cycle adjustment signal according to the first target signal and the clock signal; wherein, the first clock signal source generates a triangular wave signal;

[0084] The input of the flip-flop 12122 is connected to the output of the comparator 12121 and the second clock signal source, and is used to generate a target PWM signal according to the duty cycle adjustment signal and the second clock signal source to realize the logic control of the duty cycle adjustment signal; wherein, the second clock signal source generates a square wave signal.

[0085] exist Figure 4In the pulse counter 110, the output controls the ELVDD voltage divider circuit to generate a corresponding voltage divider, which, together with the triangular wave generated by the clock circuit, is input to the PWM comparator 12121. Based on different voltage dividers, the PWM comparator 12121 generates PWM signals R with different duty cycles. The PWM signal R and the square signal S generated by the clock are latched by the SR flip-flop 12122 to generate the final PWM signal Q.

[0086] Therefore, in this embodiment, after the pulse counter 110 counts, a corresponding voltage divider is generated based on the counting result; furthermore, pulse width modulation is performed; the comparator 12121 and the flip-flop 12122 are used together to achieve precise pulse width control. The comparator 12121 is used to compare the input signal with the reference signal to determine the high or low level of the output, while the flip-flop 12122 is used to control the duration of the output signal. By appropriately adjusting the threshold of the comparator 12121 and the parameters of the flip-flop 12122, the width of the output pulse can be precisely controlled.

[0087] Please continue to refer to this. Figure 4 In an optional embodiment of this application, the voltage boost / buck control unit 1213 includes an inverter A, a first operational amplifier OP1, a second operational amplifier OP2, a first field-effect transistor T1, and a second field-effect transistor T2.

[0088] The input terminal of the first operational amplifier OP1 is connected to the output terminal of the flip-flop 12122, and the output terminal of the first operational amplifier OP1 is connected to the gate of the first field-effect transistor T1.

[0089] The input terminal of inverter A is connected to the output terminal of flip-flop 12122, and the output terminal of inverter A is connected to the input terminal of the second operational amplifier OP2.

[0090] The output of the second operational amplifier OP2 is connected to the gate of the second field-effect transistor T2.

[0091] The drain of the first field-effect transistor T1 is connected to the source of the second field-effect transistor T2.

[0092] It should be noted that the first operational amplifier OP1 and the second operational amplifier OP2 are used to adjust and amplify the target PWM signal; the first field-effect transistor T1 and the second field-effect transistor T2 are used to turn on or off according to the adjusted and amplified target PWM signal.

[0093] Therefore, it can be seen that the first operational amplifier OP1 and the second operational amplifier OP2 regulate and amplify the target PWM signal, and the first field-effect transistor T1 and the second field-effect transistor T2 are turned on or off according to the regulated and amplified target PWM signal. The operational amplifier can filter out noise, smooth the signal, and provide a stable output, which helps to ensure the quality and stability of the output signal and reduce instability caused by interference or fluctuations.

[0094] Please continue reading. Figure 4 In an optional embodiment of this application, the voltage boost / buck control unit 1213 further includes an inductor L.

[0095] Inductor L connects the drain of the first field-effect transistor T1 and the source of the second field-effect transistor T2. The drain of the second field-effect transistor T2 is the output terminal of the voltage boost / buck control unit 1213.

[0096] In this process, the inductor L is used to store electrical energy. In this way, the conduction and cutoff of the first field-effect transistor T1 and the second field-effect transistor T2 can be controlled according to the changes in the PWM signal, thereby realizing the rise and fall of the voltage on the inductor L.

[0097] The above implementation process can be understood as follows: a PWM signal is sent to the gate of a MOSFET to control the switch, and the output voltage is adjusted by the duty cycle of the switching transistor. When the PWM signal is high, the MOSFET is turned on, and the inductor L stores energy; when the PWM signal is low, the MOSFET is turned off, the inductor L releases the stored energy, and the output voltage is smoothly boosted.

[0098] The power control circuit provided in this application embodiment uses an inverter A, a first operational amplifier OP1, a second operational amplifier OP2, a first field-effect transistor T1, a second field-effect transistor T2, and an inductor L to form a gate control. Since MOSFETs have advantages such as low on-resistance, high switching speed, and good temperature characteristics, the power control circuit provided in this application embodiment has the characteristics of simplicity, high efficiency, and stability.

[0099] A second aspect of this application also provides a power supply IC, which includes the power control circuit provided in the first aspect of this application. Typically, the power supply IC also includes temperature protection circuits, input filtering circuits, output filtering circuits, overcurrent protection circuits, and short-circuit protection circuits. When these other circuits are integrated with the power control circuit provided in the first aspect of this application into a single chip, a power supply IC including the power control circuit of the first aspect of this application is generated.

[0100] Using the power IC provided in this application embodiment, a stable required voltage can be generated efficiently; such as the three voltages AVDD, ELVDD and ELVSS required by the AMOLED screen in this application embodiment, the response speed and voltage stability of AVDD, ELVDD and ELVSS voltages are improved.

[0101] In summary, the power control circuit provided in this application embodiment includes a pulse counter 110 and a target voltage generation module 120. Specifically, the target voltage generation module 120 includes a first voltage generation submodule 121, a pulse width modulation unit 1212, and a voltage boost / buck control unit 1213. SWIRE1 and SWIRE2 count the number of pulses through the dual-input channel pulse counter 110. Then, the target voltage generation module 120 generates a parallel output signal based on the number of pulses to control the selection of a voltage generated by the voltage divider circuit and output it to the pulse width modulation unit 1212. The pulse width modulation unit 1212 adjusts the output of PWM signals with different duty cycles according to different voltages input to the voltage divider circuit. The voltage boost / buck control unit 1213 controls the switching of the boost or buck circuit based on the PWM signal. Please refer to [reference needed]. Figure 9 , Figure 9 The pulse timing diagram provided in the embodiments of this application is obtained through... Figure 9 It can be seen that the power control circuit provided in this application embodiment greatly shortens the pulse time.

[0102] For example, if the number of pulses required for different voltages is NELVSS = 60, NELVDD = 5, and NAVDD = 10, and the pulse period is M.

[0103] Using the first control circuit: maximum pulse duration = (60 + 10 + 5) * M = 75 M.

[0104] Using the second control circuit: maximum pulse duration = (60+5)*M = 65M (65M / 75M = 86.67%).

[0105] Using the power control circuit provided in the embodiments of this application: the maximum pulse duration = (60+10+5) / 2*M = 37.5M (37.5M / 75M = 50%).

[0106] Therefore, it can be seen that the power control circuit provided in this application embodiment controls the output voltage of the power IC by inputting a dual-pulse signal without adding pins, thereby further reducing the time of the pulse control signal, further improving the problem that the voltage cannot respond quickly to changes, and also reducing the problem that the long-term pulse signal is susceptible to interference.

[0107] In the embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the displayed or discussed mutual couplings, direct couplings, or communication connections may be through some communication interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms.

[0108] Furthermore, the units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0109] Furthermore, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0110] It can be replaced and can be implemented, wholly or partially, through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented, wholly or partially, in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present invention are generated.

[0111] The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means.

[0112] In this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, without necessarily requiring or implying any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0113] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A power supply control circuit, characterized in that, The power control circuit includes a pulse counter and a target voltage generation module; the target voltage generation module includes a first voltage generation submodule, a second voltage generation submodule and a third voltage generation submodule, the first voltage generation submodule including a first voltage divider unit, a pulse width modulation unit and a voltage rise and fall control unit; The input terminal of the pulse counter is connected to the dual control signals, and the output terminal of the pulse counter is connected to the target voltage generation module, and is used to generate a pulse counting result based on the pulse count of the two pulse signals generated by the dual control signals. The target voltage generation module is used to generate different target voltages based on the pulse counting results; The input terminal of the first voltage divider unit is connected to the output terminal of the pulse counter, and the output terminal of the first voltage divider unit is connected to the input terminal of the pulse width modulation unit, and is used to generate a first target signal based on the pulse counting result; the output terminal of the pulse width modulation unit is connected to the input terminal of the voltage boost / suppression control unit, and is used to adjust the duty cycle of the first target signal; the voltage boost / suppression control unit is used to generate the first target voltage based on the first target signal after adjusting the duty cycle. The second voltage generation submodule is used to generate a second target voltage, and the third voltage generation submodule is used to generate a third target voltage; wherein, the first target voltage, the second target voltage, and the third target voltage include the screen anode voltage, the screen cathode voltage, and the screen simulated voltage.

2. The circuit according to claim 1, characterized in that, The pulse counter includes a first pulse counter and a second pulse counter; the dual control signals include a first pulse control signal and a second pulse control signal. The first pulse control signal is connected to the clock input terminal of the first pulse counter; The second pulse control signal is connected to the clock input terminal of the second pulse counter; The first pulse control signal and the second pulse control signal are used to provide clock signals for the first pulse counter and the second pulse counter, respectively.

3. The circuit according to claim 2, characterized in that, The first pulse counter includes multiple first sub-counters, and the second pulse counter includes multiple second sub-counters; The output terminals of the pulse counter include odd output terminals and even output terminals; wherein, the odd output terminals include the output terminals of multiple first sub-counters, and the even output terminals include the output terminals of multiple second sub-counters; The even-numbered output terminal is connected to the odd-numbered output terminal through an inverter and an AND gate, so that the even-numbered output terminal and the odd-numbered output terminal are not both high at the same time.

4. The circuit according to claim 3, characterized in that, The first n outputs of the pulse counter are connected to the input of the first voltage generation submodule, and the first voltage generation submodule generates the first target signal based on the counting results of the first n outputs of the pulse counter. The (n+1)th to (m)th output terminals of the pulse counter are connected to the input terminals of the second voltage generation submodule, and the second voltage generation submodule generates the second target signal based on the counting results of the (n+1)th to (m)th output terminals of the pulse counter. The (m+1)th to the last output of the pulse counter is connected to the input of the third voltage generation submodule, and the third voltage generation submodule generates the third target signal based on the counting results of the (m+1)th to the last output of the pulse counter. Where m > n > 1, the second target signal includes an intermediate signal for generating the second target voltage, and the third target signal includes an intermediate signal for generating the third target voltage.

5. The circuit according to claim 1, characterized in that, The pulse width modulation unit includes: a comparator and a flip-flop; The input of the comparator is connected to the first voltage divider unit and the first clock signal source, and is used to generate a duty cycle adjustment signal according to the first target signal and the clock signal; wherein, the first clock signal source generates a triangular wave signal; The input of the flip-flop is connected to the output of the comparator and the second clock signal source, and is used to generate a target PWM signal according to the duty cycle adjustment signal and the second clock signal source, so as to realize the logic control of the duty cycle adjustment signal; wherein, the second clock signal source generates a square wave signal.

6. The circuit according to claim 5, characterized in that, The voltage boost / buck control unit includes an inverter, a first operational amplifier, a second operational amplifier, a first field-effect transistor, and a second field-effect transistor; The input terminal of the first operational amplifier is connected to the output terminal of the flip-flop, and the output terminal of the first operational amplifier is connected to the gate of the first field-effect transistor. The input terminal of the inverter is connected to the output terminal of the flip-flop, and the output terminal of the inverter is connected to the input terminal of the second operational amplifier. The output of the second operational amplifier is connected to the gate of the second field-effect transistor; The drain of the first field-effect transistor is connected to the source of the second field-effect transistor; The first operational amplifier and the second operational amplifier are used to adjust and amplify the target PWM signal; the first field-effect transistor and the second field-effect transistor are used to turn on or off according to the adjusted and amplified target PWM signal.

7. The circuit according to claim 6, characterized in that, The voltage boost / buck control unit also includes an inductor; The inductor connects the drain of the first field-effect transistor and the source of the second field-effect transistor, and the drain of the second field-effect transistor is the output terminal of the voltage boost / buck control unit; wherein, the inductor is used to store electrical energy.

8. A power supply IC, characterized in that, The power IC includes a power control circuit as described in any one of claims 1-7.

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