A reset circuit, chip, earphone and earphone assembly

Abstract

The present invention relates to a reset circuit, a chip, an earphone and an earphone assembly. The reset circuit includes: a first charging contact, receiving a working signal sent by a charging compartment, the working signal includes a reset signal and a communication signal, the reset signal includes N transition edges, N is a positive integer, and the transition edge includes a rising edge or a falling edge; a filter circuit, whose input end is coupled to a first node and is used to filter out the communication signal and output a reset signal, the first node is coupled to a first charging contact; a first shift register, coupled to the output end of the filter circuit, starts to count the number of transition edges received when receiving the first transition edge output by the filter circuit, and determines that a reset signal is received when receiving the Nth transition edge output by the filter circuit and outputs a control signal that resets the power management system. The reset circuit of the present invention will not be interfered by the communication signal, can accurately and effectively receive the reset signal, and is compatible with high and low speed transmission frequencies, expanding the scope of use.

Description

Technical Field

[0001] The present invention relates to the field of earphone technology, and in particular to a reset circuit, a chip, an earphone and an earphone assembly. Background Art

[0002] When in the charging case, the power management chip of the TWS (true wireless stereo) headset can be in low power consumption mode. When performing normal work, the power management chip of the TWS headset needs to receive a reset command sent by the charging case to ensure exit from the low power consumption mode, thereby restoring the entire power management system to the initial state of the startup state.

[0003] Since the earphones and the charging case generally use charging contacts for communication, that is, the charging contacts of the earphones are coupled with the charging contacts of the charging case to form a signal line, the communication signal and the reset signal will be transmitted through one line, which will be interfered by the communication signal, resulting in difficulty in identifying the reset signal. In addition, it is not compatible with high and low speed transmission frequencies, cannot be adapted to different charging cases, and its scope of use is limited. Summary of the invention

[0004] The purpose of the present invention is to overcome the above-mentioned technical problems and to provide a reset circuit, a chip, an earphone and an earphone assembly. The reset circuit will not be interfered by the communication signal when identifying the reset signal, can accurately and effectively receive the reset signal, and can be compatible with high and low speed transmission frequencies so as to adapt to different charging compartments, thereby expanding the scope of use.

[0005] In order to achieve the above-mentioned purpose, the first aspect of the present invention provides a reset circuit, which includes: a first charging contact, used to couple with the second charging contact of the charging bin to receive a working signal sent by the charging bin, the working signal includes a reset signal and at least one communication signal, the reset signal includes N transition edges, N is a positive integer, and the transition edge includes a rising edge or a falling edge; a filtering circuit, the input end of the filtering circuit is coupled to a first node, the first node is coupled to the first charging contact, the filtering circuit is used to filter out the at least one communication signal and output the reset signal; a first shift register, coupled to the output end of the filtering circuit, used to start counting the number of transition edges received when receiving the first transition edge output by the filtering circuit, and determine that the reset signal is received and output a control signal when receiving the Nth transition edge output by the filtering circuit, the control signal is used to reset the power management system.

[0006] Optionally, the communication signal is a first pulse signal, the reset signal is a second pulse signal, the logic high level duration of the first pulse signal is different from the logic high level duration of the second pulse signal; the logic high level duration of the first pulse signal is less than a first set duration, and the logic high level duration of the second pulse signal is greater than the first set duration, and the filtering circuit is used to filter out the pulse signal whose logic high level duration is less than the first set duration, and allow the pulse signal whose logic high level duration is greater than the first set duration to pass.

[0007] Optionally, each segment of the communication signal includes at least M of the transition edges, M is a positive integer, and N is less than M; the working signal also includes an end signal, the end signal is located after each segment of the communication signal, and is used to indicate that the communication signal has been sent, the end signal includes the transition edge, and the filtering circuit is also used to output the end signal; the reset circuit also includes a second shift register, the second shift register is coupled to the first node, the first shift register is used to keep outputting a trigger signal to the second shift register when receiving the first transition edge, the trigger signal is used to enable the second shift register to start counting the number of transition edges in the received working signal, and the second shift register outputs a first reset signal when receiving L of the transition edges, the first reset signal is used to restore the number of transition edges counted by the first shift register to an initial value, L is a positive integer, N≤L≤M.

[0008] Optionally, when the number of transition edges counted by the first shift register is restored to an initial value, the trigger signal is stopped from being output to the second shift register, so that the number of transition edges counted by the second shift register is restored to an initial value.

[0009] Optionally, the end signal includes a logic high level whose duration is greater than a first set duration, the reset signal is a second pulse signal, the duration of the logic high level of the end signal and the duration of the logic high level of the second pulse signal are both less than the second set duration, and the reset circuit also includes a timing circuit, the input end of the timing circuit is coupled to the first charging contact, wherein: the timing circuit is used to output a second reset signal through the first output end of the timing circuit when the time when the first charging contact receives the logic high level signal is greater than the second set duration, and the second reset signal is used to restore the number of transition edges counted by the first shift register to an initial value; and / or, the timing circuit is used to output a third reset signal through the second output end of the timing circuit when the time when the first charging contact receives the logic low level signal is greater than the second set duration, and the third reset signal is used to restore the number of transition edges counted by the first shift register to an initial value.

[0010] Optionally, the reset circuit further includes: a latch, configured to receive the control signal to keep outputting a control instruction according to the control signal, wherein the control instruction is used to control the reset of the power management system.

[0011] Optionally, the reset circuit also includes a first logic circuit, which is used to output a reset instruction to the first shift register upon receiving at least one of the control instruction, the first reset signal output by the second shift register of the reset circuit, the second reset signal output by the timing circuit of the reset circuit, and the third reset signal, wherein the reset instruction is used to restore the number of transition edges counted by the first shift register to an initial value.

[0012] Optionally, the control instruction is also used to restore the number of transition edges counted by the first shift register to an initial value; wherein: the latch is also used to receive a clear instruction issued by the power management system after the reset is completed, and the clear instruction is used to cause the latch to stop outputting the control instruction to the first shift register and the power management system; and / or, the power management system stops outputting a power supply signal to the latch after the reset is completed, so that the latch stops outputting the control instruction to the first shift register and the power management system.

[0013] Optionally, the reset circuit also includes a comparison circuit, which includes: a second logic circuit, whose output is coupled to a second node; a first comparator, whose first input is coupled to the first charging contact, whose second input is connected to a first reference voltage, and whose output is coupled to the first input of the second logic circuit; a second comparator, whose first input is coupled to the first charging contact, whose second input is connected to a second reference voltage, and whose output is coupled to the second input of the second logic circuit, and whose second reference voltage is different from the first reference voltage.

[0014] Optionally, the second reference voltage and the first reference voltage are greater than a set voltage, and the comparison circuit further includes: a switching device, an output of which is coupled to the second node, and an output of the second logic circuit is coupled to a first input of the switching device; two inverters connected in series, and the input of the two inverters connected in series is coupled to the first charging contact, and the output of the two inverters connected in series is coupled to a second input of the switching device.

[0015] A second aspect of the present invention provides a chip, comprising a chip body, a power management system and the above-mentioned reset circuit, wherein the reset circuit and the power management system are arranged on the chip body.

[0016] A third aspect of the present invention provides an earphone, comprising the chip provided by the second aspect.

[0017] A fourth aspect of the present invention provides an earphone assembly, wherein the wireless earphone assembly comprises a charging case and the above-mentioned earphone.

[0018] In the above scheme, the reset circuit of the present invention can first filter out the communication signal in the working signal, and then count the number of transition edges such as rising edges to determine whether the reset signal is received. In this way, the reset signal will not be interfered by the communication signal when it is identified, thereby achieving accurate and effective reception of the reset signal after the single-line communication state ends; and, by designing the filtering circuit, the communication signals of high-speed transmission frequency and / or low-speed transmission frequency can be filtered out, achieving compatibility with high and low-speed transmission frequencies, and can be adapted to different charging warehouses, thereby expanding the scope of use.

[0019] Other features and advantages of the present invention will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0021] Figure 1 A schematic diagram of a scenario in which a TWS headset communicates;

[0022] Figure 2 A schematic diagram of a reset circuit provided in an embodiment of the present application;

[0023] Figure 3 for Figure 2 The circuit waveform diagram of the working signal received by the reset circuit shown;

[0024] Figure 4 for Figure 2 An exemplary structural diagram of a comparison circuit of the reset circuit shown;

[0025] Figure 5 for Figure 2 The specific process diagram of the reset circuit receiving the working signal is shown. DETAILED DESCRIPTION

[0026] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0027] It should be noted that the meaning of "coupling" used in this article includes direct connection between two or more circuit objects without any intervening circuit objects, and also includes indirect connection between two or more circuit objects through one or more intervening circuit objects. For example, two circuit objects that are directly connected to each other are said to be "coupled" to each other. Similarly, two circuit objects are also said to be "coupled" to each other if there is one or more intervening circuit objects connected between them. In other words, "coupling" can be a direct electrical connection or an indirect electrical connection. Indirect electrical connection means that there are other components in between, such as resistors, capacitors, etc.

[0028] Figure 1 The following is a schematic diagram of a TWS headset communicating. Figure 1 As shown, the charging contacts of the TWS headset are coupled with the charging contacts of the charging compartment, so that the charging compartment can transmit communication signals and reset instructions to the TWS headset through the charging contacts. In addition, the TWS headset can also communicate with user devices such as mobile phones and computers via Bluetooth. The TWS headset can receive Bluetooth signals sent by user devices and can also send Bluetooth signals to user devices.

[0029] The use of charging contacts between TWS earphones and the charging case can provide faster transmission speeds, lower costs, higher security, higher reliability and higher availability. In addition, it can also provide better sound quality, lower latency, stronger signal stability and longer battery life.

[0030] Exemplarily, the process of using charging contacts to communicate between the TWS headset and the charging compartment can be as follows: first, the TWS headset is placed in the charging compartment, and the charging contacts of the TWS headset are coupled to the charging contacts of the charging compartment; then, the charging compartment uses a specific encoder to convert the coding instructions into electrical signals; then, the charging compartment sends this electrical signal to the power management chip of the headset through the charging contacts. Similarly, the TWS headset can also send messages to the charging compartment through the charging contacts. In other words, the charging compartment and the TWS headset can exchange information through the charging contacts. For example, the information exchanged between the TWS headset and the charging compartment through the charging contacts may include at least one of the power status of the headset, the connection status of the headset, the volume adjustment of the headset, the sound quality adjustment of the headset, the playback mode of the headset, etc.

[0031] In addition, when the TWS headset is in the charging case, the power management chip can be in low power mode. In low power mode, most of the power management systems on the power management chip can be turned off, and only a small part of the power management system works, thereby maintaining low power consumption, reducing the loss of the charging case battery and the TWS headset battery, extending battery life, and achieving long-term charging (for example, in long-distance transportation scenarios) without the need for external charging cables. However, when the power management chip of the TWS headset is working normally, it needs to be reset to ensure that the low power mode is exited and the entire power management system is restored to the initial state of the startup state.

[0032] Among them, the power-on reset method can be used to enable the earphone to receive a reset signal, thereby resetting the power management system. For example, after the earphone is placed in the charging compartment, the charging contacts of the earphone are coupled with the charging contacts of the charging compartment, and the charging compartment starts to power the earphone. At this time, the charging contacts of the earphone receive a power supply signal, which can be used as a reset signal. However, this solution will reset the working status of all earphones during operation, causing the Bluetooth module to fail to operate normally, and interrupting the communication connection between the earphone and the user device.

[0033] In addition, the coding circuit of the charging compartment can send a specific code value (reset signal) to the earphone through the charging contact, thereby resetting the power management system in the earphone. In this way, the working state of Bluetooth can be maintained during the reset, because the charging contacts and the Bluetooth module can be connected through a bypass circuit. In this way, when the power management system is reset, the bypass circuit can connect the charging compartment with the Bluetooth module for power supply (if the Bluetooth module is only powered by the battery management circuit and is not connected to the charging compartment through the bypass circuit, the Bluetooth communication between the earphone and the user device will be interrupted during the reset), ensuring that the earphone and the user device can still maintain connection and exchange information when resetting in the charging state. However, the existing coding reset scheme is easily interfered by communication signals, and it is not easy to identify reset signals. At the same time, the compatibility is single, because the communication voltage and communication speed specified by the communication protocols of different manufacturers are different.

[0034] In view of this, the embodiments of the present application provide a reset circuit, a chip, an earphone and an earphone assembly. The reset circuit will not be interfered by the communication signal when recognizing the reset signal, can accurately and effectively receive the reset signal after the single-line communication state ends, and can be compatible with high and low speed transmission frequencies so as to adapt to different charging compartments, thereby expanding the scope of use.

[0035] Figure 2 A schematic diagram of the structure of a reset circuit provided in an embodiment of the present application. Figure 3 for Figure 2 The circuit waveform diagram of the working signal received by the reset circuit shown in FIG. Figure 2As shown, the reset circuit includes a first charging contact, a filtering circuit and a first shift register. The first charging contact is used to couple with the second charging contact of the charging compartment to receive a working signal sent by the charging compartment, such as Figure 3 As shown, the working signal includes a reset signal and at least one communication signal. For example, the communication signal may include feedback information on at least one of the power status of the headset, the connection status of the headset, the volume adjustment of the headset, the sound quality adjustment of the headset, the playback mode of the headset, etc. The reset signal includes N jump edges, N is a positive integer, and the jump edge includes a rising edge or a falling edge. For example, the reset signal includes N pulse signals, forming N reset code values ​​01. Figure 3 In the example, the communication signal consists of 7 bits and the reset signal consists of 5 rising edges.

[0036] The input end of the filter circuit is coupled to the first node, the first node is coupled to the first charging contact, and the filter circuit is used to filter out at least one section of the communication signal and output a reset signal. The first shift register is coupled to the output end of the filter circuit, and is used to start counting the number of received transition edges when receiving the first transition edge output by the filter circuit, and to determine that the reset signal is received and output a control signal QN when receiving the Nth transition edge output by the filter circuit, and the control signal QN is used to reset the power management system.

[0037] The reset circuit of the present invention can first filter out the communication signal in the working signal, and then count the number of transition edges such as rising edges to determine whether the reset signal is received. In this way, the identification of the reset signal will not be interfered by the communication signal. The probability of erroneous reception can also be reduced by increasing the number N of the reset signal, thereby achieving accurate and effective reception of the reset signal after the single-line communication state ends; and, by designing the filtering circuit, communication signals with high-speed transmission frequency and / or low-speed transmission frequency can be filtered out, achieving compatibility with high and low-speed transmission frequencies, so as to adapt to different charging warehouses, thereby expanding the scope of use.

[0038] like Figure 3 As shown, the communication signal is a first pulse signal, the reset signal is a second pulse signal, and the duration of the logic high level of the first pulse signal is different from the duration of the logic high level of the second pulse signal; for example, the duration of the logic high level of the first pulse signal may be less than a first set duration, such as 3ms, and the duration of the logic high level of the second pulse signal may be greater than the first set duration. The filter circuit is used to filter out pulse signals whose duration of the logic high level is less than the first set duration, and to pass pulse signals whose duration of the logic high level is greater than the first set duration. For example, the filter circuit starts timing when the rising edge of the pulse signal is detected, and stops timing when the falling edge of the pulse signal is detected, thereby realizing the statistical duration of the logic high level of the pulse signal, and then filtering out the communication signal and outputting the reset signal.

[0039] Among them, each communication signal may include at least M transition edges, M is a positive integer, and N is less than M; the working signal also includes an end signal, the end signal is located after each communication signal, and is used to indicate that the communication signal has been sent. The end signal includes a transition edge, and the filtering circuit is also used to output the end signal.

[0040] like Figure 2 As shown, the reset circuit also includes a second shift register, which is coupled to the first node. The first shift register is used to keep outputting a trigger signal Q1 to the second shift register when receiving the first transition edge. The trigger signal Q1 is used to enable the second shift register to start counting the number of transition edges in the received working signal, and the second shift register outputs a first reset signal DL when receiving L transition edges. The first reset signal DL is used to restore the number of transition edges counted by the first shift register to an initial value (i.e., resetting the first shift register), where L is a positive integer, and N≤L≤M.

[0041] Considering that there is an end signal after the communication signal and the end signal is at a logic high level, if the logic high level duration of the end signal is greater than the first set time, the end signal will also be output from the filtering circuit. At this time, the end signal may be considered as a jump edge of the reset signal, such as a rising edge. Assuming that the reset signal has 5 rising edges, when the five-segment communication signal is received, if there is no second shift register, the end signal after the five-segment communication signal can form a reset signal (the five-segment communication signal has been filtered by the filtering circuit and will not be received by the first shift register), so that the first shift register outputs the control signal QN, but in fact the reset circuit has not received the reset signal and is still in the state of receiving the communication signal, so at this time the first shift register is mistakenly triggered to generate the control signal QN; if there is a second shift register, it will count L rising edges before the first shift register after detecting the communication signal, which will restore the number of rising edges counted by the first shift register to the initial value, such as clearing (i.e. resetting the first shift register), avoiding the output of the control signal QN, and thus preventing the power management system from resetting based on the control signal QN.

[0042] In addition, Figure 3 In the example, if there is an end signal after the communication signal, at this time, the first rising edge START1 counted by the first shift register is the rising edge of the end signal, and the second rising edge START2 counted by the first shift register is the first rising edge of the reset signal. In other examples, if there is no end signal after the communication signal, the first rising edge counted by the first shift register is the first rising edge of the reset signal.

[0043] That is to say, the first shift register is a master-set shift register, and the second shift register is a slave-set shift register. The coordinated working state of the master-slave-set shift register can eliminate the communication state from triggering a reset in error. In addition, the number of N in the reset signal can be increased to improve the fault tolerance rate, thereby ensuring that the number of rising edges in the received communication signal state statistics is stably cleared to zero, which can significantly reduce the error rate.

[0044] Furthermore, if Figure 2 As shown, by adjusting the filter frequency, the frequency band of the code value of the reset signal output by the filter circuit can be changed; by adjusting the number of code transmissions N (the reset signal includes N 0101010101...), the number of code values ​​01 that trigger the first shift register to send the control signal QN can be changed. At the same time, by adjusting the number of code transmissions L (the number of sequences 01010101... is L), the number of code values ​​01 that trigger the second shift register to send the first reset signal DL can be changed.

[0045] More information is transmitted at a high frequency within a limited time, and the communication speed is faster. For example, under high-speed transmission, the high-level duration (i.e. 1 bit) of the communication signal of some charging bins is 100ns according to the communication protocol, and the high-level duration (i.e. 1 bit) of the communication signal of another charging bin is 100uS according to the communication protocol. By adjusting the filtering frequency of the filtering circuit and matching the communication bit width (i.e. duration) of the transmission protocol to set the number of code values ​​01, compatibility with different communication protocols can be achieved to prevent conflicts with communication signals.

[0046] Furthermore, when the number of transition edges counted by the first shift register is restored to the initial value, the trigger signal Q1 is stopped from being output to the second shift register, so that the number of transition edges counted by the second shift register is restored to the initial value such as zero (i.e., the second shift register is reset).

[0047] Taking the jumping edge as a rising edge as an example, the first shift register starts working when it receives the first rising edge (that is, it counts the number of rising edges in the working signal after filtering out the communication signal), and keeps outputting the trigger signal Q1. The trigger signal Q1 can activate the second shift register, so that the second shift register starts working (that is, it counts the number of rising edges in the working signal); after the second shift register outputs the first reset signal DL, the first reset signal DL can restore the number of rising edges of the first shift register to the initial value such as zero and stop outputting the trigger signal Q1, thereby stopping the second shift register from working (the number of rising edges in the working signal counted by the second shift register is also restored to the initial value such as zero). In this way, the second shift register follows the first shift register to work or stop working. When working, the second shift register can effectively prevent the first shift register from erroneously triggering reset in the communication state, thereby reducing the error rate. When not working, it can reduce power consumption, which is beneficial to cost saving.

[0048] Exemplarily, the end signal includes a logic high level whose duration is greater than a first set duration, the reset signal is a second pulse signal, the duration of the logic high level of the end signal and the duration of the logic high level of the second pulse signal are both less than a second set duration, such as 30ms, and the reset circuit may further include a timing circuit, and the input end of the timing circuit is coupled to the first charging contact.

[0049] In some examples, the timing circuit is used to output a second reset signal VCHG_SLEEP_HIGH through the first output terminal of the timing circuit when the time when the first charging contact receives a logic high level signal is greater than a second set time length, such as 30ms. The second reset signal VCHG_SLEEP_HIGH is used to restore the number of transition edges counted by the first shift register to an initial value such as zero (i.e., resetting the first shift register).

[0050] In other examples, the timing circuit is used to output a third reset signal VCHG_SLEEP_LOW through the second output terminal of the timing circuit when the time when the first charging contact receives a logic low level signal is greater than a second set time length, such as 30ms. The third reset signal VCHG_SLEEP_LOW is used to restore the number of transition edges counted by the first shift register to an initial value such as zero (i.e., resetting the first shift register).

[0051] That is to say, when the earphones are pulled out of the charging case or installed in the charging case, when the charging case does not send a working signal (including a communication signal, an end signal, and a reset signal, etc.) to the earphones, the first charging contact of the earphones can maintain a high level for a long time (in this case, it is an empty state with a high level set for a long time) or a low level for a long time (in this case, it is an empty state with a low level set for a long time), so that the number of transition edges counted by the first shift register can be restored to the initial value such as zero (i.e., resetting the first shift register).

[0052] Continue to refer Figure 2 In order to ensure that the power management system can receive a stable reset instruction, the reset circuit may further include a latch, which is used to receive a control signal QN to keep outputting a control instruction REST_SYSTEM according to the control signal QN, and the control instruction REST_SYSTEM is used to control the power management system to reset. Exemplarily, the latch may be a D flip-flop.

[0053] Optionally, the control instruction REST_SYSTEM is also used to restore the number of transition edges counted by the first shift register to an initial value such as zero (i.e., resetting the first shift register). In some examples, the latch is also used to receive a clear instruction REST_BACK issued by the power management system after the reset is completed. The clear instruction REST_BACK is used to stop the latch from outputting the control instruction REST_SYSTEM to the first shift register and the power management system. In other examples, the power management system stops outputting the power supply signal V1 to the latch after the reset is completed, so that the latch stops outputting the control instruction REST_SYSTEM to the first shift register and the power management system.

[0054] That is to say, after the power management system performs the reset operation based on the control instruction REST_SYSTEM, it will generate a clear instruction REST_BACK so that the output end of the latch stops outputting the control instruction REST_SYSTEM. If the second shift register first generates the first reset signal DL at or before the first shift register generates QN, the first logic circuit receives the first reset signal DL and generates a reset instruction REST main to reset the first shift register (such as clearing the number of statistical transition edges to zero) so as to prevent the first shift register from outputting the control signal QN and ensure that the latch does not generate the control instruction REST_SYSTEM. At the same time, when resetting the first shift register, the output of the trigger signal Q1 will stop, so that the second shift register is also reset (such as clearing the number of statistical transition edges to zero) until the trigger signal Q1 is received again, and the second shift register starts working.

[0055] Optionally, refer to Figure 3 , a long-time set signal (which can be a logic high level or a logic low level, and the duration is, for example, 1S) can be set after the reset signal, so that after the first shift register receives the reset signal and outputs the control signal QN, the long-time set signal can reset the first shift register in time (so that the first shift register counts the number of rising edges), so that the first shift register stops outputting the trigger signal Q1, and then resets the second shift register. In addition, the REST master generated by the control signal QN can reset the first shift register again, thereby reliably ensuring that the first shift register is reset. Exemplarily, the control instruction REST_SYSTEM can be a pulse signal, which starts when the reset signal ends and ends with a duration of M, where M is greater than 1S.

[0056] like Figure 2As shown, further, the reset circuit may also include a first logic circuit, which is used to output a reset instruction REST to the first shift register upon receiving at least one of the control instruction REST_SYSTEM, the first reset signal DL output by the second shift register, the second reset signal VCHG_SLEEP_HIGH output by the timing circuit, and the third reset signal VCHG_SLEEP_LOW, and the reset instruction REST is used to restore the number of transition edges counted by the first shift register to an initial value such as zero (i.e., resetting the first shift register).

[0057] In some examples, the first logic operation circuit includes an OR gate, which includes four input terminals and an output terminal. The first input terminal of the OR gate is used to receive the control instruction REST_SYSTEM; the second input terminal of the OR gate is used to receive the first reset signal DL; the third input terminal of the OR gate is used to receive the second reset signal VCHG_SLEEP_HIGH; the fourth input terminal of the OR gate is used to receive the third reset signal VCHG_SLEEP_LOW; and the output terminal of the OR gate is used to output the reset instruction REST master. In other examples, the first logic operation circuit may include multiple logic gates, and the multiple logic gates can realize the "OR" function. The multiple logic gates may include at least two of an "AND" gate, an "OR" gate, a "NOT" gate, an "exclusive OR" gate (also known as: exclusive OR), etc.

[0058] Figure 4 for Figure 2 An exemplary structural diagram of a comparison circuit of a reset circuit is shown in FIG. Figure 2 and Figure 4 As shown, the reset circuit also includes a comparison circuit, and the comparison circuit includes a second logic circuit, a first comparator Com1 and a second comparator Com2. Exemplarily, the second logic circuit may be an AND gate. The output end of the second logic circuit is coupled to the second node. The first input end of the first comparator Com1 is coupled to the first charging contact, the second input end of the first comparator Com1 is connected to a first reference voltage such as 4.5V, and the output end of the first comparator Com1 is coupled to the first input end X of the second logic circuit. The first input end of the second comparator Com2 is coupled to the first charging contact, the second input end of the second comparator Com2 is connected to a second reference voltage such as 4V, the output end of the second comparator Com2 is coupled to the second input end Y of the second logic circuit, and the second reference voltage is different from the first reference voltage.

[0059] In this way, the comparison circuit can convert the high and low level signals generated by different charging compartments into unified high and low level signals, so that the reset circuit can adapt to the effective reset code value signals generated by different charging compartments. For example, two comparators can realize: output logic low level "0" in the range of 4.0V-4.5V; output logic high level "1" in the range of 4.5V-5V (VDD). At the same time, the comparison circuit can also shape the transition edge such as the rising edge, such as Figure 2 As shown, the comparison circuit can adjust the transition edge with a larger inclination to a transition edge closer to a vertical transition edge.

[0060] In addition, whether it is a communication signal, an end signal, or a reset signal, it meets the frequency and voltage requirements. For example, an overvoltage signal (such as static electricity) or a low voltage signal (caused by noise interference) does not meet the voltage requirements and will not pass through the comparator as a working signal. In other words, the comparator determines whether the signal meets the set threshold voltage range. If the voltage is high enough to exceed the threshold voltage, the comparator outputs logic 1, and in other cases the comparator outputs logic 0.

[0061] In some examples, the second reference voltage and the first reference voltage may be greater than a set voltage such as 2.8V or 3V, so that the voltage of the "logic low level" in the high and low levels received by the comparison circuit is relatively high (but lower than the set voltage), and the "logic high level" and "logic low level" in the high and low level signals received by the comparison circuit can both be used to power other devices.

[0062] Further, the comparison circuit may also include a switch device K and two inverters INV1 and INV2 connected in series. The switch device K may be a single pole double throw (SPDT). The output end of the switch device K is coupled to the second node, and the output end of the second logic circuit is coupled to the first input end Z1 of the switch device K. The input ends of the two inverters INV1 and INV2 connected in series are coupled to the first charging contact, and the output ends of the two inverters INV1 and INV2 connected in series are coupled to the second input end Z2 of the switch device K.

[0063] If the logic low level in the high and low level signals of the charging bin is relatively high (can be used to power other devices), the output end of the switch device K can be connected to the first input end Z1, so that the high and low level signals of the charging bin pass through the comparator. If the logic low level in the high and low level signals of the charging bin is relatively low, the output end of the switch device K can be connected to the second input end Z2, so that the high and low level signals of the charging bin pass through two inverters connected in series. Since the threshold voltage of the inverter (equivalent to the reference voltage) is relatively low, the time required for the inverter to switch the output result between 0 and 1 at the transition edge (i.e., the time required for the flipping process) is relatively short. Alternatively, the output end of the switch device K can also be connected to the first input end Z1, so that the high and low level signals of the charging bin pass through the comparator. However, when the "logic low level" in the high and low level signals is low, the flipping process of the comparator takes a long time and reacts slowly.

[0064] Figure 5 for Figure 2 The specific process diagram of the reset circuit receiving the working signal is shown in FIG. 1. The following takes the first setting time length as 3ms, the second setting time length as 30ms, the jump edge as the rising edge, and the latch as a D flip-flop as an example, and refers to Figure 2 and Figure 5 An exemplary specific working process of the reset circuit is introduced.

[0065] The timing circuit (long time setting circuit) detects the voltage at the first charging contact of the headset, which may include the following three situations:

[0066] 1) If Figure 5 As shown, if the first charging contact of the headset is at a logic high level for a long time, and the high level time is greater than 30ms (that is, the second set time is 30ms), the first output end of the timing circuit can output a logic high level "1" to the first shift register. At this time, if the high level time is not greater than 30ms, the first output end of the timing circuit can output a logic low level "0" to the first shift register or no signal.

[0067] For example, Figure 2 As shown, the first output terminal of the timing circuit can output a second reset signal VCHG_SLEEP_HIGH (logic high level “1”) to the first logic circuit, so that the first logic circuit outputs a reset instruction REST based on the second reset signal VCHG_SLEEP_HIGH to reset the first shift register.

[0068] 2) If Figure 5As shown, if the first charging contact of the headset is at a logic low level for a long time, and the low level time is greater than 30ms (that is, the second set time is 30ms), the second output end of the timing circuit can output a logic high level "1" to the first shift register. At this time, if the low level time is not greater than 30ms, the second output end of the timing circuit can output a logic low level signal "0" to the first logic circuit or output no signal.

[0069] For example, Figure 2 As shown, the second output terminal of the timing circuit can output a third reset signal VCHG_SLEEP_LOW (logic high level signal "1") to the first logic circuit, so that the first logic circuit outputs a reset instruction REST based on the third reset signal VCHG_SLEEP_LOW to reset the first shift register.

[0070] 3) After the charging case is connected to the earphones, a mixed signal (including communication signals, end signals, and reset signals, etc.) formed by a series of high and low level signals is transmitted through the charging contacts in a single line. The comparison circuit determines whether the mixed signal meets the set threshold voltage range. If the voltage is high enough to exceed the threshold voltage, logic 1 is output, and in all other cases, logic 0 is output.

[0071] At the same time, the timing circuit (long time setting circuit) will still be used to determine whether the mixed signal includes a signal of logic high level 1 or logic low level 0 with a duration greater than 30ms. If so, the timing circuit outputs VCHG_SLEEP_HIGH or VCHG_SLEEP_LOW to the first logic circuit, so that the first logic circuit generates a reset instruction REST to reset the first shift register and the second shift register. After the first shift register is reset, it stops outputting the trigger signal Q1 (trigger signal Q1 is interrupted), causing the second shift register to be reset.

[0072] Furthermore, the comparison circuit shapes the signal received by the first charging contact of the headset and then outputs a working signal. Then, the working signal passing through the comparison circuit is transmitted to the filtering circuit, and the filtering circuit filters out the communication signal in the working signal. For example, Figure 5 As shown, the high level of the communication signal is less than 3ms (i.e., the first set duration is 3ms), and the high levels of the reset signal and the end signal are greater than or equal to 3ms. The filtering circuit can prevent the communication signal less than 3ms from passing (i.e., filter out the communication signal), and allow the reset signal greater than 3ms to pass. Optionally, if the high level of the end signal is greater than 3ms, the end signal can also pass through the filtering circuit. In this way, the filtering circuit prevents / filters out the communication signal whose logic high level duration is less than 3ms in the working signal, and allows the reset signal and the end signal whose logic high level duration is greater than 3ms in the working signal to pass, and then transmit to the first shift register.

[0073] Then, the first shift register counts the number of rising edges output by the comparison circuit. Exemplarily, when the first shift register receives the first rising edge, it starts counting the number of rising edges, generates a trigger signal Q1, and sends the trigger signal Q1 to the second shift register, so that the second shift register starts working, so as to count the number of rising edges in the working signal (the working signal is not filtered by the filtering circuit, and may include a communication signal, a reset signal, an end signal, a long-time set signal such as the second reset signal VCHG_SLEEP_HIGH and the third reset signal VCHG_SLEEP_LOW) sent by the output end of the comparison circuit, and outputs the first reset signal DL to the first shift register when L transition edges are received.

[0074] like Figure 5 As shown, when the first shift register first counts and receives N rising edges (at this time, the first reset signal DL sent by the second shift register is not received), the first shift register outputs a control signal QN to the D flip-flop, and then, as shown in Figure 2 and Figure 5 As shown, the D flip-flop (latch) outputs a control instruction REST_SYSTEM to the first logic circuit and the power management system. The first logic circuit outputs a reset instruction REST_SYSTEM to the first shift register based on the control instruction REST_SYSTEM to reset the first shift register. The control instruction REST_SYSTEM is used to reset the power management system.

[0075] In addition, if Figure 2 and Figure 5 As shown, when the first shift register is in an unfull state (i.e., the number of rising edges counted has not reached N), and the control signal QN is not output, when the second shift register first counts L rising edges, it will send a first reset signal DL to the first logic circuit, so that the first logic circuit outputs a reset instruction REST to the first shift register to reset the first shift register, so that the first shift register starts to count the number of rising edges again and stops outputting the trigger signal Q1 to the second shift register, thereby resetting the second shift register.

[0076] The present invention also provides a chip, which includes a chip body, a power management system and the above reset circuit, wherein the reset circuit and the power management system are arranged on the chip body.

[0077] Furthermore, the present invention also provides an earphone, which includes the chip provided by the second aspect above.

[0078] In addition, the present invention also provides an earphone assembly, and the wireless earphone assembly includes a charging case and the above-mentioned earphone.

[0079] In summary, the present application provides a reset circuit, chip, earphones and earphone components. The reset circuit can be integrated in a power management chip and includes a code value receiving circuit, which can accurately and effectively receive the reset code value after the single-line communication state ends, will not be affected by the normal communication state, and adapts to the effective reset code value signals generated by different charging bins. The reset circuit of the present application can be applied to earphones, such as TWS earphones, that is, the reset circuit is a circuit for TWS earphones to receive the reset command sent by the charging bin, thereby providing the power management system of the TWS earphone with a method for receiving the reset signal sent by the charging bin that effectively shields communication interference and is compatible with high and low transmission frequencies.

[0080] In addition, the scheme of the embodiment of the present application adopts an analog circuit to identify the reset signal. In other examples, the reset signal can be identified by the digital circuit in the headset. Since the communication signal and the reset signal exist at the same time, the digital circuit is not convenient to shield the communication signal of a specific bandwidth. Since it is not easy to distinguish the reset signal from the normal communication signal, the circuit is relatively complex, the implementation is difficult, the cost is high, and it is easy to be interfered with, the fault tolerance rate is low, and it is not easy to achieve compatibility with different charging warehouses. Because the communication voltage and communication speed specified by the communication protocols of different manufacturers are different, for example, the logic low level in the communication signal sent to the headset by a part of the charging warehouse is 0V, and the logic high level is the power supply voltage such as 5V; the logic low level in the communication signal sent to the headset by another part of the charging warehouse is a voltage between 0V and the power supply voltage such as 5V, such as 3.8V. In addition, if necessary, the logic high level in the communication signal can also be a voltage between 0V and the power supply voltage such as 5V, such as 4.5V, which makes it difficult to achieve compatibility in the digital circuit of the system. The reset circuit of the embodiment of the present application avoids using a digital circuit to identify the reset signal, and identifies the reset signal through an analog circuit. The recognition accuracy is high, and it can be compatible with the recognition of reset code values ​​of different charging warehouses.

[0081] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A reset circuit, characterized in that: include: A first charging contact, used to couple with a second charging contact of the charging bin to receive a working signal sent by the charging bin, wherein the working signal includes a reset signal and at least one communication signal, wherein the reset signal includes N transition edges, N is a positive integer, and the transition edge includes a rising edge or a falling edge; each communication signal includes at least M transition edges, M is a positive integer, and N is less than M; the working signal also includes an end signal, which is located after each communication signal and is used to indicate that the communication signal has been sent, and the end signal includes the transition edge; A filter circuit, wherein an input end of the filter circuit is coupled to a first node, the first node is coupled to the first charging contact, the filter circuit is used to filter out the at least one communication signal and output the reset signal; the filter circuit is also used to output the end signal; a first shift register, coupled to the output end of the filtering circuit, and used to start counting the number of received transition edges when receiving the first transition edge output by the filtering circuit, and to determine that the reset signal is received and output a control signal when receiving the Nth transition edge output by the filtering circuit, wherein the control signal is used to reset the power management system; A second shift register, the second shift register is coupled to the first node, the first shift register is used to keep outputting a trigger signal to the second shift register when receiving the first transition edge, the trigger signal is used to enable the second shift register to start counting the number of transition edges in the received working signal, and the second shift register outputs a first reset signal when receiving L transition edges, the first reset signal is used to restore the number of transition edges counted by the first shift register to an initial value, L is a positive integer, N≤L≤M.

2. The reset circuit according to claim 1, characterized in that: The communication signal is a first pulse signal, the reset signal is a second pulse signal, and a logic high level duration of the first pulse signal is different from a logic high level duration of the second pulse signal; The logic high level duration of the first pulse signal is less than a first set duration, and the logic high level duration of the second pulse signal is greater than the first set duration. The filtering circuit is used to filter out the pulse signal whose logic high level duration is less than the first set duration, and to allow the pulse signal whose logic high level duration is greater than the first set duration to pass.

3. The reset circuit according to claim 1, characterized in that: When the number of transition edges counted by the first shift register is restored to an initial value, the trigger signal is stopped from being output to the second shift register, so that the number of transition edges counted by the second shift register is restored to an initial value.

4. The reset circuit according to claim 1, characterized in that: The end signal includes a logic high level whose duration is greater than a first set duration, the reset signal is a second pulse signal, the duration of the logic high level of the end signal and the duration of the logic high level of the second pulse signal are both less than the second set duration, the reset circuit also includes a timing circuit, and the input end of the timing circuit is coupled to the first charging contact, wherein: The timing circuit is used for outputting a second reset signal through the first output terminal of the timing circuit when the time for which the first charging contact receives the logic high level signal is greater than the second set time, and the second reset signal is used for restoring the number of transition edges counted by the first shift register to an initial value; and / or, The timing circuit is used to output a third reset signal through the second output terminal of the timing circuit when the time when the first charging contact receives the logic low level signal is greater than a second set time length, and the third reset signal is used to restore the number of transition edges counted by the first shift register to an initial value.

5. The reset circuit according to claim 4, characterized in that: The reset circuit also includes: A latch is used to receive the control signal to keep outputting a control instruction according to the control signal, wherein the control instruction is used to control the reset of the power management system.

6. The reset circuit according to claim 5, characterized in that: The reset circuit also includes a first logic circuit, which is used to output a reset instruction to the first shift register upon receiving at least one of the control instruction, the first reset signal output by the second shift register of the reset circuit, the second reset signal output by the timing circuit of the reset circuit, and the third reset signal, wherein the reset instruction is used to restore the number of transition edges counted by the first shift register to an initial value.

7. The reset circuit according to claim 5, characterized in that: The control instruction is also used to restore the number of the transition edges counted by the first shift register to an initial value; wherein: The latch is further used to receive a clear instruction issued by the power management system after the reset is completed, and the clear instruction is used to make the latch stop outputting the control instruction to the first shift register and the power management system; and / or, After the power management system is reset, it stops outputting the power supply signal to the latch, so that the latch stops outputting the control instruction to the first shift register and the power management system.

8. The reset circuit according to any one of claims 1 to 7, characterized in that: The reset circuit further includes a comparison circuit, and the comparison circuit includes: A second logic circuit, an output terminal of which is coupled to the second node; a first comparator, wherein a first input terminal of the first comparator is coupled to the first charging contact, a second input terminal of the first comparator is connected to a first reference voltage, and an output terminal of the first comparator is coupled to a first input terminal of the second logic circuit; A second comparator, wherein a first input terminal of the second comparator is coupled to the first charging contact, a second input terminal of the second comparator is connected to a second reference voltage, an output terminal of the second comparator is coupled to a second input terminal of the second logic circuit, and the second reference voltage is different from the first reference voltage.

9. The reset circuit according to claim 8, characterized in that: The second reference voltage and the first reference voltage are greater than a set voltage, and the comparison circuit further includes: a switch device, an output terminal of which is coupled to the second node, and an output terminal of the second logic circuit is coupled to a first input terminal of the switch device; Two inverters are connected in series, the input terminals of the two inverters are coupled to the first charging contact, and the output terminals of the two inverters are coupled to the second input terminal of the switch device.

10. A chip, characterized in that: The invention comprises a chip body, a power management system and a reset circuit according to any one of claims 1 to 9, wherein the reset circuit and the power management system are arranged on the chip body.

11. A headset, characterized in that: Comprising the chip according to claim 10.

12. An earphone assembly, characterized in that: It comprises a charging case and the earphone according to claim 11.

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