Network card, pcie link bandwidth performance test method, device and medium

Abstract

The application provides a network card, a bandwidth performance test method and device of a PCIE link and a medium, and belongs to the technical field of computers, wherein the network card comprises a bandwidth loop device, one end of the bandwidth loop device is connected with a sending engine of the network card, and the other end of the bandwidth loop device is connected with a receiving engine of the network card; and the bandwidth loop device is used for, in the case of being enabled, breaking through the internal loop of the network card to form a high-speed serial computer expansion bus standard PCIE bandwidth loop. The bandwidth loop device is arranged in the network card, the bandwidth loop device is enabled, and the internal loop of the network card is broken through, so that the high-speed serial computer expansion bus standard PCIE bandwidth loop is formed in a single network card, and then the bandwidth performance test of the PCIE link can be realized based on the single network card, and external equipment or a jig is no longer needed, and the test efficiency can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, and in particular, to a network card, a PCIE link bandwidth performance testing method, device and medium. BACKGROUND

[0002] The network card is a computer hardware for realizing communication of the computer on the network. With the rapid development of network technology, the function requirement of the network card is higher and higher. In order to ensure the normal work of the full duplex transmission and reception of the network card, the paths of the data sending path and the data receiving path of the network card are usually designed as a mutually independent mode. However, the design mode of the mutually independent and not connected can only ensure the normal transmission and reception of the data message. If more functions are required, such as the bandwidth performance testing of the PCIE link, the external device or jig needs to be relied on, and the testing efficiency is low. SUMMARY

[0003] The present application provides a network card, a PCIE link bandwidth performance testing method, device and medium, which solves the defect that the external device or jig of the network card needs to be relied on in the bandwidth performance testing of the PCIE link in the related art, and the testing efficiency is low.

[0004] In a first aspect, the present application provides a network card, comprising:

[0005] A bandwidth loop device, one end of the bandwidth loop device is connected to a sending engine of the network card, and the other end of the bandwidth loop device is connected to a receiving engine of the network card.

[0006] The bandwidth loop device is used to open the internal loop of the network card and form a PCIE bandwidth loop when being enabled.

[0007] In some embodiments, the bandwidth loop device comprises a register arranged in an Ethernet controller, and the register is used to turn on the sending engine and the receiving engine and form the PCIE bandwidth loop when the value of a state bit is set to a preset value.

[0008] In some embodiments, the bandwidth loop device further comprises a read-only memory connected to the Ethernet controller, and the read-only memory is used to store the data message to realize the cyclic sending of the data message.

[0009] In a second aspect, the present application provides a PCIE link bandwidth performance testing method, taking the network card of any one of the first aspect as a jig, comprising:

[0010] Enabling the bandwidth loop device to open the internal loop of the network card and form the PCIE bandwidth loop.

[0011] Test bandwidth performance of the PCIE link based on the PCIE bandwidth loop.

[0012] In some embodiments, the enabling the bandwidth loop device to make the internal loop of the network card be connected to form the PCIE bandwidth loop comprises:

[0013] sending an enabling instruction to a register in the bandwidth loop device, the enabling instruction being used to set a value of a state bit of the register to a preset value;

[0014] the register turns on a sending engine and a receiving engine of the network card to form the PCIE bandwidth loop.

[0015] In some embodiments, the testing the bandwidth performance of the PCIE link based on the PCIE bandwidth loop comprises:

[0016] based on the communication of the data packets in the PCIE bandwidth loop, performing real-time statistics on traffic data of the PCIE bandwidth loop to determine the bandwidth performance test result of the PCIE link.

[0017] In some embodiments, the testing the bandwidth performance of the PCIE link based on the PCIE bandwidth loop comprises:

[0018] receiving the data packets;

[0019] storing the data packets to a read-only memory space of an Ethernet controller of the network card or a read-only memory in the bandwidth loop device;

[0020] reading the data packets from the read-only memory space or the read-only memory and sending the data packets to make the data packets flow in the PCIE bandwidth loop;

[0021] performing real-time statistics on traffic data of the PCIE bandwidth loop to determine the bandwidth performance test result of the PCIE link.

[0022] In a third aspect, the present application further provides an electronic device, which comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor implements the bandwidth performance test method of the PCIE link as described above when executing the program.

[0023] In a fourth aspect, the present application further provides a non-transitory computer readable storage medium, which stores a computer program, and the computer program is executable on a processor to implement the bandwidth performance test method of the PCIE link as described above.

[0024] In a fifth aspect, the present application further provides a computer program product comprising a computer program which, when executed by a processor, implements the bandwidth performance testing method of the PCIE link according to any one of the above aspects.

[0025] In a sixth aspect, the present application provides a server comprising the network card according to any one of the above aspects.

[0026] The network card, the bandwidth performance testing method of the PCIE link, the device and the medium provided by the present application set a bandwidth loop device in the network card, one end of the bandwidth loop device is connected to the sending engine of the network card, the other end of the bandwidth loop device is connected to the receiving engine of the network card; the bandwidth loop device is used to open the internal loop of the network card when enabled, and form a high-speed serial computer expansion bus standard PCIE bandwidth loop. The present application sets a bandwidth loop device in the network card, opens the internal loop of the network card by enabling the bandwidth loop device, thereby forming a high-speed serial computer expansion bus standard PCIE bandwidth loop in a single network card, and further realizing the bandwidth performance testing of the PCIE link based on a single network card, without relying on external equipment or jigs, and improving the testing efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the present application or the related art, the following will briefly introduce the drawings needed to be used in the embodiments or the related art description. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0028] Figure 1 It is a structural schematic diagram of the network card in the related art;

[0029] Figure 2 It is a structural schematic diagram of the network card provided by one embodiment of the present application;

[0030] Figure 3 It is a structural schematic diagram of the network card provided by one embodiment of the present application;

[0031] Figure 4 It is a structural schematic diagram of the network card provided by one embodiment of the present application;

[0032] Figure 5 It is a flowchart of the bandwidth performance testing method of the PCIE link provided by one embodiment of the present application;

[0033] Figure 6 It is a flowchart of the bandwidth performance testing method of the PCIE link provided by one embodiment of the present application;

[0034] Figure 7 Fig. 3 is a flowchart of a bandwidth performance test method of a PCIE link according to an embodiment of the present application;

[0035] Figure 8 Fig. 4 is a structural diagram of an electronic device according to an embodiment of the present application;

[0036] Reference signs:

[0037] 10: bandwidth loop device; 20: sending engine; 30: receiving engine; 40: PCIE host interface; 50: Ethernet controller; 60: PCIE end sending processing unit; 70: PCIE end receiving processing unit; 80: network interface connector; 90: register; 100: read-only memory. DETAILED DESCRIPTION

[0038] In order to make the objects, technical solutions and advantages of the present application clearer, the technical solutions in the present application will be described clearly and completely below with reference to the drawings in the present application. Obviously, the described embodiments are some embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present application.

[0039] In order to solve the defect that the test efficiency is low because it needs to rely on external equipment or fixture of a network card when testing the bandwidth performance of a PCIE link in the related art, the present application provides a network card, a bandwidth performance test method and device of a PCIE link and a medium.

[0040] The execution subject of the bandwidth performance test method of the PCIE link provided by the present application can be an electronic device, which can be a terminal device (such as a smart phone, a personal computer, a learning machine, etc.), a server (such as a local server or a cloud server, which can also be a server cluster, etc.), a processor, a chip, etc.

[0041] The present application will be described below. Figures 1-8 The present application will be described below.

[0042] Figure 1 Fig. 1 is a structural diagram of a network card in the related art, as shown in the figure, the network card in the related art includes a PCIE host interface 40, a PCIE end sending processing unit 60, a sending engine 20, the sending engine 20, a network interface connector 80, a receiving engine 30 and a PCIE end receiving processing unit 70. Figure 1

[0043] ​One end of the PCIE main interface 40 is connected with one end of the PCIE end sending processing unit 60, the other end of the PCIE end sending processing unit 60 is connected with the sending engine 20, the other end of the sending engine 20 is connected with the network interface connector 80, the other end of the network interface connector 80 is connected with the receiving engine 30, the other end of the receiving engine 30 is connected with the PCIE end receiving processing unit 70, and the other end of the PCIE end receiving processing unit 70 is connected with the other end of the PCIE main interface.

[0044] From Figure 1 It can be seen that the data sending path and the data receiving path of the network card are independent of each other, so as to ensure the normal work of the full-duplex transceiving of the network card. However, if more functions are needed, for example, the bandwidth performance test of the PCIE link, external devices or jigs need to be relied on, and the test efficiency is low.

[0045] Figure 2 A structure schematic diagram of a network card provided by an embodiment of the present application is shown in FIG. 1. Figure 2 As shown in FIG. 1, the network card provided by the present application comprises a bandwidth loop device 10, one end of the bandwidth loop device 10 is connected with a sending engine 20 of the network card, and the other end of the bandwidth loop device is connected with a receiving engine 30 of the network card.

[0046] The bandwidth loop device 10 is used to, in the case of being enabled, punch through the internal loop of the network card, and form a PCIE bandwidth loop.

[0047] The network card further comprises other components: a PCIE main interface 40, an Ethernet controller 50, a PCIE end sending processing unit 60, a PCIE end receiving processing unit 70, and a network interface connector 80.

[0048] One end of the PCIE main interface 40 is connected with one end of the PCIE end sending processing unit 60, the other end of the PCIE end sending processing unit 60 is connected with the sending engine 20, the other end of the sending engine 20 is connected with the bandwidth loop device 10, the other end of the bandwidth loop device 10 is connected with the receiving engine 30, the other end of the receiving engine 30 is connected with the PCIE end receiving processing unit 70, and the other end of the PCIE end receiving processing unit 70 is connected with the other end of the PCIE main interface.

[0049] Specifically, when it is needed to form a PCIE bandwidth loop in a single network card, the bandwidth loop device 10 is enabled by sending an enable instruction, such as an enable instruction, to the bandwidth loop device 10, and in the case that the bandwidth loop device 10 is enabled, the sending engine 20 and the receiving engine 30 can be turned on, so as to open the internal loop of the network card, Figure 2 The internal loop of the network card in the above embodiment refers to a loop formed by the PCIE host interface 40, the PCIE end sending processing unit 60, the sending engine 20, the bandwidth loop device 10, the receiving engine 30 and the PCIE end receiving processing unit 70, so as to form a PCIE bandwidth loop.

[0050] When it is needed to close the PCIE bandwidth loop in a single network card, the sending engine 20 and the receiving engine 30 can be disconnected by sending a disable instruction, such as a disable instruction, to the bandwidth loop device 10, so as to disconnect the internal loop of the network card, and thus disconnect the PCIE bandwidth loop.

[0051] In the embodiment of the present application, a bandwidth loop device is arranged in the network card, one end of the bandwidth loop device is connected to the sending engine of the network card, and the other end of the bandwidth loop device is connected to the receiving engine of the network card; the bandwidth loop device is used to open the internal loop of the network card in the case of being enabled, so as to form a high-speed serial computer expansion bus standard PCIE bandwidth loop. The present application arranges a bandwidth loop device in the network card, opens the internal loop of the network card by enabling the bandwidth loop device, so as to form a high-speed serial computer expansion bus standard PCIE bandwidth loop in a single network card, and thus the bandwidth performance of the PCIE link can be tested based on a single network card, without relying on external equipment or jigs, and the testing efficiency can be improved.

[0052] In some embodiments, Figure 3 As shown in the structure schematic diagram two of the network card provided by one embodiment of the present application, Figure 3 As shown in the structure schematic diagram two of the network card provided by one embodiment of the present application,

[0053] The one end of the PCIE host interface 40 is connected with the one end of the PCIE end sending processing unit 60, the other end of the PCIE end sending processing unit 60 is connected with the sending engine 20, the other end of the sending engine 20 is connected with the register 90 arranged in the Ethernet controller 50 in the bandwidth loop device 10, the other end of the register 90 arranged in the Ethernet controller 50 in the bandwidth loop device 10 is connected with the receiving engine 30, the other end of the receiving engine 30 is connected with the PCIE end receiving processing unit 70, and the other end of the PCIE end receiving processing unit 70 is connected with the other end of the PCIE host interface.

[0054] Generally, the state bit of the register 90 has a default value of 0. When it is needed to form the PCIE bandwidth loop in the single network card, the value of the state bit of the register 90 is changed from the default value to a preset value, for example, from the default value 0 to the preset value 1, by sending an enable instruction, such as an enable instruction, to the register 90 arranged in the Ethernet controller 50, and when the value of the state bit of the register 90 is set to the preset value, the sending engine 20 and the receiving engine 30 can be turned on, so that the internal loop of the network card is opened, Figure 3 The internal loop of the network card in the embodiment of the present application refers to the loop formed between the PCIE host interface 40, the PCIE end sending processing unit 60, the sending engine 20, the register 90 in the bandwidth loop device 10, the receiving engine 30 and the PCIE end receiving processing unit 70, so as to form the PCIE bandwidth loop.

[0055] When it is needed to close the PCIE bandwidth loop in the single network card, the value of the state bit of the register 90 is restored to the default state from the preset value by sending a disable instruction, such as a disable instruction, to the register 90, and the turn-on relationship between the sending engine 20 and the receiving engine 30 can be removed, so that the internal loop of the network card is disconnected, and the PCIE bandwidth loop is disconnected.

[0056] It should be noted that when the bandwidth loop device 10 includes the register 90 arranged in the Ethernet controller 50, the read-only memory space of the Ethernet controller 50 can be used to store the data message, so as to realize the cyclic sending of the data message. The content of the data message can be customized by the user, such as a user data protocol (UDP) and a transmission control protocol (TCP), and the present application does not make a specific limitation.

[0057] In the embodiment of the present application, the register is arranged in the bandwidth loop device, the register is arranged in the Ethernet controller, the sending engine and the receiving engine are turned on by setting the value of the state bit of the register to the preset value, and the PCIE bandwidth loop is formed.

[0058] In some embodiments, Figure 4 Figure 3 is a schematic diagram of a third structure of a network card according to an embodiment of the present application, as shown in the figure, the bandwidth loop device 10 further comprises a read-only memory 100, the read-only memory 100 is connected with the Ethernet controller 50, and the read-only memory 100 is used to store data packets to realize the cyclic transmission of the data packets. Figure 4

[0059] Specifically, in the case that the storage space of the read-only memory in the Ethernet controller 50 is insufficient or has been reserved, the bandwidth loop device 10 can further comprise a read-only memory 100 in addition to the register 90 arranged in the Ethernet controller 50, the read-only memory 100 is arranged outside the Ethernet controller 50 and is connected with the Ethernet controller 50, and the read-only memory 100 is also used to store data packets, and the network card can realize the cyclic transmission of the data packets in the PCIE bandwidth loop based on the data packets stored in the read-only memory 100.

[0060] In the embodiment of the present application, the bandwidth loop device further comprises a read-only memory connected outside the Ethernet controller, the read-only memory is connected with the Ethernet controller, and the cyclic transmission of the data packets in the single network card is realized based on the data packets stored in the read-only memory, and the transmission instruction from the outside is no longer relied on, and the read-only memory can be used as a packet sender to realize self-packet sending.

[0061] The present application provides a server comprising the network card according to any one of the above embodiments, the internal loop of the network card is opened by enabling the bandwidth loop device in the network card or sending an enabling instruction to the register in the bandwidth loop device, so that the PCIE bandwidth loop is formed in the single network card, and the bandwidth performance test of the PCIE link can be realized based on the single network card in the server, and the external equipment or jig is no longer relied on, and the test efficiency can be improved.

[0062] Figure 5 Figure 1 is a flowchart of a bandwidth performance test method of a PCIE link according to an embodiment of the present application, and the network card according to any one of the above embodiments is used as a jig, as shown in the figure, the method comprises the following steps: step 510 and step 520. The method flowchart steps are only used as a possible implementation manner of the present application. Figure 5

[0063] Step 510, enabling the bandwidth loop device 10, so that the internal loop of the network card is opened to form a PCIE bandwidth loop;

[0064] Figure 2 ​​​Taking the network card shown as an example as a fixture, in specific implementation, by sending an enable command, such as an enable command, to the bandwidth loop device 10, the bandwidth loop device 10 is enabled. When the bandwidth loop device 10 is enabled, the transmitting engine 20 and the receiving engine 30 can be connected, thereby opening the internal loop of the network card. The internal loop of the network card refers to the loop formed between the PCIE main interface 40, the PCIE end transmitting processing unit 60, the transmitting engine 20, the bandwidth loop device 10, the receiving engine 30, and the PCIE end receiving processing unit 70, thereby forming a PCIE bandwidth loop.

[0065] Step 520: Based on the PCIE bandwidth loop, test the bandwidth performance of the PCIE link.

[0066] In practical implementation, the PCIe main interface 40 receives and stores data packets. The Ethernet controller 50 reads the stored data packets and sends them to the sending engine 20 via the PCIe-side sending processing unit 60. The sending engine 20 then sends the data packets to the receiving engine 30 via the bandwidth loop device 10, and then to the PCIe-side receiving processing unit 70. Finally, the data packets are sent to the PCIe main interface 40. Because the communication status of the entire PCIe link can be monitored on the platform side, the bandwidth performance of the PCIe link can be tested.

[0067] In this embodiment of the invention, by enabling the bandwidth loop device, the internal loop of the network card is opened to form a PCIe bandwidth loop; further, based on the PCIe bandwidth loop, the bandwidth performance of the PCIe link is tested, which can realize the bandwidth performance test of the PCIe link based on a single network card, without relying on external devices and fixtures, thus improving testing efficiency.

[0068] In some embodiments, Figure 6 This is a second flowchart illustrating a PCIe link bandwidth performance testing method according to an embodiment of the present invention. Figure 6 As shown, step 510 includes:

[0069] Step 610: Send an enable instruction to the register in the bandwidth loop device, the enable instruction being used to set the value of the status bit of the register to a preset value;

[0070] by Figure 3 or Figure 4 Taking the network card shown as an example as a fixture, in specific implementation, by sending an enable instruction, such as an enable instruction, to the register 90 in the bandwidth loop device 10, the value of the status bit of the register 90 is set to a preset value, thereby enabling the bandwidth loop device 10.

[0071] Step 620, the register turns on the sending engine and the receiving engine of the network card to form a PCIE bandwidth loop.

[0072] When the bandwidth loop device 10 is enabled, the register 90 can turn on the sending engine 20 and the receiving engine 30 of the network card, so as to open the internal loop of the network card, that is, the loop among the PCIE host interface 40, the PCIE end sending processing unit 60, the sending engine 20, the register 90 in the bandwidth loop device 10, the receiving engine 30 and the PCIE end receiving processing unit 70, so as to form a PCIE bandwidth loop.

[0073] In the embodiment of the application, by sending an enabling instruction to the register in the bandwidth loop device, the value of the state bit of the register is set to a preset value, the sending engine and the receiving engine of the network card are turned on, and a PCIE bandwidth loop is formed, so that the PCIE bandwidth loop can be formed based on a single network card without relying on external equipment and jigs.

[0074] In some embodiments, step 520 comprises:

[0075] Based on the communication of the data message in the PCIE bandwidth loop, the traffic data of the PCIE bandwidth loop is statistically counted in real time, and the bandwidth performance test result of the PCIE link is determined.

[0076] In a specific implementation, based on the communication of the data message in the PCIE bandwidth loop, the traffic data of the PCIE bandwidth loop is statistically counted in real time under the operating system by means of real-time statistical counting of network traffic data, the platform side can monitor the size of the actual existing traffic data on the PCIE link, that is, the bandwidth performance of the PCIE link, and the bandwidth performance test result of the PCIE link can be determined by testing the bandwidth performance of the PCIE link.

[0077] In the embodiment of the application, by statistically counting the traffic data of the PCIE bandwidth loop based on the communication of the data message in the PCIE bandwidth loop, the bandwidth performance test result of the PCIE link is determined, so that the bandwidth performance of the PCIE link can be tested based on a single network card without the aid of external equipment and jigs, and the test efficiency can be improved.

[0078] In some embodiments, Figure 7 A flowchart of a PCIE link bandwidth performance test method provided by an embodiment of the application is shown in Figure 3, which shows that the traffic data of the PCIE bandwidth loop is statistically counted in real time based on the communication of the data message in the PCIE bandwidth loop, and the bandwidth performance test result of the PCIE link is determined, comprising: Figure 7 the communication of the data message in the PCIE bandwidth loop, and the bandwidth performance test result of the PCIE link is determined, comprising:

[0079] Step 710, receiving a data packet;

[0080] Step 720, storing the data packet into a read-only memory space of an Ethernet controller of the network card, or a read-only memory 100 in the bandwidth loop device 10;

[0081] In a specific implementation, the PCIE host interface 40 receives a data packet from a platform side and stores the data packet into a read-only memory space of an Ethernet controller 50 of the network card, or a read-only memory 100 in the bandwidth loop device 10.

[0082] It should be noted that, in the case of the network card as a tool shown in Figure 2 or Figure 3 the data packet is stored into the read-only memory space of the Ethernet controller 50 of the network card; in the case of the network card as a tool shown in Figure 4 the data packet is also stored into the read-only memory 100 in the bandwidth loop device 10.

[0083] Step 730, reading the data packet from the read-only memory space or the read-only memory 100 and sending the data packet, so that the data packet flows in the PCIE bandwidth loop;

[0084] In the case of the network card as a tool shown in Figure 2 the data packet is read from the read-only memory space of the Ethernet controller 50 of the network card and sent, and the data packet flows in the PCIE bandwidth loop in Figure 1 , the PCIE bandwidth loop in Figure 2 is formed between the PCIE host interface 40, the PCIE end sending processing unit 60, the sending engine 20, the bandwidth loop device 10, the receiving engine 30 and the PCIE end receiving processing unit 70;

[0085] In the case of the network card as a tool shown in Figure 3 the data packet is read from the read-only memory space of the Ethernet controller of the network card and sent, and the data packet flows in the PCIE bandwidth loop in Figure 2 , the PCIE bandwidth loop in Figure 3 is formed between the PCIE host interface 40, the PCIE end sending processing unit 60, the sending engine 20, the register 90 in the bandwidth loop device 10, the receiving engine 30 and the PCIE end receiving processing unit 70;

[0086] In the case of the network card as a tool shown in Figure 4The network card shown as an example of a jig reads the data packet from the read-only memory 100 in the bandwidth loop device 10 and sends the data packet, which flows in the PCIE bandwidth loop, Figure 3 , Figure 4 The PCIE bandwidth loop is formed between the PCIE host interface 40, the PCIE end sending processing unit 60, the sending engine 20, the register 90 in the bandwidth loop device 10, the receiving engine 30 and the PCIE end receiving processing unit 70.

[0087] Step 740, real-time statistics of the traffic data of the PCIE bandwidth loop is performed to determine the bandwidth performance test result of the PCIE link.

[0088] In a specific implementation, based on the communication of the data packet in the PCIE bandwidth loop, real-time statistics of the traffic data of the PCIE bandwidth loop is performed under the operating system by means of real-time statistics of the network traffic data, the platform side can monitor the size of the actual traffic data on the PCIE link, that is, the bandwidth performance of the PCIE link, and the bandwidth performance of the PCIE link is tested, so that the bandwidth performance test result of the PCIE link can be determined.

[0089] In the embodiment of the application, the data packet is first received, and then stored in the read-only storage space of the Ethernet controller of the network card or the read-only memory in the bandwidth loop device; further, the data packet is read from the read-only storage space or the read-only memory and sent, and the data packet flows in the PCIE bandwidth loop; then, real-time statistics of the traffic data of the PCIE bandwidth loop is performed, so that the bandwidth performance test result of the PCIE link is determined, the bandwidth performance of the PCIE link can be tested based on a single network card, without relying on external equipment and jigs, and the test efficiency can be improved.

[0090] It should be noted that each embodiment of the present application can be freely combined, the order can be changed or executed alone, and does not need to rely on or depend on a fixed execution order.

[0091] Figure 8 The structural schematic diagram of the electronic device provided by one embodiment of the application is shown in Figure 8As shown, the electronic device can include a processor 810, a communications interface 820, a memory 830, and a communications bus 840, wherein the processor 810, the communications interface 820, and the memory 830 complete mutual communication through the communications bus 840. The processor 810 can invoke a logic instruction in the memory 830 to execute a bandwidth performance test method of a PCIE link, which includes enabling the bandwidth loop device to make the internal loop of the network card pass through to form a PCIE bandwidth loop, and testing the bandwidth performance of the PCIE link based on the PCIE bandwidth loop.

[0092] In addition, the logic instruction in the memory 830 described above can be implemented in the form of a software functional unit and sold or used as an independent product, and can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application essentially or the part that contributes to the related art or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium, includes a plurality of instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the method described in various embodiments of the present application. The foregoing storage medium includes a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, and various media that can store program codes.

[0093] On the other hand, the present application also provides a computer program product, which includes a computer program, the computer program can be stored on a non-transitory computer readable storage medium, and the computer program is executed by a processor, and the computer can execute the bandwidth performance test method of the PCIE link provided by the above-mentioned methods, which includes enabling the bandwidth loop device to make the internal loop of the network card pass through to form a PCIE bandwidth loop, and testing the bandwidth performance of the PCIE link based on the PCIE bandwidth loop.

[0094] In yet another aspect, the present application also provides a non-transitory computer readable storage medium, which stores a computer program, and the computer program is executed by a processor to implement the bandwidth performance test method of the PCIE link provided by the above-mentioned methods, which includes enabling the bandwidth loop device to make the internal loop of the network card pass through to form a PCIE bandwidth loop, and testing the bandwidth performance of the PCIE link based on the PCIE bandwidth loop.

[0095] The device embodiments described above are merely illustrative, wherein the units described as separate components can or can not be physically separate, and the components displayed as units can or can not be physical units, i.e., can be located in one place, or can be distributed to multiple network units. Part or all of the modules can be selected to achieve the purposes of the embodiments according to actual needs. Those skilled in the art can understand and implement without creative labor.

[0096] Through the description of the above embodiments, those skilled in the art can clearly understand that the embodiments can be realized by means of software and the necessary general hardware platform, and of course can also be realized by hardware. Based on such understanding, the above technical solutions can be embodied in the form of a software product, which can be stored in a computer readable storage medium, such as a ROM / RAM, a magnetic disk, an optical disk, etc., and includes a number of instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute the methods described in each embodiment or some parts of the embodiments.

[0097] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A network interface card (NIC), characterized in that, include: A bandwidth loop device, one end of which is connected to the transmitting engine of the network card, and the other end of which is connected to the receiving engine of the network card; The bandwidth loop device is used to open the internal loop of the network card when enabled, forming a high-speed serial computer expansion bus standard PCIe bandwidth loop. The bandwidth loop device includes: a register disposed in the Ethernet controller, the register being used to turn on the transmitting engine and the receiving engine to form a PCIE bandwidth loop when the value of the status bit is set to a preset value; The bandwidth loop device further includes a read-only memory (ROM), which is located outside the Ethernet controller and connected to the Ethernet controller. The ROM is used to store data packets to enable the cyclic transmission of data packets.

2. A method for testing the bandwidth performance of a PCIe link, applied to the network card as described in claim 1, characterized in that, include: Enable the bandwidth loop device to open the internal loop of the network card and form a PCIE bandwidth loop. Based on the aforementioned PCIe bandwidth loop, the bandwidth performance of the PCIe link was tested. Enabling the bandwidth loop device to open the internal loop of the network card and form a PCIe bandwidth loop includes: An enable instruction is sent to the register in the bandwidth loop device, the enable instruction being used to set the value of the status bit of the register to a preset value; The register activates the network card's transmitting and receiving engines, forming a PCIe bandwidth loop; The step of testing the bandwidth performance of the PCIe link based on the PCIe bandwidth loop includes: Based on the communication status of data packets in the PCIe bandwidth loop, the traffic data of the PCIe bandwidth loop is statistically analyzed in real time to determine the bandwidth performance test results of the PCIe link. The step of performing real-time statistics on the traffic data of the PCIe bandwidth loop based on the communication status of data packets in the PCIe bandwidth loop, and determining the bandwidth performance test results of the PCIe link, includes: Receive data packets; The data packet is stored in the read-only memory of the Ethernet controller of the network card, or in the read-only memory of the bandwidth loop device; The data packet is read from the read-only storage space or read-only memory, and the data packet is sent so that the data packet flows in the PCIe bandwidth loop; The traffic data of the PCIe bandwidth loop is statistically analyzed in real time to determine the bandwidth performance test results of the PCIe link.

3. An electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the bandwidth performance testing method for the PCIe link as described in claim 2.

4. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the bandwidth performance testing method for the PCIe link as described in claim 2.

5. A server, characterized in that, Including the network interface card as described in claim 1.

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