Time-of-flight image sensor pixel circuit and driving method thereof, image sensor

Abstract

The application relates to a time-of-flight image sensor pixel circuit, a driving method thereof and an image sensor. The pixel circuit comprises a photosensitive element, a plurality of reading control units and a correction unit. The plurality of reading control units comprise a plurality of corresponding floating diffusion points. The plurality of reading control units are used for reading and controlling the charge signals transmitted by the photosensitive element respectively. One end of the correction unit is connected to a high-level voltage signal, and the other end is connected to the corresponding floating diffusion points of the plurality of reading control units. The correction unit is used for resetting all the floating diffusion points to re-integrate when the potential of at least one floating diffusion point is lower than a preset voltage during integration. Therefore, the interference of excessive background light on the time-of-flight image sensor pixel circuit can be effectively reduced, and the charge signals transmitted by the photosensitive element can be read out smoothly.

Description

Technical Field

[0001] This application relates to the field of image sensor technology, and more specifically, to a time-of-flight image sensor pixel circuit and its driving method, and an image sensor. Background Technology

[0002] Image sensors are a crucial component of digital cameras. Based on their components, image sensors can be broadly categorized into two types: CCD (Charge Coupled Device) image sensors and CMOS (Complementary Metal-Oxide Semiconductor) image sensors. Due to their advantages such as low power consumption, low cost, and ease of standardized production, CMOS image sensors have found widespread application in various fields.

[0003] Time-of-flight (TOF) image sensor devices are mainly used in systems that acquire 3D images. They measure the distance from the imaging target to the image sensor by using the time it takes for light to travel from the light source to the object and then reflect back to the image sensor. By using each pixel of the time-of-flight image sensor for distance measurement, high-precision depth images can be obtained.

[0004] For traditional image sensors, their operating efficiency is directly related to the background light they receive. Specifically, when an image sensor receives strong background light, the voltage of the floating diffusion (FD) node in the image sensor pixel circuit will drop sharply due to the interference of the strong background light. When the voltage of the floating diffusion point drops below the turn-on voltage of the readout circuit, the readout circuit in the image sensor pixel circuit will not be able to conduct normally and will not be able to read the charge signal transmitted by the photodiode, thus causing the entire pixel circuit to fail. Summary of the Invention

[0005] In order to at least overcome the above-mentioned deficiencies in the prior art, the purpose of this application is to provide a time-of-flight image sensor pixel circuit and its driving method, as well as an image sensor.

[0006] In a first aspect, embodiments of this application provide a time-of-flight image sensor pixel circuit, the time-of-flight image sensor pixel circuit including a photosensitive element, a plurality of readout control units and a correction unit;

[0007] The plurality of read control units include a plurality of corresponding floating diffusion points, and the plurality of read control units are used to read and control the charge signal transmitted by the photosensitive element respectively; one end of the correction unit is connected to a high-level voltage signal, and the other end is connected to the plurality of floating diffusion points; wherein, the correction unit is used to reset all the floating diffusion points to re-integrate when the potential of at least one of the floating diffusion points is lower than a preset voltage during the integration period;

[0008] In one possible implementation, one end of the correction unit is connected to a high-level voltage signal, and the other end is connected to the plurality of floating diffusion points; the correction unit includes a plurality of switching transistors and a logic judgment module; the first end of the switching transistor is connected to the high-level voltage signal; the second end of the switching transistor is connected to the floating diffusion points, and the control terminal of the switching transistor is connected to the logic judgment module; the logic judgment module is composed of at least one logic circuit, and the logic judgment module is used to output a control signal to turn on the switching transistor to reset all the floating diffusion points for re-integration when at least one of the potentials of at least one of the floating diffusion points is lower than the preset voltage;

[0009] In one possible implementation, the logic judgment module includes at least two inverters and a NOR gate circuit, wherein the inverters are connected to the floating diffusion point, the inverters are connected to the input terminal of the NOR gate circuit, and the output terminal of the NOR gate circuit is connected to the switching transistor.

[0010] In one possible implementation, the logic decision module includes an inverter and a NAND gate circuit, wherein the input terminal of the NAND gate circuit is connected to the floating diffusion point, the output terminal of the NAND gate circuit is connected to the input terminal of the inverter, and the output terminal of the inverter is connected to the switching transistor.

[0011] In one possible implementation, the logic judgment module includes only an AND gate circuit, wherein the input of the AND gate circuit is connected to the floating diffusion point, and the output of the AND gate circuit is simultaneously connected to the switching transistor.

[0012] In one possible implementation, the first switching transistor and the second switching transistor are P-type transistors;

[0013] In one possible implementation, the logic judgment module includes at least two inverters and an OR gate circuit, wherein the inverters are connected to the floating diffusion point, the inverters are connected to the input terminal of the OR gate circuit, and the output terminal of the OR gate circuit is connected to the switching transistor.

[0014] In one possible implementation, the logic judgment module includes only a NAND gate circuit, wherein the input terminal of the NAND gate circuit is connected to the floating diffusion point, and the output terminal of the NAND gate circuit is connected to the switching transistor.

[0015] In one possible implementation, the NAND gate circuit is composed of at least one control transistor group and a bias transistor connected in series. The control transistor group includes two control transistors connected in series. The control terminal of the bias transistor is connected to a bias voltage. The control transistor group is connected to the high-level voltage signal through the bias transistor. Both the control transistor and the bias transistor are N-type transistors.

[0016] In one possible implementation, the first switching transistor and the second switching transistor are N-type transistors;

[0017] In one possible implementation, the read control unit includes a reset transistor, a transmission transistor, and a signal output module; one end of the reset transistor is connected to the high-level voltage signal, and the other end of the reset transistor is connected to the floating diffusion point to reset the voltage of the floating diffusion point according to a reset control signal; a first end of the signal output module is connected to the high-level voltage signal, and a control end of the signal output module is connected to the reset transistor and the floating diffusion point respectively to amplify and output the voltage signal input from the floating diffusion point;

[0018] In one possible implementation, the read control unit includes a first read control unit and a second read control unit, and the first read control unit and the second read control unit are mirror-symmetrical about the photosensitive element.

[0019] In one possible implementation, the read control unit further includes a third read control unit and a fourth read control unit, and the first read control unit, the second read control unit, the third read control unit, and the fourth read control unit are mirror-symmetrical about the photosensitive element.

[0020] In one possible implementation, the reset transistor is an N-type transistor;

[0021] In one possible implementation, the signal output module includes a source follower transistor, a first terminal of which is connected to the high-level voltage signal, a control terminal of which is connected to the floating diffusion point, a second terminal of the reset transistor, and the correction unit, and a second terminal of which is connected to the corresponding output terminal.

[0022] In one possible implementation, the signal output module includes a row selection transistor, and the source follower transistor is connected in series with the row selection transistor and connected to the corresponding output terminal through the row selection transistor;

[0023] In one possible implementation, the pixel circuit further includes a dual conversion gain control module connected between the reset transistor and the floating diffusion point. The dual conversion gain control module includes at least one dual conversion gain control transistor and a capacitor. The dual conversion gain control module is used to switch between a low conversion gain mode and a high conversion gain mode.

[0024] In one possible implementation, the pixel circuit further includes a pixel reset transistor, a first terminal of which is connected to a ground signal, a second terminal of which is connected to a second terminal of the photosensitive element, a control terminal of which is connected to a pixel reset signal, and the pixel reset transistor is used to clear the charge of the photosensitive element before the photosensitive element transmits a charge signal.

[0025] In one possible implementation, the read control unit further includes a storage capacitor, the first plate of which is connected to the floating diffusion point and the second plate of which is connected to a ground signal. The storage capacitor is used to receive and store the charge generated by the photosensitive element after the correction unit corrects and resets when the potential of at least one of the floating diffusion points is lower than the preset voltage.

[0026] In one possible implementation, the preset voltage is the turn-on voltage of the signal output module;

[0027] Secondly, embodiments of this application also provide a method for driving a pixel circuit of a time-of-flight image sensor, used to drive the aforementioned time-of-flight image sensor pixel circuit, comprising the following steps:

[0028] In the first stage, the high-level voltage signal turns on the reset transistor, and the high-level voltage signal resets the signal output module and the floating diffusion point through the reset transistor;

[0029] In the second stage, the reset transistor is turned off, the transmission transistor is turned on, and the charge accumulated by the photosensitive element is transferred to the plurality of floating diffusion points; if the potential of at least one of the floating diffusion points is lower than the preset voltage, the correction unit simultaneously applies a high-level signal from the high-level voltage signal to all the floating diffusion points, turns on the transmission transistor again, and transfers the charge accumulated by the photosensitive element to the plurality of floating diffusion points; if the potential of all the floating diffusion points is higher than the preset voltage, the charge accumulated by the photosensitive element is written into the signal output module.

[0030] In the third stage, the transmission transistor is turned off, and the signal output module is turned on to transmit the image signal;

[0031] Thirdly, embodiments of this application also provide a time-of-flight image sensor, which employs the aforementioned time-of-flight image sensor pixel circuit.

[0032] In one possible implementation, the time-of-flight image sensor includes a first chip and a second chip, wherein: the photosensitive element and the transmission transistor are disposed on the first chip; the readout control unit, excluding the transmission transistor, and the correction unit are disposed on the second chip; the first chip and the second chip are stacked and electrically connected.

[0033] In one possible implementation, the first chip is further provided with the pixel reset transistor;

[0034] Based on any of the above aspects, the beneficial effects of the time-of-flight image sensor pixel circuit and its driving method and image sensor provided in the embodiments of this application are reflected in the following: during the integration period, when the potential of at least one floating diffusion point is lower than the preset voltage, all floating diffusion points are simultaneously reset to re-integrate, thereby effectively reducing the interference of excessively strong background light on the pixel circuit of this time-of-flight image sensor when the background light is too strong, so that it can be normally turned on and the charge signal transmitted by the photosensitive element can be read out smoothly. Attached Figure Description

[0035] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings required in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 This is a schematic diagram of a pixel circuit for an image sensor in the prior art;

[0037] Figure 2 This is a schematic diagram of the pixel circuit of the time-of-flight image sensor provided in an embodiment of this application;

[0038] Figure 3 A schematic diagram of another time-of-flight image sensor pixel circuit provided in an embodiment of this application;

[0039] Figure 4 A schematic diagram of a pixel circuit for another time-of-flight image sensor provided in an embodiment of this application;

[0040] Figure 5 A schematic diagram of the pixel circuit of another time-of-flight image sensor provided in an embodiment of this application;

[0041] Figure 6 A schematic diagram of a time-of-flight image sensor pixel circuit provided in an embodiment of this application;

[0042] Figure 7 A schematic diagram of another time-of-flight image sensor pixel circuit provided in an embodiment of this application;

[0043] Figure 8 A schematic diagram of a pixel circuit for another time-of-flight image sensor provided in an embodiment of this application;

[0044] Figure 9 A schematic diagram of the pixel circuit of another time-of-flight image sensor provided in an embodiment of this application;

[0045] Figure 10 Timing diagram of pixel circuit for time-of-flight image sensor provided in embodiments of this application;

[0046] Figure 11 Another time-of-flight image sensor pixel circuit timing diagram provided in this application embodiment;

[0047] Figure 12 A schematic diagram of a time-of-flight image sensor provided in an embodiment of this application. Detailed Implementation

[0048] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the accompanying drawings in this application are for illustrative and descriptive purposes only and are not intended to limit the scope of protection of this application. Furthermore, it should be understood that the schematic drawings are not drawn to scale. The flowcharts used in this application illustrate operations implemented according to some embodiments of this application. It should be understood that the operations in the flowcharts may not be implemented in sequence, and steps without logical contextual relationships may be reversed or implemented simultaneously. In addition, those skilled in the art, guided by the content of this application, may add one or more other operations to the flowcharts, or remove one or more operations from the flowcharts.

[0049] Furthermore, the described embodiments are merely some, not all, of the embodiments of this application. The components of the embodiments of this application described and illustrated herein can typically be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0050] As described in the background section, when an image sensor receives strong background light, the voltage of the floating diffusion (FD) node in the image sensor pixel circuit drops sharply due to the interference of the strong background light. When the voltage of the floating diffusion point drops below the turn-on voltage of the readout circuit, the readout circuit in the image sensor pixel circuit will not be able to conduct normally and will not be able to read the charge signal transmitted by the photodiode, thus causing the entire pixel circuit to fail. Figure 1The example described is a pixel circuit of a conventional image sensor in the prior art. RST0 is a reset transistor, TX0 is a transmission transistor, PD0 is a photodiode, FD0 is a floating diffusion point, and Pixout is the second terminal. The voltage of the floating diffusion point FD0 is proportional to the voltage of the second terminal Pixout. rst0 is the control signal for the reset transistor RST0, and tx0 is the control signal for the transmission transistor TX0. When rst0 is high, the reset transistor RST0 is turned on and outputs a reset signal to the floating diffusion point FD0 and the second terminal Pixout. The reset signal of either the floating diffusion point FD0 or the second terminal Pixout is sampled as the reset sampling signal value Vrst. When tx0 is high, the transmission transistor TX0 is turned on and outputs the charge signal of the photodiode PD0 to the floating diffusion point FD0 and the second terminal Pixout. The charge signal of either the floating diffusion point FD0 or the second terminal Pixout is sampled as the photoelectronic sampling signal value Vfd. The difference between the reset sampling signal value Vrst and the photoelectronic sampling signal value Vfd is the image signal. The larger the charge signal, i.e., the stronger the light, the larger the difference between the reset sampling signal value Vrst and the photoelectronic sampling signal value Vfd. When the background light is too strong, the photodiode PD0 receives the incident signal from the external light and also receives part of the background light signal. Excessive background light can easily cause the output of the photodiode PD0 to tend to saturate. However, the photogenerated charge of the incident signal is actually very small in the charge signal actually output by the photodiode PD0. Thus, the voltage of the floating diffusion point FD0 and the second terminal Pixout will drop rapidly after reset, and the reset sampling signal value Vrst will also drop rapidly. When the voltage of the floating diffusion point FD0 drops below the turn-on voltage of the readout circuit, the readout circuit in the image sensor pixel circuit will not be able to conduct normally. Due to this difference, the difference between the image signal, i.e., the reset sampling signal value Vrst and the photoelectronic sampling signal value Vfd, will be greatly reduced, so there is a situation where the charge signal transmitted by the photodiode FD0 cannot be read.

[0051] To address the aforementioned technical problems, this application provides a pixel circuit for a time-of-flight image sensor, wherein the pixel array of the time-of-flight image sensor includes multiple pixel circuits arranged in rows and columns. Please refer to... Figure 2 , Figure 2This application illustrates a time-of-flight image sensor pixel circuit according to an embodiment of the present application. The pixel circuit includes a photosensitive element (PD), a first readout control unit (RC1), a second readout control unit (RC2), and a correction unit (CLB). The photosensitive element (PD) typically has unidirectional conductivity and is used to accumulate charge generated by the photoelectric effect in response to received light, thereby converting the optical signal into an electrical signal. The photosensitive element (PD) can be any photosensitive structure used to convert visible light signals into electrical signals (i.e., photocharge), such as any of a photodiode, grating, or photoconductor. As a preferred embodiment, the photosensitive element (PD) in this embodiment is a photodiode. The photosensitive element (PD) has a first terminal and a second terminal, wherein the second terminal is connected to the first readout control unit (RC1) and the second readout control unit (RC2) respectively, and the first terminal is connected to the ground signal GND. Further, the second terminal of the photosensitive element (PD) can be a cathode, and the first terminal can be an anode.

[0052] The first read control unit RC1 and the second read control unit RC2 are respectively connected to the photosensitive element PD. Both include a floating diffusion point, a reset transistor, a transmission transistor and a signal output module, and are used to read and control the charge signal transmitted by the photosensitive element PD.

[0053] One end of the reset transistor is connected to a high-level voltage signal, and the other end of the reset transistor is connected to the floating diffusion point to reset the voltage of the floating diffusion point according to the reset control signal; the first end of the signal output module is connected to the high-level voltage signal, and the control end of the signal output module is connected to the reset transistor and the floating diffusion point respectively to amplify and output the voltage signal input from the floating diffusion point.

[0054] The following combination Figure 2 The following details the contents shown: The first read control unit RC1 includes a first floating diffusion point FDA, a first reset transistor RSTA, a first transfer transistor TXA, and a first signal output module; one end of the first reset transistor RSTA is connected to a high-level voltage signal VDD, and the other end of the first reset transistor RSTA is connected to the first floating diffusion point FDA; the first end of the first signal output module is connected to the high-level voltage signal VDD, and the control end of the first signal output module is connected to the first reset transistor RSTA and the first floating diffusion point FDA; wherein, the first reset transistor RSTA is used to reset the voltage of the first floating diffusion point FDA according to the reset control signal RSTA, and the first signal output module is used to amplify and output the voltage signal input from the first floating diffusion point FDA; the first transfer transistor TXA is connected to the photosensitive element PD to the first floating diffusion point FDA to ensure that when the transfer signal pga is input, the first transfer transistor TXA is turned on and the charge accumulated by the photosensitive element PDA is transferred to the first floating diffusion point FDA.

[0055] Please continue to refer to Figure 2 The second read control unit RC2 includes a second floating diffusion point FDB, a second reset transistor RSTB, a second transfer transistor TXB, and a second signal output module. One end of the second reset transistor RSTB is connected to a high-level voltage signal VDD, and the other end of the second reset transistor RSTB is connected to the second floating diffusion point FDB. The first end of the second signal output module is connected to the high-level voltage signal VDD, and the control end of the second signal output module is connected to the second reset transistor RSTB and the second floating diffusion point FDB. The second reset transistor RSTB is used to reset the voltage of the second floating diffusion point FDB according to the reset control signal rstb, and the second signal output module is used to amplify and output the voltage signal input from the second floating diffusion point FDB. The second transfer transistor TXB connects the photosensitive element PD to the second floating diffusion point FDB to ensure that when the transfer signal pgb is input, the first transfer transistor TXB is turned on, and the charge accumulated on the photosensitive element PDB is transferred to the second floating diffusion point FDB.

[0056] It is understandable that the first read control unit RC1 and the second read control unit RC2 are mirror-symmetrical about the photosensitive element PD.

[0057] Optionally, the reset transistor can be a P-type transistor; in some embodiments, it can also be an N-type transistor. P-type transistors have low hole mobility, and with equal geometry and absolute operating voltage of a MOS transistor, their transconductance is smaller than that of an N-type transistor. However, P-type transistors generally have a higher absolute threshold voltage, requiring a higher operating voltage. Furthermore, the voltage magnitude and polarity of the power supply are not well-compatible with bipolar transistor logic circuits. In addition, their logic swing is large, the charging and discharging process is long, and the transconductance is small. Therefore, N-type transistors operate faster than P-type transistors.

[0058] Furthermore, the correction unit CLB is connected to the high-level voltage signal VDD, the first read control unit RC1, and the second read control unit RC2, respectively. One end of the correction unit CLB is connected to the high-level voltage signal VDD, and the other end of the correction unit CLB is connected to the first floating diffusion point FDA and the second floating diffusion point FDB. The correction unit CLB is used to reset the first floating diffusion point FDA and the second floating diffusion point FDB to re-integrate when at least one of the potentials of the first floating diffusion point FDA and the second floating diffusion point FDB is lower than a preset voltage during the integration period.

[0059] Specifically, the correction unit CLB includes a first switching transistor CSTA, a second switching transistor CSTB, and a logic decision module. The first terminal of both the first switching transistor CSTA and the first terminal of both the first switching transistor CSTB are connected to a high-level voltage signal VDD; the second terminal of the first switching transistor CSTA is connected to the first floating diffusion point FDA, and its control terminal is connected to the logic decision module; the second terminal of the second switching transistor CSTB is connected to the second floating diffusion point FDB, and its control terminal is also connected to the logic decision module. The first switching transistor CSTA and the second switching transistor CSTB are the same type of transistor; because the first switching transistor CSTA and the second switching transistor CSTB... Both transistors have their control terminals connected to a logic judgment module, and the first switching transistor CSTA and the second switching transistor CSTB are transistors of the same type. Therefore, when the logic judgment module outputs a signal, both transistors can simultaneously turn on or off according to the signal output by the logic judgment module. The logic judgment module consists of at least one logic circuit. When the first switching transistor CSTA receives the control signal output by the logic judgment module, it turns on the high-level voltage signal VDD with the first floating diffusion point FDA, thereby resetting the first floating diffusion point FDA. When the second switching transistor CSTB receives the control signal output by the logic judgment module, it turns on the high-level voltage signal VDD with the second floating diffusion point FDB, thereby resetting the second floating diffusion point FDB. The first terminal of the logic judgment module is connected to the first floating diffusion point FDA and the second floating diffusion point FDB, and the second terminal is connected to the first switching transistor CSTA and the second switching transistor CSTB, respectively. This is used to control the first switching transistor CSTA and the second switching transistor CSTB to simultaneously perform secondary resets on the first floating diffusion point FDA and the second floating diffusion point FDB to re-integrate when at least one of the potentials of the first floating diffusion point FDA and the second floating diffusion point FDB is lower than a preset voltage.

[0060] Understandably, the preset voltage is typically the turn-on voltage of the signal output module. In other words, when at least one of the potentials of the first floating diffusion point FDA and the second floating diffusion point FDB is lower than the turn-on voltage of the signal output module, the logic judgment module controls the first switching transistor CSTA and the second switching transistor CSTB to simultaneously perform a secondary reset on both the first floating diffusion point FDA and the second floating diffusion point FDB for re-integration. Specifically, the fact that at least one of the potentials of the first floating diffusion point FDA and the second floating diffusion point FDB is lower than the turn-on voltage of the signal output module can mean either one of them is lower than the turn-on voltage, or both are lower than the turn-on voltage. This setting ensures that the potentials of both the first floating diffusion point FDA and the second floating diffusion point FDB are higher than the turn-on voltage of the signal output module (i.e., the preset voltage), effectively reducing the interference of excessively strong background light on the pixel circuit of this time-of-flight image sensor. Under this premise, the signal output module can conduct normally and smoothly read out the charge signal transmitted by the photosensitive element.

[0061] The time-of-flight image sensor pixel circuit provided in this application also includes a pixel reset transistor AB. Please refer to [link / reference]. Figure 2 The pixel reset transistor AB is connected to the photosensitive element PD and is used to clear the charge of the photosensitive element PD before it transmits a charge signal. Specifically, the first terminal of the pixel reset transistor AB is connected to the ground signal GND, and the second terminal of the pixel reset transistor AB is connected to the second terminal of the photosensitive element PD. Its control terminal is controlled by the pixel reset signal ab. Before the photosensitive element PD transmits a charge signal, the pixel reset signal ab controls the pixel reset transistor AB to conduct. At this time, the second terminal of the photosensitive element PD is connected to the ground signal GND through the reset transistor AB, so that the photosensitive element PD clears the excess charge through the ground signal GND before reading the charge signal, thereby completing the voltage charge clearing operation of the photosensitive element PD.

[0062] Furthermore, the signal output module includes a source follower transistor and a row select transistor. The first terminal of the source follower transistor is connected to a high-level voltage signal, and its control terminal is connected to the floating diffusion point. The second terminal can be connected to the corresponding output terminal, or it can be connected in series with the row select transistor and then connected to the corresponding output terminal through the row select transistor. At the same time, the control terminal of the source follower transistor is also connected to the second terminal of the reset transistor and the correction unit CLB. In some embodiments, connecting the source follower transistor to the row select transistor can enable the source follower transistor to import the charge signal output from the first or second floating diffusion point, amplify it, and then output it to the corresponding output terminal through the row select transistor.

[0063] The following combination Figure 2 The following details are provided:

[0064] The first signal output module includes a first source follower transistor (SFA) and a first row select transistor (RSA). The first terminal of the SFA is connected to a high-level voltage signal VDD. The second terminal can be directly connected to the corresponding output terminal or connected to the first terminal of the RSA, thus enabling a serial connection between the SFA and RSA. The control terminal of the SFA is connected to the first floating diffusion point FDA. Simultaneously, the SFA is also connected to the second terminal of the first reset transistor RSTA and the correction unit CLB, i.e., the second terminal of the first switching transistor CSTA and the logic judgment module. The second terminal of the RSA is connected to the corresponding output terminal. Therefore, the SFA can connect the high-level voltage signal VDD to the first row select transistor RSA. The second signal output module includes a second source follower transistor (SFB) and a second row select transistor (RSB). The first terminal of the SFB is connected to a high-level voltage signal VDD. The second terminal can be directly connected to the corresponding output terminal or connected to the first terminal of the RSB, thus enabling a serial connection between the SFB and RSB. The control terminal of the SFB is connected to the first floating diffusion point (FDB). Simultaneously, the SFB is also connected to the second terminal of the first reset transistor (RSTB) and the correction unit (CLB), i.e., the second terminal of the first switching transistor (CSTB) and the logic judgment module. The second terminal of the RSB is connected to the corresponding output terminal; therefore, the SFB can connect the high-level voltage signal VDD to the RSB.

[0065] It is worth noting that, Figure 2This is merely a typical example of the time-of-flight image sensor pixel circuit provided in this application. In practice, the signal output module may also include only source follower transistors, i.e., only the first source follower transistor SFA and the second source follower transistor SFB. The source follower transistors can amplify and directly extract the charge signal transmitted by the floating diffusion point. Similarly, other amplification devices with different gains can be used instead. Figure 2 The row selection transistor shown can be, for example, a junction field-effect transistor or a differential amplifier, as long as it can amplify and output the voltage signal input from the floating diffusion point. This application does not impose specific limitations on this.

[0066] In the time-of-flight image sensor pixel circuit provided in this application, the logic judgment module is composed of at least one logic circuit, which is used to output a control signal to turn on the first switching transistor CSTA and the second switching transistor CSTB to reset the first floating diffusion point FDA and the second floating diffusion point FDB when at least one of the potentials of the first floating diffusion point FDA and the second floating diffusion point FDB is lower than a preset voltage. Figure 2 This diagram illustrates one type of logic decision module, comprising two inverters and one NOR gate circuit, which will be described in detail below: Figure 2 In the pixel circuit of the time-of-flight image sensor shown, the logic judgment module includes a first inverter INVA, a second inverter INVB, and a NOR gate circuit. The first inverter INVA is connected to the first floating diffusion point FDA, the second inverter INVB is connected to the second floating diffusion point FDB, the first inverter INVA and the second inverter INVB are connected in parallel to the input terminal of the NOR gate circuit NOR, and the output terminal of the NOR gate circuit NOR is simultaneously connected to the first switching transistor CSTA and the second switching transistor CSTB.

[0067] Furthermore, in Figure 2In the illustrated time-of-flight image sensor pixel circuit, the first switching transistor CSTA, the second switching transistor CSTB, the first reset transistor RSTA, and the second reset transistor RSTB are P-type transistors. Therefore, when the potential of at least one of the first floating diffusion point FDA and the second floating diffusion point FDB is lower than the turn-on voltage of the signal output module, the logic judgment module can detect whether either the first floating diffusion point FDA or the second floating diffusion point FDB is lower than the turn-on voltage of the signal output module when it receives the voltages of the first floating diffusion point FDA and the second floating diffusion point FDB. If such a situation exists, the first switching transistor CSTA and the second switching transistor CSTB are turned on, and the high-level voltage signal VDD simultaneously resets the first floating diffusion point FDA and the second floating diffusion point FDB through the first switching transistor CSTA and the second switching transistor CSTB. Specifically, this can be categorized into the following cases:

[0068] In the first scenario, when the potentials of both the first floating diffusion point FDA and the second floating diffusion point FDB are higher than the turn-on voltage of the signal output module, both the first floating diffusion point FDA and the second floating diffusion point FDB output high-level signals. The high-level signal output by the first floating diffusion point FDA is converted into a low-level signal input NOR gate circuit through the first inverter INVA, and the high-level signal output by the second floating diffusion point FDB is converted into a low-level signal input NOR gate circuit through the second inverter INVB. Since the voltage signals received by the NOR gate circuit are all low-level signals, a high-level signal is output to the first switching transistor CSTA and the second switching transistor CSTB. As mentioned above, both the first switching transistor CSTA and the second switching transistor CSTB are P-type transistors. P-type transistors conduct when they receive a low-level signal at the control terminal. Therefore, when both the control terminals of the first switching transistor CSTA and the second switching transistor CSTB receive a high-level signal, both the first switching transistor CSTA and the second switching transistor CSTB remain in the off state, and the potentials of the first floating diffusion point FDA and the second floating diffusion point FDB will not be reset a second time.

[0069] In the second scenario, when either the potential of the first floating diffusion point FDA or the potential of the second floating diffusion point FDB is lower than the turn-on voltage of the signal output module—for example, when the potential of the first floating diffusion point FDA is lower than the turn-on voltage of the signal output module—the first floating diffusion point FDA outputs a low-level signal, and the second floating diffusion point FDB outputs a high-level signal. The low-level signal output by the first floating diffusion point FDA is converted into a high-level signal input NOR gate by the first inverter INVA, and the high-level signal output by the second floating diffusion point FDB is converted into a low-level signal input NOR gate by the second inverter INVB. Since the voltage signal received by the NOR gate contains both low and high levels... If a signal is received, a low-level signal is output to the first switching transistor CSTA and the second switching transistor CSTB. As mentioned above, both the first switching transistor CSTA and the second switching transistor CSTB are P-type transistors. P-type transistors conduct when they receive a low-level signal at the control terminal. Therefore, when both the control terminals of the first switching transistor CSTA and the second switching transistor CSTB receive a low-level signal, both the first switching transistor CSTA and the second switching transistor CSTB are in the conducting state. The high-level voltage signal VDD is written to the first floating diffusion point FDA and the second floating diffusion point FDB through the first switching transistor CSTA and the second switching transistor CSTB, respectively, to simultaneously perform a secondary reset on the first floating diffusion point FDA and the second floating diffusion point FDB.

[0070] In the third scenario, when the potentials of both the first floating diffusion point FDA and the second floating diffusion point FDB are lower than the turn-on voltage of the signal output module, both the first floating diffusion point FDA and the second floating diffusion point FDB output low-level signals. The low-level signal output by the first floating diffusion point FDA is converted into a high-level signal input NOR gate by the first inverter INVA, and the low-level signal output by the second floating diffusion point FDB is converted into a high-level signal input NOR gate by the second inverter INVB. Since the voltage signals received by the NOR gate are all high-level signals, a low-level signal is output to the first switching transistor CSTA and the second switching transistor CSTB. As mentioned above, the first switching transistor CSTA and the second switching transistor CSTB... Both are P-type transistors. P-type transistors turn on when they receive a low-level signal at the control terminal. Therefore, when the control terminals of the first switching transistor CSTA and the second switching transistor CSTB both receive low-level signals, the first switching transistor CSTA and the second switching transistor CSTB are both in the on state. The high-level voltage signal VDD is written to the first floating diffusion point FDA and the second floating diffusion point FDB through the first switching transistor CSTA and the second switching transistor CSTB, respectively, to simultaneously perform a secondary reset on the first floating diffusion point FDA and the second floating diffusion point FDB.

[0071] In the time-of-flight image sensor pixel circuit provided in this application, such as Figure 3 As shown, the logic judgment module may also include an inverter and a NAND gate. Specifically, the logic judgment module includes an inverter INV and a NAND gate, wherein the input terminal of the NAND gate is connected to the first floating diffusion point FDA and the second floating diffusion point FDB, and the output terminal of the NAND gate is connected to the input terminal of the inverter INV. The output terminal of the inverter INV is simultaneously connected to the first switching transistor CSTA and the second switching transistor CSTB.

[0072] and Figure 2 The implementation shown is the same, in Figure 3 In the illustrated time-of-flight image sensor pixel circuit, the first switching transistor CSTA, the second switching transistor CSTB, the first reset transistor RSTA, and the second reset transistor RSTB are P-type transistors. Therefore, when the potential of at least one of the first floating diffusion point FDA and the second floating diffusion point FDB is lower than the turn-on voltage of the signal output module, the logic judgment module can detect whether either the first floating diffusion point FDA or the second floating diffusion point FDB is lower than the turn-on voltage of the signal output module upon receiving the voltages of the first floating diffusion point FDA and the second floating diffusion point FDB. If such a situation exists, the first switching transistor CSTA and the second switching transistor CSTB are turned on, and the high-level voltage signal VDD simultaneously resets the first floating diffusion point FDA and the second floating diffusion point FDB through the first switching transistor CSTA and the second switching transistor CSTB. The specific details are as follows:

[0073] In the first scenario, when the potentials of both the first floating diffusion point FDA and the second floating diffusion point FDB are higher than the turn-on voltage of the signal output module, both the first floating diffusion point FDA and the second floating diffusion point FDB output high-level signals to the NAND gate circuit. Since the voltage signals received by the NAND gate circuit are all high-level signals, it outputs low-level signals to the inverter INV. The inverter INV converts the low-level signals output by the NAND gate circuit into high-level signals and outputs them to the first switching transistor CSTA and the second switching transistor CSTB. As mentioned above, both the first switching transistor CSTA and the second switching transistor CSTB are P-type transistors. P-type transistors conduct when they receive a low-level signal at the control terminal. Therefore, when both the control terminals of the first switching transistor CSTA and the second switching transistor CSTB receive high-level signals, both the first switching transistor CSTA and the second switching transistor CSTB remain in the off state, and the potentials of the first floating diffusion point FDA and the second floating diffusion point FDB will not be reset a second time.

[0074] In the second scenario, when either the potential of the first floating diffusion point FDA or the potential of the second floating diffusion point FDB is lower than the turn-on voltage of the signal output module—for example, when the potential of the first floating diffusion point FDA is lower than the turn-on voltage of the signal output module—the first floating diffusion point FDA outputs a low-level signal to the NAND gate circuit, and the second floating diffusion point FDB outputs a high-level signal to the NAND gate circuit. Since one of the voltage signals received by the NAND gate circuit is a low-level signal, it outputs a high-level signal to the inverter INV. The inverter INV converts the high-level signal output by the NAND gate circuit into a low-level signal and outputs it to the first switching transistor CSTA and the second switching transistor CSTB; as before. As described in the text, both the first switching transistor CSTA and the second switching transistor CSTB are P-type transistors. P-type transistors conduct when they receive a low-level signal at the control terminal. Therefore, when both the control terminals of the first switching transistor CSTA and the second switching transistor CSTB receive a low-level signal, both the first switching transistor CSTA and the second switching transistor CSTB are in the conducting state. The high-level voltage signal VDD is written to the first floating diffusion point FDA and the second floating diffusion point FDB through the first switching transistor CSTA and the second switching transistor CSTB, respectively, to simultaneously perform a secondary reset on the first floating diffusion point FDA and the second floating diffusion point FDB.

[0075] In the third scenario, when the potentials of both the first floating diffusion point FDA and the second floating diffusion point FDB are lower than the turn-on voltage of the signal output module, both the first floating diffusion point FDA and the second floating diffusion point FDB output low-level signals to the NAND gate circuit. Since the voltage signals received by the NAND gate circuit are all low-level signals, it outputs a high-level signal to the inverter INV. The inverter INV converts the high-level signal output by the NAND gate circuit into a low-level signal and outputs it to the first switching transistor CSTA and the second switching transistor CSTB. As mentioned earlier, the first switching transistor CSTA and the second switching transistor CSTB are both P-type transistors. P-type transistors conduct when they receive a low-level signal at the control terminal. Therefore, when the first switching transistor CSTA... When both the control terminal of the first switch transistor CSTA and the control terminal of the second switch transistor CSTB receive a low-level signal, both the first switch transistor CSTA and the second switch transistor CSTB are in the on state. The high-level voltage signal VDD is written to the first floating diffusion point FDA and the second floating diffusion point FDB through the first switch transistor CSTA and the second switch transistor CSTB, respectively, to simultaneously perform a secondary reset on the first floating diffusion point FDA and the second floating diffusion point FDB.

[0076] Therefore, without changing Figure 2 Assuming that the first switching transistor CSTA and the second switching transistor CSTB shown are P-type transistors, the number of devices in the logic judgment module can be reduced by changing its internal structure and replacing it with an inverter and a NAND gate circuit, thereby simplifying the internal structure of the logic judgment module.

[0077] In the time-of-flight image sensor pixel circuit provided in this application, such as Figure 4 As shown, the logic judgment module may include only one AND gate circuit. Specifically, the logic judgment module includes an AND gate circuit, wherein the input terminal of the AND gate circuit is connected to the first floating diffusion point FDA and the second floating diffusion point FDB, and the output terminal of the AND gate circuit is simultaneously connected to the first switching transistor CSTA and the second switching transistor CSTB.

[0078] In the time-of-flight image sensor pixel circuit provided in this embodiment, the first switching transistor CSTA, the second switching transistor CSTB, the first reset transistor RSTA, and the second reset transistor RSTB are P-type transistors. Further, Figure 4 The specific scenarios in which the time-of-flight image sensor pixel circuit controls the first reset transistor RSTA and the second reset transistor RSTB to perform a secondary reset can be categorized as follows:

[0079] In the first scenario, when the potentials of both the first floating diffusion point FDA and the second floating diffusion point FDB are higher than the turn-on voltage of the signal output module, both the first floating diffusion point FDA and the second floating diffusion point FDB output high-level signals to the AND gate circuit. Since the voltage signals received by the AND gate circuit are all high-level signals, it outputs high-level signals to the first switching transistor CSTA and the second switching transistor CSTB. As mentioned above, both the first switching transistor CSTA and the second switching transistor CSTB are P-type transistors. P-type transistors conduct when they receive a low-level signal at the control terminal. Therefore, when both the control terminals of the first switching transistor CSTA and the second switching transistor CSTB receive high-level signals, both the first switching transistor CSTA and the second switching transistor CSTB remain in the off state, and the potentials of the first floating diffusion point FDA and the second floating diffusion point FDB will not be reset a second time.

[0080] In the second scenario, when either the potential of the first floating diffusion point FDA or the potential of the second floating diffusion point FDB is lower than the turn-on voltage of the signal output module—for example, when the potential of the first floating diffusion point FDA is lower than the turn-on voltage of the signal output module—the first floating diffusion point FDA outputs a low-level signal to the AND gate circuit, and the second floating diffusion point FDB outputs a high-level signal to the AND gate circuit. Since one of the voltage signals received by the AND gate circuit is a low-level signal, it outputs a low-level signal to the first switching transistor CSTA and the second switching transistor CSTB. Both the first switching transistor CSTA and the second switching transistor CSTB are in the on state, and the high-level voltage signal VDD simultaneously performs a secondary reset on the first floating diffusion point FDA and the second floating diffusion point FDB through the first switching transistor CSTA and the second switching transistor CSTB, respectively.

[0081] In the third scenario, when the potentials of both the first floating diffusion point FDA and the second floating diffusion point FDB are lower than the turn-on voltage of the signal output module, both the first floating diffusion point FDA and the second floating diffusion point FDB output low-level signals to the AND gate circuit. Since the voltage signals received by the AND gate circuit are all low-level signals, it outputs low-level signals to the first switching transistor CSTA and the second switching transistor CSTB. Both the first switching transistor CSTA and the second switching transistor CSTB are in the on state, and the high-level voltage signal VDD performs a secondary reset on the first floating diffusion point FDA and the second floating diffusion point FDB simultaneously through the first switching transistor CSTA and the second switching transistor CSTB.

[0082] Therefore, without changing Figure 2 , Figure 3Assuming that the first switching transistor CSTA and the second switching transistor CSTB shown are P-type transistors, by changing the internal structure of the logic judgment module and simplifying it to include only one AND gate circuit, the number of devices in the logic judgment module can be reduced, thereby simplifying the internal structure of the logic judgment module.

[0083] Figure 5 The illustration shows another logic judgment module configuration provided by the embodiment of this application, including two inverters and an OR gate circuit, which is described in detail below: The logic judgment module includes a first inverter INVA, a second inverter INVB and an OR gate circuit, wherein the first inverter INVA is connected to the first floating diffusion point FDA, the second inverter INVB is connected to the second floating diffusion point FDB, the first inverter INVA and the second inverter INVB are connected in parallel to the input terminal of the OR gate circuit OR, and the output terminal of the OR gate circuit OR is simultaneously connected to the first switching transistor CSTA and the second switching transistor CSTB.

[0084] Furthermore, in Figure 5 In the illustrated time-of-flight image sensor pixel circuit, the switching transistors and reset transistors can be different types of transistors or the same type of transistor; specifically, the first switching transistor CSTA and the second switching transistor CSTB are N-type transistors, and the first reset transistor RSTA and the second reset transistor RSTB can be either P-type transistors or N-type transistors. As an example, the first switching transistor CSTA and the second switching transistor CSTB are N-type transistors, and the first reset transistor RSTA and the second reset transistor RSTB can be either P-type transistors. Figure 5 The specific scenarios in which the time-of-flight image sensor pixel circuit controls the first reset transistor RSTA and the second reset transistor RSTB to perform a secondary reset can be categorized as follows:

[0085] In the first scenario, when the potentials of both the first floating diffusion point FDA and the second floating diffusion point FDB are higher than the turn-on voltage of the signal output module, both the first floating diffusion point FDA and the second floating diffusion point FDB output high-level signals. The high-level signal output by the first floating diffusion point FDA is converted into a low-level signal input OR gate through the first inverter IVA, and the high-level signal output by the second floating diffusion point FDB is converted into a low-level signal input OR gate through the second inverter IVB. Since the voltage signals received by the OR gate are all low-level signals, a low-level signal is output to the first switching transistor CSTA and the second switching transistor CSTB. As mentioned above, the first switching transistor CSTA and the second switching transistor CSTB are both N-type transistors. N-type transistors conduct when they receive a high-level signal at the control terminal. Therefore, when the control terminals of the first switching transistor CSTA and the second switching transistor CSTB both receive low-level signals, the first switching transistor CSTA and the second switching transistor CSTB remain in the off state, and the potentials of the first floating diffusion point FDA and the second floating diffusion point FDB will not be reset a second time.

[0086] In the second scenario, when either the potential of the first floating diffusion point FDA or the potential of the second floating diffusion point FDB is lower than the turn-on voltage of the signal output module—for example, when the potential of the first floating diffusion point FDA is lower than the turn-on voltage of the signal output module—the first floating diffusion point FDA outputs a low-level signal, and the second floating diffusion point FDB outputs a high-level signal. The low-level signal output by the first floating diffusion point FDA is converted into a high-level signal input OR by the first inverter INVA, and the high-level signal output by the second floating diffusion point FDB is converted into a low-level signal input OR by the second inverter INVB. Since the voltage signal received by the OR gate contains both low-level and high-level signals, a high-level signal is output to the first switching transistor CSTA and the second switching transistor CSTB. As mentioned earlier, both the first switching transistor CSTA and the second switching transistor CSTB are N-type transistors. N-type transistors conduct when they receive a high-level signal at the control terminal. Therefore, when the control terminal of the first switching transistor CSTA and the second switching transistor CSTB... When both control terminals receive a high-level signal, the first switching transistor CSTA and the second switching transistor CSTB are both in the conducting state. The high-level voltage signal VDD is written to the first floating diffusion point FDA and the second floating diffusion point FDB through the first switching transistor CSTA and the second switching transistor CSTB, respectively, and the first floating diffusion point FDA and the second floating diffusion point FDB are simultaneously reset twice.

[0087] In the third scenario, when the potential of the first floating diffusion point FDA is different from that of the second floating diffusion point FDB... When the potentials of both floating diffusion points are lower than the turn-on voltage of the signal output module, both the first floating diffusion point FDA and the second floating diffusion point FDB output low-level signals. The low-level signal output by the first floating diffusion point FDA is converted into a high-level signal input OR by the first inverter INVA, and the low-level signal output by the second floating diffusion point FDB is converted into a high-level signal input OR by the second inverter INVB. Since the voltage signals received by the OR gate are all high-level signals, a high-level signal is output to the first switching transistor CSTA and the second switching transistor CSTB. As mentioned above, the first switching transistor CSTA and the second switching transistor CSTB are both N-type transistors. N-type transistors conduct when they receive a high-level signal at the control terminal. Therefore, when the control terminals of the first switching transistor CSTA and the second switching transistor CSTB both receive a high-level signal, the first switching transistor CSTA and the second switching transistor CSTB are both in the conducting state. The high-level voltage signal VDD is written to the first floating diffusion point FDA and the second floating diffusion point FDB through the first switching transistor CSTA and the second switching transistor CSTB, respectively, to simultaneously perform a secondary reset on the first floating diffusion point FDA and the second floating diffusion point FDB.

[0088] It is understood that the P-type transistor used in the embodiments of this application can unequivocally refer to PMOS; and the N-type transistor used in the embodiments of this application can unequivocally refer to NMOS. Furthermore, due to the low hole mobility of P-type transistors, their transconductance is smaller than that of N-type transistors when the geometric dimensions and absolute values ​​of the operating voltage are equal. In addition, the absolute value of the threshold voltage of P-type transistors is generally higher, requiring a higher operating voltage, and the voltage magnitude and polarity of the power supply are not well compatible with bipolar transistor logic circuits. Therefore, PMOS logic swing is large, the charging and discharging process is long, and coupled with its low transconductance, its operating speed is lower than that of NMOS. Figure 5 In the time-of-flight image sensor pixel circuit shown, the first switching transistor CSTA and the second switching transistor CSTB in the logic judgment module are replaced with N-type transistors instead of P-type transistors in the aforementioned embodiment. This is beneficial for quickly responding and simultaneously outputting a high-level voltage signal VDD to the first floating diffusion point FDA and the second floating diffusion point FDB when both output low-level signal voltages are low, thereby performing a secondary reset and improving the operating speed of the time-of-flight image sensor pixel circuit provided in this application.

[0089] In the time-of-flight image sensor pixel circuit provided in this application, such as Figure 6As shown, the logic judgment module may include only one NAND gate circuit. Specifically, the logic judgment module includes only a NAND gate circuit NAND, wherein the input terminal of the NAND gate circuit NAND is connected to the first floating diffusion point FDA and the second floating diffusion point FDB, and the output terminal of the NAND gate circuit NAND is simultaneously connected to the first switching transistor CSTA and the second switching transistor CSTB.

[0090] In the time-of-flight image sensor pixel circuit provided in this embodiment, the switching transistors and reset transistors can be different types of transistors or the same type of transistor; specifically, the first switching transistor CSTA and the second switching transistor CSTB are N-type transistors, and the first reset transistor RSTA and the second reset transistor RSTB can be either P-type transistors or N-type transistors. As an example, the first switching transistor CSTA and the second switching transistor CSTB are N-type transistors, and the first reset transistor RSTA and the second reset transistor RSTB can be either P-type transistors. Further, Figure 6 The specific scenarios in which the time-of-flight image sensor pixel circuit controls the first reset transistor RSTA and the second reset transistor RSTB to perform a secondary reset can be categorized as follows:

[0091] In the first scenario, when the potentials of both the first floating diffusion point FDA and the second floating diffusion point FDB are higher than the turn-on voltage of the signal output module, both the first floating diffusion point FDA and the second floating diffusion point FDB output high-level signals to the NAND gate circuit. Since the voltage signals received by the NAND gate circuit are all high-level signals, it outputs low-level signals to the first switching transistor CSTA and the second switching transistor CSTB. As mentioned above, both the first switching transistor CSTA and the second switching transistor CSTB are N-type transistors. N-type transistors conduct when they receive a low-level signal at the control terminal. Therefore, when both the control terminals of the first switching transistor CSTA and the second switching transistor CSTB receive high-level signals, both the first switching transistor CSTA and the second switching transistor CSTB remain in the off state, and the potentials of the first floating diffusion point FDA and the second floating diffusion point FDB will not be reset a second time.

[0092] In the second scenario, when either the potential of the first floating diffusion point FDA or the potential of the second floating diffusion point FDB is lower than the turn-on voltage of the signal output module—for example, when the potential of the first floating diffusion point FDA is lower than the turn-on voltage of the signal output module—the first floating diffusion point FDA outputs a low-level signal to the NAND gate circuit, and the second floating diffusion point FDB outputs a high-level signal to the NAND gate circuit. Since one of the voltage signals received by the NAND gate circuit is a low-level signal, it outputs a high-level signal to the first switching transistor CSTA and the second switching transistor CSTB. Both the first switching transistor CSTA and the second switching transistor CSTB are in the on state, and the high-level voltage signal VDD simultaneously performs a secondary reset on the first floating diffusion point FDA and the second floating diffusion point FDB through the first switching transistor CSTA and the second switching transistor CSTB, respectively.

[0093] In the third scenario, when the potentials of both the first floating diffusion point FDA and the second floating diffusion point FDB are lower than the turn-on voltage of the signal output module, both the first floating diffusion point FDA and the second floating diffusion point FDB output low-level signals to the NAND gate circuit. Since the voltage signals received by the NAND gate circuit are all low-level signals, it outputs high-level signals to the first switching transistor CSTA and the second switching transistor CSTB. Both the first switching transistor CSTA and the second switching transistor CSTB are in the on state, and the high-level voltage signal VDD performs a secondary reset on the first floating diffusion point FDA and the second floating diffusion point FDB simultaneously through the first switching transistor CSTA and the second switching transistor CSTB.

[0094] Therefore, without changing Figure 5 Given that the first switching transistor CSTA and the second switching transistor CSTB shown are N-type transistors, on the one hand, by changing the internal structure of the logic judgment module and simplifying it to include only one NAND gate, the number of devices in the logic judgment module can be reduced, thereby simplifying the internal structure of the logic judgment module. On the other hand, when both the first floating diffusion point FDA and the second floating diffusion point FDB output low-level signal voltages, it can respond faster and simultaneously output a high-level voltage signal VDD to the first floating diffusion point FDA and the second floating diffusion point FDB for secondary reset, thereby improving the operating speed of the time-of-flight image sensor pixel circuit provided in this application.

[0095] As a preferred implementation, to further improve the operating speed of the pixel circuit of the time-of-flight image sensor, it is also possible to... Figure 6 All transistors in the revealed logic decision circuit (i.e., NAND gate circuit) have been replaced with N-type transistors. Please also refer to... Figure 7 This application also provides a time-of-flight image sensor pixel circuit, wherein all transistors constituting the logic judgment circuit within the logic judgment module are N-type transistors. Specifically, as shown in the example... Figure 7 As shown, the logic judgment circuit (i.e., NAND gate circuit) is composed of at least one control transistor group and a bias transistor connected in series. The control transistor group includes a first logic control transistor LGTA with its control terminal connected to a first floating diffusion point FDA, and a second logic control transistor LGTB with its control terminal connected to a second floating diffusion point FDB. The first logic control transistor LGTA and the second logic control transistor LGTB are connected in series, together forming a control transistor group. The first terminal of the first logic control transistor LGTA is connected to the ground signal GND, and the second terminal of the first logic control transistor LGTA is connected to the first terminal of the second logic control transistor LGTB. The second terminal of the second logic control transistor LGTB is simultaneously connected to the control terminals of the first switching transistor CSTA and the second switching transistor CSTB. The aforementioned logic judgment circuit also includes a bias transistor LGTC connected in series with the control transistor group. The control terminal of the bias transistor LGTC is connected to the bias voltage signal Vbias, the first terminal of the control terminal of the bias transistor LGTC is connected to a high-level voltage signal VDD, and the second terminal of the control terminal of the bias transistor LGTC is simultaneously connected to the control terminals of the first switching transistor CSTA and the second switching transistor CSTB. It is understandable that the number of control transistor groups is at least one, and can be multiple. It is known that regardless of the number of control transistor groups, the logic control transistors included therein are all paired and are all connected in series.

[0096] Furthermore, the first logic control transistor LGTA, the second logic control transistor LGTB, and the bias transistor LGTC are all N-type transistors. Since the bias transistor LGTC is an N-type transistor, to ensure its conduction, the bias voltage signal Vbias connected to its control terminal should be a preset positive bias signal. Accordingly, Figure 7 The specific scenarios in which the time-of-flight image sensor pixel circuit controls the first reset transistor RSTA and the second reset transistor RSTB to perform a secondary reset can be categorized as follows:

[0097] In the first scenario, when the potentials of both the first floating diffusion point FDA and the second floating diffusion point FDB are higher than the turn-on voltage of the signal output module, both the first floating diffusion point FDA and the second floating diffusion point FDB output high-level signals. The high-level signal output by the first floating diffusion point FDA is input to the first logic control transistor LGTA, and the high-level signal output by the second floating diffusion point FDB is input to the second logic control transistor LGTB. When both the first logic control transistor LGTA and the second logic control transistor LGTB receive high-level signals, the control terminals of the first switching transistor CSTA and the second switching transistor CSTB receive low-level signals transmitted by the ground signal GND. Since both the first switching transistor CSTA and the second switching transistor CSTB are N-type transistors, they only conduct under the condition of high-level signal transmission. At this time, the first switching transistor CSTA and the second switching transistor CSTB receive low-level signals transmitted by the ground signal GND, so the first switching transistor CSTA and the second switching transistor CSTB do not conduct and do not perform a secondary reset on the first floating diffusion point FDA and the second floating diffusion point FDB.

[0098] In the second scenario, when either the potential of the first floating diffusion point FDA or the potential of the second floating diffusion point FDB is lower than the turn-on voltage of the signal output module—for example, when the potential of the first floating diffusion point FDA is lower than the turn-on voltage of the signal output module—the first floating diffusion point FDA outputs a low-level signal to the first logic control transistor LGTA. Since the first logic control transistor LGTA is an N-type transistor, it will not conduct upon receiving a low-level signal. Consequently, because the first logic control transistor LGTA and the second logic control transistor LGTB are connected in series, the low-level signal transmitted by the ground signal GND cannot be output. Simultaneously, the forward bias signal preset at the control terminal of the bias transistor LGTC turns on the bias transistor LGTC. The high-level signal transmitted by the high-level voltage signal VDD is transmitted through the bias transistor LGTC to the control terminals of the first switching transistor CSTA and the second switching transistor CSTB. Both the first switching transistor CSTA and the second switching transistor CSTB are in the conducting state, and the high-level voltage signal VDD performs a secondary reset on the first floating diffusion point FDA and the second floating diffusion point FDB simultaneously through the first switching transistor CSTA and the second switching transistor CSTB, respectively.

[0099] In the third scenario, when the potentials of both the first floating diffusion point FDA and the second floating diffusion point FDB are lower than the turn-on voltage of the signal output module, the first floating diffusion point FDA outputs a low-level signal to the first logic control transistor LGTA, and the second floating diffusion point FDB outputs a low-level signal to the second logic control transistor LGTB. Since both the first logic control transistor LGTA and the second logic control transistor LGTB are N-type transistors, they will not conduct upon receiving a low-level signal, and since they are connected in series, they cannot output the low-level signal transmitted by the ground signal GND. At the same time, the forward bias signal preset at the control terminal of the bias transistor LGTC turns on the bias transistor LGTC, and the high-level signal transmitted by the high-level voltage signal VDD is transmitted through the bias transistor LGTC to the control terminals of the first switching transistor CSTA and the second switching transistor CSTB, thus performing a secondary reset on both the first floating diffusion point FDA and the second floating diffusion point FDB.

[0100] The above settings not only simplify the internal structure of the logic judgment module, but also further improve the operating speed of the time-of-flight image sensor pixel circuit provided in this application.

[0101] As an alternative implementation method, such as Figure 8As shown, the time-of-flight image sensor pixel circuit provided in this application also includes a dual-conversion gain control module connected between the reset transistor and the floating diffusion point. The dual-conversion gain control module includes at least one dual-conversion gain control transistor and a capacitor. The dual-conversion gain control module is used to switch between a low conversion gain mode and a high conversion gain mode, thereby controlling the exposure dynamic range of the time-of-flight image sensor. Specifically, the dual-conversion gain control module includes a first dual-conversion gain control module and a second dual-conversion gain control module; the first dual-conversion gain control module includes a first dual-conversion gain control transistor DCGA and a capacitor Cdcga. The first dual-conversion gain control transistor DCGA is serially connected between the first reset transistor RSTA and the first floating diffusion point FDA, and the lower plate of the capacitor Cdcga is connected between the first dual-conversion gain control transistor DCGA and the first reset transistor RSTA; the second dual-conversion gain control module includes a second dual-conversion gain control transistor DCGB and a capacitor Cdcgb. The gain control transistor DCGB is serially connected between the first reset transistor RSTB and the first floating diffusion point FDB. The lower plate of capacitor Cdcgb is connected between the first dual-conversion gain control transistor DCGB and the first reset transistor RSTB. Furthermore, the upper plates of capacitors Cdcga and Cdcgb are connected to voltage VCA, which can be a high-level voltage signal VDD, a ground signal GND, or other specified voltage value. Capacitors Cdcga and Cdcgb can be device capacitors or parasitic capacitances of the connection point between the reset transistor and the dual-conversion gain transistor to ground. The above settings allow for increased conversion gain with a smaller integrating capacitor under low illumination conditions, thereby improving sensitivity. Under high illumination conditions, a larger integrating capacitor increases stored charge, reducing conversion gain and improving dynamic range. Furthermore, by ensuring that the logic judgment module performs a secondary reset of the first floating diffusion point FDA or the second floating diffusion point FDB when the potential of the first floating diffusion point FDA or the second floating diffusion point FDB is lower than the turn-on voltage of the readout circuit, the dynamic range is controlled to further reduce the interference of excessive background light on the pixel circuit of this time-of-flight image sensor. This ensures that the signal output module can conduct normally and smoothly read out the charge signal transmitted by the photosensitive element.

[0102] Optionally, in the time-of-flight image sensor pixel circuit provided in this application, both the first readout control unit and the second readout control unit include a storage capacitor. The first plate of the storage capacitor is connected to the floating diffusion point, and the second plate is connected to the ground signal. The storage capacitor is used to receive and store the charge generated by the photosensitive element after the floating diffusion point of the correction unit is corrected to a higher potential when it is lower than a preset voltage. Specifically, the first readout control unit RC1 also includes a storage capacitor CA, the first plate of which is connected to the floating diffusion point FDA, and the second plate is connected to the ground signal GND; the second readout control unit RC2 also includes a storage capacitor CB, the first plate of which is connected to the floating diffusion point FDB, and the second plate is connected to the ground signal GND; both the first storage capacitor C1 and the second storage capacitor C2 are used to receive and store the charge generated by the photosensitive element PD after the correction unit CLB corrects and resets the potentials of the first floating diffusion point FDA and the second floating diffusion point FDB to a higher potential when they are lower than a preset voltage (usually the turn-on voltage of the readout circuit).

[0103] Please refer to Figure 9 , Figure 9 Another time-of-flight image sensor pixel circuit of this application is shown, which further includes a third readout control unit RC3 and a fourth readout control unit RC4; the second end of the photosensitive element is connected to the third readout control unit RC3 and the fourth readout control unit RC4 respectively.

[0104] The third read control unit RC3 and the fourth read control unit RC4 are respectively connected to the photosensitive element PD. They both include a floating diffusion point, a reset transistor, a transmission transistor and a signal output module, and are used to read and control the charge signal transmitted by the photosensitive element PD.

[0105] The following combination Figure 9The following details the contents shown: The third read control unit RC3 includes a third floating diffusion point FDC, a third reset transistor RSTC, a third transfer transistor TXC, and a third signal output module; one end of the third reset transistor RSTC is connected to a high-level voltage signal VDD, and the other end of the third reset transistor RSTC is connected to the third floating diffusion point FDC; the first end of the third signal output module is connected to the high-level voltage signal VDD, and the control end of the third signal output module is connected to the third reset transistor RSTC and the third floating diffusion point FDC; wherein, the third reset transistor RSTC is used to reset the voltage of the third floating diffusion point FDC according to the reset control signal rstc, and the third signal output module is used to amplify and output the voltage signal input from the third floating diffusion point FDC; the third transfer transistor TXC is connected to the photosensitive element PD to the third floating diffusion point FDC to ensure that when the transfer signal pgc is input, the third transfer transistor TXC is turned on to transfer the charge accumulated by the photosensitive element PDA to the third floating diffusion point FDC.

[0106] Please continue to refer to Figure 9 The fourth readout control unit RC4 includes a fourth floating diffusion point FDD, a fourth reset transistor RSTD, a fourth transfer transistor TXD, and a fourth signal output module. One end of the fourth reset transistor RSTD is connected to a high-level voltage signal VDD, and the other end of the fourth reset transistor RSTD is connected to the fourth floating diffusion point FDD. The first end of the fourth signal output module is connected to the high-level voltage signal VDD, and the control end of the second signal output module is connected to the fourth reset transistor RSTD and the fourth floating diffusion point FDD. The fourth reset transistor RSTD is used to reset the voltage of the fourth floating diffusion point FDD according to the reset control signal RSTD, and the fourth signal output module is used to amplify and output the voltage signal input from the fourth floating diffusion point FDD. The fourth transfer transistor TXD connects the photosensitive element PD to the fourth floating diffusion point FDD to ensure that when the transfer signal pgd is input, the first transfer transistor TXB is turned on, and the charge accumulated on the photosensitive element PDB is transferred to the fourth floating diffusion point FDD.

[0107] Optionally, the reset transistor can be a P-type transistor; in some embodiments, it can also be an N-type transistor.

[0108] Furthermore, the correction unit CLB is connected to the high-level voltage signal VDD, the third read control unit RC3, and the fourth read control unit RC4, respectively. One end of the correction unit CLB is connected to the high-level voltage signal VDD, and the other end of the correction unit CLB is connected to the third floating diffusion point FDC and the fourth floating diffusion point FDD. The correction unit CLB is used to reset all floating diffusion points for re-integration when at least one of the potentials of the first floating diffusion point FDA, the second floating diffusion point FDB, the third floating diffusion point FDC, and the fourth floating diffusion point FDD is lower than a preset voltage during the integration period.

[0109] Specifically, the correction unit CLB also includes a third switching transistor CSTC, a fourth switching transistor CSTD, and a logic judgment module. The first terminals of both the third and fourth switching transistors CSTC and CSTD are connected to a high-level voltage signal VDD; the second terminal of the third switching transistor CSTC is connected to the third floating diffusion point FDC, and its control terminal is connected to the logic judgment module; the second terminal of the fourth switching transistor CSTD is connected to the fourth floating diffusion point FDD, and its control terminal is also connected to the logic judgment module. The third and fourth switching transistors CSTC and CSTD are of the same type. Since the control terminals of both CSTC and CSTD are connected to the logic judgment module, and since they are of the same type, when the logic judgment module outputs a signal, both can simultaneously be turned on or off according to the signal output by the logic judgment module. The logic judgment module consists of at least one logic circuit. When the third switching transistor CSTC receives the control signal output by the logic judgment module, it turns on the high-level voltage signal VDD and the third floating diffusion point FDC, thereby resetting the third floating diffusion point FDC. The fourth switching transistor CSTD… Upon receiving the control signal output from the logic judgment module, the high-level voltage signal VDD is turned on to the fourth floating diffusion point FDD, thereby resetting the fourth floating diffusion point FDD. The first terminal of the logic judgment module is connected to the third floating diffusion point FDC and the fourth floating diffusion point FDD, respectively, and the second terminal is connected to the third switching transistor CSTC and the fourth switching transistor CSTD, respectively. This is used to reset all floating diffusion points simultaneously for re-integration when at least one of the potentials of the first floating diffusion point FDA, the second floating diffusion point FDB, the third floating diffusion point FDC, and the fourth floating diffusion point FDD is lower than a preset voltage. Through the above settings, it can be ensured that the potentials of all floating diffusion points are higher than the turn-on voltage (i.e., the preset voltage) of the signal output module, effectively reducing the interference of excessively strong background light on the pixel circuit of this time-of-flight image sensor. Under this premise, the signal output module can conduct normally and smoothly read out the charge signal transmitted by the photosensitive element.

[0110] Furthermore, both the third and fourth signal output modules include a source follower transistor and a row selection transistor. The first terminal of the source follower transistor is connected to a high-level voltage signal, and its control terminal is connected to the floating diffusion point. Its second terminal can be connected to the corresponding output terminal, or it can be connected in series with the row selection transistor and then connected to the corresponding output terminal via the row selection transistor. Simultaneously, the control terminal of the source follower transistor is also connected to the second terminal of the reset transistor and the correction unit CLB. In some embodiments, connecting the source follower transistor to the row selection transistor allows the charge signal output from the floating diffusion point to be introduced via the source follower transistor, amplified, and then output to the corresponding output terminal via the row selection transistor.

[0111] This application embodiment uses the logic judgment module in the correction unit CLB, which includes an inverter and a NOR gate circuit, as an example. In fact, the internal structure of the logic judgment module can be the same as described above. Different structural changes can be achieved by adjusting the logic circuit and the type of adjacent transistors. This application embodiment does not limit this. Specifically, the logic judgment module also includes a third inverter INVC and a fourth inverter INVD. The third inverter INVC is connected to the third floating diffusion point FDC, and the fourth inverter INVD is connected to the fourth floating diffusion point FDD. The third inverter INVC and the fourth inverter INVD are connected in parallel to the input terminal of the NOR gate circuit NOR. The output terminal of the NOR gate circuit NOR is simultaneously connected to the third switching transistor CSTC and the fourth switching transistor CSTD.

[0112] exist Figure 9In the time-of-flight image sensor pixel circuit shown, the third switching transistor CSTC, the fourth switching transistor CSTD, the third reset transistor RSTC, and the fourth reset transistor RSTD are P-type transistors. Therefore, when the potential of at least one of the floating diffusion points FDA, FDB, FDC, and FDD is lower than the turn-on voltage of the signal output module, the logic judgment module can detect whether any of these floating diffusion points is lower than the turn-on voltage of the signal output module when it receives the voltages of FDA, FDB, FDC, and FDD. If such a voltage is found, the first switching transistor CSTA, the second switching transistor CSTB, the third switching transistor CSTC, and the fourth switching transistor CSTD are turned on. The high-level voltage signal VDD simultaneously resets FDA, FDB, FDC, and FDD through these transistors. The specific details are as follows:

[0113] In the first scenario, when the potential of the first floating diffusion point FDA is equal to that of the second floating diffusion point FDB... When the potential of the first floating diffusion point FDA, the second floating diffusion point FDB, the third floating diffusion point FDC, and the fourth floating diffusion point FDD are all higher than the turn-on voltage of the signal output module, the first floating diffusion point FDA, the second floating diffusion point FDB, the third floating diffusion point FDC, and the fourth floating diffusion point FDD all output high-level signals. The low-level signals output by the floating diffusion points are converted into high-level signals by inverters and input to the NOR gate circuit. Since the voltage signals received by the NOR gate circuit are all low-level signals, a high-level signal is output to the first switching transistor CSTA, the second switching transistor CSTB, the third switching transistor CSTC, and the fourth switching transistor CSTD. As mentioned above, the first switching transistor CSTA, the second switching transistor CSTB, the third switching transistor CSTC, and the fourth switching transistor CSTD are all P-type transistors. P-type transistors conduct when they receive a low-level signal at the control terminal. Therefore, when the control terminals of the first switching transistor CSTA and the second switching transistor CSTB both receive high-level signals, the first switching transistor CSTA, the second switching transistor CSTB, the third switching transistor CSTC, and the fourth switching transistor CSTD remain in the off state, and the potentials of all floating diffusion points will not be reset a second time.

[0114] In the second scenario, when any one of the potentials of the first floating diffusion point FDA, the second floating diffusion point FDB, the third floating diffusion point FDC, and the fourth floating diffusion point FDD is lower than the turn-on voltage of the signal output module (for example, when the potential of the first floating diffusion point FDA is lower than the turn-on voltage of the signal output module, and the others are higher than the turn-on voltage of the signal output module), the low-level signal output by the floating diffusion point is converted into a high-level signal input to the NOR gate circuit via an inverter. Since the voltage signal received by the NOR gate circuit includes both low-level and high-level signals, a low-level signal is output to the first switching transistor CSTA, the second switching transistor CSTB, the third switching transistor CSTC, and the fourth switching transistor CSTD. As mentioned above, the first switching transistor CSTA, the second switching transistor CSTB, and the third switching transistor CSTD... Both TC and the fourth switching transistor CSTD are P-type transistors. P-type transistors turn on when they receive a low-level signal at the control terminal. Therefore, when the control terminals of the first switching transistor CSTA and the second switching transistor CSTB both receive low-level signals, the first switching transistor CSTA, the second switching transistor CSTB, the third switching transistor CSTC, and the fourth switching transistor CSTD are all in the on state. The high-level voltage signal VDD is written to the first floating diffusion point FDA, the second floating diffusion point FDB, the third floating diffusion point FDC, and the fourth floating diffusion point FDD through the first switching transistor CSTA, the second floating diffusion point FDB, the third floating diffusion point FDC, and the fourth floating diffusion point FDD, respectively, to simultaneously perform a secondary reset on all floating diffusion points.

[0115] In the third scenario, when the potentials of the first floating diffusion point FDA, the second floating diffusion point FDB, the third floating diffusion point FDC, and the fourth floating diffusion point FDD are all lower than the turn-on voltage of the signal output module, both the first and second floating diffusion points FDA and FDB output low-level signals. The high-level signals output by the floating diffusion points are converted into high-level signals by inverters and input to the NOR gate circuit. Since the voltage signals received by the NOR gate circuit are all high-level signals, low-level signals are output to the first switching transistor CSTA, the second switching transistor CSTB, the third switching transistor CSTC, and the fourth switching transistor CSTD. As mentioned above, the first switching transistor CSTA, the second switching transistor CSTB, the third switching transistor CSTC, and the fourth switching transistor CSTD... All are P-type transistors. P-type transistors turn on when they receive a low-level signal at the control terminal. Therefore, when the control terminals of the first switching transistor CSTA and the second switching transistor CSTB both receive low-level signals, the first switching transistor CSTA, the second switching transistor CSTB, the third switching transistor CSTC, and the fourth switching transistor CSTD are all in the on state. The high-level voltage signal VDD is written to the first floating diffusion point FDA, the second floating diffusion point FDB, the third floating diffusion point FDC, and the fourth floating diffusion point FDD through the first switching transistor CSTA, the second floating diffusion point FDB, the third floating diffusion point FDC, and the fourth floating diffusion point FDD, respectively, to simultaneously perform a secondary reset on all floating diffusion points.

[0116] Understandable Figure 9 The image shows the pixel circuit structure when the number of read control units is 4. In fact, Figure 9 This is merely one example of an embodiment of this application. In this application, the number of read control units in the pixel circuit is not limited.

[0117] Furthermore, such as Figure 2 As shown, the first read control unit RC1 and the second read control unit RC2 are mirror-symmetrical about the photosensitive element PD; in some embodiments, for example... Figure 9 The pixel circuit shown has the third readout control unit RC3 and the fourth readout control unit RC4 arranged in a mirror image symmetrical about the photosensitive element PD. This arrangement aims to maximize the use of the structural space of the time-of-flight image sensor's pixel circuit, thereby improving manufacturing efficiency. Simultaneously, it ensures a uniform distribution of the photosensitive area, enhancing light-sensing efficiency.

[0118] This application also provides a driving method for the pixel circuit of a time-of-flight image sensor. Figure 10 This is a timing diagram of the pixel circuit of the time-of-flight image sensor provided in the embodiments of this application under strong background light illumination, combined with... Figure 2 The specific implementation of the time-of-flight image sensor pixel circuit given in the document is as follows:

[0119] In the first stage, t1, also known as the pre-charge stage, a high-level voltage signal VDD turns on reset transistors RSTA and RSTB. The high-level voltage signal VDD resets the signal output module and the floating diffusion point through reset transistors RSTA and RSTB. Figure 2 For example, the reset control signal rst (including rsta and rstb signals) is set to low level because in Figure 2 In this embodiment, the first reset transistor RSTA and the second reset transistor RSTB are both P-type transistors. Therefore, the high-level voltage signal VDD resets the signal output module and the floating diffusion point through the first reset transistor RSTA and the second reset transistor RSTB. Since the high-level voltage signal VDD is a stable high-level signal, in this embodiment, the reset operation can also be understood as applying a reference voltage to the signal output module and pre-charging the floating diffusion point to stabilize it at a preset potential.

[0120] In some embodiments, the time-of-flight image sensor pixel circuit also includes a pixel reset transistor AB. Therefore, in this embodiment, while resetting the signal output module and the floating diffusion point, the pixel reset transistor AB is turned on, and the ground signal GND provides a low level to reset the photosensitive element PD. Thus, in the first stage t1, the pixel reset signal ab can also be set to the level signal corresponding to the reset control signal rst. The level of the pixel reset signal ab depends on the type of the pixel reset transistor AB. If the pixel reset transistor AB is a P-type transistor, then the pixel reset signal ab is a low-level signal; if the pixel reset transistor AB is an n-type transistor, then the pixel reset signal ab is a high-level signal. Here, as an example, the pixel reset transistor AB is an n-type transistor, and the pixel reset signal ab is a high-level signal. Since the input terminal of the photosensitive element PD is grounded, the ground signal GND provides a low-level signal to reset the photosensitive element PD.

[0121] In the second stage t2, also known as the adjustment stage, reset transistors RSTA and RSTB are turned off, and transmission transistors TXA and TXB are turned on, transferring the charge accumulated by the photosensitive element PD to the first floating diffusion point FDA and the second floating diffusion point FDB. If at least one of the potentials of the first floating diffusion point FDA and the second floating diffusion point FDB is lower than a preset voltage (usually the turn-on voltage of the signal output module), the correction unit CLB applies a high-level signal from the high-level voltage signal VDD to both the first floating diffusion point FDA and the second floating diffusion point FDB, turning on the transmission transistors TXA and TXB again and transferring the charge accumulated by the photosensitive element PD to the first floating diffusion point FDA and the second floating diffusion point FDB respectively. If the potentials of both the first floating diffusion point FDA and the second floating diffusion point FDB are higher than the preset voltage, the charge accumulated by the photosensitive element PD is written into the signal output module.

[0122] like Figure 2 As shown, in this stage, the reset control signal rst (including the rsta and rstb signals) is set to a high level, and the first reset transistor RSTA and the second reset transistor RSTB are turned off first; the transmission signals pga and pgb are alternately set to a high level, and the first transmission transistor TXA of the first read control unit RC1 and the second transmission transistor TXB of the second read control unit RC2 are alternately turned on during the exposure process of the photosensitive element PD to alternately transfer the charge accumulated by the photosensitive element PD to the first floating diffusion point FDA and the second floating diffusion point FDB, respectively. Understandably, when strong background light enters the pixel circuit through the exposure of the photosensitive element PD, it will lower the potential of the first floating diffusion point FDA and / or the potential of the second floating diffusion point FDB. See the part circled in black in the figure. When the potential of the first floating diffusion point FDA and / or the potential of the second floating diffusion point FDB is lower than a preset voltage (usually the turn-on voltage of the readout circuit), the correction unit CLB is activated to simultaneously apply a high-level signal from the high-level voltage signal VDD to the potentials of the first floating diffusion point FDA and the second floating diffusion point FDB. This resets the potentials of the first floating diffusion point FDA and the second floating diffusion point FDB, re-activating the first transmission transistor TXA and the second transmission transistor TXB, and transferring the accumulated charge of the photosensitive element PD to the first floating diffusion point FDA and the second floating diffusion point FDB, respectively. When the potentials of the first floating diffusion point FDA and the second floating diffusion point FDB are both higher than the preset voltage, the accumulated charge of the photosensitive element PD is written to the signal output module.

[0123] The third stage, t3, also known as the read-out stage, involves the transmission transistors TXA and TXB being turned off, while the signal output module is turned on to transmit the image signal. For example... Figure 2As shown, the row selection signal RS is set to a high level, and the transmission signals pga and pgb are alternately set to a low level. The first transmission transistor TXA and the second transmission transistor TXB of the second read control unit RC2 are turned off. The first source follower transistor SFA, the second source follower transistor SFB, the first row selection transistor RSA, and the second row selection transistor RSB are turned on to transmit the image signal, and the transmission of the image signal begins.

[0124] According to the timing information of this application, in the second stage t2, when the potential of the first floating diffusion point FDA and / or the potential of the second floating diffusion point FDB is lower than the preset voltage (usually the turn-on voltage of the readout circuit), the correction unit CLB is activated to control the first reset transistor RSTA and the second reset transistor RSTB to simultaneously apply a high-level signal from the high-level voltage signal VDD to the potential of the first floating diffusion point FDA and the potential of the second floating diffusion point FDB, thereby resetting the potential of the first floating diffusion point FDA and the potential of the second floating diffusion point FDB until both potentials are higher than the preset voltage, thus completing the adaptive adjustment.

[0125] Figure 11 This is another timing diagram of the pixel circuit of the time-of-flight image sensor provided in the embodiments of this application under strong background light illumination, corresponding to... Figure 9 The image sensor pixel circuitry is shown in the diagram. It is worth noting that:

[0126] because Figure 9 The pixel circuit of the time-of-flight image sensor given in the paper is compared to Figure 2 The time-of-flight image sensor pixel circuit described in the paper differs in that it includes an additional pair of readout control units. Figure 11 Another timing diagram of the time-of-flight image sensor pixel circuit provided in the embodiments of this application under strong background light illumination can be obtained from... Figure 10 This driving method can be applied similarly, but the difference between the two is:

[0127] exist Figure 10 In the diagram, the driving signals pga and pgb corresponding to the transmission transistors TXA and TXB, respectively, are given. If the duration of each transmission of photocharge signal by the photosensitive element PD is T, then the time interval between the activation of driving signals pga and pgb is T / 2. Figure 11In the diagram, the transmission transistors TXA, TXB, TXC, and TXD each have their corresponding drive signals pga, pgb, pgc, and pgd. If the duration of each transmission of photocharge signal by the photosensitive element PD is T, then the time interval between the activation of drive signals pga and pgc is T / 4, and the time interval between the activation of drive signals pgb and pgc, and between pgc and pgd is also T / 4.

[0128] In addition, this application embodiment also provides an image sensor that uses the time-of-flight image sensor pixel circuit provided in the foregoing embodiments, including a first chip and a second chip, wherein the photosensitive element and the transmission transistor are disposed on the first chip; in some embodiments, the first chip is further provided with a pixel reset transistor; the device structure of the first read control unit other than the transmission transistor, the device structure of the second read control unit other than the transmission transistor, and the correction unit are disposed on the second chip.

[0129] It is understood that in the time-of-flight image sensor pixel circuit provided in this application, the pixel circuit needs to be formed on a wafer. Multiple pixel circuits and the image sensor work together to achieve photoelectric efficiency. Only after the wafer is packaged can it constitute an image sensor chip.

[0130] like Figure 12As shown, the time-of-flight image sensor pixel circuit provided in this application is formed on two chips, a first chip A and a second chip B. This time-of-flight image sensor pixel circuit simultaneously covers both chips A and B. The first chip A includes a photosensitive element PD, a first transmission transistor TXA, and a second transmission transistor TXB. The photosensitive element PD, the first transmission transistor TXA, and the second transmission transistor TXB are interconnected. In some other embodiments of this application, the first chip A also includes a pixel reset transistor AB. The second chip B includes the remaining device structures of the first readout control unit RC1 (excluding the first transmission transistor TXA), the remaining device structures of the second readout control unit RC2 (excluding the second transmission transistor TXB), and all device structures of the correction unit CLB. In some embodiments, the first chip A and the second chip B are stacked and electrically connected. It is understood that the electrical connection can be either a metal wire connection or a wire connection using doped semiconductor materials; this application does not limit this method. The significance of this configuration is that, since the first chip A and the second chip B, which are equipped with a photosensitive element PD, a first transmission transistor TXA, and a second transmission transistor TXB, are stacked and electrically connected, the first chip A can function as an independent pixel. Within the same surface area, compared to the scheme where the first chip A and the second chip B are arranged in parallel, the pixel size within the first chip A can be reduced as much as possible, which helps to increase the proportion of the photosensitive area, thereby improving the pixel resolution and thus enhancing the operating speed and efficiency of the pixel circuit of the time-of-flight image sensor provided in this application embodiment.

[0131] In summary, this application provides a time-of-flight image sensor pixel circuit, and provides its driving method and an image sensor including the time-of-flight image sensor pixel circuit according to the working state of the time-of-flight image sensor pixel circuit. It can effectively reduce the interference of excessive background light on the time-of-flight image sensor pixel circuit, so that it can conduct normally and smoothly read out the charge signal transmitted by the photosensitive element.

[0132] The embodiments described above are merely some, not all, of the embodiments of this application. The components of the embodiments of this application typically described and illustrated in the accompanying drawings can be arranged and designed in various different configurations. Therefore, the detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of protection of this application, but merely to illustrate selected embodiments of this application. Based on this, the scope of protection of this application should be determined by the scope of the claims. Furthermore, all other embodiments that can be obtained by those skilled in the art based on the embodiments of this application without inventive effort should fall within the scope of protection of this application.

Claims

1. A pixel circuit for a time-of-flight image sensor, characterized in that, Includes a photosensitive element, several readout control units, and a calibration unit; The plurality of read control units include a plurality of floating diffusion points, and the plurality of read control units are used to read and control the charge signal transmitted by the photosensitive element respectively; one end of the correction unit is connected to a high-level voltage signal, and the other end is connected to the plurality of floating diffusion points; The correction unit is used to reset all floating diffusion points to re-integrate when the potential of at least one of the floating diffusion points is lower than a preset voltage during integration.

2. The pixel circuit as described in claim 1, characterized in that, One end of the correction unit is connected to a high-level voltage signal, and the other end is connected to the plurality of floating diffusion points. The correction unit includes a plurality of switching transistors and a logic judgment module. The first end of the switching transistor is connected to the high-level voltage signal. The second end of the switching transistor is connected to the floating diffusion points, and the control end of the switching transistor is connected to the logic judgment module. The logic judgment module is composed of at least one logic circuit. The logic judgment module is used to output a control signal to turn on the switching transistors to reset all the floating diffusion points for re-integration when the potential of at least one of the floating diffusion points is lower than the preset voltage.

3. The pixel circuit as described in claim 2, characterized in that, The logic judgment module includes at least two inverters and a NOR gate circuit, wherein the inverters are connected to the floating diffusion point, the inverters are connected to the input terminal of the NOR gate circuit, and the output terminal of the NOR gate circuit is connected to the switching transistor.

4. The pixel circuit as described in claim 2, characterized in that, The logic judgment module includes an inverter and a NAND gate circuit. The input terminal of the NAND gate circuit is connected to the floating diffusion point, and the output terminal of the NAND gate circuit is connected to the input terminal of the inverter. The output terminal of the inverter is connected to the switching transistor.

5. The pixel circuit as described in claim 2, characterized in that, The logic judgment module includes only AND gate circuits, wherein the input terminal of the AND gate circuit is connected to the floating diffusion point, and the output terminal of the AND gate circuit is simultaneously connected to the switching transistor.

6. The pixel circuit as described in claim 4 or 5, characterized in that, The switching transistor is a P-type transistor.

7. The pixel circuit as described in claim 2, characterized in that, The logic judgment module includes at least two inverters and an OR gate circuit, wherein the inverters are connected to the floating diffusion point, the inverters are connected to the input terminal of the OR gate circuit, and the output terminal of the OR gate circuit is connected to the switching transistor.

8. The pixel circuit as described in claim 2, characterized in that, The logic judgment module includes only NAND gate circuits, wherein the input terminal of the NAND gate circuit is connected to the floating diffusion point, and the output terminal of the NAND gate circuit is connected to the switching transistor.

9. The pixel circuit as described in claim 8, characterized in that, The NAND gate circuit is composed of at least one control transistor group and a bias transistor connected in series. The control transistor group includes two control transistors connected in series. The control terminal of the bias transistor is connected to a bias voltage. The control transistor group is connected to the high-level voltage signal through the bias transistor. Both the control transistor and the bias transistor are N-type transistors.

10. The pixel circuit according to any one of claims 7-9, characterized in that, The switching transistor is an N-type transistor.

11. The pixel circuit as described in claim 1, characterized in that, The read control unit includes a reset transistor, a transmission transistor, and a signal output module. One end of the reset transistor is connected to the high-level voltage signal, and the other end of the reset transistor is connected to the floating diffusion point to reset the voltage of the floating diffusion point according to the reset control signal. The first end of the signal output module is connected to the high-level voltage signal, and the control end of the signal output module is connected to the reset transistor and the floating diffusion point respectively to amplify and output the voltage signal input from the floating diffusion point.

12. The pixel circuit as described in claim 11, characterized in that, The reading control unit includes a first reading control unit and a second reading control unit, and the first reading control unit and the second reading control unit are mirror-symmetrical about the photosensitive element.

13. The pixel circuit as described in claim 12, characterized in that, The reading control unit further includes a third reading control unit and a fourth reading control unit, and the first reading control unit, the second reading control unit, the third reading control unit and the fourth reading control unit are mirror-symmetrical about the photosensitive element.

14. The pixel circuit as described in claim 12 or claim 13, characterized in that, The reset transistor is an N-type transistor.

15. The pixel circuit as described in claim 11, characterized in that, The signal output module includes a source follower transistor. The first terminal of the source follower transistor is connected to the high-level voltage signal. The control terminal of the source follower transistor is connected to the floating diffusion point, the second terminal of the reset transistor, and the correction unit. The second terminal of the source follower transistor is connected to the corresponding output terminal.

16. The pixel circuit as described in claim 15, characterized in that, The signal output module includes a row selection transistor, and the source follower transistor is connected in series with the row selection transistor and connected to the corresponding output terminal through the row selection transistor.

17. The pixel circuit as described in claim 11, characterized in that, The pixel circuit also includes a dual conversion gain control module, which is connected between the reset transistor and the floating diffusion point. The dual conversion gain control module includes at least one dual conversion gain control transistor and a capacitor. The dual conversion gain control module is used to switch between low conversion gain mode and high conversion gain mode.

18. The pixel circuit as described in claim 11, characterized in that, The pixel circuit also includes a pixel reset transistor. The first terminal of the pixel reset transistor is connected to a ground signal, the second terminal of the pixel reset transistor is connected to the second terminal of the photosensitive element, and the control terminal of the pixel reset transistor is connected to a pixel reset signal. The pixel reset transistor is used to clear the charge of the photosensitive element before the photosensitive element transmits a charge signal.

19. The pixel circuit as described in claim 11, characterized in that, The read control unit further includes a storage capacitor. The first plate of the storage capacitor is connected to the floating diffusion point, and the second plate of the storage capacitor is connected to a ground signal. The storage capacitor is used to receive and store the charge generated by the photosensitive element after the correction unit corrects and resets when the potential of at least one of the floating diffusion points is lower than the preset voltage.

20. The pixel circuit as described in claim 11, characterized in that, The preset voltage is the turn-on voltage of the signal output module.

21. A method for driving a pixel circuit of a time-of-flight image sensor, used to drive the pixel circuit of a time-of-flight image sensor as described in any one of claims 11-20, characterized in that, Includes the following steps: In the first stage, the high-level voltage signal turns on the reset transistor, and the high-level voltage signal resets the signal output module and the floating diffusion point through the reset transistor; In the second stage, the reset transistor is turned off, the transmission transistor is turned on, and the charge accumulated by the photosensitive element is transferred to the plurality of floating diffusion points; if the potential of at least one of the floating diffusion points is lower than the preset voltage, the correction unit simultaneously applies a high-level signal from the high-level voltage signal to all the floating diffusion points, turns on the transmission transistor again, and transfers the charge accumulated by the photosensitive element to the plurality of floating diffusion points; if the potential of all the floating diffusion points is higher than the preset voltage, the charge accumulated by the photosensitive element is written into the signal output module. In the third stage, the transmission transistor is turned off, and the signal output module is turned on to transmit the image signal.

22. A time-of-flight image sensor, employing the time-of-flight image sensor pixel circuit according to any one of claims 11-20.

23. The time-of-flight image sensor as claimed in claim 22, characterized in that, The time-of-flight image sensor includes a first chip and a second chip, wherein: the photosensitive element and the transmission transistor are disposed on the first chip; the readout control unit, excluding the transmission transistor, and the correction unit are disposed on the second chip; the first chip and the second chip are stacked and electrically connected.

24. The time-of-flight image sensor as claimed in claim 23, characterized in that, The pixel circuit also includes a pixel reset transistor. The first terminal of the pixel reset transistor is connected to a ground signal, the second terminal of the pixel reset transistor is connected to the second terminal of the photosensitive element, and the control terminal of the pixel reset transistor is connected to a pixel reset signal. The first chip is also provided with the pixel reset transistor.

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