Digital-to-analog converter and electronic device

Abstract

A digital-to-analog converter and an electronic device, which relate to the technical field of electronics, are used for improving the circuit matching characteristics of the current digital-to-analog converter integrated circuit. The digital-to-analog converter comprises a current source array and a switch array. The current source array comprises a plurality of effective current source units. The plurality of effective current source units are filled with metal above. The switch array comprises a plurality of switch units. Control ends of the plurality of switch units are used for receiving control signals. Input ends of the plurality of switch units are respectively used for receiving corresponding currents provided by the plurality of effective current source units. Output ends of the plurality of switch units are coupled to an output end of the digital-to-analog converter, and are used for realizing the output of an analog signal.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronics, and in particular to a digital-to-analog converter and an electronic device. BACKGROUND

[0002] In modern communication systems, to meet the requirements of signal processing speed and accuracy, high-performance integrated circuits such as digital-to-analog converters (DACs) are needed to implement signal processing and conversion. In many application scenarios, due to performance requirements (such as noise and linearity), the area of such integrated circuits may be designed to be relatively large.

[0003] For circuits containing multiple matching unit structures, such as digital-to-analog converter (DAC) current sources, the matching characteristics of the circuit pose a great challenge to DAC design. SUMMARY

[0004] Embodiments of the present application provide a digital-to-analog converter and an electronic device, for improving the circuit matching performance of the current digital-to-analog converter integrated circuit.

[0005] To achieve the above-mentioned purpose, the present application adopts the following technical solutions:

[0006] In a first aspect, the present application provides a digital-to-analog converter. The digital-to-analog converter includes a current source array and a switch array, and the current source array includes a plurality of effective current source units. The plurality of effective current source units is filled with metal above. The switch array includes a plurality of switch units. The control end of the plurality of switch units is used to receive a control signal. The input end of the plurality of switch units is used to receive the current provided by the plurality of effective current source units; the output end of the plurality of switch units is coupled to the output end of the digital-to-analog converter, for realizing the output of an analog signal. Wherein, the effective current source unit is the current source unit in the current source array of the exponential digital-to-analog converter that can generate an electrical signal and contribute to the output of an analog signal and the accuracy and performance of the digital-to-analog converter.

[0007] Based on the digital-to-analog converter provided in the first aspect, the digital-to-analog converter includes a plurality of effective current source units, and the plurality of effective current source units is filled with metal above. In advanced processes, the filling density of metal in circuit layout design has strict requirements, and filling the plurality of effective current source units with metal above can meet the requirements of the metal filling density in circuit layout design, thereby improving the circuit matching performance of the digital-to-analog converter.

[0008] Optionally, the current source array can further comprise a plurality of dummy connection current source units. The dummy connection current source units are filled with metal above. The dummy connection current source units are areas which are set for the stability of the circuit layout and the consistency of the layout environment near the effective current source units, and are not used to generate electrical signals, thus generally do not directly affect the accuracy and performance of the digital-to-analog converter. Since the effective current source units are filled with metal above, the metal can cause stress to the transistors on the effective current source units. Filling the dummy connection current source units with metal above can reduce the stress caused by the metal to the transistors on the effective current source units, while meeting the metal density requirements in the circuit layout design, thereby improving the performance of the digital-to-analog converter.

[0009] Further, the metal filled above the effective current source units can comprise top layer metal and / or sub-top layer metal. In the circuit layout design of the digital-to-analog converter, there are certain requirements for the metal filling density in each metal layer in the circuit layout. The high layer thick metal refers to the top layer metal and / or the sub-top layer metal in the circuit layout, and the high layer thick metal is generally thick and can cause stress to the transistor devices in the lower layer, thereby changing the original electrical matching relationship of the circuit.

[0010] Further, the plurality of effective current source units can have a weight ratio relationship, and the weight of each effective current source unit can be related to the number or size of the transistors in the effective current source unit. According to the basic principle of the digital-to-analog converter DAC, the plurality of current source units in the current source array have a weight ratio relationship. However, since the dummy connection current source units in the current source array are not used to generate electrical signals, the weight ratio relationship between the plurality of current source units in the current source array refers to the weight ratio relationship between the plurality of effective current source units in the current source array. In addition, the weight of the plurality of current source units in the current source array is determined according to the electrical parameters (such as current, voltage) output by each current source unit. The number of transistors in each current source unit determines the size of the electrical parameters output by each current source unit, and the number of transistors determines the total size of the current source unit, i.e., the weight of each effective current source unit is related to the number of transistors in the effective current source unit or the total size of the transistors.

[0011] Further, the plurality of switch units can have a weight ratio relationship, and the weight of the plurality of switch units is related to the number or size of the transistors in the plurality of switch units. The weight ratio relationship of the switch units and the effective current source units can be consistent, and the relationship between the weight of the switch units and the number or size of the transistors in the switch units can be referred to the above relationship between the weight of the plurality of effective current source units and the number or size of the transistors in the effective current source units, which will not be described herein again.

[0012] In a possible implementation, the current source array can include a first effective current source unit and a second effective current source unit. The first effective current source unit has a first weight, and the second effective current source unit has a second weight. The first weight is greater than or equal to the second weight. In the same metal layer, the metal filling area on the first effective current source unit is greater than or equal to the metal filling area on the second effective current source unit. In this way, the mismatch error caused by the non-uniform stress generated by the thick metal at a high layer can be reduced, thereby improving the circuit matching performance and accuracy of the digital-to-analog converter.

[0013] Further, in the same metal layer, the ratio between the metal filling area on the first effective current source unit and the metal filling area on the second effective current source unit can be consistent with the ratio between the first weight and the second weight. In this way, the mismatch error caused by the stress generated by the metal filled above the first effective current source unit and the second effective current source unit on the transistor device below can also satisfy the ratio between the first weight and the second weight, so that the first effective current source unit and the second effective current source unit can still maintain the original weight ratio after the mismatch error caused by the stress, thereby further improving the circuit matching performance and accuracy of the digital-to-analog converter DAC.

[0014] Optionally, the current source array can further include a third effective current source unit, and the third effective current source unit has a third weight. The third weight is less than the second weight. In the same metal layer, the metal filling area on the third effective current source unit is less than the metal filling area on the second effective current source unit. In this way, the mismatch error caused by the non-uniform stress generated by the thick metal at a high layer can be reduced, thereby improving the accuracy and performance of the digital-to-analog converter.

[0015] Further, in the same metal layer, the ratio between the metal filling area on the first effective current source unit, the metal filling area on the second effective current source unit, and the metal filling area on the third effective current source unit can be consistent with the ratio between the first weight, the second weight, and the third weight. In this way, the mismatch error caused by the stress generated by the metal filled above the first effective current source unit, the second effective current source unit, and the third effective current source unit on the transistor device below can also satisfy the ratio between the first weight, the second weight, and the third weight, so that the first effective current source unit, the second effective current source unit, and the third effective current source unit can still maintain the original weight ratio after the mismatch error caused by the stress, thereby further improving the circuit matching performance and accuracy of the digital-to-analog converter DAC.

[0016] Optionally, the ratio between the first weight, the second weight, and the third weight can be a binary ratio.

[0017] Optionally, the metal filling manner on the effective current source unit can be strip covering filling and / or point filling. The strip covering filling is more convenient for metal filling manufacturing, thereby reducing manufacturing cost; and the point filling can make the generated stress more uniform, thereby improving the performance of the digital-to-analog converter.

[0018] Optionally, if the layout area of the current source array exceeds the first threshold, the proportion of the total area of the metal filled on the plurality of effective current source units and the plurality of virtual connection current source units to the layout area of the current source array is greater than or equal to 5%. In this way, the integrated circuit such as the digital-to-analog converter (DAC) can meet the basic requirements of the integrated circuit process in the manufacturing process, thereby improving the circuit matching performance and reliability of the digital-to-analog converter.

[0019] In a second aspect, the present application provides an integrated circuit. The integrated circuit comprises any possible digital-to-analog converter of the first aspect. It should be understood that the integrated circuit can be any possible digital-to-analog converter of the first aspect, or can comprise any possible digital-to-analog converter of the first aspect and other types of circuits such as an analog-to-digital converter (ADC). Therefore, the beneficial effects of the integrated circuit can refer to the beneficial effects of the digital-to-analog converter provided in the first aspect, which will not be repeated here.

[0020] In a third aspect, the present application provides an electronic device. The electronic device comprises a transceiver chip and any possible digital-to-analog converter of the first aspect. The digital-to-analog converter can be arranged in the transceiver chip.

[0021] Optionally, the electronic device can further comprise a baseband processing chip, and the baseband processing chip is coupled to the transceiver chip.

[0022] Optionally, the electronic device further comprises a printed circuit board, and the transceiver chip and the baseband processing chip are arranged on the printed circuit board.

[0023] It can be understood that the electronic device of the third aspect of the present application involves the digital-to-analog converter provided in the first aspect, and therefore the beneficial effects that can be achieved can refer to the beneficial effects of the digital-to-analog converter provided in the first aspect, which will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 A circuit principle schematic diagram of a digital-to-analog converter (DAC) provided for an embodiment of the present application;

[0025] Figure 2 A structure schematic diagram of a current steering DAC provided for an embodiment of the present application;

[0026] Figure 3A schematic circuit layout of a current source array in a current-driven DAC provided for embodiments of this application;

[0027] Figure 4 A schematic diagram of a digital-to-analog converter (DAC) filled with a high-layer thick metal, provided as an embodiment of this application. Figure 1 ;

[0028] Figure 5 A graph showing the effect of stress on a digital-to-analog converter (DAC) provided for embodiments of this application;

[0029] Figure 6 A schematic diagram of a digital-to-analog converter (DAC) filled with a high-layer thick metal, provided as an embodiment of this application. Figure 2 ;

[0030] Figure 7 The principle of filling a digital-to-analog converter (DAC) with a high-layer thick metal layer is provided in the embodiments of this application. Figure 1 ;

[0031] Figure 8 The principle of filling a digital-to-analog converter (DAC) with a high-layer thick metal layer is provided in the embodiments of this application. Figure 1 ;

[0032] Figure 9 A schematic diagram of the structure of a current source array in a current-driven DAC provided for an embodiment of this application;

[0033] Figure 10 for Figure 9 A schematic diagram of the circuit layout of the current source array in the image;

[0034] Figure 11 In order to be in Figure 10 A schematic diagram of the circuit layout filled with metal for the current source array in the diagram. Figure 1 ;

[0035] Figure 12 In order to be in Figure 10 A schematic diagram of the circuit layout filled with metal for the current source array in the diagram. Figure 2 ;

[0036] Figure 13 A schematic circuit layout of a current source array in a DAC with a linear weighting relationship is provided for embodiments of this application.

[0037] Figure 14 In order to be in Figure 13 A schematic diagram of the circuit layout of the current source array filled with metal.

[0038] Figure 15 A schematic diagram of the structure of an electronic device provided for an embodiment of this application;

[0039] Figure 16 This is a schematic diagram of the structure of another electronic device provided as an embodiment of this application. Detailed Implementation

[0040] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0041] Hereinafter, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature.

[0042] Furthermore, in this application, directional terms such as "upper," "lower," "left," "right," "horizontal," and "vertical" are defined relative to the indicated placement of the components in the accompanying drawings. It should be understood that these directional terms are relative concepts, used for relative description and clarification, and can change accordingly depending on the placement of the components in the accompanying drawings.

[0043] Figure 1 This illustrates the basic principle of a digital-to-analog converter (DAC). Please refer to [link / reference]. Figure 1 A DAC consists of a digital driver circuit and an analog core circuit. The digital driver circuit receives digital signals B0, B1…B… n-2 B n-1 Input; The analog core circuit includes multiple matching circuit units, and different matching circuit units can have different weights, that is, multiple different circuit units have weights W0, W1...W1 respectively. n-2 W n-1 Digital signals B0, B1...B n-2 B n-1 After being input to the digital drive circuit, the analog signal (voltage, current) is output by combining with different circuit units in the analog core circuit. The output analog signal Aout can be expressed by the following formula:

[0044]

[0045] Among them, R ref It represents a reference quantity (which can be voltage, current, or charge).

[0046] At present, the matching characteristics of the circuit bring great challenges to the design of a digital-to-analog converter (DAC), and the matching characteristics of the circuit can refer to the matching of the metal density filling requirement in the circuit layout design, or refer to the matching performance of the weight proportion relationship in the matching circuit unit.

[0047] The following describes how to improve the circuit matching characteristics of the circuit layout of a digital-to-analog converter (DAC).

[0048] Exemplarily, Figure 2 A structure diagram of a current steering DAC is shown. Please refer to Figure 2 The current steering DAC includes a current source array and a switch array. The switch array includes a plurality of switch units. The control terminals of the plurality of switch units are configured to receive control signals. The input terminals of the plurality of switch units are respectively configured to receive corresponding currents provided by a plurality of effective current source units. The output terminals of the plurality of switch units are coupled to the output terminal of the digital-to-analog converter, and are configured to output an analog signal. That is, the current source array can be used as an analog core circuit in the current steering DAC. The plurality of current source units in the current source array have a weight relationship, and each of the plurality of current source units corresponds to a differential switch (i.e., a switch unit) having the same weight in the switch array. Under the control of input digital signals B0, B1,..., Bn, the current steering DAC determines the current flowing to the two-phase load to output the analog signal. n-2 n-1

[0049] Figure 3 A circuit layout diagram of a current source array in a current steering DAC is shown. Please refer to Figure 3 The current source array includes a plurality of effective current source units and a plurality of virtual connection current source units. The effective current source unit is a current source unit in the current source array of the exponential-to-analog converter, which can generate an electrical signal, and contributes to the output of the analog signal and the accuracy and performance of the digital-to-analog converter. The virtual connection current source unit refers to an area additionally provided for the stability of the circuit layout and the consistency of the layout environment near the effective unit, which is not used to generate an electrical signal, and thus generally does not directly affect the accuracy and performance of the digital-to-analog converter. Among them, Figure 3 The middle blank area in the current source array is a plurality of effective current source units, and the parts on both sides of the effective current source units are virtual connection current source units.

[0050] In combination with Figure 3 Please refer to Figure 4 and Figure 6 ​​Within the layout of this digital-to-analog converter (DAC), multiple effective current source units are filled with metal. In advanced manufacturing processes, the circuit layout design of DACs has strict requirements regarding the metal fill density in each metal layer within the circuit layout. By filling multiple effective current source units with metal, the metal fill density requirements in the DAC circuit layout design can be met, thereby improving the circuit matching performance of the DAC.

[0051] In addition to filling multiple active current source units with metal, metal can also be filled above multiple virtual connection current source units. Since filling metal above active current source units may cause stress on the transistors on the active current source units, filling metal above virtual connection current source units can reduce the stress effect of metal on the transistors on the active current source units while meeting the metal density requirements in the circuit layout design, thereby improving the matching performance of the digital-to-analog converter.

[0052] Optionally, in Figure 2 In the current-driven DAC shown, the multiple current source units in the current source array can have weighted relationships. However, the current source array includes multiple active current source units and multiple virtual connected current source units. Since the virtual connected current source units in the current source array are mainly used to ensure the stability (structural strength) of the integrated circuit layout and the consistency of the layout environment near the active units, they are not used to generate corresponding electrical parameters. Therefore, the weighted relationships between the multiple current source units in the current source array can be a weighted proportional relationship between the multiple active current source units.

[0053] Understandably, since the weights of multiple current source units in a current source array are determined based on the electrical parameters (such as current and voltage) output by each current source unit, and the number of transistors in each current source unit determines the magnitude of the electrical parameters output by each current source unit, it can be considered that the weight of each effective current source unit is positively correlated with the number of transistors in that effective current source unit. Furthermore, since a larger number of transistors in a current source unit results in a larger layout size for that current source unit, it can also be considered that the weight of each effective current source unit is positively correlated with the total size of the transistors in that effective current source.

[0054] Accordingly, multiple switching units can have a weighted ratio relationship, and the weight of multiple switching units is related to the number or size of transistors in the multiple switching units. The weighted ratio relationship in the switching units and the effective current source units can be consistent. The relationship between the weight of the switching unit and the number or size of transistors in the switching unit can be referred to the above-mentioned relationship between the weight of multiple effective current source units and the number or size of transistors in the effective current source units, and will not be repeated here.

[0055] It is worth noting that the thickness of the metal varies in different metal layers, and high-layer thick metal refers to the top and / or second-to-top layer metal in the circuit layout. High-layer thick metal is generally quite thick and can exert stress on the transistor devices below, altering the electrical matching relationship of the original circuit. This application primarily discusses the filling of high-layer thick metal in DAC circuit layouts. Therefore, the metal filling above the effective current source unit can include the top and / or second-to-top layer metal.

[0056] Furthermore, it should be noted that when the metal filling the effective current source unit is the top layer metal or the second-to-top layer metal, the thickness of the metal is generally large. After filling the metal, the metal will generate stress on the transistor devices in the lower layer. This stress will change the original physical characteristics of the device (such as threshold voltage and threshold current), thereby changing the electrical parameters (such as voltage and current) in the DAC circuit, which in turn reduces the accuracy and performance of the digital-to-analog converter (DAC).

[0057] For example, the effect of thick metal layers on the stress generated by a digital-to-analog converter (DAC) is explained below.

[0058] The first scenario, Figure 4 This illustration shows a schematic diagram of a digital-to-analog converter (DAC) filled with a thick layer of metal according to an embodiment of this application. Figure 1 Please refer to this. Figure 4 The schematic diagram shows that the digital-to-analog converter (DAC) only fills a portion of the effective current source cells with a thick metal layer. Since this thick metal layer exerts stress on the underlying transistor devices, the effective current source cells are significantly affected by this stress. This stress alters the weighting ratio between the multiple effective current source cells in the DAC, causing it to lose its original proportions and resulting in severe mismatch errors. Consequently, the accuracy of the DAC is reduced, and its circuit matching performance is compromised.

[0059] Figure 5 The graph showing the effect of stress on the current-driven DAC is presented. Combined with... Figure 4 Please refer to Figure 5 , Figure 5 The horizontal axis represents the number of the effective current source unit, and the vertical axis represents the magnitude of the electrical parameters (such as current magnitude) generated by the effective current source unit. Figure 5 The effective current source units in the current-controlled DAC are designed with a normalized current magnitude of 256. The current sources numbered 2, 4, and 60 are filled with metal. As shown in the figure, the currents generated by the current sources numbered 2, 4, and 60 have the largest deviation from the preset 256. Therefore, the effective current sources filled with metal are more significantly affected by stress, and the metal filling above the effective current source units can generate non-uniform stress on the transistor devices below.

[0060] The second case, Figure 6 Fig. 1 shows a schematic diagram of filling high-level thick metal on a digital-to-analog converter (DAC) according to an embodiment of the present application. Figure 2 Referring to Fig. 1, Figure 6 The DAC in Fig. 1 is filled with high-level thick metal of the same area on each active current source cell. In this case, the DAC produces the same stress on the lower transistor devices of each active current source cell. If the weight proportions of each active current source cell are the same, the mismatch error produced on each active current source cell under the influence of the high-level thick metal producing the same stress on the lower transistor devices is also the same. The weight proportions of each active current source cell can still maintain the original weight proportion relationship, so that the accuracy and circuit matching characteristics of the DAC can not be reduced.

[0061] On the contrary, if the weight proportions of each active current source cell are not the same (such as a binary proportion relationship or a linear proportion relationship), the mismatch error produced on each active current source cell under the influence of the high-level thick metal producing the same stress on the lower transistor devices is also the same, so that the weight proportions of each active current source cell cannot maintain the original weight proportion relationship, thereby causing the accuracy of the DAC to be reduced and the circuit performance to be degraded. For example, a DAC includes three active current source cells with a weight proportion of 4:2:1. Assuming that the mismatch error caused by the stress of the high-level thick metal on each active current source cell is 0.2, the weight proportion of the three active current source cells in the DAC considering the stress is changed to (4+0.2):(2+0.2):(1+0.2)=4.2:2.2:1.2.

[0062] Therefore, when the high-level thick metal is filled on the active current source cells in the circuit layout of the DAC, non-uniform stress can be produced, which can destroy the original weight matching relationship of the integrated circuit, thereby causing a mismatch error and reducing the accuracy of the DAC and degrading the performance of the DAC.

[0063] The following describes how to reduce the mismatch error caused by the non-uniform stress of the high-level thick metal.

[0064] In some embodiments, Figure 2The digital-to-analog converter (DAC) shown can include a first effective current source unit and a second effective current source unit. The first effective current source unit has a first weight, and the second effective current source unit has a second weight. To reduce the mismatch error caused by the non-uniform stress of the high-level thick metal, if the first weight is greater than or equal to the second weight, the metal filling area on the first effective current source unit can be greater than or equal to the metal filling area on the second effective current source unit in the same metal layer.

[0065] Further, in the same metal layer, the ratio between the metal filling area on the first effective current source unit and the metal filling area on the second effective current source unit can be consistent with the ratio between the first weight and the second weight. For example, assuming that the ratio between the first weight and the second weight is 2:1, the ratio between the metal filling area on the first effective current source unit and the metal filling area on the second effective current source unit can also be set to 2:1. In this way, after the first effective current source unit and the second effective current source unit are filled with the high-level thick metal, and the mismatch error caused by the stress of the high-level thick metal is considered, the weight ratio of the first effective current source unit and the second effective current source unit can still maintain the original ratio, such as 2:1, thereby reducing the mismatch error caused by the non-uniform stress and improving the accuracy and performance of the digital-to-analog converter (DAC).

[0066] Optionally, Figure 2 The digital-to-analog converter (DAC) shown can also include a third effective current source unit, and the first effective current source unit has a third weight. Similarly, to reduce the mismatch error caused by the non-uniform stress of the high-level thick metal, if the third weight is less than the second weight, the metal filling area on the third effective current source unit can be less than the metal filling area on the second effective current source unit in the same metal layer.

[0067] Further, in the same metal layer, the ratio between the metal filling area on the first effective current source unit, the metal filling area on the second effective current source unit, and the metal filling area on the third effective current source unit can be consistent with the ratio between the first weight, the second weight, and the third weight. For example, assuming that the ratio between the first weight and the second weight is 4:2:1, the ratio between the metal filling area on the first effective current source unit, the metal filling area on the second effective current source unit, and the metal filling area on the third effective current source unit can also be set to 4:2:1, thereby further reducing the mismatch error caused by the non-uniform stress and improving the accuracy and performance of the digital-to-analog converter (DAC).

[0068] Specifically, Figure 7 A principle of filling a high-level thick metal on a digital-to-analog converter (DAC) provided by an embodiment of the present application is shown Figure 1Please refer to Figure 7 A digital-to-analog converter (DAC) can include three effective current source units, weights of the three effective current source units are W x , W y and W z , respectively; and mismatch errors caused by high layer thick metal filled on the three effective current source units are ΔW x , ΔW y and ΔW z , respectively.

[0069] Suppose that a density (such as current density) of a physical size of each effective current source unit in a circuit layout is consistent, and a proportion of filled areas of the high layer thick metal on the three effective current source units is the same as a weight proportion relationship of the three effective current source units. Suppose that the effective current source unit with a weight of W x covers 4 pieces of high layer thick metal, and metal areas are x1, x2, x3 and x4, respectively; the effective current source unit with a weight of W y covers 2 pieces of high layer thick metal, and metal areas are y1 and y2, respectively; and the effective current source unit with a weight of W z covers 1 piece of high layer thick metal, and a metal area is z. Figure 7 The filled metal areas on the three effective current source units in the DAC shown in

[0070] (x1+x2+x3+x4):(y1+y2):z=W x :W y :W z ,

[0071] Since the filled metal areas on the three effective current source units in the DAC shown in Figure 7 are consistent with the weights of the three effective current source units in the DAC, mismatch errors caused by stress of the metal on the three effective current source units on lower transistor devices are also consistent with the weight proportion relationship of the three current source units, and a specific relationship is as follows:

[0072] (W x +ΔW x ):(W y +ΔW y ):(W z +ΔW z )=W x :W y :W z ,

[0073] Therefore, in the DAC shown in Figure 7The high-layer metal density on the circuit layout of the digital-to-analog converter (DAC) shown can be filled according to the original weighting relationship to reduce the mismatch error caused by stress, thereby improving the accuracy and performance of the DAC.

[0074] In addition, for some digital-to-analog converters (DACs), their current source arrays include a large number of effective current source units. When filling with metal, it is not possible to fill all the effective current source units with the weight ratio according to the weight ratio. According to the requirements of the circuit layout and design rules of each module, some effective current source units with higher weight ratios can be selected to fill with the metal according to the corresponding weight ratio to optimize the circuit matching performance.

[0075] For example, Figure 8 This application illustrates the principle of filling a digital-to-analog converter (DAC) with a high-layer thick metal layer according to an embodiment of the present application. Figure 2 .like Figure 8 As shown, the multiple effective current source units in this digital-to-analog converter (DAC) have the following weighting ratio:

[0076] W x ≥W y ≥W z ≥W a ≥W b ≥W c ,

[0077] Since effective current source units with higher weighting ratios have a significant impact on the accuracy of digital-to-analog converters (DACs), these units can be filled with thick metal layers according to their weighting ratios to optimize circuit performance. Figure 8 Only for weight ratio W x W y and W z The effective current source is filled with high-layer thick metal according to the weight ratio.

[0078] The above describes how to reduce mismatch errors caused by stress. The following section uses the high-layer metal filling of the current source array in two types of current-controlled DACs as an example for further explanation.

[0079] Taking a current-controlled DAC with a binary proportional relationship as an example, Figure 9 A schematic diagram of the current source array in a current-driven DAC provided in this application is shown. Figure 9 The current rudder DAC shown is a 6-bit current rudder, where the high 4 bits are the thermometer code (T), corresponding to 15 current sources I. MSB The lower two bits are binary code (B), corresponding to the two current sources I. LSB1 and I LSB0 Current source I MSB ILSB1 and I LSB0 The weight ratio is a binary ratio, such as I MSB :I LSB1 :I LSB0 = 4:2:1.

[0080] For example, Figure 10 It shows Figure 9 A schematic diagram of the circuit layout of the current source array. (See attached diagram.) Figure 10 As shown, a small square represents a transistor with a width / length ratio of W / L, and a current source consists of 16*3 transistors connected in parallel. Wherein current source I... MSB All elements in the middle are effective current source units, current source I LSB1 and I LSB0 There are a certain number of virtual current source units on each side. Due to current source I... MSB I LSB1 and I LSB0 The weight ratio relationship satisfies I MSB :I LSB1 :I LSB0 = 4:2:1, therefore the current source I MSB I LSB1 and I LSB0 The number of transistors in the effective current source unit also satisfies the 4:2:1 relationship.

[0081] Figure 11 In order to be in Figure 10 The schematic diagram of the circuit layout of the current source array shown is filled with metal. Figure 1 . Figure 12 for Figure 10 The schematic diagram of the circuit layout of the current source array shown is filled with metal. Figure 2 .like Figure 11 and Figure 12 As shown, current source I MSB The area of ​​the metal filling above is larger than that of the current source I. LSB1 The area of ​​the metal filling above; current source I LSB1 The area of ​​the metal filling above is larger than that of the current source I. LSB0 The area of ​​the metal filling above.

[0082] Furthermore, current source I MSB The area of ​​the metal filling above and the current source I LSB1 The ratio of the area of ​​the metal filling above is 8:4, or 4:2; or, current source I MSB The area of ​​the metal filling above and the current source I LSB0 The ratio of the area of ​​the metal filling above is 8:2, or 4:1; or current source I LSB1The ratio of the upper filled metal area to the current source I LSB0 The ratio of the upper filled metal area is 4:2, i.e. 2:1; or the current source I MSB The upper filled metal area, the current source I LSB1 The ratio of the upper filled metal area to the current source I LSB0 The ratio of the upper filled metal area is 8:4:2. In this way, the current source I MSB , I LSB1 and I LSB0 The ratio of the upper filled metal area is consistent with the weight ratio of the current source I MSB , I LSB1 and I LSB0 ; all are binary ratio relationship, such as 4:2:1.

[0083] In some embodiments, the metal filling mode on the effective current source unit can be strip coverage filling, or point filling, or a combination of strip coverage filling and point filling, for example Figure 11 The metal filling mode on the effective current source unit shown is strip coverage filling, i.e. it can be filled in a strip manner along the arrangement direction of the transistors in the current source array, vertically or horizontally. For example Figure 12 The metal filling mode on the effective current source unit shown is point filling, i.e. it can be filled with a single transistor in the current source array as a point, and the filled transistors can be arranged arbitrarily, and the filled metal area meets the corresponding requirements (such as binary ratio relationship).

[0084] The above is described by taking a DAC with a binary weight ratio as an example. The following is described by taking a DAC with a linear weight ratio as an example.

[0085] Exemplarily, Figure 13 A circuit layout diagram of a current source array in a DAC with a linear weight ratio is shown. As Figure 13 shown, the high 4 bits of the current source array in the current steering DAC are thermometer code, which is composed of 15 current source units I MSB with the same weight; the low 3 bits of the current source I MSB , I LSB1 and I LSB0 and the current source unit I MSB satisfy the linear weight ratio relationship, such as I MSB : I LSB2 : I LSB1 : I LSB0 = 4:3:2:1. Figure 13 A small square in the middle represents a W / L (width / length) transistor, and a current source is composed of 16*3 transistors in parallel. Among them, the current source IMSB All of them are effective current source units, current source I LSB2 , LSB1 and I LSB0 Each of the two sides has a certain number of virtual connection current source units. Since the weight ratio of current source I MSB , LSB2 , LSB1 and I LSB0 satisfies I MSB :I LSB2 :I LSB1 :I LSB0 = 4:3:2:1, the number of transistors in the effective current source units in current source I MSB , LSB2 , LSB1 and I LSB0 also satisfies the relationship of 4:3:2:1.

[0086] Figure 14 The schematic diagram of the metal filling method of the current source array method of the linear weight relationship in I Figure 13 is shown. Similar to I Figure 11 and I Figure 12 , the proportion of the metal area filled above current source I MSB , LSB2 , LSB1 and I LSB0 is consistent with the weight ratio of current source I MSB , LSB2 , LSB1 and I LSB0 ; it is a linear proportional relationship, such as 4:3:2:1. The specific filling method is similar to I Figure 11 and I Figure 12 , which will not be described here.

[0087] It should be understood that the weight ratio in the current source array is not limited to a binary weight ratio or a linear weight ratio. Other weight ratios, such as 4:3:1, are also applicable. The specific numerical value of the weight ratio of the current source array in the embodiments of the present application is not specially limited.

[0088] In addition, it should be noted that the metal density requirement in the integrated circuit design process can be: if the layout area of the current source array exceeds a first threshold, the total area of the metal filled above the plurality of effective current source units and the plurality of virtual connection current source units is more than 5% of the layout area of the current source array. The first threshold can be the area of the minimum window specified in the advanced process. For example, in I Figure 10 and I Figure 13 , the current source I MSBAll of them exceed the minimum window specified by the advanced process. Therefore, if the area of the metal filled above the dummy connection current source cell in the current source array cannot reach more than 5% of the layout area of the current source array, the metal can be filled above the effective current source cell, that is, the metal can be filled above Figure 10 the current source I MSB , I LSB1 and I LSB0 , as shown in Figure 11 and Figure 12 ; or the metal can be filled above Figure 13 the current source I MSB , I LSB2 , I LSB1 and I LSB0 , as shown in Figure 14 , so as to meet the metal density requirement in the integrated circuit design process, thereby improving the reliability of the circuit.

[0089] The embodiments of the present application also provide an integrated circuit. The integrated circuit can be the digital-to-analog converter DAC in the above embodiments, or can include both the digital-to-analog converter DAC in the above embodiments and other types of circuits, such as an analog-to-digital converter (ADC).

[0090] It should be understood that the DAC described in the above embodiments can be all functional modules or part of the functional modules of the chip DAC circuit, and the effective current source filled with the top metal can be all or part of the current source in the DAC.

[0091] Figure 15 A structure schematic diagram of an electronic device provided by an embodiment of the present application is shown. The electronic device can be a terminal or a base station. As shown in Figure 15 , the electronic device can include an application subsystem, a memory, a massive storage, a baseband subsystem, a radio frequency integrated circuit (RFIC), a radio frequency front end (RFFE) device, and an antenna (ANT), which can be coupled through various interconnection buses or other electrical connection methods.

[0092] Figure 15In this code, ANT_1 represents the first antenna, ANT_N represents the Nth antenna, and N is a positive integer greater than 1. Tx represents the transmit path, Rx represents the receive path, and different numbers represent different paths. FBRx represents the feedback receive path, PRx represents the main receive path, and DRx represents the diversity receive path. HB represents high frequency, LB represents low frequency, and these two refer to the relative high and low frequencies. BB represents baseband. It should be understood that... Figure 5 The labels and components in this application are for illustrative purposes only and represent only one possible implementation. Other implementations are also included in this application.

[0093] The application subsystem can serve as the main control system or main computing system for the wireless communication device. It runs the main operating system and applications, manages the hardware and software resources of the entire wireless communication device, and provides a user interface. The application subsystem may include one or more processing cores. Furthermore, it may also include driver software related to other subsystems (such as the baseband subsystem). The baseband subsystem may also include one or more processing cores, as well as hardware accelerators (HACs) and caches.

[0094] Figure 15 In this system, the RFFE device, RFIC 1 (and optional RFIC 2) together constitute the radio frequency (RF) subsystem. The RF subsystem can be further divided into an RF receive path and an RF transmit path. The RF receive path receives RF signals via an antenna, processes these signals (e.g., amplification, filtering, and down-conversion) to obtain a baseband signal, and then transmits it to the baseband subsystem. The RF transmit path receives baseband signals from the baseband subsystem, processes these baseband signals (e.g., up-conversion, amplification, and filtering) to obtain an RF signal, and finally radiates this RF signal into space via an antenna. Specifically, the RF subsystem may include antenna switches, antenna tuners, low-noise amplifiers (LNAs), power amplifiers (PAs), mixers, local oscillators (LOs), filters, and other electronic components, which can be integrated into one or more chips as needed. Antennas can sometimes also be considered part of the RF subsystem.

[0095] The baseband subsystem can extract useful information or data bits from the baseband signal or convert information or data bits into a baseband signal to be transmitted. These information or data bits can be data representing user data or control information such as voice, text, video, etc. For example, the baseband subsystem can implement signal processing operations such as modulation and demodulation, encoding and decoding, etc. For different wireless access technologies, such as 5G NR and 4G LTE, the baseband signal processing operations tend to be not exactly the same. Therefore, in order to support the integration of multiple mobile communication modes, the baseband subsystem can simultaneously include multiple processing cores, or multiple HACs.

[0096] In addition, since the radio frequency signal is an analog signal, the signal processed by the baseband subsystem is mainly a digital signal, and an analog-to-digital conversion device is also needed in the wireless communication device. The analog-to-digital conversion device includes an analog-to-digital converter (ADC) for converting an analog signal into a digital signal, and a digital-to-analog converter (DAC) for converting a digital signal into an analog signal, which can adopt the analog-to-digital converter DAC provided in the above embodiment. In the embodiment of the present application, the analog-to-digital conversion device can be arranged in the baseband subsystem, or arranged in the radio frequency subsystem, i.e. the transceiver chip.

[0097] It should be understood that in the embodiments of the present application, the processing core can represent a processor, which can be a general-purpose processor or a processor designed for a specific field. For example, the processor can be a central processing unit (CPU), a digital signal processor (DSP), a micro control unit (MCU), a graphics processing unit (GPU), an image signal processor (ISP), an audio signal processor (ASP), and a processor specially designed for artificial intelligence (AI) applications. The AI processor includes but is not limited to a neural network processing unit (NPU), a tensor processing unit (TPU), and a processor referred to as an AI engine.

[0098] Hardware accelerators can be used to implement some sub-functions that have high processing overhead, such as assembly and parsing of data packets, encryption and decryption of data packets, etc. These sub-functions can also be implemented using general-purpose processors, but due to performance or cost considerations, it can be more appropriate to use hardware accelerators. Therefore, the types and numbers of hardware accelerators can be specifically selected based on requirements. In a specific implementation, one or a combination of a field programmable gate array (FPGA) and an application specified integrated circuit (ASIC) can be used for implementation. Of course, one or more processing cores can also be used in the hardware accelerator.

[0099] Memory can be divided into volatile memory and non-volatile memory (NVM). Volatile memory refers to a memory in which the data stored therein will be lost when the power supply is interrupted. At present, volatile memory is mainly random access memory (RAM), including static RAM (SRAM) and dynamic RAM (DRAM). Non-volatile memory refers to a memory in which the data stored therein will not be lost when the power supply is interrupted. Common non-volatile memories include read only memory (ROM), optical discs, magnetic discs, and various memories based on flash memory technology, etc. Generally, the memory can be selected as volatile memory, and the mass storage can be selected as non-volatile memory, such as a magnetic disc or a flash memory.

[0100] In the embodiments of the present application, the baseband subsystem and the radio frequency subsystem together constitute a communication subsystem, which provides wireless communication functions for the wireless communication device. Generally, the baseband subsystem is responsible for managing the software and hardware resources of the communication subsystem, and can configure the working parameters of the radio frequency subsystem. One or more processing cores of the baseband subsystem can be integrated into one or more chips, which can be referred to as baseband processing chips or baseband chips. Similarly, the RFIC can be referred to as a radio frequency processing chip or a radio frequency chip. In addition, with the evolution of technology, the functional division between the radio frequency subsystem and the baseband subsystem in the communication subsystem can also be adjusted. For example, the functions of part of the radio frequency subsystem are integrated into the baseband subsystem, or the functions of part of the baseband subsystem are integrated into the radio frequency subsystem. In actual applications, based on the needs of application scenarios, the wireless communication device can use a combination of different numbers and different types of processing cores.

[0101] In the embodiments of the present application, the radio frequency subsystem can include a separate antenna, a separate radio frequency front end (RFFE) device, and a separate radio frequency chip. The radio frequency chip is also sometimes referred to as a receiver, a transmitter, a transceiver, or a transceiver chip. The antenna, the radio frequency front end device, and the radio frequency processing chip can all be manufactured and sold separately. Of course, the radio frequency subsystem can also use different devices or different integration methods based on the requirements of power consumption and performance. For example, the radio frequency front end devices can be integrated into the radio frequency chip, and even the antenna and the radio frequency front end device can be integrated into the radio frequency chip. The radio frequency chip can also be referred to as a radio frequency antenna module or an antenna module.

[0102] In the embodiments of the present application, the baseband subsystem can be a separate chip, which can be referred to as a modem chip. The hardware components of the baseband subsystem can be manufactured and sold in units of modem chips. The modem chip is also sometimes referred to as a baseband processing chip or a baseband processor. In addition, the baseband subsystem can also be further integrated into a SoC chip, and manufactured and sold in units of SoC chips. The software components of the baseband subsystem can be built into the hardware components of the chip before the chip is shipped, or can be imported into the hardware components of the chip from other non-volatile memories after the chip is shipped, or can also be downloaded and updated in an online manner through a network.

[0103] In addition, the electronic device can also include a printed circuit board, and the transceiver chip and the baseband processing chip are arranged on the printed circuit board.

[0104] Figure 16 Another structural schematic diagram of an electronic device provided in the embodiments of the present application. Figure 16 Some common devices for radio frequency signal processing in the electronic device are shown. It should be understood that, Figure 16 Although only one radio frequency receiving channel and one radio frequency transmitting channel are shown in the above-mentioned structural schematic diagram, the wireless communication device in the embodiments of the present application is not limited thereto, and the wireless communication device can include one or more radio frequency receiving channels and radio frequency transmitting channels.

[0105] For the radio frequency receiving channel, the radio frequency signal received from the antenna is sent into the radio frequency receiving channel through the selection of the antenna switch. Since the radio frequency signal received from the antenna is usually very weak, a low noise amplifier LNA is usually used for amplification. The amplified signal is first subjected to down-conversion processing by the mixer, and then subjected to filtering and analog-to-digital conversion ADC, and finally the baseband signal processing is completed. For the radio frequency transmitting channel, the baseband signal can be converted into an analog signal by a digital-to-analog converter DAC, the analog signal is subjected to up-conversion processing by the mixer to become a radio frequency signal, the radio frequency signal is subjected to processing by the filter and the power amplifier PA, and finally the radio frequency signal is radiated outward from the appropriate antenna through the selection of the antenna switch. The digital-to-analog converter DAC of the radio frequency transmitting channel can use the digital-to-analog converter DAC provided in the above embodiment.

[0106] In the mixer, the input signal and the local oscillator LO signal are mixed to achieve up-conversion (corresponding to the radio frequency transmitting channel) or down-conversion (corresponding to the radio frequency receiving channel) operation. The local oscillator LO is a commonly used term in the field of radio frequency, and is usually referred to as a local oscillator. The local oscillator is sometimes also referred to as a frequency synthesizer or frequency synthesizer (frequency synthesizer), simply referred to as frequency synthesizer. The main function of the local oscillator or frequency synthesizer is to provide the required specific frequency for radio frequency processing, such as the frequency point of the carrier. Higher frequencies can be achieved by using phase-locked loop (PLL) or delay-locked loop (DLL) devices. Lower frequencies can be achieved by directly using a crystal oscillator, or by frequency dividing the high frequency signal generated by the PLL device.

[0107] The above is only a specific embodiment of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A digital-to-analog converter, characterized in that: It includes a current source array and a switch array, wherein the current source array includes multiple effective current source units; The plurality of effective current source units are filled with metal, which generates stress applied to the plurality of effective current source units; The switch array includes multiple switch units, the control terminals of the multiple switch units are used to receive control signals, and the input terminals of the multiple switch units are used to receive the corresponding current provided by the multiple effective current source units. The output terminals of the plurality of switching units are coupled to the output terminal of the digital-to-analog converter to realize the output of analog signals.

2. The digital-to-analog converter according to claim 1, characterized in that, The current source array also includes multiple virtual connected current source units; the multiple virtual connected current source units are filled with metal.

3. The digital-to-analog converter according to claim 1, characterized in that, The metal filling above the plurality of effective current source units includes top layer metal and / or second-to-top layer metal.

4. The digital-to-analog converter according to any one of claims 1 to 3, characterized in that, The plurality of effective current source units have a weighted ratio relationship; the weight of the plurality of effective current source units is related to the number or size of the transistors in the plurality of effective current source units.

5. The digital-to-analog converter according to any one of claims 1 to 3, characterized in that, The multiple switching units have a weighted ratio relationship; the weight of the multiple switching units is related to the number or size of the transistors in the multiple switching units.

6. The digital-to-analog converter according to any one of claims 1 to 3, characterized in that, The current source array includes a first effective current source unit and a second effective current source unit. The first effective current source unit has a first weight, and the second effective current source unit has a second weight. The first weight is greater than or equal to the second weight; in the same metal layer, the metal filling area on the first effective current source unit is greater than or equal to the metal filling area on the second effective current source unit.

7. The digital-to-analog converter according to claim 6, characterized in that, Within the same metal layer, the ratio between the metal filling area of ​​the first effective current source unit and the metal filling area of ​​the second effective current source unit is consistent with the ratio between the first weight and the second weight.

8. The digital-to-analog converter according to claim 6, characterized in that, The current source array also includes a third effective current source unit, which has a third weight. The third weight is less than the second weight, and in the same metal layer, the metal filling area on the third effective current source unit is less than the metal filling area on the second effective current source unit.

9. The digital-to-analog converter according to claim 8, characterized in that, Within the same metal layer, the proportional relationship between the metal filling area on the first effective current source unit, the metal filling area on the second effective current source unit, and the metal filling area on the third effective current source unit is consistent with the proportional relationship between the first weight, the second weight, and the third weight.

10. The digital-to-analog converter according to claim 9, characterized in that, The ratio of the first weight, the second weight, and the third weight is a binary ratio.

11. The digital-to-analog converter according to any one of claims 1 to 3, characterized in that, The metal filling method on the effective current source unit is strip-shaped covering filling and / or dot-shaped filling.

12. The digital-to-analog converter according to claim 2, characterized in that, If the layout area of ​​the current source array exceeds a first threshold, the total area of ​​the metal filling above the plurality of effective current source units and the plurality of virtual connected current source units accounts for more than 5% of the layout area of ​​the current source array.

13. An electronic device, characterized in that, include: A transceiver chip, and a digital-to-analog converter as described in any one of claims 1 to 12; The digital-to-analog converter is located in the transceiver chip.

14. The electronic device according to claim 13, characterized in that, It also includes a baseband processing chip, which is coupled to the transceiver chip.

15. The electronic device according to claim 14, characterized in that, It also includes a printed circuit board, on which the transceiver chip and the baseband processing chip are disposed.

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