A low-power bandgap reference circuit, chip and method for generating a reference voltage

Abstract

The application provides a low-power bandgap reference circuit, a chip and a reference voltage generation method, and solves the problems of high power consumption and the need to use an operational amplifier and a resistor in the prior art bandgap reference, and comprises the following components connected in series: a positive temperature coefficient module comprising a first transistor, a second transistor and a first MOS tube, a difference between base-emitter voltages of the first transistor and the second transistor generating a positive temperature coefficient voltage on the first MOS tube; a clamping module comprising a first clamping MOS tube and a second clamping MOS tube, the clamping module being used to provide equal first clamping voltage and second clamping voltage; a negative temperature coefficient module comprising a first MOS tube and a second MOS tube, threshold voltages of the first MOS tube and the second MOS tube serving as a negative temperature coefficient voltage; a current mirror module proportionally copying a current of a branch in which the first transistor is located to a branch in which the negative temperature coefficient module is located and a branch in which the second transistor is located, and the negative temperature coefficient voltage and the positive temperature coefficient voltage being added together to serve as a reference voltage.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more specifically, to a low-power bandgap reference circuit, a chip, and a method for generating a reference voltage. Background Technology

[0002] A bandgap reference is one of the core modules of every analog circuit, providing a reference voltage or current for the entire module. It is widely used in analog circuit systems such as low-voltage linear regulators, phase-locked loops, and data converters. Traditional bandgap reference circuits utilize the negative temperature coefficient of the pn junction voltage of a transistor and the positive temperature coefficient of the voltage difference between the pn junctions of two transistors under different current densities to compensate for each other, thus obtaining a voltage with a near-zero temperature coefficient. Because this voltage value is approximately equal to the bandgap voltage of silicon, this circuit is called a bandgap reference circuit.

[0003] Traditional bandgap reference circuits require operational amplifiers to clamp the voltage, which increases the power consumption of the circuit. In order to reduce the power consumption of the circuit, large resistors are required. This causes the bandgap reference to consume a lot of chip area. On some chips that require low power consumption and miniaturization, such as electronic detonator chips, traditional bandgap reference circuits are difficult to meet the current requirements for low power consumption and miniaturization. Summary of the Invention

[0004] To address the aforementioned problems, this invention provides a low-power bandgap reference circuit, chip, and method for generating a reference voltage. It solves the problems of existing bandgap references requiring operational amplifiers, resistors, and having high power consumption, and proposes a low-power bandgap reference circuit without operational amplifiers or resistors.

[0005] The technical solution is as follows: a low-power bandgap reference circuit, comprising the following connected components:

[0006] The starting circuit is used to generate current when power is applied, so that the entire circuit can get out of the degeneracy point and start working;

[0007] Its characteristic is that it further includes:

[0008] A positive temperature coefficient module, comprising a first transistor, a second transistor, and a first MOS transistor, wherein the collector and base of the first transistor are connected to the drain of the first MOS transistor, and the collector and base of the second transistor are connected to the source of the first MOS transistor, and the difference between the base-emitter voltages of the first and second transistors generates a positive temperature coefficient voltage on the first MOS transistor.

[0009] A clamping module, comprising a first clamping MOS transistor and a second clamping MOS transistor, wherein the sources of the first clamping MOS transistor and the drains of the first clamping MOS transistor and the second clamping MOS transistor are respectively connected, and the clamping module is used to provide a first clamping voltage and a second clamping voltage, such that the first clamping voltage and the second clamping voltage are equal;

[0010] A negative temperature coefficient module, comprising a first MOSFET and a second MOSFET, wherein the threshold voltages of the first MOSFET and the second MOSFET are used as the negative temperature coefficient voltage;

[0011] A current mirror module, which replicates the current of the branch containing the first transistor to the branch containing the negative temperature coefficient module and the branch containing the second transistor in a proportional manner.

[0012] The negative temperature coefficient voltage and the positive temperature coefficient voltage are compensated according to the set weights and then superimposed together. The resulting voltage is used as the reference voltage.

[0013] Furthermore, the current mirror module includes interconnected MOSFETs M8, M5, M9, M6, M10, and M7. MOSFETs M8, M5, M9, and M6 constitute a first current mirror unit, and MOSFETs M10, M7, M9, and M6 constitute a second current mirror unit. The source of MOSFET M10 is connected to the sources of MOSFETs M9 and M8, the gate of MOSFET M10 is connected to the gates of MOSFETs M9 and M8, the drain of MOSFET M10 is connected to the source of MOSFET M7, the drain of MOSFET M9 is connected to the source of MOSFET M6, the drain of MOSFET M8 is connected to the source of MOSFET M5, the gate of MOSFET M7 is connected to the gates of MOSFETs M6 and M5, the drain of MOSFET M6 is connected to the drain of the first clamping MOSFET and the gate of MOSFET M7, and the drain of MOSFET M7 is connected to the drain and gate of the second clamping MOSFET.

[0014] Furthermore, the first and second transistors are transistors Q1 and Q2, respectively. The emitter of Q1 is connected to the source of the first clamped MOSFET, the emitter of Q2 is connected to the source of the second clamped MOSFET, the base of Q1 is connected to the collector of Q1, and the base of Q2 is connected to the collector of Q2.

[0015] Furthermore, transistors Q1 and Q2 are both PNP transistors.

[0016] Furthermore, the first transistor includes a plurality of transistors connected in parallel, wherein the collectors of each transistor are connected together, the bases of each transistor are connected together, and the emitters of each transistor are connected together.

[0017] Furthermore, the negative temperature coefficient module includes a first MOSFET M1 and a second MOSFET M2. The drain of the first MOSFET M1 is connected to the source of the second MOSFET M2. The collector of Q2 is connected to the source of the first MOSFET M1. The collector of Q1 is connected to the source of the second MOSFET M2. The gates of the first MOSFET M1 and the second MOSFET M2 are connected. The drain of the second MOSFET M2 is also connected to the drain of MOSFET M5 and the gate of MOSFET M1.

[0018] Furthermore, the startup circuit includes MOSFETs M11 and M12 and capacitor C1. The source of MOSFET M12 is connected to the source of MOSFET M8, the source of MOSFET M11 is connected to the gate of MOSFET M8, the gate of MOSFET M11 is connected to the drain of MOSFET M12, the drain of MOSFET M12 is connected to capacitor C1, and capacitor C1 is then connected to the source of MOSFET M1. The gate of MOSFET M12 is connected to capacitor C1.

[0019] A chip characterized in that it includes the aforementioned low-power bandgap reference circuit.

[0020] A method for generating a reference voltage, characterized by being implemented based on the aforementioned low-power bandgap reference circuit, includes the following steps:

[0021] Step 1: Obtain the negative temperature coefficient voltage by utilizing the negative temperature characteristic of the threshold voltage of the MOSFET;

[0022] Step 2: Obtain the positive temperature coefficient voltage by utilizing the positive temperature characteristic of the voltage difference between the base and emitter voltages of the transistor under different current densities;

[0023] Step 3: Obtain the current-voltage characteristics of the first and second MOSFETs under different states;

[0024] Step 4: Based on the obtained positive temperature coefficient voltage and negative temperature coefficient voltage, as well as the current and voltage characteristics of the first MOSFET and the second MOSFET under different states, obtain a reference voltage. Adjust the parameters of the first MOSFET M1 and the second MOSFET M2, the current magnitude of the branch containing transistor Q2, and the ratio of the number of transistors Q1 to Q2, so that the reference voltage satisfies the zero temperature coefficient voltage.

[0025] Furthermore, in step 1, the negative temperature coefficient voltage is obtained as follows:

[0026] V TH =V TH0 +αT

[0027] Among them, V TH The voltage has a negative temperature coefficient, meaning it is negatively correlated with temperature. α is the temperature coefficient of the threshold voltage, and α is a negative number. (V) TH0This represents the threshold voltage at 0K.

[0028] In step 2, the positive temperature coefficient voltage is obtained as follows:

[0029] Ignoring second-order effects, the current-voltage characteristics of transistors Q1 and Q2 are expressed as follows:

[0030]

[0031] This leads to the base-emitter voltage of the transistor:

[0032] Where I0 is the reverse saturation current of the transistor, V T Thermoelectric voltage;

[0033] The ratio of transistors Q1 to Q2 is M:1, and the currents flowing through transistors Q1 and Q2 are respectively I... Q1 ,I Q2 I Q2 =NI Q1 The positive temperature coefficient voltage is expressed as:

[0034]

[0035] ΔV BE =V T ln(MN)

[0036] Let ΔV BE =V x

[0037] ΔV BE The voltage difference between the base and emitter voltages of transistors Q1 and Q2 is the positive temperature coefficient voltage.

[0038] In step 3, the current-voltage characteristics of the first MOSFET and the second MOSFET under different states are obtained as follows:

[0039] The ratio of the currents flowing through the three branches containing M8, M9, and M10 is 1:1:N, therefore we can obtain...

[0040] I D1 =2I D2

[0041] I D1 I D2 This represents the current flowing through the drain terminals of MOSFETs M1 and M2;

[0042] Ignoring second-order effects, the current-voltage characteristics of the first MOSFET M1 are expressed as follows:

[0043]

[0044] Ignoring second-order effects, the current-voltage characteristics of the second MOSFET M2 are expressed as follows:

[0045]

[0046] Where, μ n C represents the electron mobility. ox V represents the gate oxide capacitance per unit area. TH V represents the threshold voltage of the MOSFET. GS V represents the gate-source voltage of a MOSFET. DS This represents the source-drain voltage of the MOSFET, and W and L are the channel width and channel length of the MOSFET, respectively.

[0047] Combined with the drain current I of MOSFETs M1 and M2 D1 I D2 The current-voltage characteristics of the first MOSFET M1 and the current-voltage characteristics of the second MOSFET M2 are then:

[0048]

[0049]

[0050] Where V ref Reference voltage;

[0051] In step 4, based on the obtained positive temperature coefficient voltage and negative temperature coefficient voltage, and the current-voltage characteristics of the first and second MOSFETs under different states, a reference voltage is obtained:

[0052]

[0053] in S1 and S2 are the aspect ratios of the channels of MOSFETs M1 and M2, respectively; W and L are the channel width and channel length of the MOSFETs, respectively; V TH Voltage with a negative temperature coefficient q is the unit charge, κ is the Boltzmann constant, and V is the charge per unit area. T Thermoelectric voltage is positively correlated with temperature.

[0054] Combining the expression for negative temperature coefficient voltage, V ref Represented as:

[0055]

[0056] Where V TH0 This represents the threshold voltage at 0K. Adjust S eff The value then makes It tends towards zero, including making V refThe voltage has a zero temperature coefficient.

[0057] In this invention, a MOS transistor operating in the linear region is used to replace the large resistor in a traditional bandgap reference, which reduces the layout area. While conventional bandgap references use operational amplifiers to clamp the voltage, this invention utilizes the relationship between the gate-source voltage and current of a MOS transistor operating in the saturation region. Since there is no operational amplifier, the power consumption of the entire circuit becomes extremely low. Taking advantage of the positive temperature characteristic of the pn junction voltage difference of a bipolar transistor under different current densities and the negative temperature characteristic of the threshold voltage of a field-effect transistor, a bandgap reference voltage with minimal temperature influence is obtained through compensation. The output voltage is stable and remains almost unchanged within a given temperature range. Attached Figure Description

[0058] Figure 1 This is a block diagram of the low-power bandgap reference circuit in the embodiment;

[0059] Figure 2 This is a circuit diagram of the low-power bandgap reference circuit in the embodiment;

[0060] Figure 3 This is a schematic diagram of the output voltage of the low-power bandgap reference circuit in the embodiment. Detailed Implementation

[0061] See Figure 1 The present invention provides a low-power bandgap reference circuit, comprising the following connected components:

[0062] Start-up circuit 1 is used to generate current when powered on, so that the entire circuit can get out of the degeneracy point and quickly enter the normal working state.

[0063] Positive temperature coefficient module 2 includes a first transistor, a second transistor, and a first MOSFET M1. The collector and base of the first transistor Q1 are connected to the drain of the first MOSFET M1, and the collector and base of the second transistor Q2 are connected to the source of the first MOSFET. The first MOSFET M1 operates in the linear region and is used as a resistor. The difference between the base-emitter voltages of the first and second transistors generates a positive temperature coefficient voltage on the first MOSFET.

[0064] Clamping module 3 includes a first clamping MOSFET M3 and a second clamping MOSFET M4. The sources of the first and second clamping MOSFETs M3 and M4 are connected to the drains of the first and second transistors Q1 and Q2, respectively. The clamping module is used to provide a first clamping voltage and a second clamping voltage, so that the first clamping voltage and the second clamping voltage are equal. When the first clamping voltage and the second clamping voltage are equal, the emitter potentials of Q1 and Q2 are equal. However, at this time, the base potentials of Q1 and Q2 are not equal. Therefore, the base-emitter voltage difference of Q1 and Q2, i.e., the positive temperature coefficient voltage, is reflected at the drain of M1.

[0065] Negative temperature coefficient module 4 includes a first MOSFET M1 and a second MOSFET M2. The negative temperature coefficient module is used to generate a negative temperature coefficient voltage.

[0066] The current mirror module 5 replicates the current in the branch where the first transistor Q1 is located to the negative temperature coefficient module 4 and the branch where the second transistor Q2 is located. The threshold voltages of the first and second MOSFETs M1 and M2 are used as the negative temperature coefficient voltages. The threshold voltage represents the voltage difference required between the gate and source when the MOSFET channel is fully turned on. This voltage difference is negatively correlated with temperature, so it can be used as a negative temperature coefficient voltage. The current and voltage characteristics of the first MOSFET M1 and the second MOSFET M2 in different operating states are used to compensate the negative temperature coefficient voltage and the positive temperature coefficient voltage according to the set weights and then superimpose them together. The obtained voltage is used as the generated reference voltage.

[0067] Specifically, in this embodiment, the current mirror module includes interconnected MOSFETs M8, M5, M9, M6, M10, and M7. MOSFETs M8, M5, M9, and M6 constitute a first current mirror unit, where the branch containing MOSFETs M8 and M5 replicates the current of the branch containing MOSFETs M9 and M6. MOSFETs M10, M7, M9, and M6 constitute a second current mirror unit, where the branch containing MOSFETs M10 and M7 replicates the current of the branch containing MOSFETs M9 and M6. The source of MOSFET M10 is connected to MOSFETs M9 and M8. The source of MOSFET M10 is connected to the gate of MOSFET M9 and MOSFET M8. The drain of MOSFET M10 is connected to the source of MOSFET M7. The drain of MOSFET M9 is connected to the source of MOSFET M6. The drain of MOSFET M8 is connected to the source of MOSFET M5. The gate of MOSFET M7 is connected to the gate of MOSFET M6 and MOSFET M5. The drain of MOSFET M6 is connected to the drain of the first clamping MOSFET and the gate of MOSFET M7. The drain of MOSFET M7 is connected to the drain and gate of the second clamping MOSFET.

[0068] Specifically, in the embodiment, the first and second transistors are PNP transistors Q1 and Q2. The emitter of Q1 is connected to the source of the first clamped MOSFET, the emitter of Q2 is connected to the source of the second clamped MOSFET, the base of Q1 is connected to the collector of Q1, and the base of Q2 is connected to the collector of Q2.

[0069] In a specific embodiment, the first transistor includes several transistors connected in parallel, with the collectors of each transistor connected together, the bases of each transistor connected together, and the emitters of each transistor connected together.

[0070] Specifically, the negative temperature coefficient module includes a first MOSFET M1 and a second MOSFET M2. The drain of the first MOSFET M1 is connected to the source of the second MOSFET M2. The collector of Q2 is connected to the source of the first MOSFET M1. The collector of Q1 is connected to the source of the second MOSFET M2. The gates of the first MOSFET M1 and the second MOSFET M2 are connected. The drain of the second MOSFET M2 is also connected to the drain of MOSFET M5 and the gate of MOSFET M1.

[0071] In one embodiment, the startup circuit includes MOSFETs M11 and M12 and capacitor C1. The source of MOSFET M12 is connected to the source of M8, the source of MOSFET M11 is connected to the gate of MOSFET M8, the gate of MOSFET M11 is connected to the drain of M12, the drain of MOSFET M12 is connected to capacitor C1, and then capacitor C1 is connected to the source of MOSFET M1. The gate of MOSFET M12 is connected to capacitor C1. The startup circuit is used to allow the core bandgap reference circuit to get rid of the zero degeneracy point, thereby ensuring the normal operation of the circuit. M11 and M12 are used as switching transistors. When the voltage is low, M11 and M12 are turned on, causing the gate potential of M8, M9, and M10 to decrease, thereby starting the circuit. When the voltage increases, M12 is turned off and the circuit stops working.

[0072] Embodiments of the present invention also provide a chip. This chip includes a bandgap reference circuit disclosed in embodiments of the present invention. This chip is, for example, a chip on an electronic detonator.

[0073] Embodiments of the present invention also provide a method for generating a reference voltage, implemented based on a low-power bandgap reference circuit disclosed in the embodiments, the method comprising the following steps:

[0074] Step 1: Obtain the negative temperature coefficient voltage by utilizing the negative temperature characteristic of the threshold voltage of the MOSFET;

[0075] Step 2: Obtain the positive temperature coefficient voltage by utilizing the positive temperature characteristic of the voltage difference between the base and emitter voltages of the transistor under different current densities;

[0076] Step 3: Obtain the current-voltage characteristics of the first and second MOSFETs under different states;

[0077] Step 4: Based on the obtained positive temperature coefficient voltage and negative temperature coefficient voltage, as well as the current and voltage characteristics of the first MOSFET and the second MOSFET under different states, obtain the reference voltage, and adjust the parameters of the first MOSFET M1 and the second MOSFET M2 so that the reference voltage meets the zero temperature coefficient voltage.

[0078] In one specific embodiment, the steps include:

[0079] Step 1: Obtain the negative temperature coefficient voltage using the negative temperature characteristic of the MOSFET threshold voltage; the negative temperature coefficient voltage is obtained as follows:

[0080] V TH =V TH0 +αT

[0081] Among them, V TH The voltage has a negative temperature coefficient, meaning it is negatively correlated with temperature. α is the temperature coefficient of the threshold voltage, and α is a negative number. (V) TH0 This represents the threshold voltage at 0K.

[0082] Step 2: Obtain the positive temperature coefficient voltage by utilizing the positive temperature characteristic of the base-emitter voltage difference of the transistor under different current densities, as follows:

[0083] Ignoring second-order effects, the current-voltage characteristics of transistors Q1 and Q2 are expressed as follows:

[0084]

[0085] This leads to the base-emitter voltage of the transistor:

[0086] Where I0 is the reverse saturation current of the transistor, V T Thermoelectric voltage;

[0087] The ratio of transistors Q1 to Q2 is M:1, and the currents flowing through transistors Q1 and Q2 are respectively I... Q1 ,I Q2 I Q2 =NI Q1 The positive temperature coefficient voltage is expressed as:

[0088]

[0089] ΔV BE =V T ln(MN)

[0090] Let ΔV BE =Vx

[0091] ΔV BE The voltage difference between the base and emitter voltages of transistors Q1 and Q2 is the positive temperature coefficient voltage.

[0092] In step 3, the current-voltage characteristics of the first MOSFET and the second MOSFET under different states are obtained as follows:

[0093] The ratio of the currents flowing through the three branches containing M8, M9, and M10 is 1:1:N, therefore we can obtain...

[0094] I D1 =2I D2

[0095] I D1 I D2 This represents the current flowing through the drain terminals of MOSFETs M1 and M2;

[0096] Ignoring second-order effects, the current-voltage characteristics of the first MOSFET M1 are expressed as follows:

[0097]

[0098] Ignoring second-order effects, the current-voltage characteristics of the second MOSFET M2 are expressed as follows:

[0099]

[0100] Where, μ n C represents the electron mobility. ox V represents the gate oxide capacitance per unit area. TH V represents the threshold voltage of the MOSFET. GS V represents the gate-source voltage of a MOSFET. DS This represents the source-drain voltage of the MOSFET, and W and L are the channel width and channel length of the MOSFET, respectively.

[0101] Combined with the drain current I of MOSFETs M1 and M2 D1 I D2 The current-voltage characteristics of the first MOSFET M1 and the current-voltage characteristics of the second MOSFET M2 are then:

[0102]

[0103]

[0104] Where V ref Reference voltage;

[0105] Step 4: Based on the obtained positive temperature coefficient voltage and negative temperature coefficient voltage, and the current-voltage characteristics of the first and second MOSFETs under different states, obtain the reference voltage:

[0106] The aforementioned step I D1 I D2 By solving the three expressions simultaneously, eliminating intermediate variables, and then solving the algebraic equation, we can obtain the expression for Verf.

[0107]

[0108] in S1 and S2 are the aspect ratios of the channels of MOSFETs M1 and M2, respectively; W and L are the channel width and channel length of the MOSFETs, respectively; V TH Voltage with a negative temperature coefficient q is the unit charge, κ is the Boltzmann constant, and V is the charge per unit area. T Thermoelectric voltage is positively correlated with temperature.

[0109] Combining the expression for negative temperature coefficient voltage, V ref Represented as:

[0110]

[0111] Where V TH0 This represents the threshold voltage at 0K.

[0112] S eff This is equivalent to setting the weight of the positive temperature coefficient voltage, S eff The value can be achieved by adjusting the parameters of the first MOSFET M1 and the second MOSFET M2, the current in the branch containing Q2, and the ratio of the number of transistors Q1 to Q2. Adjusting S... eff The value makes infinitely close to zero, making V ref It can be considered to meet the zero temperature coefficient voltage. Therefore, when designing the bandgap reference circuit of the present invention, it is only necessary to meet the channel width-to-length ratio of MOS transistors M1 and M2. It does not need to be adjusted later. The bandgap reference circuit that meets the design requirements can directly generate a reference voltage with zero temperature coefficient.

[0113] In the bandgap reference circuit of the embodiment, the negative temperature characteristic of the threshold voltage of the MOS transistor and the positive temperature characteristic of the pn junction of the transistor under different current densities are mutually compensated to obtain a zero-temperature characteristic reference voltage. This makes the circuit connection relationship different from the existing bandgap reference. Furthermore, the use of a MOS transistor operating in the linear region to replace the large resistor in the traditional bandgap reference reduces the layout area. In this invention, the relationship between the gate-source voltage and current of the MOS transistor operating in the saturation region is used to clamp the voltage. Compared with the previous bandgap references that used operational amplifiers to clamp the voltage, the power consumption of the entire circuit becomes extremely low due to the absence of operational amplifiers.

[0114] Furthermore, the bandgap reference circuit in the embodiment is easy to adjust later. It is only necessary to change the width-to-length ratio of MOS transistors M7 and M10 and the second clamping MOS transistor M4 in the second current mirror unit of the current mirror module to adjust the reference voltage. This facilitates the elimination of the difference between the bandgap reference circuit in the simulation model stage and the actual production stage, and improves the accuracy of the bandgap reference circuit.

[0115] The bandgap reference circuit of this invention provides a stable output voltage that remains almost constant within a given temperature range.

[0116] See Figure 3 The horizontal axis of the graph represents temperature, ranging from -40℃ to 100℃. The vertical axis represents voltage. This graph shows how the output voltage changes with temperature, i.e., the final derived expression. It can be seen that within the shown temperature range, the voltage changes by only 0.7275mV, while the output voltage is approximately 1179.65mV. The change is very small, with a temperature coefficient of approximately 4.4ppm / ℃. This is a very small number, meaning that for every degree Celsius change in temperature, the voltage changes by 4.4 parts per million. Therefore, it can be approximated that the output voltage does not change with temperature.

[0117] The sequence numbers of the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments. The methods disclosed in the several method embodiments provided by the present invention can be arbitrarily combined to obtain new method embodiments without conflict. The features disclosed in the several product embodiments provided by the present invention can be arbitrarily combined to obtain new product embodiments without conflict. The features disclosed in the several method or device embodiments provided by the present invention can be arbitrarily combined to obtain new method or device embodiments without conflict.

[0118] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A low-power bandgap reference circuit, comprising connected components: The starting circuit is used to generate current when power is applied, so that the entire circuit can operate away from the degeneracy point; characterized in that Also includes: A positive temperature coefficient module, comprising a first transistor, a second transistor, and a first MOS transistor M1, wherein the collector and base of the first transistor are connected to the drain of the first MOS transistor M1, and the collector and base of the second transistor are connected to the source of the first MOS transistor M1, and the difference between the base-emitter voltages of the first and second transistors generates a positive temperature coefficient voltage on the first MOS transistor M1. A clamping module, comprising a first clamping MOS transistor and a second clamping MOS transistor, wherein the sources of the first clamping MOS transistor and the drains of the first clamping MOS transistor and the second clamping MOS transistor are respectively connected, and the clamping module is used to provide a first clamping voltage and a second clamping voltage, and to make the first clamping voltage equal to the second clamping voltage; A negative temperature coefficient module, comprising a first MOSFET M1 and a second MOSFET M2, wherein the threshold voltages of the first MOSFET M1 and the second MOSFET M2 are used as negative temperature coefficient voltages. A current mirror module, which replicates the current of the branch containing the first transistor to the branch containing the negative temperature coefficient module and the branch containing the second transistor in a proportional manner. The negative temperature coefficient voltage and the positive temperature coefficient voltage are compensated according to the set weights and then superimposed together. The resulting voltage is used as the generated reference voltage. The current mirror module includes interconnected MOSFETs M8, M5, M9, M6, M10, and M7. MOSFETs M8, M5, M9, and M6 constitute a first current mirror unit, and MOSFETs M10, M7, M9, and M6 constitute a second current mirror unit. The source of MOSFET M10 is connected to the sources of MOSFETs M9 and M8, the gate of MOSFET M10 is connected to the gates of MOSFETs M9 and M8, the drain of MOSFET M10 is connected to the source of MOSFET M7, the drain of MOSFET M9 is connected to the source of MOSFET M6, the drain of MOSFET M8 is connected to the source of MOSFET M5, the gate of MOSFET M7 is connected to the gates of MOSFETs M6 and M5, the drain of MOSFET M6 is connected to the drain of the first clamping MOSFET and the gate of MOSFET M7, and the drain of MOSFET M7 is connected to the drain and gate of the second clamping MOSFET. The first and second transistors are transistors Q1 and Q2. The emitter of Q1 is connected to the source of the first clamped MOSFET, the emitter of Q2 is connected to the source of the second clamped MOSFET, the base of Q1 is connected to the collector of Q1, and the base of Q2 is connected to the collector of Q2. The drain of the first MOSFET M1 is connected to the source of the second MOSFET M2. The collector of Q2 is connected to the source of the first MOSFET M1. The collector of Q1 is connected to the source of the second MOSFET M2. The gates of the first MOSFET M1 and the second MOSFET M2 are connected. The drain of the second MOSFET M2 is also connected to the drain of MOSFET M5 and the gate of MOSFET M1.

2. A low power bandgap reference circuit according to claim 1, characterized in that: Transistors Q1 and Q2 are both PNP transistors.

3. The low-power bandgap reference circuit according to claim 2, characterized in that: The first transistor includes several transistors connected in parallel, with the collectors of each transistor connected together, the bases of each transistor connected together, and the emitters of each transistor connected together.

4. The low power bandgap reference circuit of claim 1, wherein: The startup circuit includes MOSFETs M11 and M12 and capacitor C1. The source of MOSFET M12 is connected to the source of MOSFET M8, the source of MOSFET M11 is connected to the gate of MOSFET M8, the gate of MOSFET M11 is connected to the drain of MOSFET M12, the drain of MOSFET M12 is connected to capacitor C1, and then capacitor C1 is connected to the source of MOSFET M1. The gate of MOSFET M12 is connected to capacitor C1.

5. A chip, characterized by: Includes a low-power bandgap reference circuit as described in claim 1.

6. A method of generating a reference voltage, characterized by, Based on the low-power bandgap reference circuit described in claim 1, the method includes the following steps: Step 1: Obtain the negative temperature coefficient voltage by utilizing the negative temperature characteristic of the threshold voltage of the MOSFET; Step 2: Obtain the positive temperature coefficient voltage by utilizing the positive temperature characteristic of the voltage difference between the base and emitter voltages of the transistor under different current densities; Step 3: Obtain the current-voltage characteristics of the first MOSFET M1 and the second MOSFET M2 under different states; Step 4: Based on the obtained positive temperature coefficient voltage and negative temperature coefficient voltage, as well as the current and voltage characteristics of the first MOSFET M1 and the second MOSFET M2 under different states, obtain a reference voltage. Adjust the parameters of the first MOSFET M1 and the second MOSFET M2, the current magnitude of the branch where Q2 is located, and the ratio of the number of transistors Q1 to Q2, so that the reference voltage satisfies the zero temperature coefficient voltage.

7. The method for generating a reference voltage according to claim 6, characterized in that: In step 1, the negative temperature coefficient voltage is obtained as follows: ； wherein is a negative temperature coefficient of voltage, which is negatively correlated with temperature, is a temperature coefficient of threshold voltage, is a negative number, denotes the threshold voltage at 0 K; In step 2, the positive temperature coefficient voltage is obtained as follows: Ignoring second-order effects, the current-voltage characteristics of transistors Q1 and Q2 are expressed as follows: ； Further, the base-emitter voltage of the triode is obtained: ; wherein is the reverse saturation current of the triode, is the thermal voltage; The ratio of transistors Q1 to Q2 is M:1, and the currents flowing through transistors Q1 and Q2 are respectively... , , The positive temperature coefficient voltage is expressed as: ； ； Let ; VBE is the voltage difference for the base-emitter voltage of the transistors Q1 and Q2, which is a positive temperature coefficient voltage; In step 3, the current-voltage characteristics of the first MOSFET M1 and the second MOSFET M2 under different states are obtained as follows: The ratio of the currents flowing through the three branches containing M8, M9, and M10 is 1:1:N, therefore we can obtain... ； , I1, I2represent the current flowing through the drain of MOS transistors M1, M2. Ignoring second-order effects, we obtain The current-voltage characteristics of M1 are expressed as follows: ； Ignoring second-order effects, the current-voltage characteristics of the second MOSFET M2 are expressed as follows: ； in, Indicates electron mobility. This represents the capacitance per unit area of ​​the gate oxide layer. This indicates the threshold voltage of the MOSFET. This represents the gate-source voltage of the MOSFET. This represents the source-drain voltage of the MOSFET, and W and L are the channel width and channel length of the MOSFET, respectively. the current flowing through the drain of the first MOS transistor M1 and the current flowing through the drain of the second MOS transistor M2 , , the current-voltage characteristic of the first MOS transistor M1 and the current-voltage characteristic of the second MOS transistor M2, in turn: ； ； wherein Vref is a reference voltage; In step 4, based on the obtained positive temperature coefficient voltage and negative temperature coefficient voltage, and the current-voltage characteristics of the first MOSFET M1 and the second MOSFET M2 under different states, a reference voltage is obtained: ； in , S1 and S2 are the aspect ratios of the channels of MOSFETs M1 and M2, respectively, and W and L are the channel width and channel length of the MOSFETs, respectively. Voltage with a negative temperature coefficient q is the unit charge. Boltzmann's constant, Thermoelectric voltage is positively correlated with temperature. In conjunction with the expression of the negative temperature coefficient voltage, is expressed as: ； wherein Vth(0K) represents the threshold voltage at 0K, ; adjusting the value of tends to zero, so that is a zero-temperature coefficient voltage.

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