Display panel and display device

Abstract

This invention discloses a display panel and a display device. The display panel includes: multiple pixel circuits, multiple multiplexed signal lines, and multiple multiplexing modules. At least one row of pixel circuits is connected to multiplexed signal lines extending along a first direction. Each row of pixel circuits includes multiple pixel circuits arranged along the first direction. The multiplexing module is connected to a corresponding multiplexed signal line. The multiplexing module includes a first multiplexing unit and a second multiplexing unit. The multiplexing module is used to transmit one or more of a reset voltage, a data voltage, and a first power supply voltage to the multiplexed signal line. The first multiplexing unit and the second multiplexing unit of the same multiplexing module are respectively connected to opposite ends of the same multiplexed signal line along the first direction. The first multiplexing unit and the second multiplexing unit of the same multiplexing module simultaneously transmit the same voltage to the multiplexed signal line from opposite ends, which can reduce the voltage drop on the multiplexed signal line, improve the voltage uniformity on the multiplexed signal line, and reduce power consumption.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to display panels and display devices. Background Technology

[0002] Organic light-emitting diodes (OLEDs) are a type of current-driven light-emitting device. Due to their characteristics such as self-emission, fast response, wide viewing angle, and ability to be fabricated on flexible substrates, they are increasingly being used in high-performance display fields such as flexible display panels.

[0003] Display panels typically include several sub-pixels located in the display area, each driven by a pixel circuit. Voltage on each voltage line is transmitted to the pixel circuits in each row. However, as displays become increasingly larger, voltage drops occur on the voltage lines, resulting in different voltages transmitted to different row pixel circuits. This leads to problems such as poor brightness uniformity and high overall power consumption in the display panel. Summary of the Invention

[0004] The present invention provides a display panel and a display device to improve voltage uniformity on multiplexed signal lines, reduce the number of signal lines in the display area, and improve the resolution of the display panel.

[0005] According to one aspect of the present invention, a display panel is provided, comprising: a plurality of pixel circuits, a plurality of multiplexed signal lines, and a plurality of multiplexing modules;

[0006] At least one row of pixel circuits is connected to a multiplexed signal line extending along a first direction; each row of pixel circuits includes multiple pixel circuits arranged along the first direction, and a multiplexing module is connected to the corresponding multiplexed signal line. The multiplexing module includes a first multiplexing unit and a second multiplexing unit. The multiplexing module is used to transmit one or more of a reset voltage, a data voltage, and a first power supply voltage to the multiplexed signal line. The first multiplexing unit and the second multiplexing unit of the same multiplexing module are respectively connected to the two opposite ends of the same multiplexed signal line along the first direction.

[0007] Optionally, the first multiplexing unit is located in the first border area of ​​the display panel, and the second multiplexing unit is located in the second border area of ​​the display panel. The first border area and the second border area are opposite sides of the display panel along the first direction.

[0008] Optionally, the first border area and the second border area are the top border area and the bottom border area, respectively, or the first border area and the second border area are the left border area and the right border area, respectively.

[0009] Optionally, the first multiplexing unit is used to transmit the reset voltage and the first power supply voltage to the multiplexed signal line in a time-division manner, and the second multiplexing unit is used to transmit the reset voltage, the data voltage and the first power supply voltage to the multiplexed signal line in a time-division manner, and the first multiplexing unit and the second multiplexing unit transmit the reset voltage or transmit the first power supply voltage simultaneously.

[0010] Optionally, the display panel includes a display area, pixel circuitry, and multiplexed signal lines located within the display area. The display panel also includes a power bus and a reset bus.

[0011] The power bus is connected to the multiplexing module and is used to provide the first power supply voltage to the multiplexing module.

[0012] The reset bus is connected to the multiplexing module and is used to provide reset voltage to the multiplexing module;

[0013] The multiplexing module also connects to the data voltage.

[0014] Optionally, the power bus is arranged around the display area, and / or the reset bus is arranged around the display area;

[0015] Optionally, the display panel includes a substrate, and the power bus is projected vertically onto the substrate as a closed pattern surrounding the display area.

[0016] Optionally, the display panel includes a substrate, and the vertical projection of the reset bus onto the substrate is a closed pattern arranged around the display area.

[0017] Optionally, the display panel may also include a non-display area surrounding the display area, where the multiplexing module is located;

[0018] Optionally, the power bus and reset bus are located in the non-display area.

[0019] Optionally, the first multiplexing unit includes a first transistor and a second transistor. The first terminal of the first transistor is electrically connected to the power bus located in the first frame area, the second terminal of the first transistor is electrically connected to the corresponding multiplexing signal line, and the gate of the first transistor is electrically connected to the first power control signal line.

[0020] The first terminal of the second transistor is electrically connected to the reset bus located in the first frame region, the second terminal of the second transistor is electrically connected to the corresponding multiplexed signal line, and the gate of the second transistor is electrically connected to the reset signal control line.

[0021] Optionally, the first power control signal line is arranged around the display area, and / or the reset signal control line is arranged around the display area.

[0022] Optionally, the vertical projection of the first power control signal line onto the substrate is a closed pattern surrounding the display area; the vertical projection of the reset signal control line onto the substrate is a closed pattern surrounding the display area.

[0023] Optionally, the second multiplexing unit includes a third transistor, a fourth transistor, and a selection circuit. The selection circuit includes an input terminal and at least two output terminals. The output terminals of the selection circuit are electrically connected to the multiplexed signal lines. Different output terminals of the same selection circuit are electrically connected to different multiplexed signal lines. The input terminal of the selection circuit is used to input data voltage.

[0024] The first terminal of the third transistor is electrically connected to the power bus located in the second frame area, the second terminal of the third transistor is electrically connected to the corresponding multiplexed signal line, and the gate of the third transistor is electrically connected to the first power control signal line; the first terminal of the fourth transistor is electrically connected to the reset bus located in the second frame area, the second terminal of the fourth transistor is electrically connected to the corresponding multiplexed signal line, and the gate of the fourth transistor is electrically connected to the reset signal control line.

[0025] Optionally, the selection circuit includes at least two fifth transistors, each corresponding to one of the output terminals of the selection circuit. The first terminal of the fifth transistor is connected to the data voltage, and the second terminal of the fifth transistor serves as the output terminal of the corresponding selection circuit. The gate of the fifth transistor is electrically connected to the data transmission control signal line, and the data transmission control signal lines connected to the gates of the various fifth transistors in the selection circuit are different.

[0026] Optionally, the third and fourth transistors included in the second multiplexing unit are located on the side of the selection circuit closer to the display area.

[0027] Optionally, the second multiplexing unit includes a sixth transistor, a seventh transistor, and an eighth transistor. The first terminal of the sixth transistor is electrically connected to the power bus located in the second frame area, the second terminal of the sixth transistor is electrically connected to the corresponding multiplexed signal line, and the gate of the sixth transistor is electrically connected to the first power control signal line. The first terminal of the seventh transistor is electrically connected to the reset bus located in the second frame area, the second terminal of the seventh transistor is electrically connected to the corresponding multiplexed signal line, and the gate of the seventh transistor is electrically connected to the reset signal control line. The first terminal of the eighth transistor is connected to the data voltage, the second terminal of the eighth transistor is electrically connected to the corresponding multiplexed signal line, and the gate of the eighth transistor is connected to the control signal line.

[0028] Optionally, the pixel circuit includes a driving module, a compensation module, a reset module, a storage module, a light emission control module, and a light emission module, with the first end of the driving module electrically connected to the corresponding multiplexed signal line;

[0029] The reset module is connected between the first terminal of the drive module and the control terminal of the drive module, and is used to transmit the reset voltage to the control terminal of the drive module;

[0030] The compensation module is connected between the second end of the drive module and the control end of the drive module. The compensation module is used to transmit the compensation voltage to the control end of the drive module based on the data voltage.

[0031] The storage module is connected between the control terminal of the drive module and the power line, and is used to store the voltage at the control terminal of the drive module;

[0032] The light-emitting control module is connected between the second end of the driver module and the light-emitting module. The driver module generates a driving current based on the voltage at the control end of the driver module to drive the light-emitting module to emit light.

[0033] Optionally, the display panel also includes multiple power lines extending along a second direction, the extension direction of the power lines intersecting with the extension direction of the multiplexed signal lines, the power lines being connected to a power bus for providing a first power supply voltage, and one power line being connected to the storage module of each pixel circuit in at least one row of pixel circuits.

[0034] Insulation is provided between power lines and multiplexed signal lines.

[0035] According to another aspect of the present invention, a display device is provided, comprising the display panel described above.

[0036] The display panel provided in this embodiment of the invention includes: multiple pixel circuits, multiple multiplexed signal lines, and multiple multiplexing modules. Each multiplexing module includes a first multiplexing unit and a second multiplexing unit. The multiplexing module transmits one or more of a reset voltage, a data voltage, and a first power supply voltage to the multiplexed signal lines. The first and second multiplexing units of a multiplexing module are respectively connected to opposite ends of the same multiplexed signal line along a first direction. By simultaneously transmitting the same voltage from opposite ends of the multiplexed signal line, the first and second multiplexing units of the same multiplexing module can reduce the voltage drop of the reset voltage, data voltage, or first power supply voltage on the multiplexed signal line, improve voltage uniformity on the multiplexed signal line, reduce power consumption, and improve display uniformity.

[0037] Multiplexing signal lines transmits one or more of the reset voltage, data voltage, and first power supply voltage to the pixel circuit, reducing the number of signal lines in the display area and the layout area occupied by the signal lines, which is beneficial to improving the resolution of the display panel.

[0038] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 This is a schematic diagram of the structure of a display panel;

[0041] Figure 2 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention;

[0042] Figure 3 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention;

[0043] Figure 4 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention;

[0044] Figure 5 This is a schematic diagram of the circuit structure in a display panel provided by an embodiment of the present invention;

[0045] Figure 6 This is a driving timing diagram of a display panel provided in an embodiment of the present invention;

[0046] Figure 7 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention;

[0047] Figure 8 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0048] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0049] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0050] As described in the background section, display panels suffer from poor brightness uniformity and high overall power consumption. The inventors discovered that the cause is a voltage drop on the voltage line, which results in different voltages input to each pixel circuit, leading to different driving currents generated by the pixel circuits and different luminous brightness of the sub-pixels. Figure 1 This is a schematic diagram of the structure of a display panel, for reference. Figure 1 The display panel includes a display area AA, within which multiple pixel circuits 1 are arranged. The display panel includes multiple data lines L1, reset lines L2, and voltage lines L3. For example, the pixel circuits 1 are arranged in an array, with one column of pixel circuits 1 connected to one data line L1 and one voltage line L3, and one row of pixel circuits 1 connected to one reset line L2. Assuming the display panel has k rows and h columns of pixel circuits 1, each column of pixel circuits 1 outputs a first power supply voltage through one voltage line L3, meaning there are a total of h voltage lines L3, with k pixel circuits 1 connected sequentially to each voltage line L3. In an ideal scenario where the impedance of voltage line L3 is negligible, the current flowing through each pixel circuit 1 is the same. However, in reality, voltage line L3 inevitably has a certain trace impedance. Furthermore, as the display panel screen size increases and the resolution rises, voltage line L3 becomes longer and its impedance increases, resulting in a voltage drop (IR Drop) on voltage line L3. The voltage on the side of voltage line L3 closer to the power chip area in the display panel is higher than the voltage on the side farther away from the power chip. This leads to different voltages transmitted to pixel circuits 1 at different locations, resulting in poor brightness uniformity and high power consumption in the display panel. Similarly, a voltage drop can also exist on the reset line L2. Here, h is the number of columns in pixel circuit 1, and k is the number of rows in pixel circuit 1; both h and k are greater than 0.

[0051] To address the aforementioned technical problems, this invention provides a novel display panel. Figure 2 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention, with reference to... Figure 2The display panel includes: multiple pixel circuits 1, multiple multiplexed signal lines L4, and multiple multiplexed modules;

[0052] At least one row of pixel circuits is connected to a multiplexed signal line L4 extending along the first direction X; each row of pixel circuits includes multiple pixel circuits 1 arranged along the first direction X; a multiplexing module is connected to the corresponding multiplexed signal line L4, and the multiplexing module includes a first multiplexing unit 21 and a second multiplexing unit 22. The multiplexing module is used to transmit one or more of a reset voltage Vref, a data voltage Vdata, and a first power supply voltage Vdd to the multiplexed signal line L4. The first multiplexing unit 21 and the second multiplexing unit 22 of the same multiplexing module are respectively connected to the two opposite ends of the same multiplexed signal line L4 along the first direction X.

[0053] The pixel circuit 1 can be used to generate a driving current based on the reset voltage Vref, the data voltage Vdata and the first power supply voltage Vdd, so as to drive the light-emitting module included in the pixel circuit 1 to emit light for display.

[0054] The display panel includes a display area AA, and may also include a non-display area NAA surrounding the display area AA. Multiplexed signal line L4 and pixel circuit 1 are both located in the display area AA. Pixel circuit 1 includes a light-emitting module, which emits light according to a generated driving current to achieve the display function of the display panel. The multiplexed module is located in the non-display area NAA to avoid obstructing the light emitted from the display area AA.

[0055] For example, the pixel circuits 1 are arranged in an array. Multiplexed signal lines L4 can extend along a first direction X. Multiple multiplexed signal lines L4 can extend along the first direction X and be arranged along a second direction Y. The first direction X intersects the second direction Y. Optionally, the first direction X is perpendicular to the second direction Y. Optionally, pixel circuits 1 located in the same row are connected to the same multiplexed signal line L4, while pixel circuits 1 in different rows are connected to different multiplexed signal lines L4. If the multiplexed signal line L4 is used at least to transmit the data voltage Vdata, pixel circuits 1 located in the same column are connected to the same multiplexed signal line L4, while pixel circuits 1 in different columns are connected to different multiplexed signal lines L4. The multiplexed signal lines L4 can be electrically connected one-to-one with multiplexing modules. For example, the pixel circuit 1 includes a reset module, a driving module, a light-emitting module, a compensation module, and a light-emitting control module, wherein the driving module, the light-emitting control module, and the light-emitting module are connected between a first power supply terminal and a second power supply terminal of the pixel circuit, the second power supply terminal is used to access a second power supply voltage, and the first power supply terminal is connected to the multiplexed signal line L4. The pixel circuit's operation includes a reset phase, a data writing and threshold compensation phase, and a light-emitting phase. The driving module includes transistors, whose threshold voltages can shift due to factors such as temperature and current. Threshold voltage compensation is performed during the data writing and compensation phases to improve display uniformity. In the reset phase, the multiplexing module transmits the reset voltage Vref to the multiplexing signal line L4 to reset the driving module's control terminal. In the data writing and threshold compensation phase, the multiplexing module transmits the data voltage Vdata to the multiplexing signal line L4. The compensation module transmits a compensation voltage to the driving module's control terminal based on the data voltage Vdata, achieving data writing and threshold voltage compensation. In the light-emitting phase, the multiplexing module transmits the first power supply voltage Vdd to the multiplexing signal line L4, thus forming a flow path between the first and second power supply terminals for the driving current generated by the driving module based on the data voltage, thereby driving the light-emitting module to emit light. During the operation of the display panel, the multiplexing module transmits at least two of the reset voltage Vref, data voltage Vdata, and first power supply voltage Vdd to the multiplexing signal line L4 in a time-division manner. This ensures that at least two of the three voltages are transmitted to the pixel circuit 1 via the same reset signal line L4, reducing the number of signal lines in the display area AA and improving high-resolution display. Pixel circuits 1 in the same column or row can share the same multiplexing module. Compared to existing technologies where each pixel circuit is a 7T1C circuit (i.e., each pixel circuit includes 7 transistors and 1 capacitor), this embodiment simplifies the structure of the pixel circuit 1 within the display area AA by externalizing some transistors and sharing them in the non-display area NAA. This reduces the number of transistors in each pixel circuit 1 within the display area AA, thus improving the resolution of the display panel.

[0056] The multiplexed signal line L4 can extend along the row direction of the pixel circuit 1 or along the column direction of the pixel circuit 1; this embodiment does not specifically limit this. For example, the first multiplexing unit 21 is used for time-division multiplexing of the reset voltage Vref, data voltage Vdata, and first power supply voltage Vdd, and the second multiplexing unit 22 is also used for time-division multiplexing of the reset voltage Vref, data voltage Vdata, and first power supply voltage Vdd. Alternatively, the first multiplexing unit 21 is only used for time-division multiplexing of the reset voltage Vref and first power supply voltage Vdd, and the second multiplexing unit 22 is used for time-division multiplexing of the reset voltage Vref, data voltage Vdata, and first power supply voltage Vdd. The second multiplexing unit 22 is closer to the driver chip that outputs the data voltage than the first multiplexing unit 21; therefore, only the second multiplexing unit 22 needs to be configured to transmit the data voltage Vdata.

[0057] When transmitting signals on the multiplexed signal line L4, voltage drops can occur. For example, especially when the display panel area is large, the length of the signal line transmitting the reset voltage Vref or the first power supply voltage Vdd is long, resulting in a large voltage drop on the signal line. In this embodiment, by having the first multiplexing unit 21 and the second multiplexing unit 22 of the same multiplexing module simultaneously transmit the same voltage to the multiplexed signal line L4 from opposite ends, the voltage drop of the reset voltage Vref, data voltage Vtata, or first power supply voltage Vdd on the multiplexed signal line L4 can be reduced, improving the voltage uniformity on the multiplexed signal line, reducing power consumption, and improving the uniformity of the display.

[0058] The technical solution provided by this invention allows the first and second multiplexing units of the same multiplexing module to simultaneously transmit the same voltage to the multiplexing signal line from opposite ends. This reduces the voltage drop of the reset voltage, data voltage, or first power supply voltage on the multiplexing signal line, improves voltage uniformity on the multiplexing signal line, reduces power consumption, and improves display uniformity. The multiplexing signal line transmits one or more of the reset voltage, data voltage, and first power supply voltage to the pixel circuit, thus reducing the number of signal lines transmitting these voltages to the same pixel circuit in the display area of ​​the display panel—for example, from three to one. This reduces the number of signal lines in the display area and the layout area occupied by the signal lines, which is beneficial for improving the resolution of the display panel.

[0059] Continue to refer to Figure 2 Optionally, the first multiplexing unit 21 is located in the first border area of ​​the display panel, and the second multiplexing unit 22 is located in the second border area of ​​the display panel. The first border area and the second border area are two opposite sides of the display panel along the first direction X.

[0060] Optionally, the first border area and the second border area can be the top border area and the bottom border area, respectively, or the first border area and the second border area can be the left border area and the right border area, respectively.

[0061] Both the first and second border areas are located in the non-display area (NAA) of the display panel. For example, when the driver chip providing data voltage to the pixel circuit 1 is located in the lower border area of ​​the display panel, the first border area is the upper border area, and the second border area is the lower border area. When the driver chip providing data voltage to the pixel circuit 1 is located in the left or right border area of ​​the display panel, the first border area is the left border area, and the second border area is the right border area. The display panel includes multiple display frames, and the first multiplexing unit 21 and the second multiplexing unit 22 of the same multiplexing module can be controlled to work alternately in different frames. For example, in odd-numbered frames, the first multiplexing unit 21 is used to transmit the reset voltage Vref, data voltage Vdata, and first power supply voltage Vdd to the multiplexing signal line L4 in a time-division multiplexing manner; in even-numbered frames, the second multiplexing unit 22 is used to transmit the reset voltage Vref, data voltage Vdata, and first power supply voltage Vdd to the multiplexing signal line L4 in a time-division multiplexing manner. The first multiplexing unit 21 and the second multiplexing unit 22 of the same multiplexing module work alternately in different display frames to transmit voltage, which can reduce the impact of voltage drop on the multiplexing signal line L4 and improve the uniformity of display.

[0062] Continue to refer to Figure 2 Optionally, the first multiplexing unit 21 is used to transmit the reset voltage Vref and the first power supply voltage Vdd to the multiplexed signal line L4 in a time-division manner, and the second multiplexing unit 22 is used to transmit the reset voltage Vref, the data voltage Vdata and the first power supply voltage Vdd to the multiplexed signal line L4 in a time-division manner, and the first multiplexing unit 21 and the second multiplexing unit 22 transmit the reset voltage Vref or the first power supply voltage Vdd simultaneously.

[0063] The second multiplexing unit 22 is directly or indirectly connected to the driver chip that provides the data voltage Vdata, and the second multiplexing unit 22 and the driver chip are located on the same side of the multiplexed signal line L4. Therefore, the data voltage Vdata can be transmitted to the multiplexed signal line L4 only through the second multiplexing unit 22, simplifying the layout of the signal line. During the reset phase, the first multiplexing unit 21 and the second multiplexing unit 22 of the same multiplexing module simultaneously transmit the reset voltage Vref to the connected multiplexed signal line L4 to reset the pixel circuit 1. During the data writing and threshold compensation phase, the second multiplexing unit 22 transmits the data voltage to the reset signal line L4 to complete the writing of the data voltage. During the light emission phase, the first multiplexing unit 21 and the second multiplexing unit 22 of the same multiplexing module simultaneously transmit the first power supply voltage Vdd to the connected multiplexed signal line L4 to form a path for the driving current to flow, thereby driving the light emission module to emit light according to the driving current. When transmitting signals on the multiplexed signal line L4, a voltage drop occurs. This is especially noticeable when the display panel area is large, as the length of the signal line transmitting the reset voltage Vref or the first power supply voltage Vdd is longer, resulting in a significant voltage drop on the signal line. In this embodiment, by simultaneously transmitting the reset voltage Vref or the first power supply voltage Vdd to the multiplexed signal line L4 through the first multiplexing unit 21 and the second multiplexing unit 22 of the same multiplexing module, the voltage drop of the reset voltage Vref or the first power supply voltage Vdd on the multiplexed signal line L4 can be reduced, power consumption can be lowered, and the uniformity of the display can be improved.

[0064] Figure 3 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention, with reference to... Figure 3 Optionally, the display panel includes a display area AA, pixel circuit 1 and multiplexed signal line L4 located in the display area AA, and the display panel also includes a power bus EL and a reset bus VF.

[0065] The power bus EL is connected to the multiplexing module and is used to provide the first power supply voltage to the multiplexing module;

[0066] The reset bus VF is connected to the multiplexing module and is used to provide the reset voltage to the multiplexing module;

[0067] The multiplexing module also connects to the data voltage.

[0068] Each multiplexing module is connected to the power bus EL, on which a first power supply voltage is fixedly transmitted. The multiplexing module transmits the power supply voltage from the power bus EL to the multiplexed signal line L4 during the light-emitting phase. Each multiplexing module is also connected to the reset bus VF, on which a reset voltage is fixedly transmitted. The multiplexing module transmits the reset voltage from the reset bus VF to the multiplexed signal line L4 during the reset phase. The multiplexing module also receives a data voltage; this can be done directly or indirectly through a circuit, and this embodiment does not specifically limit this. Optionally, the first multiplexing unit 21 and the second multiplexing unit 22 of the same multiplexing module are both connected to the power bus EL. Optionally, the first multiplexing unit 21 and the second multiplexing unit 22 of the same multiplexing module are both connected to the reset bus VF. Optionally, the power bus EL may include multiple first trace segments extending along the second direction Y and located in the first and second border areas respectively. The first multiplexing unit 21 and the second multiplexing unit 22 of the same multiplexing module are electrically connected to the first trace segments located in their respective border areas. Optionally, the reset bus VF may include multiple third traces extending along the second direction Y and located in the first and second border areas respectively. The first multiplexing unit 21 and the second multiplexing unit 22 of the same multiplexing module are electrically connected to the third traces located in their respective border areas.

[0069] Continue to refer to Figure 3 Optionally, the power bus EL and reset bus VF are located in the non-display area NAA. Having the power bus EL and reset bus VF in the non-display area NAA simplifies the routing layout of the display area AA, reduces the number of traces within the display area AA, and helps improve the resolution of the display panel.

[0070] Continue to refer to Figure 3 Optionally, the power bus EL is configured to surround the display area AA, and / or the reset bus VF is configured to surround the display area AA.

[0071] To reduce the voltage drop of the reset voltage or the first power supply voltage on the multiplexed signal line L4, the multiplexing module includes a first multiplexing unit and a second multiplexing unit located on both sides of the multiplexing signal line. This allows the two ends of the multiplexing signal line L4 to simultaneously write voltage to the pixel circuits in the same column when transmitting the reset voltage or the first power supply voltage. The power bus EL and the reset bus VF are both positioned around the display area AA, facilitating the connection between the first and second multiplexing units in the multiplexing module and the power bus, thus simplifying the wiring layout.

[0072] Continue to refer to Figure 3 Optionally, the display panel includes a substrate, and the power bus EL is projected vertically onto the substrate as a closed pattern surrounding the display area AA.

[0073] For example, the substrate can be a rigid substrate formed of at least one polymer material such as glass or glass fiber reinforced plastic, or a flexible substrate formed of at least one material such as polyimide (PI), polyethylene naphthalate (PEN), or polyethylene terephthalate (PET). The substrate serves a supporting function, providing support for the upper structure in the display panel, such as the driving circuit layer where the pixel circuit is located. The closed shape can be rectangular, circular, elliptical, rounded rectangle, etc., and this embodiment does not specifically limit it. Since the power bus EL is located in the non-display area NAA of the display panel, the width of the power bus EL can be relatively large to reduce the voltage drop of the first power supply voltage transmitted on the power bus EL. The width of the power bus EL can be greater than the width of the multiplexed signal line L4.

[0074] Continue to refer to Figure 3 Optionally, the display panel includes a substrate, and the vertical projection of the reset bus VF onto the substrate is a closed pattern set around the display area AA.

[0075] The vertical projection of the reset bus VF onto the substrate can be rectangular, circular, elliptical, or rounded rectangle, etc., and this embodiment does not impose a specific limitation on it. Since the reset bus VF is located in the non-display area NAA of the display panel, the width of the reset bus VF can be relatively large to reduce the voltage drop of the reset voltage transmitted on the reset bus VF. The width of the reset bus VF can be greater than the width of the multiplexed signal line L4.

[0076] The reset bus VF and the power bus EL can be located in different layers of the display panel. Therefore, the vertical projections of the reset bus VF and the power bus EL on the substrate can overlap or not; this embodiment does not impose specific limitations. When the reset bus VF and the power bus EL are located in the same layer of the display panel, their vertical projections do not overlap, avoiding voltage crosstalk between different signal lines. Optionally, the vertical projection of the reset bus VF on the substrate can be located inside or outside the vertical projection of the power bus EL on the substrate.

[0077] Regarding the specific structures of the first multiplexing unit and the second multiplexing unit, this embodiment provides several different structures, which can be found in the following descriptions. Figure 3 and Figure 4 .

[0078] Continue to refer to Figure 3 Optionally, the first multiplexing unit 21 includes a first transistor T1 and a second transistor T2. The first terminal of the first transistor T1 is electrically connected to the power bus EL located in the first frame area, the second terminal of the first transistor T1 is electrically connected to the corresponding multiplexing signal line L4, and the gate of the first transistor T1 is electrically connected to the first power control signal line ELG.

[0079] The first terminal of the second transistor T2 is electrically connected to the reset bus VF located in the first border area, the second terminal of the second transistor T2 is electrically connected to the corresponding multiplexed signal line L4, and the gate of the second transistor T2 is electrically connected to the reset signal control line VFG.

[0080] The first transistor T1 can be either an N-type or a P-type transistor, and the second transistor T2 can also be either an N-type or a P-type transistor; this embodiment does not specifically limit this. During the reset phase, the signal on the first power control signal line ELG controls the first transistor T1 to turn off, and the signal on the reset signal control line VFG controls the second transistor T2 to turn on. The turned-on second transistor T2 transmits the reset voltage from the connected reset bus VF to the multiplexed signal line L4. During the light-emitting phase, the signal on the first power control signal line ELG controls the first transistor T1 to turn on, and the signal on the reset signal control line VFG controls the second transistor T2 to turn off. The turned-on first transistor T1 transmits the first power supply voltage from the connected power bus EL to the multiplexed signal line L4. The first transistor T1 and the second transistor T2 achieve time-division multiplexing of the reset voltage and the first power supply voltage to the multiplexed signal line L4. The first multiplexing unit includes two transistors, has a simple structure, and is easy to implement.

[0081] Optionally, the first power control signal line ELG is set around the display area AA, and / or the reset signal control line VFG is set around the display area AA.

[0082] Optionally, the first power control signal line ELG, when projected vertically onto the substrate, is a closed pattern surrounding the display area AA. Optionally, the reset signal control line VFG, when projected vertically onto the substrate, is a closed pattern surrounding the display area AA.

[0083] Optionally, the vertical projection of the first power control signal line ELG onto the substrate may be located outside the vertical projections of the reset bus VF and the power bus EL onto the substrate. Optionally, the vertical projection of the reset signal control line VFG onto the substrate may be located outside the vertical projections of the reset bus VF and the power bus EL onto the substrate.

[0084] Continue to refer to Figure 3 Optionally, the second multiplexing unit 22 includes a third transistor T3, a fourth transistor T4, and a selection circuit 221. The selection circuit 221 includes an input terminal IN and at least two output terminals U1. The output terminal U1 of the selection circuit 221 is electrically connected to the multiplexing signal line L4. Different output terminals of the same selection circuit 221 are electrically connected to different multiplexing signal lines L4. The input terminal IN of the selection circuit 221 is used to input the data voltage.

[0085] The first terminal of the third transistor T3 is electrically connected to the power bus EL located in the second frame area, the second terminal of the third transistor T3 is electrically connected to the corresponding multiplexed signal line L4, and the gate of the third transistor T3 is electrically connected to the first power control signal line ELG; the first terminal of the fourth transistor T4 is electrically connected to the reset bus VF located in the second frame area, the second terminal of the fourth transistor T2 is electrically connected to the corresponding multiplexed signal line L4, and the gate of the fourth transistor T4 is electrically connected to the reset signal control line VFG.

[0086] The first multiplexing unit 21 is used to transmit the reset voltage and the first power supply voltage to the multiplexed signal line L4 in a time-division multiplexing manner. The second multiplexing unit 22 is used to transmit the reset voltage, data voltage, and the first power supply voltage to the multiplexed signal line L4 in a time-division multiplexing manner. The first multiplexing unit 21 is located in the first border area, and the second multiplexing unit 22 is located in the second border area. The first border area and the second border area are respectively the upper border area and the lower border area, or the first border area and the second border area are respectively the left border area and the right border area. The third transistor T3 can be an N-type transistor or a P-type transistor, and the fourth transistor T4 can be an N-type transistor or a P-type transistor. This embodiment does not specifically limit this. It is worth noting that the channel type of the first transistor T1 is the same as the channel type of the third transistor T3, and the channel type of the second transistor T2 is the same as the channel type of the fourth transistor T4. During the reset phase, the signal on the first power control signal line ELG controls the third transistor T3 to turn off, and the signal on the reset signal control line VFG controls the fourth transistor T4 to turn on. The selection circuit 221 turns off, and the turned-on fourth transistor T4 transmits the reset voltage from the connected reset bus VF to the multiplexed signal line L4. During the data writing and threshold compensation phase, the signal on the first power control signal line ELG controls the third transistor T3 to turn off, the signal on the reset signal control line VFG controls the fourth transistor T4 to turn off, and each selection circuit 221 transmits the data voltage input to the corresponding multiplexed signal line L4 at the corresponding output, thus writing the data voltage to the pixel circuit 1. The same selection circuit 221 transmits multiple data voltages input to the same input to multiple multiplexed signal lines L4 at their respective outputs in a time-division manner. During the light-emitting stage, the selection circuit 221 is turned off, the signal on the first power control signal line ELG controls the third transistor T3 to turn on, and the signal on the reset signal control line VFG controls the fourth transistor T4 to turn off. The turned-on third transistor T3 transmits the first power supply voltage on the connected power bus EL to the multiplexed signal line L4.

[0087] Continue to refer to Figure 3Optionally, the selection circuit 221 includes at least two fifth transistors T5, each of which corresponds to one of the output terminals of the selection circuit 221. The first terminal of the fifth transistor T5 is connected to the data voltage, and the second terminal of the fifth transistor T5 serves as the output terminal of the corresponding selection circuit 221. The gate of the fifth transistor T5 is electrically connected to the data transmission control signal line, and the data transmission control signal lines connected to the gates of the various fifth transistors T5 included in the selection circuit 221 are different.

[0088] For example, if the selection circuit 221 includes two fifth transistors T5, then the display panel includes two data transmission control signal lines, namely the first data transmission control signal line MUX1 and the second data transmission control signal line MUX2. The gate of one of the two fifth transistors T5 included in the selection circuit 221 is electrically connected to the first data transmission control signal line MUX1, and the gate of the other transistor is electrically connected to the second data transmission control signal line MUX2.

[0089] During the reset and light-emitting phases, each data transmission control signal line controls the corresponding connected fifth transistor T5 to turn off. During the data writing and threshold compensation phases, firstly, the first data transmission control signal line MUX1 controls the fifth transistor T5 connected to the first data transmission control signal line MUX1 in each selection circuit 221 to turn on, and the second data transmission control signal line MUX2 controls the fifth transistor T5 connected to the second data transmission control signal line in each selection circuit 221 to turn off. Each turned-on fifth transistor T5 transmits the data voltage connected to its respective selection circuit 221 to the corresponding multiplexed signal line L4. Then, the first data transmission control signal line MUX1 controls the fifth transistor T5 connected to the first data transmission control signal line MUX1 in each selection circuit 221 to turn off, and the second data transmission control signal line MUX2 controls the fifth transistor T5 connected to the second data transmission control signal line MUX1 in each selection circuit 221 to turn on. Each turned-on fifth transistor T5 transmits the data voltage connected to its respective selection circuit 221 to the corresponding multiplexed signal line L4, enabling pixel circuits 1 in different columns of a row to write corresponding data voltages.

[0090] exist Figure 3In the display panel shown, the multiplexing module includes a first multiplexing unit 21 and a second multiplexing unit 22. The first multiplexing unit 21 includes a first transistor T1 and a second transistor T2. The second multiplexing unit 22 includes a third transistor T3, a fourth transistor T4, and multiple fifth transistors T5. During the reset phase, the signal on the first power control signal line ELG controls the first transistor T1 and the third transistor T3 to turn off. Each data transmission control signal line controls the corresponding fifth transistor T5 to turn off. The signal on the reset signal control line VFG controls the second transistor T2 and the fourth transistor T4 to turn on. The turned-on second transistor T2 and the fourth transistor T4 control the reset voltage on the reset bus VF to be transmitted simultaneously from the first and second border areas of the display panel to the multiplexing signal line L4. This enables the reset voltage to be written simultaneously from both ends of the multiplexing signal line L4 to a connected column of pixel circuits 1, reducing the voltage drop on the multiplexing signal line L4, improving the uniformity of the reset voltage on the multiplexing signal line L4, improving display uniformity, and reducing power consumption. During the data writing and threshold compensation phase, the signal on the first power control signal line ELG controls the first transistor T1 and the third transistor T3 to turn off, the signal on the reset signal control line VFG controls the second transistor T2 and the fourth transistor T4 to turn off, and each data transmission control signal line controls the corresponding fifth transistor T5 to turn on in a time-division manner. The turned-on fifth transistor T5 transmits the data voltage to the corresponding multiplexed signal line L4. During the light-emitting stage, the signal on the reset signal control line VFG controls the second transistor T2 and the fourth transistor T4 to turn off, and each data transmission control signal line controls the corresponding fifth transistor T5 to turn off. The signal on the first power control signal line ELG controls the first transistor T1 and the third transistor T3 to turn on. The turned-on first transistor T1 and third transistor T3 control the first power supply voltage on the power bus EL to be transmitted simultaneously from the first and second border areas of the display panel to the multiplexed signal line L4. This enables the first power supply voltage to be written simultaneously from both ends of the multiplexed signal line L4 to a connected column of pixel circuits 1, reducing the voltage drop on the multiplexed signal line L4, improving the uniformity of the first power supply voltage on the multiplexed signal line L4, improving display uniformity, and reducing power consumption.

[0091] The input terminal of the selection circuit 221 is electrically connected to the data output terminal of the driver chip, and the output terminal of the selection circuit 221 is connected to multiple signal lines that transmit data voltages. In this embodiment, the output terminal of the selection circuit 221 is electrically connected to each of the multiplexed signal lines. When the number of ports of the data output terminal of the driver chip is limited, the selection circuit 221 is set in the display panel so that multiple multiplexed signal lines can be set in the display panel. When the number of ports of the data output terminal of the driver chip is limited, the display panel is already equipped with a selection circuit. In this embodiment, the second multiplexing unit directly uses the selection circuit 221 set in the display panel to control the data voltage to be written only during the data writing and threshold compensation stages, realizing the time-division writing of the reset voltage, the first power supply voltage, and the data voltage. There is no need to set up an additional circuit to control the data voltage writing, which helps to simplify the structure of the display panel. It is equivalent to multiplexing the data voltage writing module and the DEMUX module in the prior art. Optionally, the third transistor T3 and the fourth transistor T4 included in the second multiplexing unit 22 are located on the side of the selection circuit 221 near the display area AA. The selection circuit 221 is electrically connected to the driver chip that provides the data voltage. The third transistor T3 and the fourth transistor T4 are located on the side of the selection circuit 221 closer to the display area AA. This allows the distance between the reset bus VF or power bus EL located in the first frame area and the reset bus VF or power bus EL located in the second frame area to be closer, reducing the voltage drop on the reset bus or power bus EL. This ensures that the first power supply voltage written to the first electrode of the first transistor T1 and the first power supply voltage written to the third transistor T3 are as similar as possible, as are the reset voltage written to the first electrode of the second transistor T2 and the reset voltage written to the fourth transistor T4. This, in turn, ensures that the voltage written to the pixel circuits in different rows of a column is the same, improving the uniformity of the display.

[0092] When the display panel includes a sufficient number of data output terminals of the driver chips, and no selection circuit is required, an additional circuit structure is needed to control the writing of the data voltage in order to achieve time-sharing of the reset voltage, first power supply voltage, and data voltage. For details, please refer to [link to relevant documentation]. Figure 4 . Figure 4 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention, with reference to... Figure 4The second multiplexing unit 22 includes a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8. The first terminal of the sixth transistor T6 is electrically connected to the power bus EL located in the second frame area, the second terminal of the sixth transistor T6 is electrically connected to the corresponding multiplexed signal line L4, and the gate of the sixth transistor T6 is electrically connected to the first power control signal line ELG. The first terminal of the seventh transistor T7 is electrically connected to the reset bus VF located in the second frame area, the second terminal of the seventh transistor T7 is electrically connected to the corresponding multiplexed signal line L4, and the gate of the seventh transistor T7 is electrically connected to the reset signal control line VFG. The first terminal of the eighth transistor T8 is connected to the data voltage, the second terminal of the eighth transistor T8 is connected to the corresponding multiplexed signal line L4, and the gate of the eighth transistor T8 is connected to the control signal line VDAF.

[0093] Figure 4In the structure of the display panel shown, the multiplexing module includes a first multiplexing unit 21 and a second multiplexing unit 22. The first multiplexing unit 21 includes a first transistor T1 and a second transistor T2. The second multiplexing unit 22 includes a sixth transistor T6, a seventh transistor T7 and an eighth transistor T8. The first transistor T1, the second transistor T2, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 can be either N-type transistors or P-type transistors, without specific limitation. The first transistor T1 and the sixth transistor T6 have the same channel type, and the second transistor T2 and the seventh transistor T7 have the same channel type. During the reset phase, the signal on the first power control signal line ELG controls the first transistor T1 and the sixth transistor T6 to turn off, and the control signal line VDAF controls the eighth transistor T8 to turn off. The signal on the reset signal control line VFG controls the second transistor T2 and the seventh transistor T7 to turn on. The turned-on second transistor T2 and seventh transistor T7 control the reset voltage on the reset bus VF to be transmitted simultaneously from the first and second bezel areas of the display panel to the multiplexed signal line L4. This enables the reset voltage to be written simultaneously from both ends of the multiplexed signal line L4 to a connected column of pixel circuits 1, reducing the voltage drop on the multiplexed signal line L4, improving the uniformity of the reset voltage on the multiplexed signal line L4, improving display uniformity, and reducing power consumption. During the data writing and threshold compensation phase, the signal on the first power control signal line ELG controls the first transistor T1 and the sixth transistor T6 to turn off, and the signal on the reset signal control line VFG controls the second transistor T2 and the seventh transistor T7 to turn off. The control signal line VDAF controls the eighth transistor T8 to turn on, and the turned-on eighth transistor T8 transmits the corresponding data voltage to the corresponding multiplexed signal line L4. During the light-emitting stage, the signal on the reset signal control line VFG controls the second transistor T2 and the seventh transistor T7 to turn off, the control signal line VDAF controls the eighth transistor T8 to turn off, and the signal on the first power control signal line ELG controls the first transistor T1 and the sixth transistor T6 to turn on. The turned-on first transistor T1 and sixth transistor T6 control the first power supply voltage on the power bus EL to be transmitted simultaneously from the first and second border areas of the display panel to the multiplexed signal line L4, thereby realizing the simultaneous writing of the first power supply voltage from both ends of the multiplexed signal line L4 to a connected column of pixel circuits 1, reducing the voltage drop on the multiplexed signal line L4, improving the uniformity of the first power supply voltage on the multiplexed signal line L4, improving display uniformity, and reducing power consumption.

[0094] Compared to Figure 3 The display panel shown is Figure 4 The display panel shown does not include the selection circuit; an additional eighth transistor T8 controls the writing of data voltage. The structure is relatively simple and easy to implement. Except... Figure 3 and Figure 4In addition to the structure shown, when the data voltage in the control driver chip is transmitted to the multiplexed signal line, the data output terminal of the driver chip can also be directly electrically connected to the corresponding multiplexed signal line without the need for additional transistors. In this case, the driver chip can control the output of data voltage only during the data voltage writing and threshold compensation stages through its own control logic.

[0095] Figure 5 This is a schematic diagram of the circuit structure in a display panel according to an embodiment of the present invention, with reference to... Figure 5 Optionally, the pixel circuit includes a driving module 11, a compensation module 12, a reset module 13, a storage module 14, a light emission control module 15, and a light emission module 16. The first end of the driving module 11 is electrically connected to the corresponding multiplexed signal line L4.

[0096] The reset module 13 is connected between the first end of the drive module 11 and the control end of the drive module 11, and is used to transmit a reset voltage to the control end of the drive module 11.

[0097] The compensation module 12 is connected between the second end of the drive module 11 and the control end of the drive module 11. The compensation module 12 is used to transmit the compensation voltage to the control end of the drive module 11 based on the data voltage.

[0098] The storage module 14 is connected to the control terminal of the drive module 11 and is used to store the voltage of the control terminal of the drive module 11.

[0099] The light-emitting control module 15 is connected between the second terminal of the driving module 11 and the light-emitting module 16. The driving module 11 generates a driving current according to the control terminal of the driving module 11 to drive the light-emitting module 16 to emit light. The compensation voltage is a voltage that includes the data voltage and the threshold voltage of the driving module 11.

[0100] The reset module 13, compensation module 12, and light-emitting control module 15 are all switching modules. Each module's control terminal is connected to a corresponding control line to control whether the module is turned on or off. For example, the control terminal of the reset module 13 is electrically connected to the first scan line S1, the control terminal of the compensation module 12 is electrically connected to the second scan line S2, and the control terminal of the light-emitting control module 15 is electrically connected to the light-emitting control signal line EM. After each module is turned on, its two ends are connected. Taking the reset module 13 as an example, after the reset module 13 is turned on, it connects the control terminal of the drive module 11 to the first terminal of the drive module 11. After the reset module 13 is turned off, it disconnects the connection between the control terminal of the drive module 11 and the first terminal of the drive module 11. In this embodiment, the first terminal of the light-emitting control module 15 is electrically connected to the second terminal of the drive module 11, and the second terminal of the light-emitting control module 15 is electrically connected to the first terminal of the light-emitting module 16. The second terminal of the light-emitting module 16 is connected to the second power supply voltage Vss.

[0101] The first scan line S1 can extend along the second direction. The second scan line S2 can extend along the second direction. The light emission control signal line EM can extend along the second direction. The row direction can be parallel to the second direction. The column direction can be parallel to the first direction.

[0102] refer to Figure 3 and 5 Optionally, the pixel circuit may include a driving module 11 and a storage module 14. The driving module 11 is connected between the multiplexed signal line L4 and the light-emitting module 16, and the storage module 14 is connected between the control terminal of the driving module 11 and the power line VI, for storing the voltage of the control terminal of the driving module 11. Optionally, the display panel may also include multiple power lines VI, which extend along the second direction Y, intersecting the extension direction of the multiplexed signal line L4. The power lines VI are connected to a power bus EL for providing a first power supply voltage, and one power line VI is connected to the storage module 14 of each pixel circuit 1 in at least one row of pixel circuits. Optionally, each row of pixel circuits may include multiple pixel circuits arranged along the second direction Y.

[0103] Optionally, the power line VI and the multiplexed signal line L4 are insulated from each other. The power line VI can be located in the display area, and the power line VI and the multiplexed signal line L4 are arranged in an insulated, cross-shaped configuration.

[0104] Multiple power lines VI extend along the second direction Y and are arranged along the first direction X. For example, the multiplexed signal line L4 extends along the column direction of the pixel circuit arrangement, and the power lines VI extend along the row direction of the pixel circuit arrangement; that is, the extension direction of the power lines VI is perpendicular to the extension direction of the multiplexed signal line L4. Optionally, the power lines VI are electrically connected to the power bus EL. Optionally, the power lines VI are connected to the second trace segment extending along the first direction X of the power bus EL, directly obtaining the first power supply voltage on the power bus EL and transmitting the first power supply voltage to the storage module 14, providing a fixed potential to one end of the storage module 14. Optionally, the power bus EL may include multiple second trace segments extending along the first direction X and respectively located in the third and fourth border areas. The two opposite ends of the same power line VI along the second direction Y are electrically connected to the second trace segments located in the third and fourth border areas, respectively. The first and second trace segments of the power bus EL are electrically connected. Optionally, the reset bus VF may include multiple fourth trace segments extending along the first direction X and respectively located in the third and fourth border areas. The third and fourth traces of the reset bus VF are electrically connected.

[0105] Continue to refer to Figure 3 and Figure 5Optionally, the multiplexing module includes a first multiplexing unit 21 and a second multiplexing unit. The first multiplexing unit 21 is located in the first frame area, and the second multiplexing unit 22 is located in the second frame area. The two ends of the power line VI are electrically connected to the power bus EL located in the third frame area and the power bus EL located in the fourth frame area, respectively. The first frame area and the second frame area can be two frame areas opposite each other along the first direction X of the display panel, and the third frame area and the fourth frame area can be two frame areas opposite each other along the second direction Y of the display panel. Optionally, the first frame area and the second frame area are located in the upper frame area and the lower frame area, respectively, and the third frame area and the fourth frame area are located in the left frame area and the right frame area, respectively. Alternatively, the first frame area and the second frame area are located in the left frame area and the right frame area, respectively, and the third frame area and the fourth frame area are located in the upper frame area and the lower frame area, respectively.

[0106] Figure 5 The structure of the second multiplexing unit is only shown as an example. The second multiplexing unit includes a third transistor T3, a fourth transistor T4, and a selection circuit. For details, please refer to [reference needed]. Figure 3 ,and Figure 5 The output terminal U1 of the selection circuit is shown only as an example; the specific structure of the selection circuit is not shown. Figure 6 This is a driving timing diagram of a display panel provided in an embodiment of the present invention, with reference to... Figure 5 and Figure 6 Within a single frame of display, the display panel includes a reset phase t1, a data writing and threshold compensation phase t2, and a light emission phase t3. For example, the third transistor T3 and the fourth transistor T4 are both P-type transistors, and the reset module 13, the compensation module 12, and the light emission control module 15 all respond to a low-level input to their respective control terminals and a high-level input to turn them off.

[0107] During the reset phase t1, the signal on the first power control signal line ELG is at a shutdown level, for example, a high level, controlling the third transistor T3 to turn off. The signal on the reset signal control line VFG is at a conduction level, for example, a low level, controlling the fourth transistor T4 to turn on. The conducting fourth transistor T4 transmits the voltage on the reset bus VF to the multiplexed signal line L4. The signal on the second scan line S2 is at a shutdown level, for example, a high level, controlling the compensation module 12 to turn off. The signal on the first scan line S1 is at a conduction level, for example, a low level, controlling the reset module 13 to turn on. The signal on the light emission control signal line EM is at a conduction level, for example, a low level, controlling the light emission control module 15 to turn on. The conducting reset module 13 transmits the reset voltage to the control terminal of the drive module 11 and the storage module 14, resetting the drive module 11 and the storage module 14. At the same time, after the control terminal of the driving module 11 is written with a reset voltage, the driving module 11 is turned on. The reset voltage is written to the first terminal of the light-emitting module 16 through the driving module 11 and the light-emitting control module 15, thereby resetting the light-emitting module 16 and avoiding the influence of residual charge from the previous frame on the light emission of the current frame.

[0108] During the data writing and threshold compensation phase t2, the signal on the first power control signal line ELG is at a shutdown level, for example, a high level, controlling the third transistor T3 to turn off. The signal on the reset signal control line VFG is at a shutdown level, for example, a high level, controlling the fourth transistor T4 to turn off. The selection circuit controls the corresponding output terminal U1 to output the data voltage so that the data voltage is transmitted to the multiplexed signal line L4. The signal on the first scan line S1 is at a shutdown level, for example, a high level, controlling the reset module 13 to turn off. The signal on the light emission control signal line EM is at a shutdown level, for example, a high level, controlling the light emission control module 15 to turn off. The signal on the second scan line S2 is at a conduction level, for example, a low level, controlling the compensation module 12 to conduct. The conducting compensation module 12 transmits the compensation voltage generated based on the data voltage and the threshold voltage of the driving module 11 to the control terminal of the driving module 11, realizing the writing of the data voltage and the compensation of the threshold voltage.

[0109] During the light-emitting stage t3, the signal on the reset signal control line VFG is at a shutdown level, for example, a high level, controlling the fourth transistor T4 to turn off. The signal on the first power control signal line ELG is at a conduction level, for example, a low level, controlling the third transistor T3 to turn on. The conducting third transistor T3 transmits the first power supply voltage on the power bus EL to the multiplexed signal line L4. The signal on the first scan line S1 is at a high level, controlling the reset module 13 to turn off. The signal on the second scan line S2 is at a shutdown level, for example, a high level, controlling the compensation module 12 to turn off. The signal on the light-emitting control signal line EM is at a conduction level, for example, a low level, controlling the light-emitting control module 15 to turn on. The driving module 11 generates a driving current based on the data voltage, which is transmitted to the light-emitting module 16 through the conducting light-emitting control module 15 to drive the light-emitting module 16 to emit light.

[0110] It is worth noting that in this embodiment, the display panel includes n rows of pixel circuits, where n ≥ 2, corresponding to n second scan lines S2. The first row of pixel circuits is connected to the first scan line S2-1, and so on, with the nth row of pixel circuits connected to the nth scan line S2-n. This embodiment exemplarily demonstrates that illumination is performed only after the data voltage of all rows of pixel circuits has been written. For example, during the driving process of the pixel circuits, a first-level shift register providing the first scan signal S1 or the illumination control signal EM can drive two rows of pixel circuits, i.e., a one-to-two approach is adopted, where the first-level shift register simultaneously provides the first scan signal S1 or the illumination control signal EM to two rows of pixel circuits.

[0111] The operation of the display panel can include three methods. The first method involves sequentially turning on the reset module 13 in each row of pixel circuits. After all rows of pixel circuits have been reset, the compensation module 12 in each row of pixel circuits is then turned on to write data voltage. Once the data voltage for all rows of pixel circuits has been written, the light-emitting control module 15 is turned on row by row to achieve sequential light emission from the pixel circuits. The second method involves writing data voltage immediately after the first row of pixel circuits has been reset. After the data voltage is written, the light-emitting stage begins. The operation of the second to last row of pixel circuits follows the same process. The third method involves sequentially turning on the reset module 13 in each row of pixel circuits. After all rows of pixel circuits have been reset, the compensation module 12 in each row of pixel circuits is then turned on. After the first row of pixel circuits has completed data writing and threshold compensation, the light-emitting stage begins. The second row of pixel circuits also enters the light-emitting stage after completing data writing and threshold compensation, and so on.

[0112] Figure 7 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention. Figure 7 for Figure 5 A specific structural diagram of the corresponding display panel is shown in the reference diagram. Figure 5 and Figure 7 Optionally, the driving module 11 includes a ninth transistor T9, the reset module 13 includes a tenth transistor T10, the compensation module 12 includes an eleventh transistor T11, the light-emitting control module 15 includes a twelfth transistor T12, and the storage module 14 includes a storage capacitor Cst. The first terminal of the tenth transistor T10 is electrically connected to the first terminal of the ninth transistor T9, the second terminal of the tenth transistor T10 is electrically connected to the gate of the ninth transistor T9, and the gate of the tenth transistor T10 is electrically connected to the first scan line S1. The first terminal of the ninth transistor T9 is also electrically connected to the multiplexed signal line L4. The first terminal of the eleventh transistor T11 is electrically connected to the second terminal of the ninth transistor T9, the second terminal of the eleventh transistor T11 is electrically connected to the gate of the ninth transistor T9, and the gate of the eleventh transistor T11 is electrically connected to the second scan line S2. The first terminal of the twelfth transistor T12 is electrically connected to the second terminal of the ninth transistor T9, the second terminal of the twelfth transistor T12 is electrically connected to the first terminal of the light-emitting module 16, and the gate of the twelfth transistor T12 is electrically connected to the light-emitting control signal line EM. The first terminal of the storage module Cst is electrically connected to the gate of the ninth transistor T9, and the second terminal of the storage module Cst is electrically connected to the power line VI. Figure 7 The specific working process of the structure shown is as follows Figure 5 The same applies and will not be repeated here. It is worth noting that when resetting the driving module 11 and the storage module 14, the scanning driving circuit connected to the gate of the tenth transistor T10 can control the simultaneous conduction of all tenth transistors T10 on the screen, thus simultaneously resetting all driving modules 11 on the screen. Alternatively, the scanning driving circuit connected to the gate of the tenth transistor T10 can control the simultaneous conduction of the tenth transistors T10 on half of the screen, thus simultaneously resetting the driving modules 11 on half of the screen. Then, the tenth transistors T10 on the other half of the screen can be simultaneously conducted to simultaneously reset the driving modules 11 on the other half of the screen. Alternatively, the scanning driving circuit connected to the gate of the twelfth transistor T12 can control the simultaneous conduction of the twelfth transistor T12 on either the entire screen or half of the screen, thus simultaneously resetting the light-emitting modules 16 on either the entire screen or half of the screen.

[0113] This invention also provides a display device. Figure 8 This is a schematic diagram of a display device provided in an embodiment of the present invention, with reference to... Figure 8 The display device 01 includes the aforementioned display panel 02. The display device 01 can be... Figure 8 The mobile phone shown can also be a computer, television, smart wearable display device, etc., and the embodiments of the present invention do not make any special limitations in this regard. The beneficial effects of the display device are the same as those of the display panel, and will not be described again here.

[0114] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0115] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A display panel, characterized in that, include: Multiple pixel circuits, multiple multiplexed signal lines, and multiple multiplexed modules; At least one row of the pixel circuits is connected to the multiplexed signal line extending along the first direction; Each row of pixel circuits includes a plurality of pixel circuits arranged along a first direction. The multiplexing module is connected to the corresponding multiplexing signal line. The multiplexing module includes a first multiplexing unit and a second multiplexing unit. The multiplexing module is used to transmit one or more of a reset voltage, a data voltage, and a first power supply voltage to the multiplexing signal line. The first multiplexing unit and the second multiplexing unit of the same multiplexing module are respectively connected to the two opposite ends of the same multiplexing signal line along the first direction. During the reset phase, the first and second multiplexing units of the same multiplexing module simultaneously transmit the reset voltage to the connected multiplexing signal line; during the data writing and threshold compensation phase, the second multiplexing unit transmits the data voltage to the multiplexing signal line. During the light-emitting phase, the first multiplexing unit and the second multiplexing unit of the same multiplexing module simultaneously transmit the first power supply voltage to the connected multiplexing signal line; The pixel circuit includes a driving module, a compensation module, a reset module, a storage module, a light emission control module, and a light emission module. The first end of the driving module is electrically connected to the corresponding multiplexed signal line. The reset module is connected between the first end of the drive module and the control end of the drive module, and is used to be turned on during the reset phase to transmit the reset voltage to the control end of the drive module. The compensation module is connected between the second end of the driving module and the control end of the driving module. The compensation module is used to transmit a compensation voltage to the control end of the driving module based on the data voltage during the data writing and threshold compensation stages. The storage module is connected between the control terminal and the power line of the drive module, and is used to store the voltage of the control terminal of the drive module; The light-emitting control module is connected between the second end of the driving module and the light-emitting module. The driving module is used to generate a driving current to drive the light-emitting module to emit light during the light-emitting stage according to the voltage of the control end of the driving module. The light-emitting control module is used to turn on during the reset stage, and the reset voltage is written to the first end of the light-emitting module through the driving module and the light-emitting control module.

2. The display panel according to claim 1, characterized in that, The first multiplexing unit is located in the first border area of ​​the display panel, and the second multiplexing unit is located in the second border area of ​​the display panel. The first border area and the second border area are two opposite sides of the display panel along the first direction.

3. The display panel according to claim 2, characterized in that, The first border area and the second border area are respectively the top border area and the bottom border area, or the first border area and the second border area are respectively the left border area and the right border area.

4. The display panel according to claim 1, characterized in that, The display panel includes a display area, the pixel circuit and the multiplexed signal lines are located in the display area, and the display panel also includes a power bus and a reset bus. The power bus is connected to the multiplexing module and is used to provide a first power supply voltage to the multiplexing module; The reset bus is connected to the multiplexing module and is used to provide the reset voltage to the multiplexing module; The multiplexing module is also connected to the data voltage.

5. The display panel according to claim 4, characterized in that, The power bus is arranged around the display area, and / or the reset bus is arranged around the display area.

6. The display panel according to claim 4, characterized in that, The display panel includes a substrate, and the power bus, when projected vertically onto the substrate, forms a closed pattern surrounding the display area.

7. The display panel according to claim 4, characterized in that, The display panel includes a substrate, and the vertical projection of the reset bus onto the substrate is a closed pattern arranged around the display area.

8. The display panel according to claim 4, characterized in that, The display panel also includes a non-display area surrounding the display area, and the multiplexing module is located in the non-display area.

9. The display panel according to claim 4, characterized in that, The power bus and the reset bus are located in the non-display area.

10. The display panel according to claim 4, characterized in that, The first multiplexing unit includes a first transistor and a second transistor. The first terminal of the first transistor is electrically connected to the power bus located in the first frame area, the second terminal of the first transistor is electrically connected to the corresponding multiplexing signal line, and the gate of the first transistor is electrically connected to the first power control signal line. The first terminal of the second transistor is electrically connected to the reset bus located in the first frame region, the second terminal of the second transistor is electrically connected to the corresponding multiplexed signal line, and the gate of the second transistor is electrically connected to the reset signal control line.

11. The display panel according to claim 10, characterized in that, The display panel includes a substrate, the first power control signal line is disposed around the display area, and / or the reset signal control line is disposed around the display area.

12. The display panel according to claim 10, characterized in that, The display panel includes a substrate, and the vertical projection of the first power control signal line on the substrate is a closed pattern arranged around the display area; the vertical projection of the reset signal control line on the substrate is a closed pattern arranged around the display area.

13. The display panel according to claim 4, characterized in that, The second multiplexing unit includes a third transistor, a fourth transistor, and a selection circuit. The selection circuit includes an input terminal and at least two output terminals. The output terminals of the selection circuit are electrically connected to the multiplexed signal lines. Different output terminals of the same selection circuit are electrically connected to different multiplexed signal lines. The input terminal of the selection circuit is used to input data voltage. The first terminal of the third transistor is electrically connected to the power bus located in the second frame area, the second terminal of the third transistor is electrically connected to the corresponding multiplexed signal line, and the gate of the third transistor is electrically connected to the first power control signal line; the first terminal of the fourth transistor is electrically connected to the reset bus located in the second frame area, the second terminal of the fourth transistor is electrically connected to the corresponding multiplexed signal line, and the gate of the fourth transistor is electrically connected to the reset signal control line.

14. The display panel according to claim 13, characterized in that, The selection circuit includes at least two fifth transistors, each of which corresponds to an output terminal of the selection circuit. The first terminal of each fifth transistor is connected to the data voltage, and the second terminal of each fifth transistor serves as the output terminal of the corresponding selection circuit. The gate of each fifth transistor is electrically connected to a data transmission control signal line, and the data transmission control signal lines connected to the gates of the various fifth transistors in the selection circuit are different.

15. The display panel according to claim 13, characterized in that, The second multiplexing unit includes a third transistor and a fourth transistor located on the side of the selection circuit closer to the display area.

16. The display panel according to claim 4, characterized in that, The second multiplexing unit includes a sixth transistor, a seventh transistor, and an eighth transistor. The first terminal of the sixth transistor is electrically connected to the power bus located in the second frame area, the second terminal of the sixth transistor is electrically connected to the corresponding multiplexed signal line, and the gate of the sixth transistor is electrically connected to the first power control signal line. The first terminal of the seventh transistor is electrically connected to the reset bus located in the second frame area, the second terminal of the seventh transistor is electrically connected to the corresponding multiplexed signal line, and the gate of the seventh transistor is electrically connected to the reset signal control line. The first terminal of the eighth transistor is connected to the data voltage, the second terminal of the eighth transistor is electrically connected to the corresponding multiplexed signal line, and the gate of the eighth transistor is connected to the control signal line.

17. The display panel according to claim 1, characterized in that, The display panel also includes multiple power lines extending along a second direction, the extension direction of the power lines intersecting with the extension direction of the multiplexed signal lines, the power lines being connected to a power bus for providing the first power supply voltage, and one power line being connected to the storage module of each pixel circuit in at least one row of pixel circuits. The power line and the multiplexed signal line are insulated from each other.

18. A display device, characterized in that, Includes the display panel as described in any one of claims 1-17.

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