Exposure head and image forming apparatus

Abstract

An exposure head for exposing a photosensitive drum includes a substrate, a plurality of strip-shaped semiconductor chips provided with a plurality of light emitting elements for emitting light and a drive circuit for driving the light emitting elements, and arranged on the substrate, and a lens array that converges light from the light emitting elements onto the photosensitive drum. The drive circuit operates between a first potential and a second potential, the light emitting elements operate between a third potential and a fourth potential, and a potential difference between the third potential and the fourth potential is equal to or greater than a potential difference between the first potential and the second potential.

Description

TECHNICAL FIELD

[0001] The present application relates to an exposure head that exposes a photosensitive drum, and an image forming apparatus including the exposure head. BACKGROUND

[0002] Hitherto, as a printer of an electrophotographic system, a printer that exposes a photosensitive drum by using an exposure head of LED, organic EL, or the like to form a latent image is generally known. Such an exposure head includes a light emitting element row arranged in a longitudinal direction of the photosensitive drum and a rod lens array that forms an image of light of the light emitting element row on the photosensitive drum. The LED or organic EL serving as the light emitting element is an array of light emitting elements whose irradiation direction of light from a light emitting surface is parallel to an optical axis of the rod lens array.

[0003] Here, in the exposure head, the length of the array of light emitting elements is determined in accordance with the width of an image forming region on the photosensitive drum, and the interval between the light emitting elements is determined in accordance with the image resolution of the printer. For example, in a 1200 dpi printer, since the interval between pixels is 21.16 μm (rounded down to two decimal places), the interval between the light emitting elements is also 21.16 μm. Since the printer using such an exposure head uses a smaller number of components compared to a printer of a laser scanning system that performs deflection scanning of a laser beam using a polygonal motor, it is easy to reduce the size and cost of the apparatus.

[0004] In addition, in recent years, a technique of reducing the size of the apparatus by mounting the light emitting element and the drive circuit on the same chip is also known. For example, an exposure head in which an integrated circuit for driving and an electrode are formed on a Si substrate, and an organic EL film is deposited thereon to integrate the light emitting element and the drive circuit as one chip is known. In addition, Japanese Patent Publication No. 2015-112856 discloses an exposure head in which a TFT circuit and an organic EL are provided on a transparent glass substrate.

[0005] However, in the exposure head having a configuration in which the light emitting element and the drive circuit are integrated as one chip according to the related art, it is necessary to form the integrated circuit by utilizing a semiconductor process of relatively high withstand voltage in order to secure the forward voltage of the light emitting element and to obtain a predetermined light emission amount. In the case where the drive circuit is formed by such a semiconductor process of high withstand voltage, there is a problem that the size of the transistor increases, as a result, the chip size increases. SUMMARY

[0006] An object of the present application is to provide an exposure head that is capable of forming a drive circuit by utilizing a semiconductor process of low withstand voltage while securing the forward voltage of a light emitting element and capable of reducing the chip size in a configuration in which the light emitting element and the drive circuit are formed as one chip.

[0007] A representative configuration of the present application is an exposure head configured to expose a photosensitive drum, the exposure head including: a substrate; a plurality of strip-shaped semiconductor chips each including a plurality of light emitting elements that emit light and a drive circuit that drives the light emitting elements, the plurality of strip-shaped semiconductor chips being arranged on the substrate; and a lens array configured to collect light from the light emitting elements on the photosensitive drum, wherein the drive circuit operates between a first potential and a second potential, the light emitting elements operate between a third potential and a fourth potential, and a potential difference between the third potential and the fourth potential is equal to or greater than a potential difference between the first potential and the second potential.

[0008] Further features of the present application will become apparent from the following description of exemplary embodiments with reference to the attached drawings. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 is a schematic view of an image forming apparatus according to a first embodiment of the present application.

[0010] Figure 2 (a) of FIG. 1 and Figure 2 (b) of FIG. 1 are schematic views of an exposure head and a photosensitive drum according to the first embodiment of the present application.

[0011] Figure 3 (a) of FIG. 2, Figure 3 (b) of FIG. 2, and Figure 3 (c) of FIG. 2 are schematic views that illustrate a configuration of the exposure head according to the first embodiment of the present application.

[0012] Figure 4 is a schematic view of a light emitting element array chip of the exposure head according to the first embodiment of the present application.

[0013] Figure 5 is a cross-sectional view taken along line A-A of Figure 4 FIG. 3.

[0014] Figure 6 (a) of FIG. 4 and Figure 6 (b) of FIG. 4 are schematic views that illustrate an arrangement of light emitting elements of the light emitting element array chip of the exposure head according to the first embodiment of the present application.

[0015] Figure 7 is a schematic view that illustrates a modification of the arrangement of the light emitting elements of the light emitting element array chip of the exposure head according to the first embodiment of the present application.

[0016] Figure 8 is a plan view that illustrates a positional relationship between a light emitting portion of the exposure head and a rod lens according to the first embodiment of the present application.

[0017] Figure 9is a block diagram illustrating a configuration of an exposure head according to a first embodiment of the present application.

[0018] Figure 10 is a block diagram illustrating a configuration of a light emitting element array chip of an exposure head according to the first embodiment of the present application.

[0019] Figure 11 is a circuit configuration diagram of a data holding section of a light emitting element array chip of an exposure head according to the first embodiment of the present application.

[0020] Figure 12 is a block diagram illustrating a configuration of an analog section of an exposure head according to the first embodiment of the present application.

[0021] Figure 13 is a block diagram illustrating a configuration of a power supply section of an exposure head according to the first embodiment of the present application.

[0022] Figure 14 is a flowchart of an operation of an exposure head according to the first embodiment of the present application.

[0023] Figure 15 is a timing chart illustrating a power supply voltage supplied to a light emitting element array chip of an exposure head according to the first embodiment of the present application.

[0024] Figure 16 is a timing chart of a light emitting element array chip of an exposure head according to the first embodiment of the present application.

[0025] Figure 17 is a block diagram illustrating a configuration of a light emitting element array chip of an exposure head according to a second embodiment of the present application.

[0026] Figure 18 is a block diagram illustrating a configuration of an analog section of an exposure head according to the second embodiment of the present application.

[0027] Figure 19 is a block diagram illustrating a configuration of a power supply section of an exposure head according to the second embodiment of the present application.

[0028] Figure 20 is a flowchart of an operation of an exposure head according to the second embodiment of the present application.

[0029] Figure 21 is a timing chart illustrating a power supply voltage supplied to a light emitting element array chip of an exposure head according to the second embodiment of the present application. DETAILED DESCRIPTION

[0030] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

[0031] (First Embodiment)

[0032] <Configuration of the image forming apparatus>

[0033] The configuration of the image forming apparatus 1 according to the first embodiment of the present application will be described in detail with reference to Figure 1

[0034] The image forming apparatus 1 includes a scanner section 100, an image creating section 103, a fixing section 104, a feeding / conveying section 105, and a registration roller 110.

[0035] The scanner section 100 illuminates a document placed on a document substrate to optically read an image of the document, and converts the read image into an electric signal to create image data. The scanner section 100 outputs the created image data to a printer controller (not shown).

[0036] The image creating section 103 operates under the control of the printer controller to form an image on a sheet conveyed from the registration roller 110, and conveys the sheet on which the image is formed to the fixing section 104. The image creating section 103 includes four image creating units that perform a series of electrophotographic processes including charging, exposure, development, and transfer. The image creating section 103 forms a full-color image on a sheet by the four image creating units arranged in the order of cyan (C), magenta (M), yellow (Y), and black (K). After a predetermined time has elapsed from the start of the cyan image creation, the four image creating units sequentially perform the magenta, yellow, and black image creation operations.

[0037] Specifically, the image creating section 103 includes a photosensitive drum 102, an exposure head 106, a charger 107, a developing device 108, a transfer belt 111, and an optical sensor 113.

[0038] The photosensitive drum 102 serving as an image bearing member is attached to the image forming apparatus 1 by an attachment member (not shown) and is rotationally driven.

[0039] The exposure head 106 is attached to the image forming apparatus 1 by an attachment member (not shown). The exposure head 106 includes four exposure heads 106a, 106b, 106c, and 106d corresponding to the four image creating units. The exposure head 106 collects light emitted in accordance with image data on the photosensitive drum 102, and performs exposure to form a latent image (electrostatic latent image) on the photosensitive drum 102. Note that details of the configuration of the exposure head 106 will be described below.

[0040] The charger 107 charges the photosensitive drum 102.

[0041] The developing device 108 supplies toner to the latent image formed on the photosensitive drum 102, and develops the latent image to form a toner image (developer image) on the photosensitive drum 102. ​

[0042] The transfer belt 111 conveys the sheet conveyed from the registration roller 110 to the fixing section 104. The toner image developed by the developing device 108 is transferred to the sheet conveyed by the transfer belt 111.

[0043] The optical sensor 113 is provided at a position facing the transfer belt 111, and detects the position of the test chart printed on the transfer belt 111, so as to obtain the color offset amount between the image creating units. The optical sensor 113 outputs the detection result of the position of the test chart to an image controller section (not shown). Based on the detection result of the position of the test chart input from the optical sensor 113, the image controller section performs control to obtain the color offset amount between the image creating units of the image creating section 103 and correct the image position of each color. The full-color toner image without color offset is transferred to the sheet by the control.

[0044] The fixing section 104 is realized by a combination of rollers, and incorporates a heat source such as a halogen heater (not shown). The fixing section 104 dissolves and fixes the toner on the sheet on which the toner image is transferred by the image creating section 103 by heat and pressure, and discharges the sheet on which the toner is fixed to the outside of the image forming apparatus 1 by the discharge roller 112.

[0045] The feeding / conveying section 105 includes an intra-body feeding unit 109a, an intra-body feeding unit 109b, an external feeding unit 109c, and a manual feeding unit 109d, and feeds the sheet from the feeding unit instructed in advance and conveys the sheet to the registration roller 110.

[0046] The timing at which the toner image formed in the image creating section 103 is transferred to the sheet, the registration roller 110 conveys the sheet conveyed from the feeding / conveying section 105 to the transfer belt 111.

[0047] The printer controller controls the operation of the scanner section 100, the image creating section 103, the fixing section 104, and the feeding / conveying section 105. The printer controller communicates with an MFP controller that controls the entire MFP (the entire image forming apparatus 1), and controls the operation while managing the state of the scanner section 100, the image creating section 103, the fixing section 104, and the feeding / conveying section 105 according to the instruction of the MFP controller.

[0048] <Configuration of exposure head>

[0049] The configuration of the exposure head 106 according to the first embodiment of the present application will be described in detail with reference to Figures 2 to 3

[0050] Figure 2 (a) of FIG. 1 illustrates the arrangement of the exposure head 106 with respect to the photosensitive drum 102, and Figure 2 ​Fig. 2A(b) illustrates a state in which light emitted from the light emitting element group 201 is collected on the photosensitive drum 102 by the rod lens array 203.

[0051] Figure 3 Fig. 2A(a) illustrates a surface of the printed circuit board 202 opposite to a surface on which the light emitting element group 201 is mounted (hereinafter, referred to as "non-light emitting element mounting surface"), and Figure 3 Fig. 2A(b) illustrates a surface on which the light emitting element group 201 is mounted (hereinafter, referred to as "light emitting element mounting surface"). In addition, Figure 3 Fig. 2A(c) illustrates a state of a boundary portion between the light emitting element array chip 400-m (m is an integer of 1 or more and 19 or less) and 400-m+1.

[0052] The exposure head 106 includes the light emitting element group 201, the printed circuit board 202, the rod lens array 203, and the housing 204.

[0053] The light emitting element group 201 is mounted on the light emitting element mounting surface of the printed circuit board 202, and has 20 strip-shaped light emitting element array chips 400-1 to 400-20 arranged in a two-row configuration in a staggered manner. The light emitting element array chips 400-1 to 400-20 of each row are arranged in a longitudinal direction of the printed circuit board 202.

[0054] In the light emitting element array chips 400-1 to 400-20 serving as semiconductor chips, the light emitting elements 602 are arranged at a predetermined pitch in a longitudinal direction (main scanning direction) and a lateral direction (sub-scanning direction) of the light emitting element array chips 400-1 to 400-20. In each of the light emitting element array chips 400-1 to 400-20, 748 light emitting elements 602 are arranged at a predetermined image resolution pitch in an X direction as the longitudinal direction. Here, the image resolution pitch is 1200 dpi (approximately 21.16 μm). In addition, as an example, here, an end-to-end distance of the 748 light emitting elements 602 in each of the light emitting element array chips 400-1 to 400-20 is about 15.8 mm.

[0055] In the light emitting element group 201, since the 20 light emitting element array chips 400-1 to 400-20 are arranged in the longitudinal direction, the number of light emitting elements that can be exposed is 14960, and image formation corresponding to an image width of about 316 mm becomes possible.

[0056] In this example, the light emitting element array chip 400-1 is positioned at the boundary portion between the light emitting element array chip 400-1 and 400-2. Figure 3The image resolution pitch of the light emitting elements 602-n and the light emitting element 602-1 at the boundary between the light emitting element array chips 400-1 to 400-20 illustrated in (c) of FIG. 4A is also 1200 dpi (about 21.16 pm). In addition, the interval S in the lateral direction between the light emitting element 602-n and the light emitting element 602-1 is about 127 pm (six pixels at 1200 dpi, and four pixels at 800 dpi). In addition, the interval L in the longitudinal direction between the light emitting element 602-n and the light emitting element 602-1 is about 21.16 pm (one pixel at 1200 dpi). Note that the interval S and the interval L between the light emitting element 602-n and the light emitting element 602-1 are not limited to the above values.

[0057] As Figure 3 illustrated in (a) of FIG. 4A, the printed circuit board 202 serving as the board is provided with the connector 305 and a driver IC (not illustrated) for driving the light emitting element group 201 on the non-light emitting element mounting surface. As Figure 3 illustrated in (b) of FIG. 4A, the light emitting element group 201 is mounted on the light emitting element mounting surface serving as the surface of the printed circuit board 202.

[0058] The connector 305 is connected to the driver IC and a power supply (not illustrated) provided on the light emitting element non-mounting surface of the printed circuit board 202 via signal lines (not illustrated), and is also connected to the light emitting element group 201.

[0059] The rod lens array 203 is arranged at a predetermined distance from the light emitting element group 201, is arranged at a predetermined distance from the photosensitive drum 102, and forms an image of the light emitted from the light emitting element group 201 on the photosensitive drum 102.

[0060] The rod lens array 203 and the printed circuit board 202 are attached to the housing 204.

[0061] The exposure head 106 having the above configuration is assembled individually in a factory, and focus adjustment and light amount adjustment for adjusting the light spot at the light collecting position to a predetermined size are performed. Here, in the focus adjustment, the attachment position of the rod lens array 203 is adjusted in such a manner that the distance between the rod lens array 203 and the light emitting element group 201 becomes a desired distance. In the light amount adjustment, the individual light emitting elements 602 of the light emitting element group 201 are caused to emit light independently and sequentially, and the drive current for each light emitting element 602 is adjusted in such a manner that the light collected on the photosensitive drum 102 by the rod lens array 203 has a predetermined light amount.

[0062] <Configuration of light emitting element array chip>

[0063] Reference will be made to Figure 4The configuration of the light-emitting element array chips 400-1 to 400-20 of the exposure head 106 according to the first embodiment of the present invention will be described in detail.

[0064] The light-emitting element array chip 400 is a chip configured by setting a light-emitting element 602 on a Si substrate, and includes a light-emitting substrate 402, a light-emitting part 404, a circuit part 406, and a wiring bonding pad (WB pad) 408.

[0065] The light-emitting substrate 402 is a Si substrate, and the light-emitting part 404 and wiring bonding pad 408 are disposed on the light-emitting substrate 402. The circuit part 406 for controlling the light-emitting part 404 is built into the light-emitting substrate 402. Here, with the development of process technology for forming integrated circuits, Si substrates have been used as substrates for various integrated circuits. Therefore, it is advantageous to form high-speed and high-functionality circuits at high density and to have low-cost large-diameter wafers available.

[0066] The light-emitting part 404 includes a light-emitting element 602. Note that the details of the configuration of the light-emitting part 404 will be described below.

[0067] The circuit section 406 has a circuit configuration including an analog drive circuit, a digital control circuit, or both an analog drive circuit and a digital drive circuit, and controls the light-emitting section 404.

[0068] The wiring bonding pad 408 supplies power to the circuit section 406, or performs signal input and output between the light-emitting element array chip 400 and the outside.

[0069] <Configuration of the light-emitting part>

[0070] Reference Figure 5 The arrangement of the light-emitting portions 404 of the light-emitting element array chips 400-1 to 400-20 of the exposure head 106 according to the first embodiment of the present invention will be described in detail.

[0071] The light-emitting part 404 includes a portion of the light-emitting substrate 402 and the upper electrode 508 facing each other, and a light-emitting layer 506 in the facing portion, and is configured by sequentially stacking a plurality of lower electrodes 504, light-emitting layers 506 and upper electrodes 508 on the light-emitting substrate 402.

[0072] The lower electrode 504 is a single electrode and is formed on the light emitting substrate 402. The lower electrode 504 has a width W in the X direction, and a plurality of lower electrodes 504 adjacent to each other in the X direction are provided with a predetermined interval d therebetween. The lower electrode 504 is formed by using a process rule of about 0.2 μm and a Si integrated circuit processing technique that achieves high precision, together with the formation of the circuit portion 406, and is connected to a driving portion (not shown) of the circuit portion 406. As a result, the lower electrode 504 can be arranged at high density and high precision, and the light emitting points of the light emitting elements 602 are substantially the same as the light emitting points of the lower electrode 504, and therefore, the light emitting elements 602 can be arranged at high density.

[0073] The lower electrode 504 is preferably formed of a metal having high reflectivity with respect to the light emitting wavelength of the light emitting layer 506, and is formed of silver (Ag), aluminum (Al), an alloy of silver and aluminum, or the like.

[0074] The light emitting layer 506 is formed on the lower electrode 504 and is, for example, an organic EL film or an inorganic EL film. In the case where the light emitting layer 506 is an organic EL film, as needed, the light emitting layer 506 is a stacked structure including functional layers such as an electron transport layer, a hole transport layer, an electron injection layer, a hole injection layer, an electron blocking layer, and a hole blocking layer.

[0075] In the case where the light emitting layer 506 is formed of a material susceptible to moisture such as an organic EL layer or an inorganic EL layer, it is desirable to perform sealing so as to prevent moisture from entering the light emitting portion 404. The light emitting layer 506 is prevented from moisture entering the light emitting portion 404 by a sealing film formed of a single thin film of, for example, silicon oxide, silicon nitride, aluminum oxide, or the like, or by thin films of silicon nitride, aluminum oxide, or the like stacked. As a method for forming the sealing film, a method excellent in covering performance of a structure such as a step is preferable, and, for example, an atomic layer deposition method (ALD method) or the like can be used.

[0076] The light emitting layer 506 can be formed continuously or can be divided in substantially the same size as the lower electrode 504. In addition, the material, the configuration, and the forming method of the sealing film are merely examples and are not limited to the above-described examples, and it is enough if a suitable material, a configuration, and a forming method are appropriately selected.

[0077] The upper electrode 508 is a common electrode and is formed on the light emitting layer 506. The upper electrode 508 is preferably transparent to the light emitting wavelength of the light emitting layer 506, and a transparent electrode formed of indium tin oxide (ITO) can be used.

[0078] The light emitting section 404 having the above configuration causes the light emitting layer 506 to emit light at a position corresponding to the selected lower electrode 504 by energizing the light emitting layer 506 through the selected lower electrode 504 among the plurality of lower electrodes 504 and the upper electrode 508. As a result, the light emitting section 404 emits light through the upper electrode 508 positioned on the side of the light emitting layer 506 opposite to the side on which the light emitting substrate 402 is positioned.

[0079] By using a transparent electrode formed of indium tin oxide or the like as the upper electrode 508, the aperture ratio becomes substantially 100%, and the light emitted from the light emitting layer 506 is emitted as is. In addition, by forming the lower electrode 504 using a Si integrated circuit processing technique having high precision, the lower electrode 504 can be arranged at high density, and thus, it is possible to cause substantially the entire area of the light emitting section 404 to emit light, and it is possible to enhance the utilization efficiency of the light emitting section 404. Here, the area of the light emitting section 404 is an area obtained by adding the total area of the plurality of lower electrodes 504 to the total area of the plurality of intervals d.

[0080] <Arrangement of light emitting elements of light emitting section>

[0081] The arrangement of the light emitting elements 602 of the light emitting section 404 of the exposure head 106 according to the first embodiment of the present application will be described in detail with reference to Figures 6 to 8

[0082] In Figure 6 , Figure 6 (a) of FIG. illustrates an example in which the plurality of light emitting elements 602 are arranged in a row, and Figure 6 (b) of FIG. is a schematic cross-sectional view of the light emitting element row 604. Figure 7 FIG. illustrates an example in which the light emitting section 404 is configured by arranging a plurality of light emitting element rows 604 in the Y direction of the figure.

[0083] In Figure 6 (a) and Figure 6 (b), W1 is the width of the light emitting element 602 in the X direction, and d1 is the interval between the light emitting elements 602 adjacent to each other in the X direction. In Figure 7 , W2 is the width of the light emitting element 602 in the Y direction, and d2 is the interval between the light emitting elements 602 adjacent to each other in the Y direction.

[0084] Further, in Figure 6 (b), for example, the light emitting element 602-3 is a portion surrounded by a line having alternate long and short dashes.

[0085] ​The light emitting element row 604 is configured by arranging a plurality of light emitting elements 602 at predetermined intervals (pitch) in the X direction. The predetermined interval is, for example, 21 μm or 16 μm in the case where the image resolution in the Y direction is 1200 dpi. As an example, W1 is 19.8 μm, and as an example, d1 is 0.68 μm.

[0086] Here, in the case where the light emitting layer 506 is sufficiently thin, the light emitting point of the light emitting element 602 is substantially the same as the light emitting point of the lower electrode 504, and W1 can be regarded as Figure 5 W of the light emitting element 602, and d1 can be regarded as Figure 5 d of the light emitting element 602.

[0087] The light emitting element row 604 is not limited to the case where the light emitting elements 602 are arranged in one row in the X direction as illustrated in (a) of Figure 6 , and the light emitting elements 602 can also be arranged in a plurality of rows in the Y direction as illustrated in (b) of Figure 7 . Figure 7 The case where 748 light emitting elements 602 (602-1 to 4_1 to 748) are arranged in the X direction and four rows (604-1 to 604-4) are arranged in the Y direction different from the X direction as a matrix is illustrated. Here, W2 is 19.8 μm, which is the same as W1. Here, d2 is 0.68 μm, which is the same as d1, and the case where the light emitting elements 602 are arranged at a pitch of 21.16 μm (1200 dpi) in the Y direction is exemplified.

[0088] The rod lens array 203 collects light emitted from the light emitting element group 201 on the photosensitive drum 102. Here, the number of light emitting element rows 604 in the Y direction is, for example, four. Here, as illustrated in Figure 8 , the pitch of the light emitting elements 602 in the X direction is 21.16 μm. Here, as illustrated in Figure 8 , the pitch of the light emitting elements 602 in the Y direction is 21.16 μm. Here, as illustrated in Figure 8 , the diameter of the rod lens array 203 is 290 μm. In this example, one rod lens array 203 is configured to collect light emitted from a plurality of light emitting elements 602.

[0089] <Exposure head circuit configuration>

[0090] The circuit configuration of the exposure head 106 according to the first embodiment of the present application will be described in detail with reference to Figure 9 .

[0091] In the case where the exposure head 106 is used Figure 9In the description, the circuit configuration of one exposure head 106 of a single color will be described for the sake of simplifying the description, but actually, each of the four exposure heads 106 of the four colors has the same circuit configuration. These four exposure heads 106 perform parallel processing at the same time.

[0092] The exposure head 106 includes an image controller section 700 that sends a signal or data for controlling the printed circuit board 202 to the printed circuit board 202 and performs processing of image data and processing of exposure timing. The signal and data sent from the image controller section 700 to the printed circuit board 202 include a clock signal, image data, a signal indicating start of reception of image data (hereinafter, referred to as a "line synchronization signal"), and a communication signal.

[0093] Specifically, the image controller section 700 includes an image data generation section 701, a chip data conversion section 702, a CPU 703, a synchronization signal generation section 704, a +5V generation circuit 710, a -5V generation circuit 711, and a switch (SW) 714.

[0094] Here, the image controller section 700 and the printed circuit board 202 are connected through a clock signal line 705, a line synchronization signal line 706, an image data signal line 707, a communication signal line 708, a +5V power supply line 712, and a -5V power supply line 713.

[0095] The clock signal line 705 connects the chip data conversion section 702 and each of the light emitting element array chips 400-1 to 400-20.

[0096] The line synchronization signal line 706 connects the chip data conversion section 702 and only the light emitting element array chip 400-1.

[0097] The image data signal line 707 connects the chip data conversion section 702 and each of the light emitting element array chips 400-1 to 400-20. Here, the number of the image data signal lines 707 is four, which is the same as the number of the light emitting element rows 604.

[0098] The communication signal line 708 connects the CPU 703 and each of the light emitting element array chips 400-1 to 400-20.

[0099] The +5V power supply line 712 connects the +5V generation circuit 710 and each of the light emitting element array chips 400-1 to 400-20.

[0100] The -5V power supply line 713 connects the switch (SW) 714 and each of the light emitting element array chips 400-1 to 400-20.

[0101] The image data generation section 701 performs dithering processing on image data input from the scanner section 100 or received and input from the outside of the image forming apparatus 1 at an image resolution instructed by the CPU 703 to generate image data for printout. The image data generation section 701 generates, for example, image data of one line x four rows (number of rows of light emitting elements) by performing dithering processing at an image resolution of 1200 dpi on each of the main scanning direction and the sub-scanning direction. The image data generation section 701 outputs the generated image data to the chip data conversion section 702.

[0102] The chip data conversion section 702 divides the image data input from the image data generation section 701 for each of the light emitting element array chips 400-1 to 400-20 in synchronization with a line synchronization signal input from the synchronization signal generation section 704. The chip data conversion section 702 outputs the divided image data to each of the light emitting element array chips 400-1 to 400-20 via the image data signal line 707. At the same time, the chip data conversion section 702 outputs a line synchronization signal to the light emitting element array chip 400-1 via the line synchronization signal line 706 and outputs a clock signal to the light emitting element array chips 400-1 to 400-20 via the clock signal line 705.

[0103] The CPU 703 sets a period in which the surface of the photosensitive drum 102 moves in the rotation direction by a predetermined pixel size at a predetermined rotation speed of the photosensitive drum 102 as one line period, and instructs the time interval of the signal period to the synchronization signal generation section 704.

[0104] For example, the CPU 703 sets a period in which the surface of the photosensitive drum 102 moves in the rotation direction by a pixel size of 1200 dpi (about 21.16 μm) at a predetermined rotation speed of the photosensitive drum 102 as one line period. Then, for example, in a case where exposure is performed at a speed of 200 mm / sec in the conveyance direction, the CPU 703 sets one line period to 105.8 μs (rounded down to one decimal place), and instructs the time interval of the signal period to the synchronization signal generation section 704. At this time, the CPU 703 calculates the speed in the conveyance direction by using a set value (fixed value) of the print speed set in a speed controller (not illustrated) that controls the speed of the photosensitive drum 102.

[0105] The CPU 703 instructs the image data generating section 701 of the image resolution. The CPU 703 outputs a power control signal to the switch 714 to turn the switch 714 on. The CPU 703 transmits and receives a communication signal to and from each of the light emitting element array chips 400-1 to 400-20 via the communication signal line 708. The CPU 703 sets a setting value in the communication signal based on header information and the like to be described below stored in the header information storage section 709, and outputs the communication signal with the setting value set to the light emitting element array chips 400-1 to 400-20 via the communication signal line 708.

[0106] The synchronization signal generating section 704 generates a line synchronization signal based on a time interval of a signal cycle instructed by the CPU 703, and outputs the generated line synchronization signal to the chip data conversion section 702.

[0107] The +5V generating circuit 710 converts a power supply voltage of +12V applied from a +12V power supply into a voltage of +5V, and supplies the voltage to each of the light emitting element array chips 400-1 to 400-20 via the +5V power supply line 712. As the +5V generating circuit 710, a general switching regulator circuit can be applied.

[0108] The -5V generating circuit 711 converts a power supply voltage of +12V applied from a +12V power supply into a voltage of -5V, and supplies the voltage to the switch 714. As the -5V generating circuit 711, a general switching regulator circuit can be applied.

[0109] The switch 714 serving as a switching element is turned on or off according to whether or not a power control signal is input from the CPU 703, thereby switching whether or not a voltage of -5V is supplied to the light emitting element array chips 400. When the power control signal is input from the CPU 703, the switch 714 is turned on, and a voltage of -5V is supplied to each of the light emitting element array chips 400-1 to 400-20 via the -5V power supply line 713. In a case where the switch 714 is turned off and a voltage of -5V is not supplied to the light emitting element array chips 400-1 to 400-20, the -5V power supply line 713 is in a floating state.

[0110] The printed circuit board 202 includes the light emitting element array chips 400-1 to 400-20 and the header information storage section 709.

[0111] The light emitting element array chip 400-1 and the light emitting element array chip 400-2 are connected by the signal line 708-1. The light emitting element array chip 400-2 and the light emitting element array chip 400-3 are connected by the signal line 708-2. Similarly, the light emitting element array chip 400-3 and the subsequent light emitting element array chip are connected one after another by the signal line 708-3 and the subsequent signal line.

[0112] Each of the light emitting element array chips 400-1 to 400-20 generates a row synchronization signal for the next chip based on an input row synchronization signal, and outputs the row synchronization signal to the next light emitting element array chip 400-1 to 400-20 via the signal line 708-1 and the subsequent signal line. Each of the light emitting element array chips 400-1 to 400-20 causes the light emitting element 602 to emit light based on an input clock signal, a row synchronization signal, image data, and a setting value set in a communication signal.

[0113] The header information storage section 709 is connected to the CPU 703 via the communication signal line 708. The header information storage section 709 is a storage device that stores header information such as light emitting amounts of the light emitting element array chips 400-1 to 400-20 and mounting position information.

[0114] <Configuration of circuit of light emitting element array chip>

[0115] The configuration of the circuit of the light emitting element array chip 400-1 to 400-20 of the exposure head 106 according to the first embodiment of the present application will be described in detail with reference to Figures 10 to 13

[0116] Since the configurations of the circuits of the light emitting element array chips 400-1 to 400-20 are the same, the configuration of the circuit of the light emitting element array chip 400-1 will be described, and the description of the configurations of the circuits of the light emitting element array chips 400-2 to 400-20 will be omitted. Further, since the clock signal is input to all of the blocks of the digital section 800, the clock signal line 705 is connected to all of the blocks of the digital section 800, but the description thereof will be omitted in Figure 10

[0117] The light emitting element array chip 400-1 includes the light emitting section 404 and the circuit section 406. The circuit section 406 includes the digital section 800 and the analog section 801.

[0118] ​​The clock signal, the image data signal, and the line synchronization signal are input from the chip data conversion section 702 to the digital section 800, and the communication signal is input from the CPU 703 to the digital section 800. The digital section 800 generates a drive signal (a pulse signal) for causing the light emitting element 602 to emit light based on the setting value set in the communication signal, the image data signal, and the line synchronization signal in synchronization with the clock signal, and outputs the generated drive signal to the analog section 801. The digital section 800 generates a line synchronization signal for the next chip based on the line synchronization signal, and outputs the generated line synchronization signal for the next chip to the light emitting element array chip 400-2 which is the next chip via the signal line 708-1.

[0119] Specifically, the digital section 800 includes a communication IF section 802, a register section 803, a line synchronization signal generation section 804, a reception signal generation section 805, and data holding sections 806-001 to 806-748.

[0120] The communication IF section 802 is connected to the CPU 703 via the communication signal line 708.

[0121] The setting value set in the communication signal input from the CPU 703 via the communication IF section 802 is written in the register section 803. The register section 803 reads the setting value written by the CPU 703, outputs the read setting value to the analog section 801 as drive current information, and outputs the read setting value to the reception signal generation section 805 as delay time information. Here, the drive current information is information on a set current value of a drive current flowing through the light emitting section 404, and is a digital value. In addition, the delay time information is information on a delay time in which the output of the data latch signal is to be delayed, and is a digital value.

[0122] The line synchronization signal generation section 804 delays the line synchronization signal input from the line synchronization signal line 706 by a predetermined time, generates a line synchronization signal for the next chip, and outputs the line synchronization signal to the light emitting element array chip 400-2 via the signal line 708-1.

[0123] The reception signal generation section 805 outputs the data latch signal we001 to the data holding section 806-001 at a timing in which the delay time in the delay time information input from the register section 803 is delayed, based on the line synchronization signal input via the line synchronization signal line 706.

[0124] The clock signal and the data latch signals wen (n = 1 to 748) are input to each of the data holding sections 806-001 to 806-748, and four lines of image data 1 to 4 are input at a timing in which the data latch signal wen is input.

[0125] AsFigure 11 As illustrated in the middle, each of the data holding sections 806-001 to 806-748 latches input image data 1 to 4, generates drive signals 1 to 4, and outputs the drive signals to four flip-flop circuits 807 and four gate circuits 808 of the analog section 801. Each of the data holding sections 806-001 to 806-748 includes one flip-flop circuit 809 that delays an input data latch signal wen by one clock and outputs the delayed data latch signal we(n+1) to the next data holding section 806-001 to 806-748.

[0126] The analog section 801 controls the drive of the light emitting section 404 on the basis of the drive current information input from the register section 803 and the drive signals input from the data holding sections 806-001 to 806-748.

[0127] Specifically, as Figure 12 As illustrated in the middle, the analog section 801 includes a drive circuit 900 including a current setting DAC 901, a current control MOSFET 902, and a switching MOSFET 903.

[0128] The drive circuit 900 is connected one-to-one to the light emitting element 602, and the number of the drive circuits 900 provided is the same as the number of the light emitting elements 602. In the present embodiment, 2992 drive circuits 900 (= 748 x 4 rows) are provided for one of the light emitting element array chips 400-1 to 400-20. Since all the drive circuits 900 have the same configuration, the configuration of only one drive circuit 900 will be described for the sake of simplicity of description.

[0129] The current setting DAC 901 converts a digital value of the drive current flowing through the light emitting section 404 indicated by the drive current information input from the register section 803 of the digital section 800 into an analog voltage, and outputs the analog voltage to a gate terminal G of the current control MOSFET 902.

[0130] The current control MOSFET 902 is a Pch MOSFET, and has a source terminal S connected to a power supply voltage VDD, a gate terminal G connected to an output terminal of the DAC 901, and a drain terminal D connected to a source terminal S of the switching MOSFET 903. The current control MOSFET 902 is configured in such a manner that the drive current for the light emitting element 602 flowing from the source terminal S to the drain terminal D increases as the analog voltage input from the current setting DAC 901 increases.

[0131] The switch MOSFET 903 is a Pch MOSFET. The switch MOSFET 903 has a source terminal S connected to the drain terminal D of the current control MOSFET 902, a gate terminal G connected to the output terminal of the data holding portion 806, and a drain terminal D connected to the anode terminal A of the light emitting element 602 of the light emitting portion 404. The binary drive signals 1 to 4 indicating high levels or low levels are input from the data holding portions 806-001 to 806-748 to the gate terminal G of the switch MOSFET 903.

[0132] The switch MOSFET 903 turns on when a high-level drive signal is input to the gate terminal G, and turns off when a low-level drive signal is input to the gate terminal G. When a high-level drive signal is input to the gate terminal G and the switch MOSFET 903 turns on, a current that becomes a drive current of the light emitting element 602 controlled by the current control MOSFET 902 flows from the source terminal S toward the drain terminal D.

[0133] Next, the power supply configuration for each of the digital portion 800, the analog portion 801, and the light emitting element 602 will be described in detail with reference to Figure 13

[0134] In Figure 13 , the description of the blocks inside the digital portion 800 is omitted for simplicity of description, and only one drive circuit 900 and one light emitting element 602 in the analog portion 801 are described.

[0135] A voltage of +5V is supplied as a power supply voltage from the +5V power supply line 712 to the digital portion 800. The digital portion 800 is connected to GND (0V) as a reference potential. Therefore, each block of the digital portion 800 operates at voltages of +5V and 0V. A voltage in the range of 0V to 5V is applied to the gate terminal of the switch MOSFET 903.

[0136] A voltage of +5V is supplied as a power supply voltage from the +5V power supply line 712 to the current setting DAC 901 of the analog portion 801. The current setting DAC 901 is connected to GND (0V) as a reference potential. As a result, a voltage in the range of 0V to 5V is applied to the gate terminal of the current control MOSFET 902. A voltage of +5V is supplied as a power supply voltage from the +5V power supply line 712 to the source terminal of the current control MOSFET 902.

[0137] ​The light emitting element 602 is, for example, an organic EL, and has an anode terminal A connected to a drain terminal of the switching MOSFET 903 and a cathode terminal K connected to the -5V power supply line 713. A voltage of -5V is supplied from the -5V power supply line 713 to the cathode terminal K of the light emitting element 602. In the light emitting element 602, a forward voltage of about 6V is generally generated by a driving current of several μA. In this case, the potential of the anode terminal A of the light emitting element 602 is about +1V obtained by adding +6V and -5V.

[0138] Since the drain-source voltage of the current control MOSFET 902 and the switching MOSFET 903 is about 1.5V, a voltage of about 9V is obtained by adding the drain-source voltage of 1.5V x 2 = 3V and the forward voltage of 6V of the light emitting element 602. Therefore, in order for the light emitting element 602 to emit light, the light emitting element array chip 400-1 to 400-20 needs a voltage of about 9V or more. Since the light emitting element array chip 400-1 to 400-20 can drive the light emitting element 602 in a range of 10V of +5V and -5V, the light emitting element 602 can emit light.

[0139] Hitherto, in a configuration in which an EL film is stacked on a circuit portion by deposition or the like, in consideration of the drain-source voltage of the MOSFET, it is necessary to form the light emitting element array chip by using a semiconductor process of 9V or more in order to secure the forward voltage of 6V of the light emitting element. On the other hand, in the present embodiment, +5V and -5V are supplied as power supply voltages to drive the light emitting element 602 in a range of 10V, and the digital portion 800 and the analog portion 801 are configured by a semiconductor process of +5V from GND. As a result, in the present embodiment, the size of the current control MOSFET 902 and the switching MOSFET 903 can be reduced, and the chip size of the light emitting element array chip 400-1 to 400-20 can be reduced.

[0140] <Operation of exposure head>

[0141] The operation of the exposure head 106 according to the first embodiment of the present application will be described in detail with reference to Figure 14 and Figure 15

[0142] The exposure head 106 starts the operation at the timing when the main power of the image forming apparatus 1 is turned on.

[0143] First, the CPU 703 determines whether or not there is a request for a print job from the user (S1).

[0144] In the case where there is no request for a print job from the user (S1: No), the CPU 703 repeats the operation of step S1. ​

[0145] On the other hand, in a case where there is a request for a print job from the user (S1: YES), the CPU 703 writes a setting value in the register section 803 of the light emitting element array chip 400-1 to 400-20 to perform register setting (S2).

[0146] Next, the CPU 703 outputs a power control signal to the switch 714 to supply a voltage of -5V to the cathode electrode of the light emitting element 602 of the light emitting element array chip 400-1 to 400-20 (-5V ON) (S3).

[0147] Next, the CPU 703 starts to output image data to the light emitting element array chip 400-1 to 400-20 at a predetermined timing to expose the photosensitive drum 102 (S4).

[0148] Next, the CPU 703 determines whether the print job has ended (S5).

[0149] In a case where the print job has not ended (S5: NO), the CPU 703 repeats the operation of step S5.

[0150] On the other hand, in a case where the print job has ended (S5: YES), the CPU 703 stops transmitting the power control signal to the switch 714, thereby causing the potential of the cathode electrode of the light emitting element 602 to enter a floating state, and ends the operation.

[0151] Next, the operation of the exposure head 106 will be described in more detail with reference to Figure 15

[0152] Referring to Figure 15 At time t=t0, the power of the image forming apparatus 1 is turned on, and a power voltage of +12V is supplied to the +5V generating circuit 710 and the -5V generating circuit 711. As a result, after time t=t1, the voltage of the +5V power line 712 becomes +5V. At this time, since the switch 714 is off, the -5V power line 713 is in a floating state (0V in Figure 15 ).

[0153] At time t=t1, upon receiving a job request from the user, the CPU 703 outputs a power control signal to the switch 714, whereby the potential of the -5V power line 713 becomes -5V, and the light emitting element 602 can be driven.

[0154] At time t=t2, at the end of the job, the CPU 703 stops outputting the power control signal to the switch 714 to turn off the switch 714, thereby causing the -5V power line 713 to be in a floating state (0V in Figure 15 ).

[0155] ​Operation of light emitting element array chip

[0156] The operation of the light emitting element array chips 400-1 to 400-20 of the exposure head 106 according to the first embodiment of the present application will be described in detail with reference to Figure 16 Four lines of image data (D1[1] to D1[4]) are simultaneously input to the data holding section 806-001. The data holding section 806-001 latches the image data (D1[1] to D1[4]) at the timing when the data latch signal we001 is input from the reception signal generating section 805, and generates the drive signals (P001[1] to P001[4]).

[0157] In addition, the data holding section 806-001 outputs a data latch signal we002 obtained by delaying the input data latch signal we001 by one clock to the next data holding section 806-002.

[0158] Similarly to the data holding section 806-001, four lines of image data (D2[1] to D2[4]) are simultaneously input to the data holding section 806-002. The data holding section 806-002 latches the image data (D2[1] to D2[4]) at the timing when the data latch signal we002 is input from the data holding section 806-001, and generates the drive signals (P002[1] to P002[4]).

[0159] In addition, the data holding section 806-002 outputs a data latch signal we003 obtained by delaying the input data latch signal we002 by one clock to the next data holding section 806-003.

[0160] In this way, the data holding sections 806-001 to 806-748 sequentially latch the image data while sequentially outputting the data latch signals.

[0161] The data holding sections 806-001 to 806-748 latch the image data, and output the latched signals as the drive signals to the analog section 801. Since four lines of image data are latched by one data latch signal, the data holding sections 806-001 to 806-748 simultaneously output the drive signals for four lines (for four pixels).

[0162]

[0163] ​As described above, in the configuration in which the light emitting element 602 and the analog section 801 are formed on the same chip, a voltage (-5V) lower than the voltages (+5V and a reference potential (GND)) supplied to the analog section 801 is supplied to the cathode electrode of the light emitting element 602. As a result, since the analog section 801 can be formed by using a semiconductor process with a relatively low withstand voltage, the size of the analog section 801 can be reduced, and the chip size can be reduced.

[0164] In addition, in the non-exposure time, the potential of the cathode electrode of the light emitting element 602 connected to the -5V power supply line 713 is brought into a floating state. As a result, the leakage current from the current control MOSFET 902 and the switching MOSFET 903 to the light emitting element 602, which is generated even in the off state in the non-exposure time, can be suppressed, and the power consumption can be suppressed.

[0165] In the present embodiment, the analog section 801 operates between a first potential +5V and a second potential 0V, and the light emitting element 602 operates between a third potential +1V and a fourth potential -5V. In addition, the potential difference between the third potential +1V and the fourth potential -5V is equal to or greater than the potential difference between the first potential +5V and the second potential 0V. As a result, in the configuration in which the light emitting element 602 and the analog section 801 are formed as one chip, while the forward voltage of the light emitting element 602 is ensured, the analog section 801 can be formed by using a semiconductor process with a low withstand voltage, and the chip size can be reduced.

[0166] In addition, in the present embodiment, the third potential +1V is lower than the first potential +5V, and the fourth potential -5V is lower than the second potential 0V. The potential difference between the second potential 0V and the fourth potential -5V is equal to or greater than the potential difference between the first potential +5V and the second potential 0V. The second potential 0V is a ground potential, the first potential +5V is a positive potential with respect to the ground potential, and the fourth potential -5V is a negative potential with respect to the ground potential.

[0167] In addition, in the present embodiment, in the case where the switch 714 is switched in a manner that no current is supplied to the light emitting element 602, the potential of the cathode terminal K of the light emitting element 602 becomes a fifth potential of at least 0V higher than the fourth potential -5V. The fifth potential 0V is equal to the second potential 0V.

[0168] In addition, in the present embodiment, the fourth potential -5V is lower than the first potential +5V. The second potential 0V is a ground potential. The third potential +1V is higher than the second potential 0V.

[0169] In the present embodiment, the voltage is not limited to +5V and -5V, and any voltage other than +5V and -5V can be supplied as long as the voltage can drive the light emitting element 602. For example, a 10V voltage range of +4V and -6V can be ensured in addition to the 10V voltage range of +5V and -5V.

[0170] In the present embodiment, 20 light emitting element array chips 400-1 to 400-20 are provided on the printed circuit board 202, but the present application is not limited thereto, and any number of light emitting element array chips can be provided on the printed circuit board 202 as necessary.

[0171] (Second Embodiment)

[0172] Since the configuration of the image forming apparatus according to the second embodiment of the present application is the same as that of the image forming apparatus 1 illustrated in Figure 1 , a description thereof is omitted. In addition, in the configuration of the exposure head according to the present embodiment, since the configuration other than the circuit configuration of the exposure head is the same as that in Figures 3 to 8 , a description of the configuration other than the circuit configuration of the exposure head is omitted.

[0173] The above first embodiment has a configuration in which the cathode electrodes of the plurality of light emitting elements 602 are common, but the present embodiment has a configuration in which the anode electrodes of the plurality of light emitting elements 602 are common.

[0174] <Configuration of Circuit of Exposure Head>

[0175] The configuration of the circuit of the exposure head according to the second embodiment of the present application will be described in detail with reference to Figure 17 .

[0176] In Figure 17 , portions having the same configuration as that in Figure 9 are denoted by the same reference numerals, and a description thereof is omitted.

[0177] The exposure head according to the present embodiment includes an image controller section 1301 that transmits a signal or data for controlling the printed circuit board 1302 to the printed circuit board 1302 and performs processing of image data and processing of exposure timing. The signal and data transmitted from the image controller section 1301 to the printed circuit board 1302 include a clock signal, image data, a line synchronization signal, and a communication signal.

[0178] Specifically, the image controller section 1301 includes an image data generation section 701, a chip data conversion section 702, a CPU 703, a synchronization signal generation section 704, a +5V generation circuit 710, a switch 714, and a +10V generation circuit 1303.

[0179] Here, the image controller section 1301 and the printed circuit board 1302 are connected by the clock signal line 705, the horizontal synchronization signal line 706, the image data signal line 707, the communication signal line 708, the +5V power supply line 712, and the +10V power supply line 1304.

[0180] The +10V power supply line 1304 connects the switch 714 and each of the light emitting element array chips 1400-1 to 1400-20.

[0181] The +10V generation circuit 1303 converts a power supply voltage of +12V applied from an external +12V power supply into a +10V voltage, and supplies the voltage to the switch 714. As the -5V generation circuit 711, a general switching regulator circuit can be applied.

[0182] The switch 714 is turned on or off according to whether a power supply control signal is input from the CPU 703, thereby switching whether a voltage of +10V is supplied to the light emitting element array chips 1400. When the power supply control signal is input from the CPU 703, the switch 714 is turned on, and a voltage of +10V is supplied to each of the light emitting element array chips 1400-1 to 1400-20 via the +10V power supply line 1304. In a case where the switch 714 is turned off and a voltage of +10V is not supplied to the light emitting element array chips 1400-1 to 1400-20, the +10V power supply line 1304 is in a floating state.

[0183] The printed circuit board 1302 includes the head information storage section 709 and the light emitting element array chips 1400-1 to 1400-20. Note that the arrangement and alignment of the light emitting element array chips 1400-1 to 1400-20 on the printed circuit board 1302 are the same as those of the light emitting element array chips 400-1 to 400-20 on the printed circuit board 302.

[0184] The light emitting element array chip 1400-1 and the light emitting element array chip 1400-2 are connected by the signal line 708-1. The light emitting element array chip 1400-2 and the light emitting element array chip 1400-3 are connected by the signal line 708-2. Similarly, the light emitting element array chip 1400-3 and the subsequent light emitting element array chips are connected one after another by the signal line 708-3 and the subsequent signal lines.

[0185] Each of the light-emitting element array chips 1400-1 to 1400-20 generates a horizontal synchronization signal for the next chip, and outputs the horizontal synchronization signal to the next light-emitting element array chip 1400-2 to 1400-20 via signal line 708-1 and subsequent signal lines. Each of the light-emitting element array chips 1400-1 to 1400-20 causes the light-emitting element 602 to emit light based on the input clock signal, horizontal synchronization signal, image data, and setting values ​​set in the communication signal.

[0186] Head information storage unit 709 is connected to CPU 703 via communication signal line 708. Head information storage unit 709 is a storage device that stores head information such as the light emission amount and installation position information of light-emitting element array chips 1400-1 to 1400-20.

[0187] Because the light-emitting parts of the light-emitting element array chips 1400-1 to 1400-20 have the same... Figure 5 The configuration of the light-emitting part 404 shown in the middle diagram is the same, so its description is omitted.

[0188] <Circuit configuration of light-emitting element array chip>

[0189] Reference Figure 18 The circuit configuration of the light-emitting element array chips 1400-1 to 1400-20 of the exposure head according to the second embodiment of the present invention will be described in detail.

[0190] Since the circuit configurations of the light-emitting element array chips 1400-1 to 1400-20 are identical, the circuit configuration of light-emitting element array chip 1400-1 will be described, and the descriptions of the circuit configurations of light-emitting element array chips 1400-2 to 1400-20 will be omitted. Figure 18 In, it has the same Figure 12 In the configuration, the parts with the same configuration are represented by the same reference symbols, and their descriptions are omitted.

[0191] The light-emitting element array chip 1400-1 includes a light-emitting section 404 and a circuit section 406. The circuit section 406 includes a digital section 800 and an analog section 801.

[0192] In this embodiment, 2992 driving circuits 900 (748 x 4 rows) are provided for one of the light-emitting element array chips 1400-1 to 1400-20. Since all driving circuits 900 have the same configuration, for the sake of simplicity, the configuration of only one driving circuit 900 will be described.

[0193] The current-controlled MOSFET 902 is a Pch MOSFET. The current-controlled MOSFET 902 has a source terminal connected to the cathode of the light-emitting element 602, a gate terminal connected to the output terminal of the current-setting DAC 901, and a drain terminal connected to the source terminal of the switching MOSFET 903. The current-controlled MOSFET 902 is configured such that the current flowing from the source terminal to the drain terminal increases with the increase of the analog voltage input from the current-setting DAC 901.

[0194] The switching MOSFET 903 is a Pch MOSFET and has a source terminal connected to the drain terminal of the current control MOSFET 902, a gate terminal connected to the output terminal of the data holding section 806, and a drain terminal connected to GND. Binary drive signals 1 to 4 indicating a high or low level are input to the gate terminal of the switching MOSFET 903 from the data holding sections 806-001 to 806-748.

[0195] The switching MOSFET 903 is turned on when a high-level drive signal is input to the gate terminal and turned off when a low-level drive signal is input to the gate terminal. When a high-level drive signal is input to the gate terminal and the switching MOSFET 903 is turned on, the current that drives the light-emitting element 602, which is controlled by the current-controlled MOSFET 902, flows from the source terminal to the drain terminal.

[0196] Next, we will refer to Figure 19 The power supply configuration of each of the digital unit 800, analog unit 801, and light-emitting element 602 is described in detail.

[0197] exist Figure 19 In, it has the same Figure 11 In the configuration, the same configuration parts are represented by the same reference symbols, and their descriptions are omitted. Additionally, in Figures 20 to 21 In order to simplify the description, the description of the blocks inside the digital section 800 is omitted, and only a driving circuit 900 and a light-emitting element 602 in the analog section 801 are described.

[0198] A +10V voltage is supplied from the +10V power supply line 1304 to the anode terminal A of the light-emitting element 602, and the cathode terminal is connected to the source terminal of the current-controlled MOSFET 902. The light-emitting element 602 is, for example, an organic EL, and typically generates a forward voltage of about 6V with a drive current of a few μA. That is, the potential of the cathode terminal K of the light-emitting element 602 becomes about +4V, which is obtained by subtracting 6V from +10V.

[0199] Since the drain-source voltage of the current control MOSFET 902 and the switching MOSFET 903 is about 1.5 V, by adding the drain-source voltage of 1.5 V x 2 = 3 V to the forward voltage of 6 V of the light emitting element 602, a voltage of about 9 V is obtained. Therefore, in order for the light emitting element 602 to emit light, the light emitting element array chip 1400-1 to 1400-20 needs a voltage of about 9 V or more. Since the light emitting element array chip 1400-1 to 1400-20 can drive the light emitting element 602 in the range of 10 V from GND (0 V) to +10 V, the light emitting element 602 can emit light.

[0200] Hitherto, in a configuration in which an EL film is stacked on a circuit portion by deposition or the like, in consideration of the drain-source voltage of a MOSFET, it has been necessary to form a light emitting element array chip by using a semiconductor process of 9 V or more in order to secure the forward voltage of 6 V of a light emitting element. On the other hand, in the present embodiment, GND and +10 V are supplied as power supply voltages to drive the light emitting element 602 in the range of 10 V, and the digital portion 800 and the analog portion 801 are configured by a semiconductor process of +5 V from GND. As a result, in the present embodiment, it is possible to reduce the size of the current control MOSFET 902 and the switching MOSFET 903, and it is possible to reduce the chip size of the light emitting element array chip 1400-1 to 1400-20.

[0201] <Operation of exposure head>

[0202] The operation of the exposure head 106 according to the second embodiment of the present application will be described in detail with reference to Figure 21

[0203] The exposure head 106 starts operation at the timing when the main power supply of the image forming apparatus 1 is turned on.

[0204] First, the CPU 703 determines whether or not there is a request for a print job from a user (S11).

[0205] In the case where there is no request for a print job from a user (S11: No), the CPU 703 repeats the operation of Step S11.

[0206] On the other hand, in the case where there is a request for a print job from a user (S11: Yes), the CPU 703 writes a setting value in the register portion 803 of the light emitting element array chip 1400-1 to 1400-20 to perform register setting (S12).

[0207] ​Next, the CPU 703 outputs a power control signal to the switch 714 to supply a voltage of +10V to the anode electrode of the light emitting element 602 of the light emitting element array chip 1400-1 to 1400-20 (+10V ON) (S13).

[0208] Next, the CPU 703 starts outputting image data to the light emitting element array chips 1400-1 to 1400-20 at a predetermined timing to expose the photosensitive drum 102 (S14).

[0209] Next, the CPU 703 determines whether the print job has ended (S15).

[0210] In a case where the print job has not ended (S15: No), the CPU 703 repeats the operation of step S15.

[0211] On the other hand, in a case where the print job has ended (S15: Yes), the CPU 703 stops transmitting the power control signal to the switch 714, thereby causing the potential of the anode electrode of the light emitting element 602 to enter a floating state, and ends the operation.

[0212] Next, the operation of the exposure head 106 will be described in more detail with reference to Figure 21 The operation of the exposure head 106 will be described in more detail.

[0213] Referring to Figure 21 At time t=t10, the power of the image forming apparatus 1 is turned on, and a power voltage of +12V is supplied to the +5V generating circuit 710 and the +10V generating circuit 1303. As a result, after time t=t10, the voltage of the +5V power line 712 becomes +5V. At this time, since the switch 714 is off, the potential of the +10V power line 1304 is in a floating state (0V in Figure 21 ).

[0214] At time t=tll, upon receiving a job request from a user, the CPU 703 outputs a power control signal to the switch 714, thereby the potential of the +10V power line 1304 becomes +10V, and the light emitting element 602 can be driven.

[0215] At time t=t12, at the end of the job, the CPU 703 stops outputting a power control signal to the switch 714 and causes the switch 714 to be off, thereby causing the potential of the +10V power line 1304 to be in a floating state (0V in ​ ).

[0216] As described above, in the configuration in which the light emitting element 602 and the analog section 801 are formed on the same chip, a voltage (+10V) higher than the voltages (+5V and the reference potential (GND)) supplied to the analog section 801 is supplied to the anode electrode of the light emitting element 602. As a result, since the analog section 801 can be formed by using a semiconductor process with a relatively low withstand voltage, the size of the analog section 801 can be reduced, and the chip size can be reduced.

[0217] In addition, in the non-exposure, the potential of the anode electrode of the light emitting element 602 connected to the +10V power supply line 1304 is made to be in a floating state. As a result, the leakage current from the current control MOSFET 902 and the switching MOSFET 903 to GND, which generates even in the off state at the time of non-exposure, can be suppressed, and the power consumption can be suppressed.

[0218] In the present embodiment, the analog section 801 operates between a first potential +5V and a second potential 0V, and the light emitting element 602 operates between a third potential +10V and a fourth potential +4V. In addition, the potential difference between the third potential +10V and the fourth potential +4V is equal to or greater than the potential difference between the first potential +5V and the second potential 0V. As a result, in the configuration in which the light emitting element 602 and the analog section 801 are formed as one chip, while the forward voltage of the light emitting element 602 is secured, the analog section 801 can be formed by using a semiconductor process with a low withstand voltage, and the chip size can be reduced.

[0219] In addition, in the present embodiment, the third potential +10V is higher than the first potential +5V, and the fourth potential +4V is higher than the second potential 0V. The potential difference between the first potential +5V and the third potential +10V is equal to or greater than the potential difference between the first potential +5V and the second potential 0V.

[0220] In addition, in the present embodiment, in the case where the switch 714 is switched in a manner that no current is supplied to the light emitting element 602, the potential becomes a fifth potential of at least 0V lower than the first potential +5V. The fifth potential 0V is equal to the second potential 0V.

[0221] Further, in the present embodiment, the fourth potential +4V is lower than the first potential +5V. The second potential 0V is a ground potential. The third potential +10V is higher than the second potential 0V.

[0222] In the present embodiment, the voltages are not limited to +5V and +10V, and can be voltages other than 5V and 10V, as long as the light emitting element 602 can be driven.

[0223] In the present embodiment, 20 light emitting element array chips 1400-1 to 1400-20 are provided on the printed circuit board 1302, but the present application is not limited thereto, and any number of light emitting element array chips can be provided on the printed circuit board 1302 as necessary.

[0224] Needless to say, the present application is not limited to the above embodiments, and various modifications can be made without departing from the spirit of the present application.

[0225] Although the present application has been described with reference to exemplary embodiments, the present application is not limited to the disclosed exemplary embodiments. The following claims are to be given the broadest interpretation to encompass all modifications, equivalent structures and functions.

[0226] This application claims priority based on Japanese Patent Application No. 2020-210272, filed December 18, 2020, the entire contents of which are incorporated herein by reference.

Claims

1. An exposure head configured to expose a photosensitive drum, the exposure head comprising: a substrate; a plurality of strip-shaped semiconductor chips each including a plurality of light emitting elements that emit light and a drive circuit that drives the light emitting elements, the plurality of strip-shaped semiconductor chips being arranged on the substrate; and a lens array configured to collect light from the light emitting elements on the photosensitive drum, wherein the drive circuit is supplied with a first power supply voltage and a second power supply voltage, the light emitting elements are supplied with a third power supply voltage and a fourth power supply voltage, and a potential difference between the third power supply voltage and the fourth power supply voltage is greater than a potential difference between the first power supply voltage and the second power supply voltage.

2. The exposure head according to claim 1, the light emitting elements have an anode terminal connected to the third power supply voltage and a cathode terminal connected to the fourth power supply voltage, wherein the third power supply voltage is lower than the first power supply voltage, and the fourth power supply voltage is lower than the second power supply voltage.

3. The exposure head according to claim 1 or 2, a potential difference between the second power supply voltage and the fourth power supply voltage is equal to or greater than a potential difference between the first power supply voltage and the second power supply voltage. wherein 4. The exposure head according to claim 1, the second power supply voltage is a ground potential, wherein the first power supply voltage is a positive potential with respect to the ground potential, and the fourth power supply voltage is a negative potential with respect to the ground potential.

5. The exposure head according to claim 1, the light emitting elements have an anode terminal connected to the third power supply voltage and a cathode terminal connected to the fourth power supply voltage, wherein the third power supply voltage is higher than the first power supply voltage, and the fourth power supply voltage is higher than the second power supply voltage.

6. The exposure head according to claim 5, a potential difference between the first power supply voltage and the third power supply voltage is equal to or greater than a potential difference between the first power supply voltage and the second power supply voltage. wherein 7. The exposure head according to claim 1, the fourth power supply voltage is lower than the first power supply voltage. wherein, 8. The exposure head according to claim 1, the second power supply voltage is a ground potential. wherein 9. The exposure head according to claim 1, the third power supply voltage is higher than the second power supply voltage. wherein 10. The exposure head according to claim 1, the light emitting elements include an organic EL film. wherein, 11. The exposure head according to claim 10, the organic EL film is formed on the drive circuit. wherein 12. An image forming apparatus comprising: a charger configured to charge a photosensitive drum; the exposure head according to any one of claims 1 to 11 configured to expose the photosensitive drum charged by the charger to form an electrostatic latent image on the photosensitive drum; and a developing device configured to develop the electrostatic latent image to form a developer image on the photosensitive drum. ​

Images