Piezoresistive mems absolute pressure sensor and method of manufacturing the same

Abstract

The application discloses a piezoresistive MEMS absolute pressure sensor and a manufacturing method thereof, and belongs to the field of MEMS sensors. In the method, a groove structure is formed at a silicon substrate, the groove structure forms a vacuum cavity under subsequent bonding of the silicon substrate and a top silicon wafer, a piezoresistive structure is formed at the top silicon wafer, and when the piezoresistive structure is exposed, a zero-layer alignment mark on the silicon substrate is positioned through a micropore array. Thus, without using a double-sided photolithography process, the piezoresistive structure of the top silicon wafer and the vacuum cavity of the silicon substrate can be accurately aligned through one-time exposure process, and the problem of offset error caused by alignment of upper and lower two layers after the multiple double-sided photolithography processes is avoided.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of MEMS sensors, in particular to a piezoresistive MEMS absolute pressure sensor and a manufacturing method thereof. BACKGROUND

[0002] In the related art, the size of pressure is often responded in real time by the deformation of an electric response type pressure sensor under the action of pressure, wherein the deformation of the sensor is converted into the change of an electric performance parameter of the sensor. Among them, the piezoresistive pressure sensor has simple preparation process, high response stability, strong anti-interference ability, high sensitivity, good linearity and simple subsequent processing circuit, so it has been widely used and become a research hotspot in the field of flexible pressure sensors.

[0003] The piezoresistive absolute pressure sensor includes three main components, namely a piezoresistor, a stress film and a vacuum cavity. Commonly, a Wheatstone bridge composed of four piezoresistors is used to convert the pressure acting on the sensor into the change of the resistance value of the piezoresistor through the stress change of the film, and then the changed resistance value is detected by the corresponding measurement circuit, and finally the size of the measured pressure acting on the film is measured.

[0004] In the manufacturing process of the traditional piezoresistive absolute pressure sensor, the stress film and the vacuum cavity are usually formed by using deep etching technology and wafer bonding technology. In this process, double-sided photolithography technology is used multiple times to realize the alignment between the patterns of the upper and lower silicon wafers. However, multiple double-sided photolithography processes will increase the alignment error between the patterns of the upper and lower layers, and thus the piezoresistive pressure sensor often has large sensitivity drift, zero output and zero drift. How to solve the problem of zero drift caused by the above process deviation and manufacture high-quality piezoresistive pressure sensors is the subject that the applicant is committed to solve and wants to overcome. SUMMARY

[0005] The present application provides a piezoresistive MEMS absolute pressure sensor and a manufacturing method thereof, which can solve the problem of zero drift caused by process deviation and thus manufacture high-quality piezoresistive pressure sensors.

[0006] In one aspect, the present application provides a piezoresistive MEMS absolute pressure sensor manufacturing method, which comprises:

[0007] providing an N-type silicon substrate;

[0008] forming a zero-layer alignment mark above the N-type silicon substrate;

[0010] forming a groove structure according to the zero-layer alignment mark;

[0011] growing an oxide layer above the N-type silicon substrate;

[0011] a top silicon wafer is provided above the oxide layer;

[0012] the top silicon wafer is bonded with the N-type substrate, and a CSOI structure with a vacuum cavity is formed between the top silicon wafer and the N-type substrate;

[0013] a micro-hole trench array is formed at the top silicon wafer above the zero-layer alignment mark, and the micro-hole trench array is used for positioning the zero-layer alignment mark;

[0014] a piezoresistive structure is formed at the top silicon wafer;

[0015] an oxide isolation medium layer is deposited, and a contact hole pattern is formed at the oxide isolation medium layer;

[0016] a metal wiring is formed at the contact hole pattern;

[0017] a passivation layer is grown, and a metal pad is formed at the passivation layer at a position corresponding to the contact hole pattern.

[0018] In another aspect, the application provides a piezoresistive MEMS absolute pressure sensor, which comprises:

[0019] an N-type silicon substrate, a zero-layer alignment mark is formed above the N-type silicon substrate, and a groove structure is formed at the zero-layer alignment mark;

[0020] an oxide layer is formed above the N-type silicon substrate;

[0021] a top silicon wafer is formed above the oxide layer and is bonded with the N-type substrate, and a CSOI structure with a vacuum cavity is formed between the top silicon wafer and the N-type substrate;

[0022] a micro-hole trench array is formed at the top silicon wafer above the zero-layer alignment mark;

[0023] a piezoresistive structure is formed at the top silicon wafer;

[0024] an oxide isolation medium layer is formed above the top silicon wafer and has a contact hole pattern;

[0025] a metal wiring is formed at the contact hole pattern;

[0026] a passivation layer is formed above the oxide isolation medium layer and has a metal pad at a position corresponding to the contact hole pattern.

[0027] The application provides a piezoresistive MEMS absolute pressure sensor and a manufacturing method thereof. In the method, a groove structure is formed at a silicon substrate, the groove structure forms a vacuum cavity under subsequent bonding of the silicon substrate and a top silicon wafer, a piezoresistive structure is formed at the top silicon wafer, and when the piezoresistive structure is exposed, a zero layer alignment mark on the silicon substrate is positioned by a micropore array. In this way, without using a double-sided photolithography process, the piezoresistive structure of the top silicon wafer and the vacuum cavity of the silicon substrate can be accurately aligned by one-time exposure process, and the problem of offset error caused by alignment of the upper and lower two layers after multiple double-sided photolithography processes in the related art is avoided. BRIEF DESCRIPTION OF DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the specific embodiments or prior art description will be briefly introduced. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0029] Figures 1 to 9 A product structure schematic diagram in the piezoresistive MEMS absolute pressure sensor manufacturing method is shown.

[0030] Figure 10 An alignment mark and a hole and groove array top view schematic diagram are shown.

[0031] Figure 11 A top view and a cross-sectional view of an alignment mark and a hole and groove array are shown. Figure 10

[0032] A top view and a cross-sectional view of an alignment mark and a hole and groove array are shown. Figure 12 Figure 10 A glue coating schematic diagram using a micropore and groove array structure is shown.

[0033] Figure 13 A glue coating schematic diagram using a large opening groove structure is shown.

[0034] EMBODIMENT Figure 14 The technical solutions in the present application will be described clearly and completely below with reference to the drawings. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0035] The technical solutions in the present application will be described clearly and completely below with reference to the drawings. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0036] ​In the description of the application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation of the application. In addition, the terms "first", "second", "third" are only for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0037] In the description of the application, it should be noted that unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connecting" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the internal communication of two elements, it can be wireless connection, or it can be wired connection. For those skilled in the art, the specific meaning of the above terms in the application can be understood according to the specific circumstances.

[0038] In addition, the technical features involved in different embodiments of the application described below can be combined with each other as long as there is no conflict.

[0039] Please refer to Figures 1 to 9 , which shows the product structure schematic diagram under the manufacturing method of piezoresistive MEMS absolute pressure sensor.

[0040] Step one, provide N-type silicon substrate 1.

[0041] Step two, form zero layer alignment mark A above the N-type silicon substrate.

[0042] As shown in Figure 1 and Figure 2 , the zero layer alignment mark A is formed on the N-type silicon substrate by using photoetching and etching process.

[0043] Step three, form groove structure 2 according to zero layer alignment mark A.

[0044] In one possible implementation, as shown in Figure 3 , first, make a front slot pattern according to the zero layer alignment mark A, and then form the groove structure 2 at the front slot pattern by etching process.

[0045] Step four, grow an oxide layer 3 above the N-type silicon substrate.

[0046] As shown in Figure 4 , grow an oxide layer 3 on the N-type substrate by furnace tube process.

[0047] Step five, a top silicon wafer 4 is provided above the oxide layer 3.

[0048] Continuing as shown in Figure 4 , a top silicon wafer 4 is provided above the oxide layer 3.

[0049] Step six, the top silicon wafer 4 is bonded with the N-type substrate, and a CSOI structure with a vacuum cavity is formed between the top silicon wafer 4 and the N-type substrate.

[0050] Continuing as shown in Figure 4 , the top silicon wafer 4 is bonded with the N-type substrate by wafer fusion bonding technology, and a CSOI (Cavity SOI) structure with a vacuum cavity is formed between the top silicon wafer 4 and the N-type substrate.

[0051] Step seven, a micro-hole slot array 5 is formed at the top silicon wafer 4 above the zero-layer alignment mark A, and the micro-hole slot array 5 is used to position the zero-layer alignment mark A.

[0052] As shown in Figure 5 , a micro-hole slot array 5 is formed on the top silicon wafer 4 above the position of the zero-layer alignment mark A by using photolithography and deep silicon etching process.

[0053] Step eight, a piezoresistive structure 6 is formed at the top silicon wafer 4.

[0054] As shown in Figure 6 , the piezoresistive structure 6 is formed by photolithography, implantation, push well, etc. When the piezoresistive structure 6 is exposed, the zero-layer alignment mark A on the silicon substrate is positioned by the micro-hole array, so that the accurate alignment of the piezoresistive structure 6 of the top silicon layer and the vacuum slot structure of the substrate layer can be realized by one-time exposure process.

[0055] Step nine, an oxide isolation medium layer 7 is deposited and a contact hole pattern 8 is formed at the oxide isolation medium layer 7.

[0056] As shown in Figure 7 , the oxide isolation medium layer 7 is deposited by using LPCVD, and the contact hole pattern 8 is formed by photolithography and etching process.

[0057] Step ten, a metal wiring 9 is formed at the contact hole pattern 8.

[0058] As shown in 8, metal aluminum is sputtered, and the metal wiring 9 is formed at the contact hole pattern 8 by photolithography and etching process.

[0059] Step eleven, a passivation layer 10 is grown, and a metal pad 11 is formed at the passivation layer 10 at the corresponding position of the contact hole pattern 8.

[0060] As shown in Figure 9As shown, the passivation layer 10 is grown by PECVD, and the passivation layer 10 is a silicon nitride film, and the metal pad 11 is formed by a photolithography and etching process.

[0061] In a conventional piezoresistive absolute pressure sensor manufacturing process, a deep etching technique and wafer bonding technique are usually used to form a stress film and a vacuum cavity. In this process, double-sided photolithography is used multiple times to achieve alignment between the patterns on the upper and lower silicon wafers. However, the multiple double-sided photolithography processes increase the alignment error between the patterns on the upper and lower silicon wafers. As a result, piezoresistive pressure sensors often have large sensitivity drift, zero output, and zero drift. How to solve the zero drift problem caused by the above process deviation and manufacture high-quality piezoresistive pressure sensors is a problem that the applicant is trying to solve and overcome.

[0062] The present application provides a piezoresistive MEMS absolute pressure sensor and a manufacturing method thereof, which can solve the zero drift problem caused by process deviation and further manufacture high-quality piezoresistive pressure sensors. In the method, a groove structure 2 is formed on a silicon substrate, the groove structure 2 forms a vacuum cavity after the silicon substrate is bonded with a top layer silicon wafer 4, and a piezoresistive structure 6 is formed on the top layer silicon wafer 4. When the piezoresistive structure 6 is exposed to light, a zero layer alignment mark A on the silicon substrate is positioned by a micropore array. In this way, without using double-sided photolithography, the piezoresistive structure 6 on the top silicon wafer and the vacuum cavity on the silicon substrate can be accurately aligned by one exposure process, avoiding the problem of alignment error between the patterns on the upper and lower layers caused by multiple double-sided photolithography processes in related technologies.

[0063] The core of the present application is to accurately align the pattern (piezoresistive structure) on the top layer silicon wafer and the pattern (vacuum cavity) on the substrate silicon wafer without using double-sided photolithography. In general, different brands of photolithography machines have different shapes, sizes, and positions of alignment marks on wafers. For example, Figure 10 As shown in figures i) to j), b) is an alignment mark example of German Schott, c) is an alignment mark example of Dutch ASM, and d) is an alignment mark example of Japanese Canon. The coordinate position of the alignment mark corresponding to the used photolithography machine on the wafer is determined, and a hole slot array pattern is made on the top layer silicon wafer in a certain area range containing the alignment mark by deep silicon etching process. Figure 11 When the top silicon layer is etched through and stops on the substrate wafer oxide layer, as shown in the top view (1), the zero layer alignment mark on the bottom layer substrate silicon wafer can be clearly seen.

[0064] Of course, it should be noted that, Figure 10 The above is only an example and does not limit the alignment mark and hole slot array of the present application.

[0065] The skilled in the art should understand that, in order to facilitate the demonstration of the manufacturing process of the present technology, the holes and grooves drawn in the figure are not completely and closely arranged together (there is still a certain interval between the holes and grooves), and in fact the hole diameter and groove interval of the hole and groove array are microns, so that the alignment marks at the bottom of the hole and groove array can be clearly identified by the photoetching machine.

[0066] In addition, the skilled in the art should understand that, in the process of semiconductor chip processing, the groove structure can have a certain influence on some production process steps. For example, a deeper and wider groove can cause uneven spin coating of photoresist, which can cause deviation in the size of the exposed pattern, affect the morphology of the subsequent etching process structure, and even cause the accumulation of photoresist in the groove, resulting in the inability to completely remove the photoresist. In the present application, the depth of the hole and groove is the thickness of the top layer of silicon, and the thickness of the top silicon of the piezoresistive pressure sensor is determined by its pressure range. Within a certain range (for example, 50kpa~3000kpa), the larger the range means that the top silicon layer needs to be thicker, generally several microns to several tens of microns. When the top silicon layer is below 20um, a micro-hole and groove array (see Figure 11 ) or a wide groove structure (see Figure 12 ) can be selected. However, when the thickness of the top silicon layer exceeds 20um, only a micro-hole and groove array (see Figure 11 ) can be selected, because the dense micro-hole array does not affect the uniformity of the photoresist coating and does not cause the accumulation of photoresist in the micro-hole and groove.

[0067] As shown in Figure 13 , a photoresist coating diagram using a micro-hole and groove array structure is shown, Figure 14 a photoresist coating diagram using a large opening groove structure is shown. By comparison, it is found that the advantage of using a micro-hole and groove array structure is that the photoresist does not accumulate in the groove.

[0068] It should also be understood that the positions of the various units in the sensor structure can be arranged and adjusted as needed, which is within the scope of the present application. In addition, the shape, size, position of the alignment mark, and the shape, size, depth, position, and area of the hole and groove array in the present application can also be selected according to the brand and model of the photoetching machine used, and can be adjusted arbitrarily.

[0069] Obviously, the above embodiments are only examples for clear illustration, and are not limitations on the embodiments. Based on the above description, other different forms of changes or variations can be made by those skilled in the art. Here, all the embodiments do not need to be exhausted, and the obvious changes or variations derived therefrom are still within the scope of protection of the present application.

Claims

1. A method of manufacturing a piezoresistive MEMS absolute pressure sensor, characterized by, The method comprises: providing an N-type silicon substrate; forming a zero-layer alignment mark above the N-type silicon substrate; forming a groove structure according to the zero-layer alignment mark; growing an oxide layer above the N-type silicon substrate; providing a top silicon wafer above the oxide layer; bonding the top silicon wafer with the N-type silicon substrate to form a CSOI structure with a vacuum cavity between the top silicon wafer and the N-type silicon substrate; forming a micro-hole groove array at the top silicon wafer above the zero-layer alignment mark for positioning the zero-layer alignment mark; forming a piezoresistive structure at the top silicon wafer; depositing an oxide isolation medium layer and forming a contact hole pattern at the oxide isolation medium layer; forming a metal wiring at the contact hole pattern; growing a passivation layer and forming a metal pad at the passivation layer at a position corresponding to the contact hole pattern.

2. The method of claim 1, wherein, The zero-layer alignment mark is formed by a photolithography and etching process.

3. The method of claim 1, wherein, The groove structure formed according to the zero-layer alignment mark comprises: aligning the zero-layer alignment mark to make a front groove pattern; forming a groove structure at the front groove pattern by an etching process.

4. The method of claim 1, wherein, The oxide layer is grown by a furnace tube process.

5. The method of claim 1, wherein, The top silicon wafer and the N-type silicon substrate are bonded by a wafer fusion bonding technology.

6. The method of claim 1, wherein, The micro-hole groove array is obtained by a photolithography and deep silicon etching process on the top silicon wafer.

7. The method of claim 1, wherein, The piezoresistive structure is formed by a photolithography, implantation and push-well process.

8. The method of claim 1, wherein, The oxide isolation medium layer is deposited by an LPCVD and the contact hole pattern is formed by a photolithography and etching process.

9. The method of claim 1, wherein, The metal wiring formed at the contact hole pattern comprises: sputtering metal aluminum; forming the metal wiring at the contact hole pattern by a photolithography and etching process.

10. The method of claim 1, wherein, The passivation layer is grown by a PECVD and is a silicon nitride film, and the metal pad is formed by a photolithography and etching process.

11. A piezoresistive MEMS absolute pressure sensor, characterized by, The piezoresistive MEMS absolute pressure sensor comprises: an N-type silicon substrate with a zero-layer alignment mark formed thereon and a groove structure formed at the zero-layer alignment mark; an oxide layer above the N-type silicon substrate; a top silicon wafer above the oxide layer and bonded with the N-type silicon substrate to form a CSOI structure with a vacuum cavity between the top silicon wafer and the N-type silicon substrate; a micro-hole groove array formed at the top silicon wafer above the zero-layer alignment mark; a piezoresistive structure formed at the top silicon wafer; an oxide isolation medium layer above the top silicon wafer with a contact hole pattern formed thereon; a metal wiring at the contact hole pattern; a passivation layer above the oxide isolation medium layer with a metal pad formed at a position corresponding to the contact hole pattern.

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