An in-memory 2-bit data multiply-accumulate circuit and memory
By designing a multiply-accumulate calculation circuit for 2-bit data in memory, and utilizing a combination of storage modules and calculation circuits, and employing specific logic gates to implement multiply-accumulate operations, the problem of processor speed limitation when dealing with large amounts of data is solved, thus improving the computational efficiency of neural networks.
Patent Information
- Application Number
- CN202310408778.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-04-17
- Publication Date
- 2026-02-17
- Estimated Expiration
- 2043-04-17
AI Technical Summary
In traditional computing methods, processors cannot keep up with the speed when processing large amounts of data, which limits the computing speed of neural networks and necessitates improving the data throughput of in-memory computing circuits.
Design a multiply-accumulate calculation circuit for 2-bit stored data, including first and second storage modules, calculation circuit and switch, which are connected by bit lines and global bit lines. NMOS and PMOS transistors are used to realize data storage and calculation, and AND gate, OR gate and NAND gate are used to perform multiply-accumulate operations.
It reduces computation cycles, increases data throughput, and improves the computation speed of neural networks.
Smart Images
Figure CN116702846B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of integrated circuits, and in particular to an in-memory 2bit data multiply-accumulate calculation circuit and a memory. BACKGROUND
[0002] The traditional way of calculating data is to calculate only by the processor. Due to the development of neural networks, when the data volume is large, the processing volume is too large, and the processing speed of the processor cannot keep up, so there is a digital in-memory calculation circuit. The digital in-memory calculation circuit is currently widely concerned by the industry and academia. SUMMARY
[0003] The purpose of the present application is to provide an in-memory 2bit data multiply-accumulate calculation circuit and a memory, which realizes the multiply-accumulate operation of 2bit input data and 2bit weight data in the in-memory calculation circuit, helps to improve the data throughput of the in-memory calculation circuit, and further speeds up the calculation speed of the neural network.
[0004] To solve the above technical problems, the present application adopts the following technical scheme:
[0005] One aspect of the embodiment of the present application provides an in-memory 2bit data multiply-accumulate calculation circuit, which comprises: a first storage module and a second storage module, the first input end of the first storage module and the first input end of the second storage module are connected to a first bit line, the second input end of the first storage module and the second input end of the second storage module are connected to a second bit line, the first storage module stores or outputs first weight data through the first bit line and the second bit line, and the second storage module stores or outputs second weight data through the first bit line and the second bit line; a first calculation circuit, a second calculation circuit, a third calculation circuit and a fourth calculation circuit, the first input end of the first calculation circuit, the first input end of the second calculation circuit and the first input end of the third calculation circuit are connected to a first global bit line inputting first input data, the second input end of the first calculation circuit, the second input end of the second calculation circuit and the fourth input end of the third calculation circuit are connected to the first bit line, the third input end of the first calculation circuit, the third input end of the second calculation circuit, the third input end of the third calculation circuit and the first input end of the fourth calculation circuit are connected to a second global bit line inputting second input data, the fourth input end of the first calculation circuit, the fourth input end of the second calculation circuit, the second input end of the third calculation circuit and the second input end of the fourth calculation circuit are connected to the second bit line, the first calculation circuit is used to calculate the first bit data of the multiply-accumulate result, the second calculation circuit is used to calculate the second bit data of the multiply-accumulate result, the third calculation circuit is used to calculate the third bit data of the multiply-accumulate result, and the fourth calculation circuit is used to calculate the fourth bit data of the multiply-accumulate result.
[0006] In some embodiments, the computing circuit further comprises a first switch and a second switch, two ends of the first switch are connected with a first bit line and a first global bit line respectively, and two ends of the second switch are connected with a second bit line and a second global bit line respectively.
[0007] In some embodiments, the first storage module and the second storage module have the same structure, the first storage module comprises a third switch, a fourth switch and a storage circuit, one end of the third switch is connected with one end of the storage circuit, the other end of the third switch is connected with the first bit line, one end of the fourth switch is connected with the other end of the storage circuit, and the other end of the fourth switch is connected with the second bit line.
[0008] In some embodiments, the first switch, the second switch, the third switch and the fourth switch are all NMOS tubes.
[0009] In some embodiments, the storage circuit comprises a first NMOS tube, a first PMOS tube, a second NMOS tube and a second PMOS tube, a gate of the first NMOS tube is connected with a gate of the first PMOS tube, a drain of the second PMOS tube, a drain of the second NMOS tube and one end of the fourth switch, a gate of the second NMOS tube is connected with a gate of the second PMOS tube, a drain of the first PMOS tube, a drain of the first NMOS tube and one end of the third switch, sources of the first PMOS tube and the second PMOS tube are connected with a power supply, and sources of the first NMOS tube and the second NMOS tube are grounded.
[0010] In some embodiments, the first computing circuit comprises a first AND gate, a second AND gate and a third AND gate, a first input end of the first AND gate is connected with the first global bit line, a second input end of the first AND gate is connected with the first bit line, a first input end of the second AND gate is connected with the second global bit line, a second input end of the second AND gate is connected with the second bit line, an output end of the first AND gate is connected with a first input end of the third AND gate, an output end of the second AND gate is connected with a second input end of the third AND gate, and an output end of the third AND gate outputs first bit data of a multiply-accumulate result.
[0011] In some embodiments, the second computing circuit comprises a fourth AND gate, a fifth AND gate and a first NAND gate, a first input end of the fourth AND gate is connected with the first global bit line, a second input end of the fourth AND gate is connected with the first bit line, a first input end of the first NAND gate is connected with the second global bit line, a second input end of the first NAND gate is connected with the second bit line, an output end of the fourth AND gate is connected with a first input end of the fifth AND gate, an output end of the first NAND gate is connected with a second input end of the fifth AND gate, and an output end of the fifth AND gate outputs second bit data of the multiply-accumulate result.
[0012] In some embodiments, the third calculation circuit includes a sixth AND gate, a second NAND gate, a third NAND gate, a fourth NAND gate and an OR gate, a first input end of the second NAND gate is connected with the first global bit line, a second input end of the second NAND gate is connected with the second bit line, a first input end of the third NAND gate is connected with the second global bit line, a second input end of the third NAND gate is connected with the first bit line, a first output end of the second NAND gate is connected with a first input end of the fourth NAND gate and a first input end of the OR gate, an output end of the third NAND gate is connected with a second input end of the fourth NAND gate and a second input end of the OR gate, an output end of the fourth NAND gate is connected with a first input end of the sixth AND gate, an output end of the OR gate is connected with a second input end of the sixth AND gate, and an output end of the sixth AND gate outputs the third bit data of the multiply-accumulate result.
[0013] In some embodiments, the fourth calculation circuit includes a seventh AND gate, a first input end of the seventh AND gate is connected with the second global bit line, a second input end of the seventh AND gate is connected with the second bit line, and an output end of the seventh AND gate outputs the fourth bit data of the multiply-accumulate result.
[0014] An aspect of the embodiment of the present application provides a memory, which includes the calculation circuit as described above.
[0015] According to the in-memory 2bit data multiply-accumulate calculation circuit and the memory, the following beneficial effects can be achieved: the in-memory 2bit data multiply-accumulate calculation circuit can simultaneously perform multiply-accumulate calculation on 2bit input data and 2bit weight data, and compared with the single-bit data calculation mode, the in-memory 2bit data multiply-accumulate calculation circuit reduces the calculation period, and helps to improve the data throughput.
[0016] It should be understood that the above general description and the following detailed description are only exemplary and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS
[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.
[0018] Figure 1 The schematic diagram of the in-memory 2bit data multiply-accumulate calculation circuit according to the embodiment. DETAILED DESCRIPTION
[0019] With reference to the drawings of the embodiments of the application, the technical solutions in the embodiments of the application will be clearly and completely described, obviously, the described embodiments are only a part of the embodiments of the application, rather than all the embodiments of the application. Based on the embodiments of the application, all the other embodiments obtained by a person of ordinary skill in the art without creative work are within the protection scope of the application.
[0020] The terms "first", "second", "third" are only for descriptive purpose, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second", "third" can explicitly or implicitly include one or more of the features. In the description of the application, unless otherwise specified and limited, the meaning of "a plurality of" is two or more than two.
[0021] In the description of the application, it should be noted that, unless otherwise explicitly specified and limited, the terms "communication", "installation", "connection", "connection" should be understood in a broad sense, for example, it can be fixed connection, or detachable connection, or integral connection; can be mechanical connection, or electrical connection; can be directly connected, or indirectly connected through intermediate medium, can be the communication inside two elements. For a person of ordinary skill in the art, the specific meaning of the above terms in the application can be understood according to the specific circumstances.
[0022] Example implementations will now be described more fully with reference to the accompanying drawings. Example implementations may, however, be implemented in many different forms and should not be construed as limited to the examples set forth herein; rather, these example implementations are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example implementations to those skilled in the art. The accompanying drawings are included to provide a further understanding of the disclosure and are incorporated into and constitute a part of this specification. The drawings are not intended to be restrictive in any way. Like reference numerals in the drawings designate like parts, and thus repeated descriptions may be omitted.
[0023] The technical solutions of the embodiments of the present application will be briefly described below:
[0024] According to some embodiments, as Figure 1As shown, the computing circuit includes: a first storage module and a second storage module, the first input end of the first storage module and the second storage module is connected with the first bit line BL, the second input end of the first storage module and the second storage module is connected with the second bit line BLB, the first storage module stores or outputs the first weight data through the first bit line BL and the second bit line BLB, the second storage module stores or outputs the second weight data through the first bit line BL and the second bit line BLB; a first computing circuit, a second computing circuit, a third computing circuit and a fourth computing circuit, the first input end of the first computing circuit, the first input end of the second computing circuit and the first input end of the third computing circuit are connected with the first global bit line GBL inputting the first input data, the second input end of the first computing circuit, the second input end of the second computing circuit and the fourth input end of the third computing circuit are connected with the first bit line BL, the third input end of the first computing circuit, the third input end of the second computing circuit, the third input end of the third computing circuit and the first input end of the fourth computing circuit are connected with the second global bit line GBLB inputting the second input data, the fourth input end of the first computing circuit, the fourth input end of the second computing circuit, the second input end of the third computing circuit and the second input end of the fourth computing circuit are connected with the second bit line BLB, the first computing circuit is used for calculating the first bit data S3 of the multiply-accumulate result, the second computing circuit is used for calculating the second bit data S2 of the multiply-accumulate result, the third computing circuit is used for calculating the third bit data S1 of the multiply-accumulate result, and the fourth computing circuit is used for calculating the fourth bit data S0 of the multiply-accumulate result.
[0025] Based on the above embodiment, due to the development of neural networks, when the data volume is large, the processing volume is too large, and the processing speed of the processor cannot keep up, so there is an in-memory computing circuit, and therefore the in-memory 2bit data multiply-accumulate computing circuit of the application is designed, compared with the single-bit data computing mode, the in-memory 2bit data multiply-accumulate computing circuit reduces the computing period, which helps to improve the data throughput.
[0026] The first weight data, the second weight data, the first input data, the second input data, the first bit data S3, the second bit data S2, the third bit data S1 and the fourth bit data S0 are all 1-bit data. In some embodiments of the present application, the first weight data is output through the first bit line BL, and the second weight data is output through the second bit line BLB. The first weight data and the second weight data are multiplied with the first input data and the second input data, that is, the multiplication of 2-bit input data and 2-bit weight data, and there are 4-bit outputs. The first weight data, the second weight data, the first input data and the second input data are taken as input data to perform multiply-accumulate calculation through the first calculation circuit, the second calculation circuit, the third calculation circuit and the fourth calculation circuit, and the first weight data, the second weight data, the first input data and the second input data are multiplied and accumulated to obtain the first bit data S3, the second bit data S2, the third bit data S1 and the fourth bit data S0 of the multiply-accumulate result, wherein the first bit data S3 is the highest bit of the multiply-accumulate result, the second bit data S2 is the second highest bit of the multiply-accumulate result, the third bit data S1 is the second lowest bit of the multiply-accumulate result, and the fourth bit data S0 is the lowest bit of the multiply-accumulate result.
[0027] The accompanying drawings are incorporated in and constitute a part of the specification. Figure 1 The preferred embodiments of the present disclosure are further described in detail.
[0028] According to some embodiments, as shown in Figure 1 The calculation circuit further includes a first switch N8 and a second switch N9, two ends of the first switch N8 are connected with the first bit line BL and the first global bit line GBL respectively, and two ends of the second switch N9 are connected with the second bit line BLB and the second global bit line GBLB respectively.
[0029] When the first bit line BL and the first global bit line GBL need to be electrically connected, the first switch N8 is closed to achieve the electrical connection, and when the second bit line BLB and the second global bit line GBLB need to be electrically connected, the second switch N9 is closed to achieve the electrical connection.
[0030] According to some embodiments, as shown in Figure 1 The first storage module and the second storage module have the same structure, the first storage module includes a third switch N2, a fourth switch N3 and a storage circuit, one end of the third switch N2 is connected with one end of the storage circuit, the other end of the third switch N2 is connected with the first bit line BL, one end of the fourth switch N3 is connected with the other end of the storage circuit, and the other end of the fourth switch N3 is connected with the second bit line BLB.
[0031] The working principle based on the above embodiments is as follows: when storing the first weight data into the first storage module, the storage operation can be performed by closing the third switch N2 and the fourth switch N3. Only one storage module can be used for storage operations at a time. When the first storage module is performing a storage operation, the second storage module is closed; when the second storage module is performing a storage operation, the first storage module is closed. When the first storage module outputs the first weight data, the third switch N2 or the fourth switch N3 is closed for output. During the calculation process of this application, when the first storage module outputs the first weight data, the third switch N2 is closed to output the first weight data to the first bit line BL.
[0032] According to some embodiments, such as Figure 1 As shown, the first switch N8, the second switch N9, the third switch N2 and the fourth switch N3 all use NMOS transistors.
[0033] According to some embodiments, such as Figure 1 As shown, the storage circuit includes a first NMOS transistor N0, a first PMOS transistor P0, a second NMOS transistor N1, and a second PMOS transistor P1. The gate of the first NMOS transistor N0 is connected to the gate of the first PMOS transistor P0, the drain of the second PMOS transistor P1, the drain of the second NMOS transistor N1, and one end of a fourth switch N3. The gate of the second NMOS transistor N1 is connected to the gate of the second PMOS transistor P1, the drain of the first PMOS transistor P0, the drain of the first NMOS transistor N0, and one end of a third switch N2. The sources of both the first PMOS transistor P0 and the second PMOS transistor P1 are connected to a power supply, and the sources of both the first NMOS transistor N0 and the second NMOS transistor N1 are grounded.
[0034] According to some embodiments, such as Figure 1 As shown, the first calculation circuit includes a first AND gate AND0, a second AND gate AND1, and a third AND gate AND2. The first input of the first AND gate AND0 is connected to the first global bit line GBL, and the second input of the first AND gate AND0 is connected to the first bit line BL. The first input of the second AND gate AND1 is connected to the second global bit line GBLB, and the second input of the second AND gate AND1 is connected to the second bit line BLB. The output of the first AND gate AND0 is connected to the first input of the third AND gate AND2, and the output of the second AND gate AND1 is connected to the second input of the third AND gate AND2. The output of the third AND gate AND2 outputs the first bit data S3 of the multiplication and accumulation result.
[0035] The working principle of the above embodiment is as follows: First AND gate AND0 receives the first input data from the first global bit line GBL. Simultaneously, first AND gate AND0 receives the first weight data from the first storage module through the first bit line BL. First AND gate AND0 performs an AND operation on the first weight data and the first input data, and outputs the AND result to the third AND gate AND2. Second AND gate AND1 receives the second input data from the second global bit line GBLB. Simultaneously, second AND gate AND1 receives the second weight data from the second storage module through the second bit line BLB. Second AND gate AND1 performs an AND operation on the second weight data and the second input data, and outputs the AND result to the third AND gate AND2. Third AND gate AND2 performs an AND operation on the AND result of first AND gate AND0 and the AND result of second AND gate AND1 to obtain the first bit data S3 of the multiplication and accumulation result.
[0036] According to some embodiments, such as Figure 1 As shown, the second calculation circuit includes a fourth AND gate AND3, a fifth AND gate AND4, and a first NAND gate NAND0. The first input of the fourth AND gate AND3 is connected to the first global bit line GBL, and the second input of the fourth AND gate AND3 is connected to the first bit line BL. The first input of the first NAND gate NAND0 is connected to the second global bit line GBLB, and the second input of the first NAND gate NAND0 is connected to the second bit line BLB. The output of the fourth AND gate AND3 is connected to the first input of the fifth AND gate AND4, and the output of the first NAND gate NAND0 is connected to the second input of the fifth AND gate AND4. The output of the fifth AND gate AND4 outputs the second bit data S2 of the multiplication and accumulation result.
[0037] The working principle of the above embodiments is as follows: The fourth AND gate AND3 receives the first input data from the first global bit line GBL. Simultaneously, the fourth AND gate AND3 receives the first weight data from the first storage module through the first bit line BL. The fourth AND gate AND3 performs an AND operation on the first weight data and the first input data, and outputs the AND result to the fifth AND gate AND4. The first NAND gate NAND0 receives the second input data from the second global bit line GBL. Simultaneously, the first NAND gate NAND0 receives the second weight data from the second storage module through the second bit line BLB. The first NAND gate NAND0 performs a NAND operation on the second weight data and the second input data, and outputs the NAND result to the fifth AND gate AND4. The fifth AND gate AND4 performs an AND operation on the AND result of the fourth AND gate AND3 and the NAND result of the first NAND gate NAND0, obtaining the second bit data S2 of the multiplication and accumulation result.
[0038] According to some embodiments, such as Figure 1As shown, the third calculation circuit includes a sixth AND gate AND5, a second NAND gate NAND1, a third NAND gate NAND2, a fourth NAND gate NAND3, and an OR gate OR0. The first input of the second NAND gate NAND1 is connected to the first global bit line GBL, and the second input of the second NAND gate NAND1 is connected to the second bit line BLB. The first input of the third NAND gate NAND2 is connected to the second global bit line GBLB, and the second input of the third NAND gate NAND2 is connected to the first bit line BL. The first output of the second NAND gate NAND1 is connected to the first input of the fourth NAND gate NAND3 and the first input of the OR gate OR0. The output of the third NAND gate NAND2 is connected to the second input of the fourth NAND gate NAND3 and the second input of the OR gate OR0. The output of the fourth NAND gate NAND3 is connected to the first input of the sixth AND gate AND5, and the output of the OR gate OR0 is connected to the second input of the sixth AND gate AND5. The output of the sixth AND gate AND5 outputs the third bit data S1 of the multiplication and accumulation result.
[0039] The working principle of the above embodiment is as follows: The second NAND gate NAND1 receives the first input data from the first global bit line GBL. Simultaneously, the second NAND gate NAND1 receives the second weight data from the second storage module through the second bit line BLB. The second NAND gate NAND1 performs a NAND operation on the second weight data and the first input data, and then outputs the NAND result to the fourth NAND gate NAND3 and OR gate OR0. The third NAND gate NAND2 receives the second input data from the second global bit line GBL. Simultaneously, the third NAND gate NAND2 receives the first weight data from the first storage module through the first bit line BL. The third NAND gate NAND2 performs a NAND operation on the first weight data and the second input data, and then outputs the NAND result to the fourth NAND gate NAND3 and OR gate OR0. The fourth NAND gate NAND3 performs a NAND operation on the NAND result of the second NAND gate NAND1 and the NAND result of the third NAND gate NAND2, and then outputs the NAND result to the sixth AND gate AND5. The OR gate OR0 performs an OR operation on the NAND results of the second NAND gate NAND1 and the third NAND gate NAND2, and outputs the OR result of OR gate OR0 to the sixth AND gate AND5. The sixth AND gate AND5 performs an AND operation on the NAND results of the fourth NAND gate NAND3 and the OR result of OR gate OR0 to obtain the third bit data S1 of the multiplication and accumulation result.
[0040] According to some embodiments, such as Figure 1As shown, the fourth calculation circuit includes a seventh AND gate AND6. The first input of the seventh AND gate AND6 is connected to the second global bit line GBLB, the second input of the seventh AND gate AND6 is connected to the second bit line BLB, and the output of the seventh AND gate AND6 outputs the fourth bit data S0 of the multiplication and accumulation result.
[0041] The working principle based on the above embodiment is as follows: the seventh AND gate AND6 receives the second input data of the second global bit line GBLB, and at the same time, the seventh AND gate AND6 receives the second weight data of the second storage module through the second bit line BLB. The seventh AND gate AND6 performs AND-NOT operation on the second weight data and the second input data to obtain the fourth bit data S0 of the multiplication and accumulation result.
[0042] The overall working principle is as follows: the first weight data and the second weight data are input as two-bit binary digital signals, and the first input data and the second input data are input as two-bit binary digital signals. Then, the multiplication and accumulation calculation circuit of the 2-bit data in memory calculates the multiplication and accumulation result, as shown in Table 1. Substituting the first weight data, the second weight data, the first input data, and the second input data into the multiplication and accumulation calculation circuit of the 2-bit data in memory of this application yields the corresponding result. The corresponding calculation results of the first input data, the second input data, the first weight data, and the second weight data are shown in Table 1 below.
[0043] Table 1
[0044]
[0045]
[0046] According to some embodiments, this application provides a memory that includes the computing circuitry described above.
[0047] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.
[0048] Although this disclosure has been described with reference to several typical embodiments, it should be understood that the terminology used is descriptive and exemplary, and not restrictive. Because this disclosure can be embodied in many forms without departing from the spirit or substance of this application, it should be understood that the above embodiments are not limited to any of the foregoing details, but should be interpreted broadly within the spirit and scope defined by the appended claims. Therefore, all variations and modifications falling within the scope of the claims or their equivalents should be covered by the appended claims.
Claims
1. A multiply-accumulate calculation circuit storing 2 bits of data, characterized in that, The computing circuit includes: A first storage module and a second storage module, wherein the first input terminals of the first storage module and the second storage module are both connected to the first bit line, and the second input terminals of the first storage module and the second storage module are both connected to the second bit line, wherein the first storage module stores or outputs first weight data through the first bit line and the second bit line, and the second storage module stores or outputs second weight data through the first bit line and the second bit line; The system comprises a first calculation circuit, a second calculation circuit, a third calculation circuit, and a fourth calculation circuit. The first input terminals of the first, second, and third calculation circuits are all connected to a first global bit line for inputting first input data. The second, third, and fourth input terminals of the first, second, and third calculation circuits are all connected to a first bit line. The third, fourth, and fifth input terminals of the first, second, third, and fourth calculation circuits are all connected to a second global bit line for inputting second input data. The fourth, third, and fourth input terminals of the first, second, third, and fourth calculation circuits are all connected to a second bit line. The first calculation circuit is used to calculate the first bit of the multiply-accumulate result; the second calculation circuit is used to calculate the second bit of the multiply-accumulate result; the third calculation circuit is used to calculate the third bit of the multiply-accumulate result; and the fourth calculation circuit is used to calculate the fourth bit of the multiply-accumulate result.
2. The computing circuit according to claim 1, characterized in that, The computing circuit further includes a first switch and a second switch. The two ends of the first switch are respectively connected to a first bit line and a first global bit line, and the two ends of the second switch are respectively connected to a second bit line and a second global bit line.
3. The computing circuit according to claim 2, characterized in that, The first storage module has the same structure as the second storage module. The first storage module includes a third switch, a fourth switch, and a storage circuit. One end of the third switch is connected to one end of the storage circuit, and the other end of the third switch is connected to the first bit line. One end of the fourth switch is connected to the other end of the storage circuit, and the other end of the fourth switch is connected to the second bit line.
4. The computing circuit according to claim 3, characterized in that, The first switch, the second switch, the third switch and the fourth switch are all NMOS transistors.
5. The computing circuit according to claim 3, characterized in that, The storage circuit includes a first NMOS transistor, a first PMOS transistor, a second NMOS transistor, and a second PMOS transistor. The gate of the first NMOS transistor is connected to the gate of the first PMOS transistor, the drain of the second PMOS transistor, the drain of the second NMOS transistor, and one end of a fourth switch. The gate of the second NMOS transistor is connected to the gate of the second PMOS transistor, the drain of the first PMOS transistor, the drain of the first NMOS transistor, and one end of a third switch. The sources of both the first PMOS transistor and the second PMOS transistor are connected to a power supply, and the sources of both the first NMOS transistor and the second NMOS transistor are grounded.
6. The computing circuit according to claim 1, characterized in that, The first calculation circuit includes a first AND gate, a second AND gate, and a third AND gate. The first input of the first AND gate is connected to the first global bit line, the second input of the first AND gate is connected to the first bit line, the first input of the second AND gate is connected to the second global bit line, the second input of the second AND gate is connected to the second bit line, the output of the first AND gate is connected to the first input of the third AND gate, the output of the second AND gate is connected to the second input of the third AND gate, and the output of the third AND gate outputs the first bit of the multiplication and accumulation result.
7. The computing circuit according to claim 1, characterized in that, The second calculation circuit includes a fourth AND gate, a fifth AND gate, and a first NAND gate. The first input of the fourth AND gate is connected to the first global bit line, and the second input of the fourth AND gate is connected to the first bit line. The first input of the first NAND gate is connected to the second global bit line, and the second input of the first NAND gate is connected to the second bit line. The output of the fourth AND gate is connected to the first input of the fifth AND gate, and the output of the first NAND gate is connected to the second input of the fifth AND gate. The output of the fifth AND gate outputs the second bit of the multiplication and accumulation result.
8. The computing circuit according to claim 1, characterized in that, The third calculation circuit includes a sixth AND gate, a second NAND gate, a third NAND gate, a fourth NAND gate, and an OR gate. The first input of the second NAND gate is connected to the first global bit line, the second input of the second NAND gate is connected to the second bit line, the first input of the third NAND gate is connected to the second global bit line, the second input of the third NAND gate is connected to the first bit line, the first output of the second NAND gate is connected to the first input of the fourth NAND gate and the first input of the OR gate, the output of the third NAND gate is connected to the second input of the fourth NAND gate and the second input of the OR gate, the output of the fourth NAND gate is connected to the first input of the sixth AND gate, the output of the OR gate is connected to the second input of the sixth AND gate, and the output of the sixth AND gate outputs the third bit of the multiplication-accumulation result.
9. The computing circuit according to claim 1, characterized in that, The fourth calculation circuit includes a seventh AND gate, the first input of which is connected to the second global bit line, the second input of which is connected to the second bit line, and the output of which outputs the fourth bit of the multiplication and accumulation result.
10. A memory, characterized in that, The memory includes the computing circuitry as described in any one of claims 1 to 9.