A gallium oxide enhanced device and its manufacturing method

Abstract

The present invention discloses a gallium oxide enhancement-mode device and its fabrication method. First, an N-type gallium oxide epitaxial layer and a P-type gallium oxide epitaxial layer are grown sequentially on a gallium oxide substrate through epitaxial growth. Then, the length of the current-conducting layer is defined through photolithography. The source and channel lengths are formed through self-alignment, followed by ion implantation to form a bias region. Finally, metal is deposited on the upper and lower surfaces of the device and annealed to form ohmic contacts. The source and drain metals are then thickened to form contact electrodes, ultimately forming a planar gallium oxide enhancement-mode device. This invention addresses the technical difficulty of effectively forming P-type doping in gallium oxide semiconductors through ion implantation to form P-well MOSFETs.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and in particular relates to a gallium oxide enhancement mode device and a manufacturing method thereof. Background Art

[0002] In power switch applications, Baliga's figure-of-merit (BFOM) is an indicator used to indicate the suitability of semiconductor materials for power electronics. It is expressed as: BFOM = εμE 3 , where ε is the dielectric constant, μ is the mobility, and E is the breakdown electric field strength of the semiconductor. The BFOM value is roughly positively correlated with the sixth power of the bandgap width Eg. Therefore, a larger bandgap width means that wide-bandgap semiconductors have lower power loss and higher conversion efficiency in power device applications, thus enabling more excellent and ideal power electronics applications. Among wide-bandgap semiconductor materials, Ga2O3 has a bandgap of 4.8eV, an ideal breakdown electric field strength of 8MV / cm, and a high BFOM value of 3400, which is approximately four times that of GaN and ten times that of SiC. Therefore, in today's power electronics applications with higher power density and lower power consumption requirements, Ga2O3 materials have greater research significance and broader market application prospects. In contrast to the ease of n-type doping, there are currently no reports of successful p-type doping in Ga2O3, which limits its application in bipolar power devices compared to materials that can undergo bipolar doping. Since gallium oxide lacks an effective P-type semiconductor, it cannot be made into a conventional MOSFET like SiC and GaN. It can only be made into a MISFET device or JFET device in which the drain, source and drift region are all N-type conductive.

[0003] For example, to achieve enhancement-mode devices and reduce the electric field at the metal-semiconductor interface, an enhancement-mode MISFET (EMISFET) device is fabricated by etching a gallium oxide epitaxial layer to form grooves on the surface. Insulating dielectrics such as SiO2 and Al2O3 are then deposited into the grooves to form the gate dielectric. Compared to planar MISFETs, EMISFETs exhibit a normally-off characteristic because the metal or polysilicon gate can completely deplete the conductive channel. Furthermore, the gate electrode has a certain depth, effectively shielding some of the electric field during reverse bias, reducing the surface electric field to a certain extent and minimizing leakage current. However, due to the characteristics of gallium oxide materials, achieving a deep gate dielectric deposition cannot be achieved through thermal oxidation. Instead, deep trenches must be formed in the gallium oxide material and then the gate dielectric deposited on the surface of the deep trenches. The deep trench depth results in uneven gate dielectric thickness, affecting the uniformity of the device threshold voltage. The gate trench lacks effective PN junction protection, resulting in a high electric field strength at the bottom of the trench, making avalanche breakdown more likely to occur and reducing device reliability. In addition, for trench-type gallium oxide devices to achieve enhanced functions, the spacing between the two trenches needs to be less than 0.35μm. Currently, electron beam lithography machines are often used to define this distance, but electron beam lithography machines are expensive and have slow lithography efficiency, and do not have the ability to be mass-produced. Therefore, this structure cannot meet the requirements of industrial application. Summary of the Invention

[0004] In view of the shortcomings of the existing technology, the purpose of the present invention is to provide a gallium oxide enhancement mode device and a manufacturing method thereof, so as to solve the problem that there is no effective P-type ion implantation to form P-Well in the gallium oxide device, which makes it impossible to effectively manufacture the gallium oxide MOSFET.

[0005] To achieve the above object, the present invention adopts the following technical solutions:

[0006] The present invention provides a method for preparing a gallium oxide enhancement mode device, comprising the following steps:

[0007] S1. Sequentially growing an N-type gallium oxide epitaxial layer and a P-type gallium oxide epitaxial layer on a gallium oxide substrate;

[0008] S2. Apply photoresist on the surface of the epitaxial layer, photolithographically form an injection window for the conductive layer, ion-implant Si elements to form the conductive layer, the bottom of the conductive layer contacts the N-type gallium oxide epitaxial layer, and after the implantation is completed, remove the photoresist;

[0009] S3. Apply photoresist to the surface of the epitaxial layer and pattern it to form a window for the source injection region. Ion implant Si element to form the source injection region. The depth of the source injection region is greater than the distance between the top of the conductive layer and the surface of the epitaxial layer. Part of the source injection region is above the conductive layer. After the implantation is completed, remove the photoresist.

[0010] S4. Apply photoresist to the surface of the epitaxial layer and pattern it. Form an injection window for the bias region above the source injection region. Ion implantation of N or Mg elements forms the bias region. After the implantation is complete, remove the photoresist. Then, activate and anneal in an argon atmosphere at 900-1200°C for 30-60 minutes.

[0011] S5. Al2O3 layer and polysilicon are sequentially deposited on the surface of the epitaxial layer, and then a photoresist is applied to the polysilicon surface and patterned, and the polysilicon and Al2O3 layers without photoresist protection areas are etched to form a gate. After etching is completed, the photoresist is removed;

[0012] S6. Depositing an ohmic contact metal on the surface of the epitaxial layer, evaporating an ohmic metal on the back of the substrate, and annealing in a nitrogen atmosphere at 450-600°C for 1-5 minutes to form a first ohmic contact layer and a second ohmic contact layer, respectively;

[0013] S7. depositing a passivation layer on the gate surface;

[0014] S8. Deposit metal on the upper and lower surfaces of the device, respectively, to form a source electrode on the upper surface and a drain electrode on the lower surface.

[0015] Furthermore, in step S1, the thickness of the N-type gallium oxide epitaxial layer is 5-10 μm, the doping element is silicon, and the doping concentration is 1×10 16 ~1×10 17 cm -3 The thickness of the P-type gallium oxide epitaxial layer is 0.5 to 1 μm, the doping elements are magnesium and nitrogen, and the doping concentration is 1×10 17 ~1×10 19 cm -3 .

[0016] Furthermore, in step S1, the growth method of the P-type gallium oxide epitaxial layer is to anneal the N-type gallium oxide epitaxial layer in an oxygen atmosphere at 1000-1400° C. for 1-24 hours.

[0017] Furthermore, in step S2, the doping concentration of the conductive layer is 5×10 17 ~1×10 20 cm -3 .

[0018] Furthermore, in step S3, the doping concentration of the source injection region is 5×10 17 ~1×10 20 cm -3 .

[0019] Furthermore, in step S4, the doping concentration of the bias region is 5×10 17 ~1×10 20 cm-3 .

[0020] The present invention also provides a gallium oxide enhanced mode device prepared by the above preparation method.

[0021] Furthermore, the conductive layer or the source injection region is discontinuous in the longitudinal direction, and the projection shape of the conductive layer or the source injection region on the surface of the epitaxial layer is circular, hexagonal, rectangular or irregular.

[0022] Furthermore, the projection of the conductive layer on the surface of the epitaxial layer is nested in the projection of the source injection region on the surface of the epitaxial layer.

[0023] Furthermore, the bias regions are longitudinally discontinuously and periodically arranged, and the projection shape of the bias regions on the surface of the epitaxial layer is circular, hexagonal, rectangular or irregular.

[0024] Compared with the prior art, the present invention has the following beneficial effects:

[0025] The present invention solves the technical problem of gallium oxide semiconductors being unable to form effective P-type doping through ion implantation to form a P-well MOSFET. By using epitaxial growth and co-doping with magnesium and nitrogen, P-type epitaxy with a low activation rate can be achieved. The weak P-type structure provides support for the production of planar MOSFETs. The planar device structure of the present invention can be completed using conventional i-line and g-line lithography machines to complete the lithography process, eliminating the reliance on expensive and inefficient electron beam lithography machines. This not only improves lithography efficiency, making mass production of gallium oxide enhancement mode devices possible, but also allows the production of short-channel devices through advanced lithography processes, reducing channel resistance while maintaining reverse withstand voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 Schematic diagram of the structure of a gallium oxide enhancement mode device in some embodiments;

[0027] Figure 2 This is a schematic diagram of the process flow for manufacturing a gallium oxide enhancement mode device according to the present invention;

[0028] Figure 3 is another structural schematic diagram of a gallium oxide enhancement mode device in some embodiments;

[0029] Figure 4 Schematic diagram of the projection shape of the conductive layer and the source injection region on the surface of the epitaxial layer in some embodiments;

[0030] Figure 5 Schematic diagram of the projection relationship between the conductive layer and the source injection region on the surface of the epitaxial layer in some embodiments;

[0031] Figure 6Schematic diagram of the projection shape of the bias region on the surface of the epitaxial layer in some implementation methods. DETAILED DESCRIPTION

[0032] The present invention will be further described in detail below with reference to specific examples so that those skilled in the art can more clearly understand the present invention. The examples are only used to illustrate the present invention and are not intended to limit the scope of the present invention. In the examples of the present invention, unless otherwise specified, all raw material components are commercially available products well known to those skilled in the art; unless otherwise specified, the technical means used are conventional means well known to those skilled in the art.

[0033] An embodiment of the present invention provides a method for preparing a gallium oxide enhancement mode device, comprising the following steps:

[0034] S1. An N-type gallium oxide epitaxial layer 2 and a P-type gallium oxide epitaxial layer 3 are sequentially grown on a gallium oxide substrate 1;

[0035] S2. Apply photoresist on the surface of the epitaxial layer, photolithography to form an implantation window for the conductive layer 4, ion implantation of Si elements to form the conductive layer 4, the bottom of the conductive layer 4 is in contact with the N-type gallium oxide epitaxial layer 2, after the implantation is complete, remove the photoresist;

[0036] S3. Apply photoresist to the surface of the epitaxial layer and pattern it to form a window for the source injection region 5. Ion implantation of Si element forms the source injection region 5. The depth of the source injection region 5 is greater than the distance from the top of the conductive layer 4 to the surface of the epitaxial layer. Part of the source injection region 5 is above the conductive layer 4. After the implantation is completed, remove the photoresist.

[0037] S4. Apply photoresist to the surface of the epitaxial layer and pattern it. Form an injection window for the bias region 6 above the source injection region 5. Ion implantation of N or Mg elements forms the bias region 6. After the implantation is complete, remove the photoresist. Then, activate and anneal in an argon atmosphere at 900 to 1200°C for 30 to 60 minutes.

[0038] S5. Al2O3 layer 7 and polysilicon 8 are sequentially deposited on the surface of the epitaxial layer, and then a photoresist is applied to the surface of the polysilicon 8 and patterned, and the polysilicon 7 and Al2O3 layers 8 without a photoresist protection zone are etched to form a gate. After etching is completed, the photoresist is removed;

[0039] S6. Depositing an ohmic contact metal on the surface of the epitaxial layer, evaporating an ohmic metal on the back of the substrate 1, and annealing in a nitrogen atmosphere at 450 to 600 ° C for 1 to 5 minutes to form a first ohmic contact layer 9 and a second ohmic contact layer 10, respectively;

[0040] S7. Depositing a passivation layer 11 on the gate surface;

[0041] S8. Deposit metal on the upper and lower surfaces of the device respectively, forming a source electrode 12 on the upper surface and a drain electrode 13 on the lower surface.

[0042] In some embodiments, in step S1, the thickness of the N-type gallium oxide epitaxial layer 2 is 5 to 10 μm, the doping element is silicon, and the doping concentration is 1×10 16 ~1×10 17 cm -3 The thickness of the P-type gallium oxide epitaxial layer 3 is 0.5 to 1 μm, and the doping elements are magnesium and nitrogen, with a doping concentration of 1×10 17 ~1×10 19 cm -3 .

[0043] In some embodiments, in step S1, the P-type gallium oxide epitaxial layer 3 is grown by annealing the N-type gallium oxide epitaxial layer 2 in an oxygen atmosphere at 1000-1400°C for 1-24 hours. The N-type gallium oxide epitaxial layer 2 can be oxidized by O2 to form a quasi-P-type epitaxial layer. When a positive bias is applied to the device gate voltage, the quasi-P-type epitaxial layer can accumulate electrons, thereby turning on the device.

[0044] In some embodiments, in step S2, the doping concentration of the conductive layer 4 is 5×10 17 ~1×10 20 cm -3 .

[0045] In some embodiments, in step S3, the doping concentration of the source injection region 5 is 5×10 17 ~1×10 20 cm -3 .

[0046] In some embodiments, in step S4, the doping concentration of the bias region 6 is 5×10 17 ~1×10 20 cm -3 .

[0047] Some embodiments of the present invention provide a gallium oxide enhancement mode device structure such as Figure 1 The specific production process is as shown in Figure 2 As shown:

[0048] 1) On the gallium oxide substrate 1, HVPE epitaxial growth method is used to sequentially grow Si-doped gallium oxide with a thickness of 10 μm and a doping concentration of 2×10 16 cm -3 The N-type epitaxial layer 2 has a thickness of 1 μm, is doped with Mg and N elements, and has a doping concentration of 5×10 17 cm -3 P-type epitaxial layer 3;

[0049] 2) Apply photoresist on the surface of the P-type epitaxial layer 3, and form an injection window for the conductive layer 4 by photolithography. At room temperature, Si elements are injected into the surface of the P-type epitaxial layer 3 to form the current conductive layer 4. The doping concentration is 5×10 18 cm -3 The conductive layer 4 penetrates the P-type epitaxial layer 3 and the bottom penetrates the N-type gallium oxide epitaxial layer 2; after the injection is completed, the photoresist is removed;

[0050] 3) Apply photoresist on the surface of the P-type epitaxial layer 3 and pattern it to form windows for the source injection region 5. The distance between the two windows is the length of the trench. Implant Si elements into the surface of the P-type epitaxial layer 3 to form the source injection region 5. The doping concentration is 5×10 18 cm -3 The depth of the source injection region 5 is greater than the distance between the top of the conductive layer 4 and the surface of the epitaxial layer 3, and part of the source injection region 5 is above the conductive layer 4; after the injection is completed, the photoresist is removed;

[0051] 4) Apply photoresist on the surface of the P-type epitaxial layer 3 and pattern it, form an injection window for the bias region 6 above the source injection region 5, and ion implant N or Mg elements to form the bias region 6 with an implantation concentration of 1×10 19 cm -3 After the implantation, the photoresist was removed and then activated and annealed in an argon atmosphere at 1000°C for 30 minutes.

[0052] 5) A 30 nm thick Al2O3 layer 7 and a 1 μm thick phosphorus-doped polysilicon 8 are sequentially deposited on the surface of the P-type epitaxial layer 3. Then, a photoresist is applied to the surface of the polysilicon 8 and patterned. The polysilicon 8 and the Al2O3 layer 7 without the photoresist protection zone are etched away to form a gate. After the etching is completed, the photoresist is removed.

[0053] 6) Depositing an ohmic contact metal on the surface of the P-type epitaxial layer 3 by lift-off, evaporating an ohmic metal on the back side of the substrate 1, and annealing them in a nitrogen atmosphere at 470°C for 1 minute to form a first ohmic contact layer 9 and a second ohmic contact layer 10, respectively. The deposited metals are Ti / Au with thicknesses of 20 nm / 80 nm;

[0054] 7) Depositing silicon oxide or silicon nitride on the gate surface using PECVD or BPSG, and opening holes to form the passivation layer 11 of the device;

[0055] 8) Metal is deposited on the upper and lower surfaces of the device as electrode thickening metal, and the deposited metal is Au / Ti / Al with a thickness of 20nm / 20nm / 4000nm; the upper surface thickened metal and the first ohmic contact layer 9 form the device source 12, and the lower surface thickened metal and the second ohmic contact layer 10 form the device drain 13.

[0056] Other embodiments provide gallium oxide enhancement mode device structures such as Figure 3 As shown, there is no Al2O3 layer and polysilicon above the conductive layer 4.

[0057] In some embodiments, the conductive layer 4 or the source injection region 5 is discontinuous in the longitudinal direction, and the projection of the conductive layer 4 or the source injection region 5 on the surface of the epitaxial layer has various shapes, such as circular, hexagonal, rectangular or irregular shapes and combinations thereof. Figure 4 As shown, Figure 4 In (a), the projection shapes of the conductive layer 4 and the source injection region 5 are both circular; Figure 4 In (b), the projection shape of the conductive layer 4 is circular, and the projection shape of the source injection region 5 is hexagonal; Figure 4 In (c), the projection shape of the conductive layer 4 is rectangular, and the projection shape of the source injection region 5 is circular; Figure 4 In (d), the projection shape of the conductive layer 4 is a rectangle, and the source injection region 5 is a continuous strip.

[0058] The projections of the conducting layer 4 and the source injection region 5 on the surface of the epitaxial layer have various nested relationships, such as Figure 5 In some embodiments, the projection area of the source injection region 5 on the surface of the epitaxial layer is smaller than the projection area of the conductive layer 4, and the projection of the source injection region 5 is nested in the projection of the conductive layer 4, as shown in FIG. Figure 5 (a) Figure 5 In other embodiments, the projection area of the source injection region 5 on the surface of the epitaxial layer is larger than the projection area of the conductive layer 4, and the projection of the conductive layer 4 is nested in the projection of the source injection region 5, as shown in FIG. Figure 5 (c) Figure 5 (d) shown.

[0059] In some embodiments, the bias regions 6 are longitudinally discontinuous and periodically arranged, and the projection shape of the bias regions 6 on the surface of the epitaxial layer is circular, hexagonal, rectangular or irregular, or a combination thereof. Figure 6 As shown, Figure 6 In (a), the offset region 6 is continuous in the longitudinal direction; Figure 6 In (b), the bias region 6 is longitudinally discontinuous, and its projection on the epitaxial layer surface is rectangular and periodically arranged; Figure 6 In (c), the offset region 6 is longitudinally discontinuous, and its projection on the epitaxial layer surface is a hexagonal shape, which is arranged periodically; Figure 6 In (d), the bias region 6 is discontinuous in the longitudinal direction, and its projection shape on the surface of the epitaxial layer is a combination of a circle and a hexagon, which are arranged in a staggered periodic manner.

[0060] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for preparing a gallium oxide enhancement mode device, characterized in that: The following steps are involved: S1. Sequentially growing an N-type gallium oxide epitaxial layer and a P-type gallium oxide epitaxial layer on a gallium oxide substrate; S2. Apply photoresist on the surface of the epitaxial layer, photolithographically form an injection window for the conductive layer, ion-implant Si elements to form the conductive layer, the bottom of the conductive layer contacts the N-type gallium oxide epitaxial layer, and after the implantation is completed, remove the photoresist; S3. Apply photoresist to the surface of the epitaxial layer and pattern it to form a window for the source injection region. Ion-implant Si element to form the source injection region. The depth of the source injection region is greater than the distance from the top of the conductive layer to the surface of the epitaxial layer. Part of the source injection region is above the conductive layer. After the implantation is complete, the photoresist is removed; S4. Apply photoresist to the surface of the epitaxial layer and pattern it. Form an injection window for the bias region above the source injection region. Ion implantation of N or Mg elements forms the bias region. After the implantation is complete, remove the photoresist. Then, activate and anneal in an argon atmosphere at 900-1200°C for 30-60 minutes. S5. Al2O3 layer and polysilicon are sequentially deposited on the surface of the epitaxial layer, and then a photoresist is applied to the polysilicon surface and patterned, and the polysilicon and Al2O3 layers without photoresist protection areas are etched to form a gate. After etching is completed, the photoresist is removed; S6. Depositing an ohmic contact metal on the surface of the epitaxial layer, evaporating an ohmic metal on the back of the substrate, and annealing in a nitrogen atmosphere at 450-600°C for 1-5 minutes to form a first ohmic contact layer and a second ohmic contact layer, respectively; S7. depositing a passivation layer on the gate surface; S8. Deposit metal on the upper and lower surfaces of the device, respectively, to form a source electrode on the upper surface and a drain electrode on the lower surface.

2. The method for preparing a gallium oxide enhancement mode device according to claim 1, wherein: In step S1, the thickness of the N-type gallium oxide epitaxial layer is 5-10 μm, the doping element is silicon, and the doping concentration is 1×10 16 ~1×10 17 cm -3 ; The P-type gallium oxide epitaxial layer has a thickness of 0.5 to 1 μm, and is doped with magnesium and nitrogen at a doping concentration of 1×10 17 ~1×10 19 cm -3 .

3. The method for preparing a gallium oxide enhancement mode device according to claim 1, wherein: In step S1, the growth method of the P-type gallium oxide epitaxial layer is to anneal the N-type gallium oxide epitaxial layer in an oxygen atmosphere at 1000-1400° C. for 1-24 hours.

4. The method for preparing a gallium oxide enhancement mode device according to claim 1, wherein: In step S2, the doping concentration of the conductive layer is 5×10 17 ~1×10 20 cm -3 .

5. The method for preparing a gallium oxide enhancement mode device according to claim 1, wherein: In step S3, the doping concentration of the source injection region is 5×10 17 ~1×10 20 cm -3 .

6. The method for preparing a gallium oxide enhancement mode device according to claim 1, wherein: In step S4, the doping concentration of the bias region is 5×10 17 ~1×10 20 cm -3 .

7. A gallium oxide enhanced-mode device prepared by the preparation method according to any one of claims 1 to 6.

8. The gallium oxide enhancement-mode device according to claim 7, characterized in that: The conductive layer or the source injection region is discontinuous in the longitudinal direction, and the projection shape of the conductive layer or the source injection region on the surface of the epitaxial layer is circular, hexagonal, rectangular or irregular.

9. The gallium oxide enhancement mode device according to claim 7, characterized in that: The projection of the conductive layer on the surface of the epitaxial layer is nested in the projection of the source injection region on the surface of the epitaxial layer.

10. The gallium oxide enhancement-mode device according to claim 7, characterized in that: The bias regions are longitudinally discontinuously and periodically arranged, and the projection shape of the bias regions on the surface of the epitaxial layer is circular, hexagonal, rectangular or irregular.

Images