A shielded split-trench-gate 4h-sic mos device with adjustable potential in the shielded region

Abstract

The present application belongs to the technical field of power semiconductor, and particularly relates to a split trench gate 4H-SiC MOS device with adjustable shielding region potential. The present application adopts a trench MOS structure, connects the shielding region and the source electrode through a multi-stage trench perpendicular to the gate trench, so that the shielding region potential is adjustable, the shielding effect of the shielding layer on the gate oxide layer electric field is improved, the degradation of the device switching performance is avoided, a JFET region can be formed between the shielding regions, and the short circuit capability of the device is improved. Meanwhile, the device adopts a split trench gate structure, integrates a Schottky diode at the bottom of the gate trench to realize a reverse current continuation function, and further improves the switching performance of the device. A JFET modulation region is arranged to reduce the influence of the Schottky contact region on the on-resistance of the device, and meanwhile, the risk of channel punch-through is reduced. The split trench gate 4H-SiC MOS device with adjustable shielding region potential provided by the present application has better switching characteristics and reverse recovery performance, ensures that the device has low on-state loss, and improves the reliability of the device.

Description

Technical Field

[0001] This invention belongs to the field of power semiconductor technology, specifically relating to a split trench gate 4H-SiC MOS device with adjustable shielding region potential. Background Technology

[0002] As a typical representative of third-generation wide-bandgap semiconductor materials, SiC material has advantages such as high critical breakdown field strength, high carrier saturation drift velocity, and high thermal conductivity, giving it unique advantages in the fabrication of high-voltage and high-power semiconductor devices.

[0003] Compared to traditional planar MOS devices, SiC trench MOS devices have a more compact cell design and reduce the influence of the JFET region, thereby achieving higher power density and reducing the on-resistance of the device. However, trench MOS devices have the problem of excessive electric field in the gate oxide layer. Usually, a shielding layer can be used to shield the electric field at the bottom of the trench, but the floating shielding area will increase the switching loss of the device.

[0004] Meanwhile, the parasitic body diode in SiC MOS devices has a high forward voltage drop, resulting in high reverse recovery losses. Due to defects in SiC epitaxial materials, the long-term conduction of the body diode can also lead to bipolar degradation, degrading the device's performance. In engineering practice, using an externally connected Schottky diode in reverse parallel to provide a new freewheeling path would undoubtedly increase circuit complexity and introduce additional parasitic effects. Summary of the Invention

[0005] To improve the reliability of the gate oxide layer and enhance the dynamic characteristics of SiC MOS devices, this invention proposes a split-trench gate 4H-SiC MOS device with adjustable shielding region potential. This device employs a trench MOS structure, connecting the shielding region to the source through multiple trenches perpendicular to the gate trench. This allows for adjustable shielding region potential, improving the shielding effect of the shielding layer on the gate oxide electric field and preventing degradation of the device's switching performance. A JFET region can be formed within the shielded area, improving the device's short-circuit capability. Simultaneously, the device utilizes a split-trench gate structure, integrating a Schottky diode at the bottom of the gate trench to achieve reverse freewheeling, further improving the device's switching performance. A JFET modulation region is also included to reduce the impact of the Schottky contact region on the device's on-resistance and mitigate the risk of channel punch-through.

[0006] The technical solution of this invention is as follows:

[0007] A split trench gate 4H-SiC MOS device with adjustable shielding potential includes a drain 1, an N+ substrate 2, an N- epitaxial layer 3, a shielding region 4, a JFET modulation region 5, a Schottky contact region 6, a P-type base region 7, an N+ contact region 8, a P+ contact region 9, a gate dielectric layer 10, a gate 11, and a source 12. The drain 1 is located on the lower surface of the N+ substrate 2, and the N- epitaxial layer 3 is located on the upper surface of the N+ substrate 2. The gate dielectric layer 10 and the gate 11 form a trench gate. The JFET modulation region 5 and the P-type base region 7 are located in the N- epitaxial layer 3 on both sides of the trench gate, and the JFET modulation region 5 and the P-type base region 7 are isolated by the N- epitaxial layer 3. The upper part of the side of the JFET modulation region 5 contacts the lower part of the side of the gate dielectric layer 10. The Schottky contact region 6... Located at the bottom of the gate dielectric layer 10, the lower part of the side of the JFET modulation region 5 contacts the side of the Schottky contact region 6, and the junction depth of the lower surface of the JFET modulation region 5 is greater than that of the lower surface of the Schottky contact region 6; the N+ contact region 8 and the P+ contact region 9 are located side by side on the upper surface of the P-type base region 7, and the N+ contact region 8 is located on the side closer to the trench gate; the P+ contact region 9 penetrates the device along the longitudinal direction of the device, unlike the P+ contact region 9, the N+ contact region 8, the P-type base region 7, and the JFET modulation region 5 extend to the middle of the device along the longitudinal direction of the device, and the area of ​​the N+ contact region 8 between the longitudinal direction and the edge of the device is filled by the gate dielectric layer 10; the area of ​​the P-type base region 7 between the longitudinal direction and the edge of the device is connected to the N+ contact region 6. The area corresponding to the width of contact region 8 is still filled by the gate dielectric layer 10, and the remaining area is the N-epipolar layer 3; the area of ​​JFET modulation region 5 in the longitudinal direction and at the edge of the device is also filled with the gate dielectric layer 10. The height of this filled portion is the same as the part where the side of JFET modulation region 5 contacts the side of the gate dielectric layer 10, and the width of this filled portion is less than the width of N+ contact region 8; the shielding region 4 is located at the bottom of Schottky contact region 6, and does not completely cover the bottom of Schottky contact region 6 in the transverse direction of the device. In the transverse direction of the device, one side of the bottom of shielding region 4 extends into JFET modulation region 5. In the longitudinal direction of the device, shielding region 4 penetrates the device, and shielding region 4 extends along the JFET modulation region 5 and P-type base region 7. In the N-epipolar layer 3 between the longitudinal direction of the device and the edge of the device, it extends along the side of the gate dielectric layer 10 to contact the bottom of the P+ contact region 9. The portion of the shielding region 4 extending along the gate dielectric layer 10 contacts the JFET modulation region 5 and the P-type base region 7. The source 12 is located on the device surface and is connected to the N+ contact region 8 and the P+ contact region 9, respectively. The Schottky contact region 6 also penetrates the gate dielectric layer 10 in the vertical direction to connect with the source 12. The portion of the Schottky contact region 6 penetrating the gate dielectric layer 10 has the same width as the gate 11 in the transverse direction of the device and is located in the middle of the gate dielectric layer 10 between the two P+ contact regions 9 in the transverse direction. The centerline of the portion penetrating in the longitudinal direction of the device coincides with the centerline of the gate 11.

[0008] The longitudinal direction of the device described in the above scheme is a third-dimensional direction that is perpendicular to both the transverse and vertical directions of the device. The transverse direction of the device is usually defined as the direction from the source to the drain, which corresponds to the x-axis in the direct three-dimensional coordinate system. The vertical direction of the device is the direction from bottom to top, which corresponds to the y-axis. Therefore, the longitudinal direction of the device corresponds to the z-axis.

[0009] The beneficial effects of this invention are as follows:

[0010] The grounded shielding region and split gate configuration result in low gate-drain capacitance, improving dynamic characteristics and reducing switching losses. When the device is in the blocking state, the shielding region protects the channel and gate oxide layer, preventing premature breakdown and effectively reducing the electric field strength of the gate oxide layer, thus providing excellent blocking characteristics and gate oxide layer reliability. When the device is in the conducting state, the JFET modulation region mitigates the resistance degradation caused by the shielding region and Schottky contact region, resulting in low conduction losses. The Schottky contact region provides a diode freewheeling path for reverse conduction, where the diode V... F The low and unipolar conductivity gives the device better reverse recovery characteristics and avoids the bipolar degradation problem. Attached Figure Description

[0011] Figure 1 This is a schematic diagram of a split trench gate 4H-SiC MOS device with adjustable shielding region potential, as an example. Detailed Implementation

[0012] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0013] Example

[0014] like Figure 1 As shown, the device in this example includes: 1. Drain, 2. N+ substrate, 3. N- epitaxial layer, 4. Shielding region, 5. JFET modulation region, 7. P-type base region, 9. P+ contact region, 8. N+ contact region, 6. Schottky contact region, 10. Gate dielectric layer, 11. Gate, 12. Source.

[0015] Drain 1, N+ substrate 2 and N- epitaxial layer 3 are stacked sequentially from bottom to top;

[0016] JFET modulation region 5 is located in the middle layer of N-epitaxial layer 3, and is separated from P-type base region 7 by N-epitaxial layer 3;

[0017] P+ contact region 9 and N+ contact region 8 are located above P-type base region 7;

[0018] The JFET modulation region 5, P-type base region 7, P+ contact region 9, and N+ contact region 8 are distributed alternately on both sides of the gate.

[0019] The gate trench has multiple levels of trenches in the vertical direction, and these multiple levels of trenches are distributed discontinuously in the middle of the gate trench.

[0020] Schottky contact region 6 is located at the bottom of the gate trench and is connected to the source 12 via a multi-level trench. The two sides of the bottom are shielding regions 4.

[0021] The shielding area 4 is connected to the P+ contact area 9 via the outer side of the multi-level trench;

[0022] The gate 11 is disposed in the gate trench, and the space between it and the Schottky contact region 6 is filled with a gate dielectric layer 10;

[0023] The source electrode 12 is located on the upper surface, connecting the P+ contact region 9, the N+ contact region 8, and the Schottky contact region 6.

[0024] The working principle of this example is:

[0025] When the gate voltage exceeds the threshold voltage, inverted electrons appear in the channel, forming a current path between the source and drain, and the device is in the ON state. At this time, electrons flow from the source 1, through the P-type base region 7, the N-epitaxial layer 3, the JFET modulation region 5, the N-epitaxial layer 3, and the N+ substrate 2, finally reaching the drain 1. During this process, the JFET modulation region 5 expands the electron path, suppressing the resistance degradation caused by the Schottky contact region 6 and the shielding region 4, giving the device good conduction characteristics. Simultaneously, the periodically distributed shielding region 4 improves the device's short-circuit withstand capability. When the gate voltage is below the threshold voltage, the channel is turned off, and the drain is at a high potential, placing the device in a forward withstand voltage state, primarily supported by the shielding region 4. The combined effect of the shielding region 4 and the Schottky contact region 6 significantly reduces the electric field in the gate dielectric 10. The N-epitaxial layer 3 separates the JFET modulation region 5 from the P-type base region 7, reducing the risk of punch-through in the P-type base region 7.

[0026] In freewheeling mode, the Schottky diode formed between the Schottky contact region 6, the JFET modulation region 5, and the N-epitaxial layer conducts, short-circuiting the body diode, reducing the reverse recovery time, and preventing bipolar degradation. The shielding region 4 and the Schottky contact region 6 reduce the parasitic capacitance between the gate 11 and the drain 1, giving the device higher dv / dt capability and improving its switching speed. Simultaneously, the shielding region 4 is connected to the source 12 via the P+ contact region 9, making the shielding region 4 and the source at the same potential, thus avoiding the negative impact of a floating shielding region 4 on the device's switching characteristics.

[0027] In this embodiment, the drain 1 is formed on the back side of the N+ substrate 2 by metal sputtering; the JFET modulation region 5 and the shielding region 4 at the bottom of the trench can be implemented by secondary epitaxy; the shielding region 4, P-type base region 7, P+ contact region 9 and N+ contact region 8 outside the multi-level trench can all be formed by high-temperature ion implantation; the gate trench and multi-level trench are etched by photolithography and etching processes, the source 12 is formed by metal sputtering, the gate dielectric layer 10 can be formed in the trench by deposition process, and the gate 9 is formed in the gate oxide layer 8 by polysilicon deposition.

Claims

1. A split trench gate 4H-SiC MOS device with adjustable shielding region potential, comprising a drain (1), an N-type gate (2), and an N-type gate (3), wherein the N-type gate is a 4H-SiC MOS device with adjustable shielding region potential. + Substrate (2), N - Epitaxial layer (3), shielding region (4), JFET modulation region (5), Schottky contact region (6), P-type base region (7), N + Contact area (8), P + Contact region (9), gate dielectric layer (10), gate (11) and source (12); the drain (1) is located in N + The lower surface of substrate (2), N - Epitaxial layer (3) is located in N + The upper surface of the substrate (2); the gate dielectric layer (10) and the gate (11) constitute a trench gate; characterized in that, The JFET modulation region (5) and P-type base region (7) are located on both sides of the trench gate in the N - epitaxial layer (3), and the JFET modulation region (5) and P-type base region (7) are separated by the N - epitaxial layer (3), the upper part of the side of the JFET modulation region (5) is in contact with the lower part of the side of the gate dielectric layer (10); the Schottky contact region (6) is located at the bottom of the gate dielectric layer (10), the lower part of the side of the JFET modulation region (5) is in contact with the side of the Schottky contact region (6), and the junction depth of the lower surface of the JFET modulation region (5) is greater than that of the Schottky contact region (6); the N + contact region (8) and P + contact region (9) are located on the upper surface of the P-type base region (7) in parallel, and the N + contact region (8) is located on one side close to the trench gate; the P + contact region (9) penetrates the device along the longitudinal direction of the device, and is in contact with the P + contact region (9) is different from the N + contact region (8), P-type base region (7) and JFET modulation region (5) extend to the middle of the device along the longitudinal direction of the device, and the N + contact region (8) is filled with the gate dielectric layer (10) in the area between the longitudinal direction of the device and the edge of the device; the area between the longitudinal direction of the P-type base region (7) and the edge of the device is filled with the N + contact region (8) corresponding to the width of the area is still filled with the gate dielectric layer (10), and the remaining area is the N - epitaxial layer (3); the area between the longitudinal direction of the JFET modulation region (5) and the edge of the device is also filled with the gate dielectric layer (10), the height of the filled part is the same as the part where the side of the JFET modulation region (5) is in contact with the side of the gate dielectric layer (10), and the width of the filled part is less than the N + width of the contact region (8); the shielding region (4) is located at the bottom of the Schottky contact region (6), and does not completely cover the bottom of the Schottky contact region (6) along the transverse direction of the device, part of the bottom of the shielding region (4) extends into the JFET modulation region (5) in the transverse direction of the device, and the shielding region (4) penetrates the device in the longitudinal direction of the device, and the N - epitaxial layer (3) along the side of the gate dielectric layer (10) extends to the bottom of the P + contact region (9), the part of the shielding region (4) extending along the gate dielectric layer (10) is in contact with the JFET modulation region (5) and the P-type base region (7); the source (12) is located on the surface of the device and is in contact with the N + contact region (8) and P + The contact area (9) is connected; the Schottky contact area (6) also penetrates the gate dielectric layer (10) in the vertical direction of the device to connect with the source (12). The portion of the Schottky contact area (6) penetrating the gate dielectric layer (10) has the same width in the transverse direction of the device as the gate (11), and the P on both sides in the transverse direction of the device is connected. + The middle part of the gate dielectric layer (10) between the contact areas (9) and the center line of the part that penetrates in the longitudinal direction of the device coincides with the center line of the gate (11); the transverse direction of the device is the direction from the source to the drain, the vertical direction of the device is the direction from bottom to top, and the longitudinal direction of the device is the direction that is perpendicular to both the transverse and vertical directions of the device.

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