Method and system for correcting delay error of RF-PWM signal

Abstract

The present invention discloses a method and system for correcting delay errors of RF-PWM signals, and relates to the technical field of signal delay error correction. The method is applied to an all-digital transmitter, comprising: based on the maximum value of the delay control word signal and with the minimum error vector amplitude as the goal, a coarse delay offset set is traversed using a cyclic sequential method to determine the optimal coarse delay offset set of the all-digital transmitter; based on the optimal coarse delay offset set and with the minimum third harmonic value as the goal, a fine delay offset set is traversed using a cyclic sequential method to determine the optimal fine delay offset set of the all-digital transmitter; and based on the optimal coarse delay offset set and the optimal fine delay offset set, a five-level RF-PWM signal is corrected. By constructing the optimal coarse delay offset set and the optimal fine delay offset set, the present invention can improve the correction accuracy of the RF-PWM signal.

Description

Technical Field

[0001] The present invention relates to the technical field of all-digital transmitters, and in particular to a method and system for correcting delay errors of RF-PWM signals. Background Art

[0002] In recent years, with the rapid growth in demand for communications services, the widespread use of complex modulation schemes, and the continuous increase in signal rates and bandwidths, the demand for multi-mode and multi-band hardware has continued to rise. Green communications, exemplified by low power consumption, have become a development trend and goal in wireless communications technology. For the transmitter, the need to process signals with larger bandwidths and higher peak-to-average power ratios (PAPRs), along with requirements for greater reconfigurability and compatibility, has placed tremendous pressure on the design of traditional transmitters. Meanwhile, the all-digital transmitter (ADTx), a revolutionary technology, differs from traditional transmitter systems in both its structure and mechanism. It offers technical advantages such as high efficiency, high linearity, and flexible reconfigurability and programmability, and is expected to play a key role in future wireless communications systems.

[0003] In recent years, ADTx technology has rapidly developed, with the emergence of various architectures, including orthogonal ADTx, polarization ADTx, and outphasing ADTx. Among them, the outphasing ADTx architecture, based on multi-level active harmonic cancellation radio frequency pulse width modulation (RF-PWM) combined with digital delay line (DDL) technology, offers significant advantages in coding efficiency, system complexity, and processing speed. RF-PWM is considered one of the most efficient pulse coding technologies currently suitable for ADTx applications. Its implementation is simple, with high coding efficiency (the coding efficiency is the ratio of the power of the RF signal to the pulse coding signal), and it can convert quantization noise into harmonic components, requiring only a low-pass filter for signal recovery. The resulting multi-level active harmonic cancellation RF-PWM algorithm eliminates specific subharmonics by designing pulse width and position, significantly reducing filter circuit design requirements and hardware costs.

[0004] The pulse signals generated by multi-level RF-PWM typically have more than four levels, with a five-level being the most basic active harmonic cancellation RF-PWM signal form. When implementing a five-level harmonic cancellation RF-PWM algorithm using a DDL-based DDRFM, four delay lines are used to independently delay the input carrier pulse signal, and then the desired five-level pulse modulation signal is synthesized through an amplifier circuit. However, in practical circuits, time asynchrony between the signals in each channel can occur. This is primarily due to the following reasons: First, sampling delay errors exist between the four delay control word signals output by the baseband signal after digital signal processing; second, manufacturing non-idealities of components such as delay lines and power amplifiers, as well as inconsistencies in the characteristics of different delay lines, can cause delay errors between the signals output by different delay lines. Since the performance of the RF-PWM algorithm is directly proportional to the signal's temporal resolution, even small delay errors can significantly degrade the overall DDRFM performance. Therefore, correction for these potential delay errors is necessary to ensure the quality of the DDL-based active harmonic cancellation RF-PWM signal and the performance of the DDRFM unit. Summary of the Invention

[0005] The purpose of the present invention is to provide a method and system for correcting the delay error of an RF-PWM signal, which can realize the adaptive correction processing function of the delay error with a small computational overhead without adding a dedicated compensation circuit, thereby improving the linear performance of the output signal.

[0006] To achieve the above object, the present invention provides the following solutions:

[0007] A method for correcting delay errors of RF-PWM signals, the method being applied to a fully digital transmitter, the fully digital transmitter comprising: a digital signal processing unit, a delay line unit, and a multi-level switching power amplifier unit connected in sequence;

[0008] The digital signal processing unit is used to process the baseband signal using an active harmonic elimination 5-level RF-PWM algorithm to obtain a first delayed control word signal, a second delayed control word signal, a third delayed control word signal, and a fourth delayed control word signal;

[0009] The delay line unit is configured to delay the first square wave signal using a first delay control word signal to obtain a first square wave delayed signal, delay the second square wave signal using a second delay control word signal to obtain a second square wave delayed signal, delay the third square wave signal using a third delay control word signal to obtain a third square wave delayed signal, and delay the fourth square wave signal using a fourth delay control word signal to obtain a fourth square wave delayed signal;

[0010] The multi-level switching power amplifier unit is configured to determine a five-level RF-PWM signal based on a first square wave delay signal, a second square wave delay signal, a third square wave delay signal, and a fourth square wave delay signal; the five-level RF-PWM signal is synthesized by combining the first three-level RF-PWM signal and the second three-level RF-PWM signal; the first three-level RF-PWM signal is synthesized by combining the first square wave delay signal and the second square wave delay signal; and the second three-level RF-PWM signal is synthesized by combining the third square wave delay signal and the fourth square wave delay signal;

[0011] The delay error correction method comprises:

[0012] According to the maximum value of the delay control word signal and with the goal of minimizing the error vector magnitude, a cyclic sequential method is used to traverse the coarse delay offset set to determine the optimal coarse delay offset set for the all-digital transmitter; the delay control word signal is the first delay control word signal, the second delay control word signal, the third delay control word signal, or the fourth delay control word signal;

[0013] According to the optimal coarse delay offset set, with the third harmonic value minimized, a cyclic sequential method is used to traverse the fine delay offset set to determine the optimal fine delay offset set of the all-digital transmitter;

[0014] The five-level RF-PWM signal is corrected according to the optimal coarse delay offset set and the optimal fine delay offset set.

[0015] Optionally, the bit width of the first delay control word signal, the bit width of the second delay control word signal, the bit width of the third delay control word signal, and the bit width of the fourth delay control word signal are all the same;

[0016] The accuracy of the first delay control word signal, the accuracy of the second delay control word signal, the accuracy of the third delay control word signal, and the accuracy of the fourth delay control word signal are all the same;

[0017] The frequency of the first square wave signal, the frequency of the second square wave signal, the frequency of the third square wave signal, and the frequency of the fourth square wave signal are all equal to the frequency of the carrier signal; the phase of the first square wave signal, the phase of the second square wave signal, the phase of the third square wave signal, and the phase of the fourth square wave signal are all equal to the phase of the carrier signal.

[0018] Optionally, determining an optimal coarse delay offset set for the all-digital transmitter based on a maximum value of the delay control word signal includes:

[0019] Let the total number of iterations D = 1;

[0020] Construct an empty set as the set of error vector magnitude values ​​at the Dth iteration;

[0021] Determine the maximum value of the delay control word signal as the coarse delay error threshold;

[0022] Determine any number smaller than half of the coarse delay error threshold as a coarse step;

[0023] Rounding the ratio of the coarse delay error threshold to the coarse step to obtain a first single-stage iteration number threshold;

[0024] Construct an array of iteration times (m, k, p, q) and a set of coarse step delay offsets {δ1, δ2, δ3, δ4}; where δ1 is the first coarse delay offset; δ2 is the second coarse delay offset; δ3 is the third coarse delay offset; and δ4 is the fourth coarse delay offset.

[0025] Determine {0,0,0,0} as the coarse step delay offset set at the (0,0,0,0)th iteration;

[0026] Superimposing the coarse step delay offset set at the (m, k, p, q)th iteration onto the delayed control word signal, and obtaining the error vector magnitude value of the corresponding 5-level RF-PWM signal as the error vector magnitude value at the (m, k, p, q)th iteration;

[0027] Add the error vector magnitude value and the coarse step delay offset set at the (m, k, p, q)th iteration as an element pair to the error vector magnitude value set at the Dth iteration;

[0028] Determine the sum of the first coarse delay offset at the (m, k, p, q)th iteration and the coarse step as the first coarse delay offset at the (m+1, k, p, q)th iteration;

[0029] Increasing the value of the first-order iteration number m by 1, and determining whether the first-order iteration number m is greater than the first single-order iteration number threshold, to obtain a first determination result;

[0030] If the first judgment result is no, then return to the step of "superimposing the coarse step delay offset set at the (m, k, p, q)th iteration onto the delayed control word signal, and obtaining the error vector magnitude value corresponding to the 5-level RF-PWM signal as the error vector magnitude value at the (m, k, p, q)th iteration";

[0031] If the first judgment result is yes, then increase the value of k by 1, and determine whether the second-order iteration number k is greater than the first single-order iteration number threshold, to obtain a second judgment result;

[0032] If the second judgment result is no, set the number of first-order iterations m=0, and return to the step of "superimposing the coarse step delay offset set at the (m, k, p, q)th iteration on the delayed control word signal to obtain the error vector magnitude value corresponding to the 5-level RF-PWM signal, which is the error vector magnitude value at the (m, k, p, q)th iteration";

[0033] If the second judgment result is yes, then the value of p is increased by 1, and it is determined whether the third-order iteration number p is greater than the first single-order iteration number threshold, to obtain a third judgment result;

[0034] If the third judgment result is no, then set the number of first-order iterations m=0, set the number of second-order iterations k=0, and return to the step of "superimposing the coarse step delay offset set at the (m, k, p, q)th iteration on the delayed control word signal to obtain the error vector magnitude value corresponding to the 5-level RF-PWM signal, which is the error vector magnitude value at the (m, k, p, q)th iteration";

[0035] If the third judgment result is yes, then the value of q is increased by 1, and it is determined whether the third-order iteration number q is greater than the first single-order iteration number threshold, to obtain a fourth judgment result;

[0036] If the fourth judgment result is no, then set the number of first-order iterations m=0, the number of second-order iterations k=0, and the number of third-order iterations p=0, and return to the step of "superimposing the coarse step delay offset set at the (m, k, p, q)th iteration on the delayed control word signal to obtain the error vector magnitude value corresponding to the 5-level RF-PWM signal, which is the error vector magnitude value at the (m, k, p, q)th iteration";

[0037] If the fourth judgment result is yes, the coarse step delay offset set in the element pair containing the minimum EVM value in the EVM value set at the Dth iteration is determined as the preferred coarse step delay offset set.

[0038] Optionally, after determining that the coarse step delay offset set in the element pair containing the minimum error vector magnitude value in the error vector magnitude value set at the D-th iteration is the preferred coarse step delay offset set at the D-th iteration, the method further includes:

[0039] Determine whether the total number of iterations D reaches a total number of iterations threshold, and obtain a fifth determination result;

[0040] If the result of the fifth judgment is no, the coarse step is updated, the value of the total number of iterations D is increased by 1, and the process returns to the step of "rounding the ratio of the coarse delay error threshold to the coarse step to obtain the first single-stage iteration number threshold";

[0041] If the fifth judgment result is yes, then determining the preferred coarse step delay offset set with the smallest corresponding error vector amplitude value in the preferred coarse step delay offset sets during multiple iterations as the optimal coarse step delay offset set.

[0042] Optionally, after determining the optimal coarse delay offset set of the all-digital transmitter according to the maximum value of the delay control word signal, the method further includes:

[0043] Correcting the first delay control word signal using a first coarse delay offset in the optimal coarse delay offset set to obtain a coarsely corrected first delay control word signal;

[0044] performing correction processing on the second delay control word signal using a second coarse delay offset in the optimal coarse delay offset set to obtain a coarsely corrected second delay control word signal;

[0045] performing correction processing on the third delay control word signal using a third coarse delay offset in the optimal coarse delay offset set to obtain a coarsely corrected third delay control word signal;

[0046] performing correction processing on the fourth delay control word signal using a fourth coarse delay offset in the optimal coarse delay offset set to obtain a coarsely corrected fourth delay control word signal;

[0047] The coarsely corrected first delay control word signal, the coarsely corrected second delay control word signal, the coarsely corrected third delay control word signal, and the coarsely corrected fourth delay control word signal are determined to be coarsely corrected delay control word signals.

[0048] Optionally, determining an optimal fine delay offset set for the all-digital transmitter based on the optimal coarse delay offset set includes:

[0049] Construct the empty set as the set of third harmonic values;

[0050] determining a fine step; the fine step being smaller than the coarse step;

[0051] Determine any number smaller than half of the coarse delay error threshold as a fine step;

[0052] Determining a second single-stage iteration number threshold according to the fine step;

[0053] Construct an array of iteration counts (b, c, v, t) and a set of fine step delay offsets {θ1, θ2, θ3, θ4}; where θ1 is the first fine delay offset; θ2 is the second fine delay offset; θ3 is the third fine delay offset; and θ4 is the fourth fine delay offset.

[0054] Determine {0,0,0,0} as the fine step delay offset set at the (0,0,0,0)th iteration;

[0055] Superimposing the fine step delay offset set at the (b, c, v, t)th iteration onto the coarse correction delay control word signal, and obtaining the third harmonic value of the corresponding 5-level RF-PWM signal as the third harmonic value at the (b, c, v, t)th iteration;

[0056] Adding the third harmonic value and the fine step delay offset set at the (b, c, v, t)th iteration as an element pair to the third harmonic value set;

[0057] Determine the sum of the first fine delay offset at the (b, c, v, t)th iteration and the fine step as the first fine delay offset at the (b+1, c, v, t)th iteration;

[0058] Increment the value of the first-order iteration number b by 1, and determine whether the first-order iteration number b is greater than the second single-order iteration number threshold, to obtain a sixth determination result;

[0059] If the result of the sixth judgment is no, then the process returns to the step of "superimposing the fine step delay offset set at the (b, c, v, t)th iteration onto the coarse correction delay control word signal to obtain the third harmonic value of the corresponding 5-level RF-PWM signal, which is the third harmonic value at the (b, c, v, t)th iteration."

[0060] If the sixth judgment result is yes, then the value of c is increased by 1, and it is determined whether the second-order iteration number c is greater than the second single-order iteration number threshold, to obtain a seventh judgment result;

[0061] If the result of the seventh judgment is no, then the number of first-order iterations b is set to 0, and the process returns to the step of "superimposing the fine step delay offset set at the (b, c, v, t)th iteration onto the coarse correction delay control word signal to obtain the third harmonic value of the corresponding 5-level RF-PWM signal as the third harmonic value at the (b, c, v, t)th iteration".

[0062] If the seventh judgment result is yes, then the value of v is increased by 1, and it is determined whether the third-order iteration number v is greater than the second single-order iteration number threshold, to obtain an eighth judgment result;

[0063] If the result of the eighth judgment is no, then the number of first-order iterations b is set to 0, the number of second-order iterations c is set to 0, and the process returns to step "superimposing the fine step delay offset set at the (b, c, v, t)th iteration onto the coarse correction delay control word signal to obtain the third harmonic value of the corresponding 5-level RF-PWM signal as the third harmonic value at the (b, c, v, t)th iteration".

[0064] If the eighth judgment result is yes, then the value of t is increased by 1, and it is determined whether the third-order iteration number t is greater than the second single-order iteration number threshold, to obtain a ninth judgment result;

[0065] If the ninth judgment result is no, then set the first-order iteration number b=0, the second-order iteration number c=0, and the third-order iteration number v=0, and return to the step of "superimposing the fine step delay offset set at the (b, c, v, t)th iteration onto the coarse correction delay control word signal to obtain the third harmonic value of the corresponding 5-level RF-PWM signal as the third harmonic value at the (b, c, v, t)th iteration";

[0066] If the ninth judgment result is yes, the fine step delay offset set in the element pair containing the minimum third harmonic value in the third harmonic value set at the Dth iteration is determined as the optimal fine step delay offset set.

[0067] Optionally, correcting the five-level RF-PWM signal according to the optimal coarse delay offset set and the optimal fine delay offset set includes:

[0068] Correcting the coarsely corrected first delay control word signal using a first fine delay offset in the optimal fine step delay offset set to obtain a finely corrected first delay control word signal;

[0069] Correcting the coarsely corrected second delay control word signal using a second fine delay offset in the optimal fine step delay offset set to obtain a finely corrected second delay control word signal;

[0070] Correcting the roughly corrected third delay control word signal using a third fine delay offset in the optimal fine step delay offset set to obtain a finely corrected third delay control word signal;

[0071] Correcting the coarsely corrected fourth delay control word signal using a fourth fine delay offset in the optimal fine step delay offset set to obtain a finely corrected fourth delay control word signal;

[0072] The corrected 5-level RF-PWM signal is determined according to the finely corrected first delayed control word signal, the finely corrected second delayed control word signal, the finely corrected third delayed control word signal, and the finely corrected fourth delayed control word signal.

[0073] A delay error correction system for an RF-PWM signal, comprising:

[0074] an optimal coarse delay offset set determination module, configured to determine an optimal coarse delay offset set for the all-digital transmitter by traversing the coarse delay offset set in a cyclic sequential manner based on the maximum value of the delay control word signal and with the goal of minimizing the error vector magnitude; the delay control word signal being the first delay control word signal, the second delay control word signal, the third delay control word signal, or the fourth delay control word signal;

[0075] An optimal fine delay offset set formulating module is configured to determine an optimal fine delay offset set for the all-digital transmitter by traversing the fine delay offset set based on the optimal coarse delay offset set and taking the third harmonic value as the minimum, using a cyclic sequential method;

[0076] A 5-level RF-PWM signal correction module is configured to correct the 5-level RF-PWM signal according to the optimal coarse delay offset set and the optimal fine delay offset set.

[0077] According to the specific embodiments provided by the present invention, the present invention discloses the following technical effects:

[0078] The present invention provides a method and system for correcting delay errors in RF-PWM signals, applicable to an all-digital transmitter. The method includes: determining an optimal coarse delay offset set for the all-digital transmitter based on the maximum value of a delay control word signal; the delay control word signal being a first delay control word signal, a second delay control word signal, a third delay control word signal, or a fourth delay control word signal; determining an optimal fine delay offset set for the all-digital transmitter based on the optimal coarse delay offset set; and correcting a five-level RF-PWM signal based on the optimal coarse delay offset set and the optimal fine delay offset set. By constructing the optimal coarse delay offset set and the optimal fine delay offset set, the present invention can improve the correction accuracy of the RF-PWM signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0079] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0080] Figure 1 This is a structural diagram of a fully digital transmitter in Example 1 of the present invention;

[0081] Figure 2 Flowchart of the delay error correction method of RF-PWM signal in embodiment 1 of the present invention. DETAILED DESCRIPTION

[0082] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0083] The object of the present invention is to provide a method, system and electronic equipment for correcting delay errors of RF-PWM signals, which can improve the correction accuracy of RF-PWM signals.

[0084] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0085] Example 1

[0086] This embodiment provides a method for correcting delay errors of RF-PWM signals, which is applied to a fully digital transmitter, such as Figure 1 The all-digital transmitter includes: a digital signal processing unit, a delay line unit (DDL) and a multi-level switching power amplifier unit connected in sequence; the delay line unit includes a first delay line sub-unit D1, a first delay line sub-unit D2, a first delay line sub-unit D3 and a first delay line sub-unit D4 connected in parallel.

[0087] The digital signal processing unit is used to process the baseband signals (I and Q) using the active harmonic elimination 5-level RF-PWM algorithm to obtain the first delayed control word signal b1, the second delayed control word signal b2, the third delayed control word signal b3, the fourth delayed control word signal b4 and the square wave signal f c The square wave signal includes a first square wave signal, a second square wave signal, a third square wave signal, and a fourth square wave signal. The bit width of the first delay control word signal, the bit width of the second delay control word signal, the bit width of the third delay control word signal, and the bit width of the fourth delay control word signal are all the same; the accuracy of the first delay control word signal, the accuracy of the second delay control word signal, the accuracy of the third delay control word signal, and the accuracy of the fourth delay control word signal are all the same; the frequency of the first square wave signal, the frequency of the second square wave signal, the frequency of the third square wave signal, and the frequency of the fourth square wave signal are all equal to the frequency of the carrier signal. The phase of the first square wave signal, the phase of the second square wave signal, the phase of the third square wave signal, and the phase of the fourth square wave signal are all equal to the phase of the carrier signal.

[0088] The delay line unit is used to use the first delay control word signal to delay the first square wave signal to obtain a first square wave delayed signal, use the second delay control word signal to delay the second square wave signal to obtain a second square wave delayed signal, use the third delay control word signal to delay the third square wave signal to obtain a third square wave delayed signal, and use the fourth delay control word signal to delay the fourth square wave signal to obtain a fourth square wave delayed signal.

[0089] The multi-level switching power amplifier unit is used to determine the 5-level RF-PWM signal (S 5-RFPWM ); the 5-level RF-PWM signal is obtained by synthesizing the first 3-level RF-PWM signal and the second 3-level RF-PWM signal; the first 3-level RF-PWM signal is obtained by synthesizing the first square wave delayed signal and the second square wave delayed signal; the second 3-level RF-PWM signal is obtained by synthesizing the third square wave delayed signal and the fourth square wave delayed signal. Specifically, the circuit for generating the 5-level RF-PWM signal consists of three parts: a digital signal processing unit, a digital delay line (DDL) unit, and a switching power amplifier unit; the digital signal processing device can be, but is not limited to, an FPGA, a DSP, or other devices; if the phase resolution of the digital delay line DDL is 2π / R, where R is a positive integer greater than 1, the value range of the delay control word is equal to [0, R-1], and the maximum value of the delay control word signal M=R-1.

[0090] like Figure 2 , the delay error correction method includes:

[0091] Step 101: Based on the maximum value of the delay control word signal and with the goal of minimizing the error vector magnitude, a cyclic sequential method is used to traverse the coarse delay offset set to determine the optimal coarse delay offset set for the all-digital transmitter; the delay control word signal is the first delay control word signal, the second delay control word signal, the third delay control word signal, or the fourth delay control word signal.

[0092] Step 102: Based on the optimal coarse delay offset set, with the third harmonic value minimized, a cyclic sequential method is used to traverse the fine delay offset set to determine the optimal fine delay offset set for the all-digital transmitter.

[0093] Step 103: Correct the five-level RF-PWM signal according to the optimal coarse delay offset set and the optimal fine delay offset set.

[0094] Step 101 includes:

[0095] Let the total number of iterations D=1.

[0096] An empty set is constructed as the set of error vector magnitude values ​​at the D-th iteration.

[0097] The maximum value of the delay control word signal is determined as a coarse delay error threshold.

[0098] Any number smaller than half of the coarse delay error threshold is determined as a coarse step.

[0099] The ratio of the coarse delay error threshold to the coarse step is rounded to obtain the first single-stage iteration number threshold.

[0100] Construct an array of iteration times (m, k, p, q) and a set of coarse step delay offsets {δ1, δ2, δ3, δ4}; where δ1 is the first coarse delay offset; δ2 is the second coarse delay offset; δ3 is the third coarse delay offset; and δ4 is the fourth coarse delay offset.

[0101] Determine {0,0,0,0} as the coarse step delay offset set at the (0,0,0,0)th iteration;

[0102] The coarse step delay offset set at the (m, k, p, q)th iteration is superimposed on the delayed control word signal to obtain the error vector magnitude value of the corresponding 5-level RF-PWM signal at the (m, k, p, q)th iteration.

[0103] The error vector magnitude value and the coarse step delay offset set at the (m, k, p, q)th iteration are added as an element pair to the error vector magnitude value set at the Dth iteration.

[0104] The sum of the first coarse delay offset and the coarse step at the (m, k, p, q)th iteration is determined as the first coarse delay offset at the (m+1, k, p, q)th iteration.

[0105] The value of the first-order iteration number m is increased by 1, and it is determined whether the first-order iteration number m is greater than the first single-order iteration number threshold value to obtain a first determination result.

[0106] If the first judgment result is no, then return to the step of "superimposing the coarse step delay offset set at the (m, k, p, q)th iteration on the delayed control word signal, and obtaining the error vector amplitude value of the corresponding 5-level RF-PWM signal as the error vector amplitude value at the (m, k, p, q)th iteration".

[0107] If the first judgment result is yes, the value of k is increased by 1, and it is determined whether the second-order iteration number k is greater than the first single-order iteration number threshold to obtain a second judgment result.

[0108] If the second judgment result is no, set the number of first-order iterations m = 0, and return to the step of "superimposing the coarse step delay offset set at the (m, k, p, q)th iteration on the delayed control word signal to obtain the error vector amplitude value corresponding to the 5-level RF-PWM signal, which is the error vector amplitude value at the (m, k, p, q)th iteration".

[0109] If the second judgment result is yes, the value of p is increased by 1, and it is determined whether the third-order iteration number p is greater than the first single-order iteration number threshold to obtain a third judgment result.

[0110] If the result of the third judgment is no, set the number of first-order iterations m = 0, set the number of second-order iterations k = 0, and return to the step of "superimposing the coarse step delay offset set at the (m, k, p, q)th iteration on the delayed control word signal to obtain the error vector amplitude value corresponding to the 5-level RF-PWM signal, which is the error vector amplitude value at the (m, k, p, q)th iteration".

[0111] If the third judgment result is yes, the value of q is increased by 1, and it is determined whether the third-order iteration number q is greater than the first single-order iteration number threshold to obtain a fourth judgment result.

[0112] If the result of the fourth judgment is no, then set the number of first-order iterations m = 0, the number of second-order iterations k = 0, the number of third-order iterations p = 0, and return to the step of "superimposing the coarse step delay offset set at the (m, k, p, q)th iteration on the delayed control word signal to obtain the error vector amplitude value corresponding to the 5-level RF-PWM signal, which is the error vector amplitude value at the (m, k, p, q)th iteration".

[0113] If the fourth judgment result is yes, the coarse step delay offset set in the element pair containing the minimum error vector magnitude value in the error vector magnitude value set at the Dth iteration is determined as the preferred coarse step delay offset set.

[0114] Specifically, after determining that the coarse step delay offset set in the element pair containing the minimum error vector magnitude value in the error vector magnitude value set at the D-th iteration is the preferred coarse step delay offset set at the D-th iteration, the method further includes:

[0115] It is determined whether the total number of iterations D reaches the total number of iterations threshold to obtain a fifth determination result.

[0116] If the fifth judgment result is no, the coarse step is updated, the value of the total number of iterations D is increased by 1, and the process returns to the step of "rounding the ratio of the coarse delay error threshold to the coarse step to obtain the first single-stage iteration number threshold".

[0117] If the fifth judgment result is yes, then the preferred coarse step delay offset set with the smallest corresponding error vector amplitude value in the preferred coarse step delay offset sets during multiple iterations is determined as the optimal coarse step delay offset set.

[0118] Specifically, after step 101, the method further includes:

[0119] Step 104: Correct the first delay control word signal using the first coarse delay offset in the optimal coarse delay offset set to obtain a coarsely corrected first delay control word signal.

[0120] Step 105: Correct the second delay control word signal using the second coarse delay offset in the optimal coarse delay offset set to obtain a coarsely corrected second delay control word signal.

[0121] Step 106: Correct the third delay control word signal using the third coarse delay offset in the optimal coarse delay offset set to obtain a coarsely corrected third delay control word signal.

[0122] Step 107: Correct the fourth delay control word signal using the fourth coarse delay offset in the optimal coarse delay offset set to obtain a coarsely corrected fourth delay control word signal.

[0123] Step 108 : Determine the roughly corrected first delay control word signal, the roughly corrected second delay control word signal, the roughly corrected third delay control word signal, and the roughly corrected fourth delay control word signal as roughly corrected delay control word signals.

[0124] Step 102 includes:

[0125] Construct the empty set as the set of third harmonic values.

[0126] Determine the fine step; the fine step is smaller than the coarse step.

[0127] Any number smaller than half of the coarse delay error threshold is determined as a fine step.

[0128] According to the fine step, the second single-stage iteration number threshold is determined.

[0129] Construct an array of iteration times (b, c, v, t) and a set of fine step delay offsets {θ1, θ2, θ3, θ4}; where θ1 is the first fine delay offset; θ2 is the second fine delay offset; θ3 is the third fine delay offset; and θ4 is the fourth fine delay offset.

[0130] Determine {0,0,0,0} as the fine step delay offset set at the (0,0,0,0)th iteration.

[0131] The fine step delay offset set at the (b, c, v, t)th iteration is superimposed on the coarse correction delay control word signal to obtain the third harmonic value of the corresponding 5-level RF-PWM signal at the (b, c, v, t)th iteration.

[0132] The third harmonic value and the fine step delay offset set at the (b, c, v, t)th iteration are added as an element pair to the third harmonic value set.

[0133] The sum of the first fine delay offset and the fine step at the (b, c, v, t)th iteration is determined to be the first fine delay offset at the (b+1, c, v, t)th iteration.

[0134] The value of the first-order iteration number b is increased by 1, and it is determined whether the first-order iteration number b is greater than the second single-order iteration number threshold value to obtain a sixth determination result.

[0135] If the result of the sixth judgment is no, then return to the step of "superimposing the fine step delay offset set at the (b, c, v, t)th iteration on the coarse correction delay control word signal to obtain the third harmonic value of the corresponding 5-level RF-PWM signal as the third harmonic value at the (b, c, v, t)th iteration".

[0136] If the sixth judgment result is yes, the value of c is increased by 1, and it is determined whether the second-order iteration number c is greater than the second single-order iteration number threshold to obtain the seventh judgment result.

[0137] If the result of the seventh judgment is no, set the number of first-order iterations b = 0, and return to the step of "superimposing the fine step delay offset set at the (b, c, v, t)th iteration on the coarse correction delay control word signal to obtain the third harmonic value of the corresponding 5-level RF-PWM signal as the third harmonic value at the (b, c, v, t)th iteration".

[0138] If the seventh judgment result is yes, the value of v is increased by 1, and it is determined whether the third-order iteration number v is greater than the second single-order iteration number threshold to obtain the eighth judgment result.

[0139] If the result of the eighth judgment is no, set the number of first-order iterations b = 0, set the number of second-order iterations c = 0, and return to the step of "superimposing the fine step delay offset set at the (b, c, v, t)th iteration on the coarse correction delay control word signal to obtain the third harmonic value of the corresponding 5-level RF-PWM signal as the third harmonic value at the (b, c, v, t)th iteration".

[0140] If the eighth judgment result is yes, the value of t is increased by 1, and it is determined whether the third-order iteration number t is greater than the second single-order iteration number threshold to obtain a ninth judgment result.

[0141] If the result of the ninth judgment is no, then set the number of first-order iterations b = 0, the number of second-order iterations c = 0, the number of third-order iterations v = 0, and return to the step of "superimposing the fine step delay offset set at the (b, c, v, t)th iteration on the coarse correction delay control word signal to obtain the third harmonic value of the corresponding 5-level RF-PWM signal as the third harmonic value at the (b, c, v, t)th iteration".

[0142] If the ninth judgment result is yes, the fine step delay offset set in the element pair containing the minimum third harmonic value in the third harmonic value set at the Dth iteration is determined as the optimal fine step delay offset set.

[0143] Step 103 includes:

[0144] The first delay control word signal after the coarse correction is corrected using the first fine delay offset in the optimal fine step delay offset set to obtain the first delay control word signal after the fine correction.

[0145] The second delay control word signal after the coarse correction is corrected using the second fine delay offset in the optimal fine step delay offset set to obtain the second delay control word signal after the fine correction.

[0146] The third delay control word signal after the coarse correction is corrected using the third fine delay offset in the optimal fine step delay offset set to obtain the third delay control word signal after the fine correction.

[0147] The fourth delay control word signal after the coarse correction is corrected using the fourth fine delay offset in the optimal fine step delay offset set to obtain the fourth delay control word signal after the fine correction.

[0148] The corrected 5-level RF-PWM signal is determined according to the finely corrected first delayed control word signal, the finely corrected second delayed control word signal, the finely corrected third delayed control word signal, and the finely corrected fourth delayed control word signal.

[0149] Example 2

[0150] Specifically, the delay error correction method for RF-PWM signals provided in this embodiment includes a large-step delay error fast estimation stage and a small-step delay error precise estimation stage; the large-step delay error fast estimation stage obtains a coarse delay error pre-estimate value; the small-step delay error precise estimation stage obtains a fine delay error pre-estimate value;

[0151] The steps of the large step delay error fast estimation stage include:

[0152] Determine the scanning interval of the rough delay error pre-estimate value: suppose the maximum value of the delayed control word signal is M, then the scanning interval is [0, M].

[0153] Determine the scanning step of the rough delay error estimate: let the scanning step be L, and the value range of L is [2,M / 2].

[0154] Let the number of times a single delayed control word signal is scanned be N. According to the scanning step, N=M / L times.

[0155] The first delay control word signal, the second delay control word signal, the third delay control word signal, and the fourth delay control word signal are determined to be delay control word signals to be adjusted.

[0156] The step delay offset set is {δ1,δ2,δ3,δ4}, and the initial values ​​are all 0.

[0157] Construct the empty set as the set of vector magnitude values.

[0158] After the time delay offset is superimposed on the delay control word signal to be adjusted, an error vector magnitude value corresponding to the 5-level RF-PWM signal is obtained as an error vector magnitude value and stored in a vector magnitude value set.

[0159] The value of δ1 is increased by L, and it is determined whether δ1 is less than M to obtain a first determination result.

[0160] If the first judgment result is yes, return to the step of "superimposing the delay offset on the delay control word signal to be adjusted, obtaining the error vector amplitude value corresponding to the 5-level RF-PWM signal as the error vector amplitude value, and storing it in the vector amplitude value set".

[0161] If the first judgment result is no, set the value of δ1 to 0, and determine whether δ2 is less than M to obtain the second judgment result.

[0162] If the second judgment result is yes, increase the value of δ2 by L, and return to the step of "superimposing the delay offset on the delay control word signal to be adjusted, obtaining the error vector amplitude value corresponding to the 5-level RF-PWM signal as the error vector amplitude value, and storing it in the vector amplitude value set."

[0163] If the second judgment result is no, set the value of δ2 to 0, and determine whether δ3 is less than M to obtain the third judgment result.

[0164] If the third judgment result is yes, the value of δ3 is increased by L, and the process returns to the step of "adding the delay offset to the delay control word signal to be adjusted, obtaining the error vector amplitude value corresponding to the 5-level RF-PWM signal as the error vector amplitude value, and storing it in the vector amplitude value set".

[0165] If the third judgment result is no, set the value of δ3 to 0, and determine whether δ4 is less than M to obtain the fourth judgment result.

[0166] If the fourth judgment result is yes, the value of δ4 is increased by L, and the process returns to the step of "adding the delay offset to the delay control word signal to be adjusted, obtaining the error vector amplitude value corresponding to the 5-level RF-PWM signal as the error vector amplitude value, and storing it in the vector amplitude value set".

[0167] If the fourth determination result is negative, the large-step fast estimation phase ends.

[0168] The sequence number of the minimum value in the search vector amplitude value set is searched. According to the search number N, the coarse delay mismatch error estimation value set {δ1c, δ2c, δ3c, δ4c} can be calculated.

[0169] Then, based on the coarse delay mismatch error estimate set {δ1c, δ2c, δ3c, δ4c}, a small-step precise estimation is started. Within the neighborhood of δic (i∈1,2,3,4), a sequential method is used to add the phase offset of the highest precision step to the control word data of each delay line. The magnitude of the third harmonic of the output 5-level RF-PWM signal under different offset conditions is measured or calculated. The delay corresponding to the minimum value in the third harmonic set is searched to obtain the corresponding delay mismatch error estimate value set I.

[0170] Specifically, the steps of the small-step fine delay error estimation stage include:

[0171] Determine the scanning interval of the fine delay error estimate: Assume that the width of the precise scanning interval is [-l,l], where l≤L.

[0172] Determine the scanning step of the fine delay error pre-estimate value: the scanning step corresponds to the highest accuracy of the frequency control word, that is, 1.

[0173] Let n be the number of times a single delayed control word signal is scanned in a small step. According to the scanning step, n=21+1 times.

[0174] The first delay control word signal, the second delay control word signal, the third delay control word signal, and the fourth delay control word signal are determined to be delay control word signals to be adjusted.

[0175] Let the first, second, third and fourth small step delay offset sets be {θ1,θ2,θ3,θ4}, and the initial values ​​be {δ1c-l,δ2c-l,δ3c-l,δ4c-l}.

[0176] Construct the empty set as the set of third harmonic values.

[0177] After the time delay offset is superimposed on the delay control word signal to be adjusted, the third harmonic value of the corresponding 5-level RF-PWM signal is obtained and stored in the third harmonic value set.

[0178] The value of θ1 is increased by 1, and it is determined whether θ1 is less than δ1c+1 to obtain a fifth determination result.

[0179] If the result of the fifth judgment is yes, return to the step of "adding the delay offset to the delay control word signal to be adjusted, obtaining the third harmonic value of the corresponding 5-level RF-PWM signal, and storing it in the third harmonic value set".

[0180] If the fifth judgment result is no, let the value of θ1 be δ1c-1, and judge whether θ2 is less than δ2c+1 to obtain the sixth judgment result.

[0181] If the result of the sixth judgment is yes, the value of θ2 is increased by 1, and the process returns to the step of "adding the delay offset to the delay control word signal to be adjusted, obtaining the third harmonic value of the corresponding 5-level RF-PWM signal, and storing it in the third harmonic value set".

[0182] If the sixth judgment result is no, let the value of θ2 be δ2c-1, and judge whether θ3 is less than δ3c+1 to obtain the seventh judgment result.

[0183] If the result of the seventh judgment is yes, the value of θ3 is increased by 1, and the process returns to the step of "adding the delay offset to the delay control word signal to be adjusted, obtaining the third harmonic value of the corresponding 5-level RF-PWM signal, and storing it in the third harmonic value set".

[0184] If the seventh judgment result is no, let the value of θ3 be δ3c-1, and judge whether θ4 is less than δ4c+1 to obtain the eighth judgment result.

[0185] If the result of the eighth judgment is yes, the value of θ4 is increased by 1, and the process returns to the step of "adding the delay offset to the delay control word signal to be adjusted, obtaining the third harmonic value of the corresponding 5-level RF-PWM signal, and storing it in the third harmonic value set".

[0186] If the result of the eighth judgment is no, the small-step fine delay error estimation phase ends.

[0187] By searching for the sequence number of the minimum value in the set of third harmonic values, a set of fine delay mismatch error estimation values ​​{θ1p, θ2p, θ3p, θ4p} can be calculated.

[0188] According to the set of fine delay mismatch error estimation values, the delay control word signal to be adjusted is adjusted to realize the correction processing of the delay mismatch error of the 5-level RF-PWM full digital transmitter.

[0189] Specifically, this embodiment may include more than one large-step delay error fast estimation stage, wherein the step values ​​of different large-step delay error fast estimation stages are different. In this embodiment, the processing of down-conversion, sampling decision, and calculation of error vector magnitude (EVM) and third harmonic of the output 5-level RF-PWM signal can be implemented by a dedicated receiving circuit or completed by a USRP or a test instrument.

[0190] The present invention uses a delay error scanning and positioning strategy that combines large-step rapid estimation with small-step precise estimation based on error vector amplitude and third harmonic as parameters. A cyclic sequential method is used to add a large phase offset to the delay line control word data of different channels to obtain a corresponding set of rough estimation values ​​of the delay mismatch error; based on the rough estimation results, the minimum step phase offset is added to the delay line control word data of different channels, and the delay mismatch error estimation value is obtained by comparing the third harmonic performance of the 5-level RF-PWM signal output under different offset conditions; finally, the delay mismatch error can be corrected by adding the offset of the corresponding delay mismatch error estimation value to the delay line control word data of each channel. The present invention can realize the adaptive correction processing function of the delay error with a small computational overhead without adding a compensation circuit, thereby improving the linear performance of the output signal.

[0191] Example 3

[0192] In order to execute the method corresponding to the above embodiment 1 to achieve the corresponding functions and technical effects, a system for correcting delay errors of RF-PWM signals is provided below, including:

[0193] An optimal coarse delay offset set determination module is configured to determine an optimal coarse delay offset set for a fully digital transmitter by traversing the coarse delay offset set in a cyclic sequential manner based on the maximum value of the delay control word signal and with the goal of minimizing the error vector magnitude; the delay control word signal being the first delay control word signal, the second delay control word signal, the third delay control word signal, or the fourth delay control word signal.

[0194] The optimal fine delay offset set formulation module is used to traverse the fine delay offset set based on the optimal coarse delay offset set, with the third harmonic value as the goal, using a cyclic sequential method to traverse the fine delay offset set and determine the optimal fine delay offset set of the all-digital transmitter.

[0195] A 5-level RF-PWM signal correction module is configured to correct the 5-level RF-PWM signal according to the optimal coarse delay offset set and the optimal fine delay offset set.

[0196] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Reference can be made to the common and similar parts between the various embodiments. For the systems disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the method description.

[0197] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The above examples are only intended to help understand the method and core concept of the present invention. At the same time, those skilled in the art will find that the specific implementation methods and application scopes may vary based on the concept of the present invention. In summary, the contents of this specification should not be construed as limiting the present invention.

Claims

1. A method for correcting delay errors of RF-PWM signals, characterized in that: The method is applied to an all-digital transmitter, which comprises: a digital signal processing unit, a delay line unit and a multi-level switching power amplifier unit connected in sequence; The digital signal processing unit is used to process the baseband signal using an active harmonic elimination 5-level RF-PWM algorithm to obtain a first delayed control word signal, a second delayed control word signal, a third delayed control word signal, and a fourth delayed control word signal; The delay line unit is configured to delay the first square wave signal using a first delay control word signal to obtain a first square wave delayed signal, delay the second square wave signal using a second delay control word signal to obtain a second square wave delayed signal, delay the third square wave signal using a third delay control word signal to obtain a third square wave delayed signal, and delay the fourth square wave signal using a fourth delay control word signal to obtain a fourth square wave delayed signal; The multi-level switching power amplifier unit is configured to determine a five-level RF-PWM signal based on a first square wave delay signal, a second square wave delay signal, a third square wave delay signal, and a fourth square wave delay signal; the five-level RF-PWM signal is synthesized by synthesizing the first three-level RF-PWM signal and the second three-level RF-PWM signal; the first three-level RF-PWM signal is synthesized by synthesizing the first square wave delay signal and the second square wave delay signal; and the second three-level RF-PWM signal is synthesized by synthesizing the third square wave delay signal and the fourth square wave delay signal; The delay error correction method comprises: According to the maximum value of the delay control word signal and with the goal of minimizing the error vector magnitude, a cyclic sequential method is used to traverse the coarse delay offset set to determine the optimal coarse delay offset set for the all-digital transmitter; the delay control word signal is the first delay control word signal, the second delay control word signal, the third delay control word signal, or the fourth delay control word signal; According to the optimal coarse delay offset set, with the third harmonic value minimized, a cyclic sequential method is used to traverse the fine delay offset set to determine the optimal fine delay offset set of the all-digital transmitter; The five-level RF-PWM signal is corrected according to the optimal coarse delay offset set and the optimal fine delay offset set.

2. The method for correcting delay error of an RF-PWM signal according to claim 1, wherein: The bit width of the first delay control word signal, the bit width of the second delay control word signal, the bit width of the third delay control word signal, and the bit width of the fourth delay control word signal are all the same; The accuracy of the first delay control word signal, the accuracy of the second delay control word signal, the accuracy of the third delay control word signal, and the accuracy of the fourth delay control word signal are all the same; The frequency of the first square wave signal, the frequency of the second square wave signal, the frequency of the third square wave signal, and the frequency of the fourth square wave signal are all equal to the frequency of the carrier signal; The phase of the first square wave signal, the phase of the second square wave signal, the phase of the third square wave signal, and the phase of the fourth square wave signal are all equal to the phase of the carrier signal.

3. The method for correcting delay error of RF-PWM signal according to claim 1, wherein: According to the maximum value of the delay control word signal and with the goal of minimizing the error vector magnitude, a cyclic sequential method is used to traverse the coarse delay offset set to determine the optimal coarse delay offset set of the all-digital transmitter, including: Let the total number of iterations D = 1; Construct an empty set as the set of error vector magnitude values ​​at the Dth iteration; Determine the maximum value of the delay control word signal as the coarse delay error threshold; Determine any number smaller than half of the coarse delay error threshold as a coarse step; Rounding the ratio of the coarse delay error threshold to the coarse step to obtain a first single-stage iteration number threshold; Construct an array of iteration times (m, k, p, q) and a set of coarse step delay offsets {δ1, δ2, δ3, δ4}; where δ1 is the first coarse delay offset; δ2 is the second coarse delay offset; δ3 is the third coarse delay offset; and δ4 is the fourth coarse delay offset. Determine {0,0,0,0} as the coarse step delay offset set at the (0,0,0,0)th iteration; Superimposing the coarse step delay offset set at the (m, k, p, q)th iteration onto the delayed control word signal, and obtaining an error vector magnitude value corresponding to the 5-level RF-PWM signal as the error vector magnitude value at the (m, k, p, q)th iteration; Add the error vector magnitude value and the coarse step delay offset set at the (m, k, p, q)th iteration as an element pair to the error vector magnitude value set at the Dth iteration; Determine the sum of the first coarse delay offset at the (m, k, p, q)th iteration and the coarse step as the first coarse delay offset at the (m+1, k, p, q)th iteration; Increasing the value of the first-order iteration number m by 1, and determining whether the first-order iteration number m is greater than the first single-order iteration number threshold, to obtain a first determination result; If the first judgment result is no, then return to the step of "superimposing the coarse step delay offset set at the (m, k, p, q)th iteration onto the delayed control word signal, and obtaining the error vector magnitude value corresponding to the 5-level RF-PWM signal as the error vector magnitude value at the (m, k, p, q)th iteration"; If the first judgment result is yes, then increase the value of k by 1, and determine whether the second-order iteration number k is greater than the first single-order iteration number threshold, to obtain a second judgment result; If the second judgment result is no, then set the number of first-order iterations m=0, and return to the step of "superimposing the coarse step delay offset set at the (m, k, p, q)th iteration onto the delayed control word signal, and obtaining the error vector magnitude value corresponding to the 5-level RF-PWM signal as the error vector magnitude value at the (m, k, p, q)th iteration"; If the second judgment result is yes, then the value of p is increased by 1, and it is determined whether the third-order iteration number p is greater than the first single-order iteration number threshold, to obtain a third judgment result; If the third judgment result is no, then set the number of first-order iterations m=0, set the number of second-order iterations k=0, and return to step "superimposing the coarse step delay offset set at the (m, k, p, q)th iteration onto the delayed control word signal to obtain the error vector magnitude value corresponding to the 5-level RF-PWM signal as the error vector magnitude value at the (m, k, p, q)th iteration"; If the third judgment result is yes, then the value of q is increased by 1, and it is determined whether the fourth-order iteration number q is greater than the first single-order iteration number threshold, to obtain a fourth judgment result; If the fourth judgment result is no, then set the number of first-order iterations m=0, the number of second-order iterations k=0, and the number of third-order iterations p=0, and return to the step of "superimposing the coarse step delay offset set at the (m, k, p, q)th iteration on the delayed control word signal to obtain the error vector magnitude value corresponding to the 5-level RF-PWM signal as the error vector magnitude value at the (m, k, p, q)th iteration"; If the fourth judgment result is yes, the coarse step delay offset set in the element pair containing the minimum EVM value in the EVM value set at the Dth iteration is determined as the preferred coarse step delay offset set.

4. The method for correcting delay error of an RF-PWM signal according to claim 3, wherein: After determining that the coarse step delay offset set in the element pair containing the minimum error vector magnitude value in the error vector magnitude value set at the D-th iteration is the preferred coarse step delay offset set at the D-th iteration, the method further includes: Determine whether the total number of iterations D reaches a total number of iterations threshold, and obtain a fifth determination result; If the result of the fifth judgment is no, the coarse step is updated, the value of the total number of iterations D is increased by 1, and the process returns to step "rounding the ratio of the coarse delay error threshold to the coarse step to obtain the first single-stage iteration number threshold"; If the fifth judgment result is yes, then determining the preferred coarse step delay offset set with the smallest corresponding error vector amplitude value in the preferred coarse step delay offset sets during multiple iterations as the optimal coarse step delay offset set.

5. The method for correcting delay error of RF-PWM signal according to claim 4, characterized in that: After determining the optimal coarse delay offset set of the all-digital transmitter according to the maximum value of the delay control word signal, the method further includes: Correcting the first delay control word signal using a first coarse delay offset in the optimal coarse delay offset set to obtain a coarsely corrected first delay control word signal; performing correction processing on the second delay control word signal using a second coarse delay offset in the optimal coarse delay offset set to obtain a coarsely corrected second delay control word signal; performing correction processing on the third delay control word signal using a third coarse delay offset in the optimal coarse delay offset set to obtain a coarsely corrected third delay control word signal; performing correction processing on the fourth delay control word signal using a fourth coarse delay offset in the optimal coarse delay offset set to obtain a coarsely corrected fourth delay control word signal; The coarsely corrected first delay control word signal, the coarsely corrected second delay control word signal, the coarsely corrected third delay control word signal, and the coarsely corrected fourth delay control word signal are determined to be coarsely corrected delay control word signals.

6. The method for correcting delay error of RF-PWM signal according to claim 5, characterized in that: According to the optimal coarse delay offset set, with the third harmonic value minimized as the goal, a cyclic sequential method is used to traverse the fine delay offset set to determine the optimal fine delay offset set of the all-digital transmitter, including: Construct the empty set as the set of third harmonic values; determining a fine step; the fine step being smaller than the coarse step; Determine any number smaller than half of the coarse delay error threshold as a fine step; Determining a second single-stage iteration number threshold according to the fine step; Construct an array of iteration counts (b, c, v, t) and a set of fine step delay offsets {θ1, θ2, θ3, θ4}; where θ1 is the first fine delay offset; θ2 is the second fine delay offset; θ3 is the third fine delay offset; and θ4 is the fourth fine delay offset. Determine {0,0,0,0} as the fine step delay offset set at the (0,0,0,0)th iteration; Superimposing the fine step delay offset set at the (b, c, v, t)th iteration onto the coarse correction delay control word signal, and obtaining the third harmonic value of the corresponding 5-level RF-PWM signal as the third harmonic value at the (b, c, v, t)th iteration; Adding the third harmonic value and the fine step delay offset set at the (b, c, v, t)th iteration as an element pair to the third harmonic value set; Determine the sum of the first fine delay offset at the (b, c, v, t)th iteration and the fine step as the first fine delay offset at the (b+1, c, v, t)th iteration; Increment the value of the first-order iteration number b by 1, and determine whether the first-order iteration number b is greater than the second single-order iteration number threshold, to obtain a sixth determination result; If the result of the sixth judgment is no, then return to the step of "superimposing the fine step delay offset set at the (b, c, v, t)th iteration onto the coarse correction delay control word signal to obtain the third harmonic value of the corresponding 5-level RF-PWM signal as the third harmonic value at the (b, c, v, t)th iteration"; If the sixth judgment result is yes, then the value of c is increased by 1, and it is determined whether the second-order iteration number c is greater than the second single-order iteration number threshold, to obtain a seventh judgment result; If the result of the seventh judgment is no, then the number of first-order iterations b is set to 0, and the process returns to step "superimposing the fine step delay offset set at the (b, c, v, t)th iteration onto the coarse correction delay control word signal to obtain the third harmonic value of the corresponding 5-level RF-PWM signal as the third harmonic value at the (b, c, v, t)th iteration"; If the seventh judgment result is yes, then the value of v is increased by 1, and it is determined whether the third-order iteration number v is greater than the second single-order iteration number threshold, to obtain an eighth judgment result; If the result of the eighth judgment is no, then the number of first-order iterations b is set to 0, the number of second-order iterations c is set to 0, and the process returns to step "superimposing the fine step delay offset set at the (b, c, v, t)th iteration onto the coarse correction delay control word signal to obtain the third harmonic value of the corresponding 5-level RF-PWM signal, which is the third harmonic value at the (b, c, v, t)th iteration"; If the eighth judgment result is yes, then the value of t is increased by 1, and it is determined whether the fourth-order iteration number t is greater than the second single-order iteration number threshold, to obtain a ninth judgment result; If the ninth judgment result is no, then the number of first-order iterations b is set to 0, the number of second-order iterations c is set to 0, and the number of third-order iterations v is set to 0, and the process returns to step "superimposing the fine step delay offset set at the (b, c, v, t)th iteration onto the coarse correction delay control word signal to obtain the third harmonic value of the corresponding 5-level RF-PWM signal as the third harmonic value at the (b, c, v, t)th iteration"; If the ninth judgment result is yes, the fine step delay offset set in the element pair containing the minimum third harmonic value in the third harmonic value set at the Dth iteration is determined as the optimal fine step delay offset set.

7. The method for correcting delay error of RF-PWM signal according to claim 6, characterized in that: Correcting the five-level RF-PWM signal according to the optimal coarse delay offset set and the optimal fine delay offset set includes: Correcting the coarsely corrected first delay control word signal using a first fine delay offset in the optimal fine step delay offset set to obtain a finely corrected first delay control word signal; Correcting the coarsely corrected second delay control word signal using a second fine delay offset in the optimal fine step delay offset set to obtain a finely corrected second delay control word signal; Correcting the roughly corrected third delay control word signal using a third fine delay offset in the optimal fine step delay offset set to obtain a finely corrected third delay control word signal; Correcting the coarsely corrected fourth delay control word signal using a fourth fine delay offset in the optimal fine step delay offset set to obtain a finely corrected fourth delay control word signal; The corrected 5-level RF-PWM signal is determined according to the finely corrected first delayed control word signal, the finely corrected second delayed control word signal, the finely corrected third delayed control word signal, and the finely corrected fourth delayed control word signal.

8. A delay error correction system for RF-PWM signals, characterized in that: The delay error correction system for RF-PWM signals applies the delay error correction method for RF-PWM signals according to any one of claims 1 to 7, and the delay error correction system for RF-PWM signals includes: an optimal coarse delay offset set determination module, configured to determine an optimal coarse delay offset set for the all-digital transmitter by traversing the coarse delay offset set in a cyclic sequential manner based on the maximum value of the delay control word signal and with the goal of minimizing the error vector magnitude; the delay control word signal being the first delay control word signal, the second delay control word signal, the third delay control word signal, or the fourth delay control word signal; An optimal fine delay offset set formulating module is configured to determine an optimal fine delay offset set for the all-digital transmitter by traversing the fine delay offset set based on the optimal coarse delay offset set and taking the third harmonic value as the minimum, using a cyclic sequential method; A 5-level RF-PWM signal correction module is configured to correct the 5-level RF-PWM signal according to the optimal coarse delay offset set and the optimal fine delay offset set.

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