Dynamic biasing circuit for doherty power amplifier

Abstract

A circuit includes a Doherty power amplifier circuit to amplify an input signal and generate an amplified signal of the input signal. The Doherty power amplifier circuit includes a first power amplifier circuit to operate in class C. The circuit further includes a biasing circuit electrically coupled to the first power amplifier circuit. The biasing circuit is to generate a bias based on the input signal and bias the first power amplifier circuit using the generated bias.

Description

Technical Field

[0001] This invention generally relates to power amplification, and in certain embodiments to dynamic biasing techniques and mechanisms for Doherty power amplifiers. Background Technology

[0002] Power amplifiers (PAs), used to convert low-power signals to high-power signals, are widely used in various fields such as wireless communication. For example, in wireless communication, PAs are used to generate high-power radio frequency (RF) signals to drive transmitting antennas at base stations or user equipment. PA design goals may include optimizing certain performance parameters such as gain, power output, bandwidth, power efficiency, and linearity.

[0003] In modern wireless communication systems and networks, such as 5G and higher, advanced modulation schemes are used for high spectral efficiency, in which case the RF signal may exhibit a large peak-to-average power ratio (PAPR). This results in significant variations in instantaneous output power. Conventional RF amplifiers, when used to amplify such RF signals, will exhibit rather low average efficiency at high PAPRs. It has been noted that Doherty amplifiers can adapt to high PAPRs, thereby improving amplification efficiency. Doherty amplifiers are increasingly used in wireless communication and other applicable fields. Summary of the Invention

[0004] The embodiments of dynamic biasing of the Doherty amplifier described in this invention generally achieve technical advantages.

[0005] According to one aspect of the present invention, a circuit is provided, comprising: a power amplifier circuit for amplifying a first input signal and generating an amplified signal of the first input signal, the power amplifier circuit including a first power amplifier circuit for operation in Class C; and a bias circuit electrically coupled to the first power amplifier circuit, the bias circuit being configured to generate a bias based on a control signal to bias the first power amplifier circuit, the control signal being based on the first input signal.

[0006] Alternatively, in any of the above aspects, the bias circuit is used to generate the bias based on the power of the first input signal.

[0007] Optionally, in any of the above aspects, the power amplifier circuit is a Doherty power amplifier.

[0008] Optionally, in any of the above aspects, the bias circuit is configured to receive the control signal as a function of the first input signal, and generate the bias based on the control signal.

[0009] Optionally, in any of the foregoing aspects, the bias circuit includes a first transistor, the first transistor comprising: an emitter electrically coupled to the first power amplifier circuit, the bias being output at the emitter; a collector electrically coupled to a first power supply; and a base electrically coupled to the control signal.

[0010] Optionally, in any of the foregoing aspects, the bias circuit further includes: a first capacitor electrically connected between the base of the first transistor and ground; a first resistor electrically connected between the base of the first transistor and a second power supply; a second transistor including an emitter electrically connected to the ground via the second resistor, a collector electrically connected to the base of the first transistor, and a base electrically connected to the ground via the second capacitor; and a first diode electrically connected between the base of the second transistor and the control signal.

[0011] Optionally, in any of the above aspects, the bias circuit further includes: a third resistor connected in series with a fourth resistor at a first terminal of the third resistor and located between the second power supply and the collector of the third transistor; the first diode being electrically connected between the base of the second transistor and the first terminal of the third resistor; and the third transistor including an emitter electrically coupled to the first input signal and an emitter electrically connected to the grounded base via a third capacitor.

[0012] Optionally, in any of the above aspects, the bias circuit further includes: a fifth resistor, a second diode, and a third diode connected in series, the fifth resistor having a first terminal connected to the second power supply and a second terminal connected to the anode of the second diode and the base of the third transistor; the third diode having a cathode connected to the ground.

[0013] Optionally, in any of the above aspects, the power amplifier circuit further includes a second power amplifier circuit for operation in Class AB, wherein the first power amplifier circuit is used to receive the first input signal and generate a first amplified signal of the first input signal, and the second power amplifier circuit is used to receive the first input signal and generate a second amplified signal of the first input signal.

[0014] Optionally, in any of the above aspects, the circuit further includes a combiner circuit for combining the first amplified signal of the first input signal and the second amplified signal of the first input signal to obtain the amplified signal of the first input signal.

[0015] According to another aspect of the present invention, a circuit is provided, comprising: a Doherty power amplifier circuit for amplifying a first input signal and generating an amplified signal of the first input signal, the Doherty power amplifier circuit including a first power amplifier circuit for operation in Class C; and a bias circuit electrically coupled to the first power amplifier circuit, the bias circuit being configured to generate a bias based on the first input signal to bias the first power amplifier circuit.

[0016] Alternatively, in any of the above aspects, the bias circuit is used to generate the bias based on the power of the first input signal.

[0017] Alternatively, in any of the above aspects, the bias is a current bias or a voltage bias.

[0018] Optionally, in any of the above aspects, the bias circuit is configured to receive a second signal as a function of the first input signal and generate the bias based on the second signal.

[0019] Optionally, in any of the foregoing aspects, the bias circuit includes a first transistor, the first transistor comprising: an emitter electrically coupled to the first power amplifier circuit, the bias being output at the emitter; a collector electrically coupled to a first power supply; and a base electrically coupled to the second signal.

[0020] Optionally, in any of the foregoing aspects, the bias circuit further includes: a first capacitor electrically connected between the base of the first transistor and ground; a first resistor electrically connected between the base of the first transistor and a second power supply; a second transistor including an emitter electrically connected to the ground via the second resistor, a collector electrically connected to the base of the first transistor, and a base electrically connected to the ground via the second capacitor; and a first diode electrically connected between the base of the second transistor and the second signal.

[0021] Optionally, in any of the above aspects, the bias circuit further includes: a third resistor connected in series with a fourth resistor at a first terminal of the third resistor and located between the second power supply and the collector of the third transistor; the first diode being electrically connected between the base of the second transistor and the first terminal of the third resistor; and the third transistor including an emitter electrically coupled to the first input signal and an emitter electrically connected to the grounded base via a third capacitor.

[0022] Optionally, in any of the above aspects, the bias circuit further includes: a fifth resistor, a second diode, and a third diode connected in series, the fifth resistor having a first terminal connected to the second power supply and a second terminal connected to the anode of the second diode and the base of the third transistor; the third diode having a cathode connected to the ground.

[0023] Optionally, in any of the above aspects, the Doherty power amplifier circuit further includes a second power amplifier circuit for operation in Class AB, wherein the first power amplifier circuit is used to receive the first input signal and generate a first amplified signal of the first input signal, and the second power amplifier circuit is used to receive the first input signal and generate a second amplified signal of the first input signal.

[0024] Optionally, in any of the above aspects, the circuit further includes a combiner circuit for combining the first amplified signal of the first input signal and the second amplified signal of the first input signal to obtain the amplified signal of the first input signal.

[0025] According to another aspect of the present invention, a method is provided, comprising: amplifying a first input signal by a power amplifier circuit, the power amplifier circuit including a first power amplifier circuit for operation in Class C; and biasing the first power amplifier circuit according to a control signal based on the first input signal.

[0026] Optionally, in any of the above aspects, the method further includes: generating a bias based on the control signal to bias the first power amplifier circuit.

[0027] Optionally, in any of the above aspects, the method further includes: obtaining an amplified signal of the first input signal.

[0028] Optionally, in any of the above aspects, the method further includes: generating the control signal based on the first input signal.

[0029] Alternatively, in any of the above aspects, a bias circuit electrically coupled to the first power amplifier circuit is used to bias the first power amplifier circuit.

[0030] The advantages mentioned above include enhanced efficiency over a wide dynamic range of output power, improved linearity, and a higher 1dB compression point for power amplifier circuits such as the Doherty power amplifier. Attached Figure Description

[0031] To gain a more complete understanding of the invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0032] Figure 1 A schematic diagram of a conventional Doherty amplifier is shown;

[0033] Figure 2 The method for biasing is shown. Figure 1 A schematic diagram of the bias circuit of the peak power amplifier (PA) of the Doherty amplifier in the image.

[0034] Figure 3 A schematic diagram of an embodiment of the Doherty amplifier is shown;

[0035] Figure 4 The method for biasing is shown. Figure 3 A schematic diagram of the bias circuit for an embodiment of the peak PA of the Doherty amplifier;

[0036] Figure 5 The graphs illustrate the gain and efficiency of the output power of conventional and Doherty amplifiers biased according to embodiments of the invention;

[0037] Figure 6 A block diagram of an embodiment of the electronic device is shown;

[0038] Figure 7 A flowchart of an embodiment method for amplifying a signal is shown.

[0039] Unless otherwise indicated, corresponding numbers and symbols in different figures generally refer to corresponding parts. The figures are drawn to clearly illustrate relevant aspects of the embodiments and are not necessarily drawn to scale. Detailed Implementation

[0040] The following section discusses in detail the making and use of embodiments of the present invention. However, it should be understood that the concepts disclosed herein can be embodied in various specific contexts, and the specific embodiments discussed herein are merely illustrative and not intended to limit the scope of the claims. Furthermore, it should be understood that various changes, substitutions, and modifications can be made to this document without departing from the spirit and scope of the invention as defined by the appended claims.

[0041] In conventional approaches, Doherty power amplifiers (PAs) use a fixed bias to bias the peak PA of a Doherty PA. Embodiments of the present invention provide a biasing scheme for dynamically biasing the peak PA of a Doherty PA. Specifically, the peak PA is biased using a bias typically generated based on the signal input to the Doherty PA. In one example, the signal at the Doherty PA input can be directly correlated with the transmitter modulation signal. The peak PA of the Doherty amplifier can also be biased based on the transmitter modulation signal. These embodiments can improve the efficiency of the Doherty PA, improve linearity, and extend the 1dB compression point of the Doherty PA over a wide dynamic range of output signal power.

[0042] The biasing scheme described in this embodiment can be applied to a Doherty PA and any other suitable power amplifier. In some embodiments, a circuit is provided that includes a Doherty PA circuit for amplifying an input signal and generating an amplified signal of the input signal. The Doherty PA circuit includes a first power amplifier circuit for operation in Class C. The circuit also includes a bias circuit electrically coupled to the first power amplifier circuit. The bias circuit is used to generate a bias based on the input signal and to bias the first power amplifier circuit using the generated bias. Embodiments will be provided in more detail below.

[0043] Figure 1 A conventional Doherty amplifier (or power amplifier) ​​100 is shown. In this invention, the terms "power amplifier," "PA," and "amplifier" are used interchangeably. The form, size, and circuitry of a Doherty power amplifier circuit may vary depending on the application. Figure 1As shown in the example, the Doherty amplifier 100 includes a drive PA 102, a bias circuit 104 for biasing the drive PA 102, a power divider 106 electrically coupled to the drive PA 102, a carrier PA (also called a main PA) 108, a bias circuit 110 for biasing the carrier PA 108, a peak PA (also called an auxiliary PA) 112, a bias circuit 114 for biasing the peak PA 112, and a power combiner 116. Each of the carrier PA 108 and the peak PA 112 is electrically coupled between the power divider 106 and the power combiner 116.

[0044] Driver PA 102 receives the input signal (denoted as Pin) amplified by Doherty amplifier 100, amplifies the signal Pin, and outputs the amplified signal to power divider 106. Bias circuit 104 generates a bias (which can be current or voltage) to bias driver PA 102, which can be biased to operate in Class AB. Driver PA 102 can be a current amplifier or a voltage amplifier.

[0045] Power divider 106 receives an amplified signal from driver PA 102 and directs the amplified signal to two different paths: a main path and an auxiliary path. On the main path, the output signal P1 of power divider 106 is directed to carrier PA 108. On the auxiliary path, the output signal P2 of power divider 106 is directed to peak PA 112.

[0046] Carrier PA 108 is biased by bias circuit 110 to operate in Class AB. Peak PA 112 is biased by bias circuit 114 to operate in Class C. Both carrier PA 108 and peak PA 112 may include transistors. Carrier PA 108 and / or peak PA 112 can be configured using any transistor technology. For example, they can use bipolar transistors, such as heterojunction bipolar transistors (HBTs), field-effect transistors (FETs), such as metal-oxide-semiconductor field-effect transistors (MOSFETs), etc.

[0047] Carrier PA 108 amplifies the input signal P1 and outputs signal S1. Peak PA 112 amplifies the input signal P2 and outputs signal S2. Power combiner 116 combines signals S1 and S2 and generates output signal Pout, which can be referred to as the amplified signal of the input signal Pin amplified by Doherty amplifier 100.

[0048] Typically, a conventional Doherty amplifier 100 is designed such that peak PA 112 is normally closed before carrier PA 108 begins compression. Therefore, before carrier PA 108 begins compression, Pout may only include S1, and S2 is not generated. When carrier PA 108 begins compression, peak PA 112 turns on. In this case, both carrier PA 108 and peak PA 112 are active, and S1 and S2 are combined, for example, added and output as Pout.

[0049] Figure 2 The method for biasing is shown. Figure 1 A schematic diagram of an exemplary bias circuit for the peak PA of the Doherty amplifier is shown. For ease of illustration, in Figure 2 The Doherty amplifier 100 is renumbered as Doherty amplifier 200, and its components are also renumbered. As shown in the figure, Doherty amplifier 200 includes a driver PA 202, a bias circuit 204 for biasing the driver PA 202, a power divider 206, a carrier PA 208, a bias circuit 210 for biasing the carrier PA 208, a peak PA 212, a bias circuit 214 for biasing the peak PA 212, and a power combiner 216. These components are similar to... Figure 1 The corresponding components are shown.

[0050] Specifically Figure 2 An example of bias circuit 214 is shown, which generates a constant bias for biasing peak amplifier 212. As shown, bias circuit 214 includes transistor Q1. The collector (also called the collector terminal) of transistor Q1 is electrically coupled to the power supply Vcc. The emitter (also called the emitter terminal) of transistor Q1 is electrically coupled to peak PA 212. Bias circuit 214 generates a bias at the emitter to bias peak PA 212. The base (also called the base terminal) of transistor Q1 is electrically coupled to ground through capacitor C1. The base of transistor Q1 is also electrically coupled to ground through resistor R1. The base of transistor Q1 is also electrically coupled to a regulated power supply, such as battery voltage Vbat, through resistors R2 and R3. Resistors R2 and R3 are connected in series. The junction of R2 and R3 is electrically coupled to the anode of diode D1. The cathode of diode D1 is connected to the anode of diode D2. The cathode of diode D2 is connected to ground. The bias circuit 214 is only an exemplary circuit for biasing the peak PA with a constant bias, but other suitable circuits may also be used.

[0051] Embodiments of the present invention provide a biasing scheme for dynamically biasing the peak PA of a Doherty amplifier. Specifically, the peak PA is biased using a bias generated based on the input signal of the Doherty amplifier. For example, the input signal at the Doherty PA may be correlated with a transmitter modulation signal. The peak PA of the Doherty amplifier may also be biased based on the transmitter modulation signal. Therefore, the peak PA can adaptively turn off as the input power level changes. The biasing scheme of these embodiments can be applied to Doherty amplifiers and any other suitable power amplifiers. The advantages of these embodiments include, for example, the ability to maintain a deep shutdown of the peak PA of the Doherty amplifier at low output power levels (by not supplying bias current to the peak PA and preventing premature self-biasing), and to maintain a slightly on peak PA at high output power levels by supplying a very small bias current to the Doherty amplifier. These embodiments enable the Doherty PA to improve efficiency, linearity, and extend compression by 1 dB over a wide dynamic range of output power.

[0052] Figure 3 A schematic diagram of an embodiment of a Doherty amplifier 300, in which the input signal is dynamically biased to a peak PA, is shown. As shown, the Doherty amplifier 300 includes a driver PA 302, a bias circuit 304 for biasing the driver PA 302, a power divider 306, a carrier PA 308 biased to operate in Class AB, a bias circuit 310 for biasing the carrier PA 308, a peak PA 312 biased to operate in Class C, and a power combiner 316. These components are similar to... Figure 1 The corresponding components are shown in the diagram. Typically, driver PA 302 receives and amplifies the input signal Pin, which will be amplified by Doherty amplifier 300, driving PA to generate signal P0. Power divider 306 receives signal P0 as input, directs output signal P1 to carrier PA 308 and output signal P2 to peak PA 312. Carrier PA 308 receives and amplifies P1 to generate signal S1. Peak PA 312 receives and amplifies P2 to generate signal S2. S1 and S2 are then combined by power combiner 316 to generate the output signal Pout of Doherty amplifier 300.

[0053] The carrier PA 308 and peak PA 312 can each be designed using the same or different techniques. Peak PA 312 is biased by bias circuit 314. Bias circuit 314 receives control signal 318 and generates a bias based on control signal 318 to bias peak PA 312. Control signal 318 can be configured such that peak PA 312 is normally off when carrier PA 308 is not compressed and turned on when carrier PA 308 begins compression. In some embodiments, control signal 318 can be based on input signal Pin or, for example, a signal from the transmitter (…). Figure 6 Other signals related to Pin are generated (as shown in the example below). Therefore, the bias generated by the bias circuit 314 based on the control signal can vary with the input signal Pin. In one example, the control signal 318 can be configured as a function of the input signal Pin, for example, denoted as Ctrl = f(Pin), where “Ctrl” represents the control signal, “f()” represents the function, and “Pin” is the input signal. For example, the control signal 318 can be a function of the power of the input signal Pin; therefore, the bias generated by the bias circuit 314 is based on the power of the input signal Pin. Thus, the peak PA 312 can be dynamically biased as the input signal power changes. This functionality can be configured based on various factors or considerations such as circuit design goals and / or constraints, hardware size, the application of the Doherty amplifier, and the power range of the output signal. This functionality can be in the form of hardware, software, firmware, or a combination thereof.

[0054] The bias circuit 314 can be implemented integratedly or as a separate circuit with the Doherty amplifier 300. The bias circuit 314 can generate a bias as either current or voltage. The control signal 318 can be generated based on the input signal Pin or another signal directly related to Pin via software, hardware, firmware, or a combination thereof. Those skilled in the art will recognize that the bias circuit 314 can have various forms and structures without departing from the principles of the invention.

[0055] Figure 4 To illustrate the use of bias Figure 3 The diagram shows a schematic of the bias circuit for an embodiment of the peak PA of the Doherty amplifier 300. For ease of illustration, in... Figure 4 The Doherty Amplifier 300 has been renumbered as the Doherty Amplifier 400. The Doherty Amplifier 400 is similar to... Figure 3 The Doherty amplifier 300 shown here will not be described further.

[0056] Specifically Figure 4A bias circuit 414 is shown as an example of the bias circuit 314 in Figure 300. The bias circuit 414 is used to provide a bias to the peak PA of the Doherty amplifier 400 based on the input signal Pin of the Doherty amplifier 400, as described above. Figure 3 The bias circuit 414 is provided by way of example only. Those skilled in the art will recognize that other variations, substitutions, and modifications of the bias circuit 414 may also be applied.

[0057] like Figure 4 As shown, bias circuit 414 includes transistor Q1. Transistor Q1 has a collector electrically coupled to power supply Vcc, an emitter electrically coupled to the peak PA of Doherty amplifier 400, and a base electrically coupled to ground via capacitor C1. The base of transistor Q1 is also electrically coupled to power supply Vbat via resistor R1. The base of transistor Q1 is also electrically coupled to the collector of transistor Q2. Transistor Q2 has an emitter electrically coupled to ground via resistor R2 and a base electrically coupled to ground via capacitor C2. The base of transistor Q2 is also electrically coupled to the cathode of diode D1, and the anode of diode D1 is electrically coupled to the connection node A of resistors R3 and R4. Resistors R3 and R4 are connected in series between power supply Vbat and the collector of transistor Q3. Transistor Q3 has a base electrically coupled to ground via capacitor C3 and an emitter electrically coupled to the drive PA of Doherty amplifier 400. The base of transistor Q3 is also electrically coupled to the anode of diode D2. Resistor R5, diode D2, and diode D3 are connected in series between the power supply Vbat and ground. The cathode of diode D3 is electrically connected to ground, and resistor R5 has a terminal electrically connected to Vbat. Transistors Q1, Q2, and Q3 can be implemented using the same transistor technology or different transistor technologies.

[0058] Transistor Q3, resistor R5, capacitor C3, and diodes D2 and D3 can form a bias circuit 404 to bias the driver PA of the Doherty amplifier 400. In one example, resistors R3 and R4 may also be part of the bias circuit 404. In another example, resistors R3 and R4 may not be needed to bias the driver PA. Bias can be provided to the driver PA at the emitter of transistor Q3. In this example, the driver PA may be biased to operate in class AB.

[0059] In this example, the signal at the anode of diode D1 can be considered as about Figure 3The control signal under discussion. The control signal can vary with the input signal Pin, and in this example, with the power of the input signal Pin. A bias is applied to the peak value PA at the emitter of transistor Q1 and can vary with the control signal, and thus with the power of the input signal to the Doherty amplifier 400.

[0060] As the Doherty amplifier 400 receives an input signal, when the input signal power of the Doherty amplifier 400 is low, the voltage at the anode of diode D1 is high enough to saturate transistor Q2, and transistor Q1 is turned off. In this case, no bias current flows to the peak PA, so the peak PA is off. As the input signal power increases, the current at the collector of transistor Q3 increases, which reduces the voltage applied to diode D1, and at some point, the voltage at the base of Q1 begins to increase. When the voltage at the base of Q1 reaches a first voltage level (based on the technology used to implement Q1), i.e., when the input signal power reaches a first power level, Q1 begins to receive a minimal current through R1 to its base. In this case, a minimal bias current flows through Q1, so the peak PA becomes slightly active. As used herein, "slightly active" means that the peak PA starts to operate and produces a smaller gain compared to the gain obtained when operating at a self-biased input power level (which is called fully active). When the input signal power increases beyond a first power level, the current flowing to the base of Q1 increases, thus increasing the bias current flowing through Q1 to the peak PA. This increased bias current causes the peak PA to generate an increased gain. When the input signal power reaches a second power level (higher than the first power level), the voltage applied to diode D1 decreases to a level that turns off Q2, and the voltage at the base of Q1 reaches a second voltage level (based on the technology used to implement Q1). In this case, Q1 begins to provide a constant bias current to the peak PA. For input power levels higher than the second power level, the bias current reaching the peak PA typically remains constant. Therefore, with the bias of the peak PA generated based on the input signal, the peak PA starts operating and generates a certain gain when the input signal power reaches the first power level. This differs from the conventional fixed bias scheme, in which the peak PA only starts operating when the input signal power reaches the self-bias level (i.e., the input signal power level is high enough to turn on the peak PA), and no bias current is applied to the peak PA. Therefore, this embodiment increases the gain of the peak PA at a certain input power level, thus increasing the gain of the Doherty PA.

[0061] Example circuits, such as bias circuits for peak PAs, may include field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), radio-frequency integrated circuits (RFICs), and combinations of various hardware and logic circuit systems for performing at least the functions described herein.

[0062] Figure 5 The graphs show the gain and efficiency of the Doherty amplifier with respect to the output power, with the peak PA biased in the conventional and according to embodiments of the present invention, respectively; the x-axis represents the output power of the Doherty amplifier (in dBm). The y-axis on the left represents the power gain of the Doherty amplifier (in dB), and the y-axis on the right represents the efficiency of the Doherty amplifier (in %).

[0063] Curve 502 shows the gain obtained by the Doherty amplifier, where the peak PA of the Doherty amplifier is determined according to the above description. Figure 3 and 4 The discussed embodiment uses biasing, i.e., dynamic biasing based on the power of the input signal amplified by the Doherty amplifier. Curve 504 shows the gain obtained by the Doherty amplifier, where the peak PA of the Doherty amplifier is conventionally biased, i.e., using constant bias. As can be seen, curve 502 shows a significant increase in gain with increasing output power compared to curve 504. Curve 506 shows the efficiency obtained by the Doherty amplifier, where the peak PA of the Doherty amplifier is biased according to the above description regarding... Figure 3 and 4 The discussed embodiments are used for biasing. Curve 508 shows the efficiency achieved by the Doherty amplifier, where the peak PA of the Doherty amplifier is conventionally biased. As can be seen, curve 506 shows an increase in efficiency compared to curve 508. From Figure 5 As can be seen, compared with the traditional constant bias scheme, the bias scheme of the embodiment improves the gain and efficiency of the Doherty amplifier.

[0064] Figure 6 A schematic diagram of an exemplary transmitter device 600 in which embodiments of the present invention can be applied is shown. Figure 6Only an exemplary transmitter device is shown. Those skilled in the art will recognize that transmitter device 600 can have various forms and structures, and other variations, substitutions, and modifications of transmitter device 600 may be applicable. Digital information 602, such as data to be transmitted by transmitter device 600, is received by digital baseband processing block 604, which processes the digital information 602 in the baseband and outputs a processed baseband signal. The processed baseband signal is received by modulation block 606, which modulates the processed baseband signal to a frequency suitable for transmission to generate a frequency-modulated signal. Modulation block 606 may also perform pre-amplification filtering on the frequency-modulated signal to generate a pre-amplified signal Pin. Signal Pin may be similar to... Figure 3-4 The Pin shown is then sent to the driver PA 608, and subsequently to the Doherty PA 610 for amplification. The driver PA 608 can be similar to... Figure 3 The driving PA 302 is shown in the diagram. The Doherty PA 610 may include a peak PA biased based on a pin or a frequency-modulated signal rather than a pin bias. The filter / antenna switch 612 may filter the output Pout of the Doherty PA 610 and direct the filtered signal to the antenna 614 for transmission.

[0065] Figure 7 A flowchart of an embodiment method 700 for amplifying a signal is shown. As shown, method 700 includes amplifying an input signal via a power amplifier circuit (block 702). The power amplifier circuit includes a first power amplifier circuit for operation in Class C. Method 700 also includes biasing the first power amplifier circuit according to a control signal based on the input signal (block 704). Method 700 may further include generating a bias based on the control signal to bias the first power amplifier circuit. Method 700 may further include generating a control signal based on a first input signal. The first power amplifier circuit can use, for example... Figure 4 The bias circuit 414 shown is used for biasing.

[0066] Despite the detailed description, it should be understood that various changes, substitutions, and modifications can be made to this document without departing from the spirit and scope of the invention as defined by the appended claims. Furthermore, the scope of the invention is not intended to be limited to the specific embodiments described herein, and those skilled in the art will readily appreciate from the invention that processes, machines, articles of manufacture, compositions of matter, components, methods, or steps (including those currently existing or to be developed hereafter) can perform substantially the same functions or achieve substantially the same effects as the corresponding embodiments described herein. Therefore, the appended claims are intended to encompass such processes, machines, articles of manufacture, compositions of matter, components, methods, or steps within their scope.

Claims

1. A power amplifier, characterized in that, include: A power amplifier circuit for amplifying a first input signal and generating an amplified signal of the first input signal, the power amplifier circuit including a first power amplifier circuit for operation in Class C; A bias circuit, electrically coupled to the first power amplifier circuit, the bias circuit being configured to generate a bias based on a control signal to bias the first power amplifier circuit, the control signal being based on the first input signal; The bias circuit includes a first transistor, a first capacitor, a first resistor, a second transistor, and a first diode, wherein the first transistor includes: The emitter is electrically coupled to the first power amplifier circuit, and the bias is output at the emitter. The collector is electrically coupled to the first power source; The base is electrically coupled to the control signal; The first capacitor is electrically connected between the base of the first transistor and ground; The first resistor is electrically connected between the base of the first transistor and the second power supply; The second transistor includes an emitter electrically connected to the ground via a second resistor, a collector electrically connected to the base of the first transistor, and a base electrically connected to the ground via a second capacitor; The first diode is electrically connected between the base of the second transistor and the control signal.

2. The power amplifier according to claim 1, characterized in that, The bias circuit is used to generate the bias based on the power of the first input signal.

3. The power amplifier according to claim 1 or 2, characterized in that, The power amplifier circuit is a Doherty power amplifier.

4. The power amplifier according to claim 1, characterized in that, The bias circuit is used to receive the control signal as a function of the first input signal, and to generate the bias based on the control signal.

5. The power amplifier according to claim 1, characterized in that, The bias circuit further includes: The third resistor is connected in series with the fourth resistor at the first terminal of the third resistor and is located between the second power supply and the collector of the third transistor. The first diode is connected between the base of the second transistor and the first terminal of the third resistor. The third transistor includes an emitter electrically coupled to the first input signal and a base electrically connected to the ground via a third capacitor.

6. The power amplifier according to claim 5, characterized in that, The bias circuit further includes: A fifth resistor, a second diode, and a third diode are connected in series. The fifth resistor has a first terminal connected to the second power supply and a second terminal connected to the anode of the second diode and the base of the third transistor. The third diode has a cathode connected to the ground.

7. The power amplifier according to claim 1, characterized in that, The power amplifier circuit further includes a second power amplifier circuit for operation in Class AB, wherein the first power amplifier circuit is used to receive the first input signal and generate a first amplified signal of the first input signal, and the second power amplifier circuit is used to receive the first input signal and generate a second amplified signal of the first input signal.

8. The power amplifier according to claim 7, characterized in that, It also includes a combiner circuit, which is used to combine the first amplified signal of the first input signal and the second amplified signal of the first input signal to obtain the amplified signal of the first input signal.

9. A power amplifier, characterized in that, include: Doherty power amplifier circuit for amplifying a first input signal and generating an amplified signal of the first input signal, the Doherty power amplifier circuit including a first power amplifier circuit for operation in Class C; A bias circuit, electrically coupled to the first power amplifier circuit, the bias circuit being used to generate a bias based on the first input signal to bias the first power amplifier circuit; The bias circuit includes a first transistor, a first capacitor, a first resistor, a second transistor, and a first diode, wherein the first transistor includes: The emitter is electrically coupled to the first power amplifier circuit, and the bias is output at the emitter. The collector is electrically coupled to the first power source; The base is electrically coupled to the second signal; The first capacitor is electrically connected between the base of the first transistor and ground; The first resistor is electrically connected between the base of the first transistor and the second power supply; The second transistor includes an emitter electrically connected to the ground via a second resistor, a collector electrically connected to the base of the first transistor, and a base electrically connected to the ground via a second capacitor; The first diode is electrically connected between the base of the second transistor and the second signal.

10. The power amplifier according to claim 9, characterized in that, The bias circuit is used to generate the bias based on the power of the first input signal.

11. The power amplifier according to claim 9 or 10, characterized in that, The bias is either a current bias or a voltage bias.

12. The power amplifier according to claim 9, characterized in that, The bias circuit is used to receive a second signal as a function of the first input signal, and to generate the bias based on the second signal.

13. The power amplifier according to claim 9, characterized in that, The bias circuit further includes: The third resistor is connected in series with the fourth resistor at the first terminal of the third resistor and is located between the second power supply and the collector of the third transistor. The first diode is connected between the base of the second transistor and the first terminal of the third resistor. The third transistor includes an emitter electrically coupled to the first input signal and a base electrically connected to the ground via a third capacitor.

14. The power amplifier according to claim 13, characterized in that, The bias circuit further includes: A fifth resistor, a second diode, and a third diode are connected in series. The fifth resistor has a first terminal connected to the second power supply and a second terminal connected to the anode of the second diode and the base of the third transistor. The third diode has a cathode connected to the ground.

15. The power amplifier according to claim 9, characterized in that, The Doherty power amplifier circuit further includes a second power amplifier circuit for operation in Class AB, wherein the first power amplifier circuit is used to receive the first input signal and generate a first amplified signal of the first input signal, and the second power amplifier circuit is used to receive the first input signal and generate a second amplified signal of the first input signal.

16. The power amplifier according to claim 15, characterized in that, It also includes a combiner circuit, which is used to combine the first amplified signal of the first input signal and the second amplified signal of the first input signal to obtain the amplified signal of the first input signal.

17. A power amplification method, characterized in that, include: The first input signal is amplified by a power amplifier circuit, the power amplifier circuit including a first power amplifier circuit for operation in Class C; The first power amplifier circuit is biased according to a control signal based on the first input signal; The first power amplifier circuit is biased using a bias circuit electrically coupled to the first power amplifier circuit. The bias circuit includes a first transistor, a first capacitor, a first resistor, a second transistor, and a first diode, wherein the first transistor includes: The emitter is electrically coupled to the first power amplifier circuit, and the bias is output at the emitter. The collector is electrically coupled to the first power source; The base is electrically coupled to the control signal; The first capacitor is electrically connected between the base of the first transistor and ground; The first resistor is electrically connected between the base of the first transistor and the second power supply; The second transistor includes an emitter electrically connected to the ground via a second resistor, a collector electrically connected to the base of the first transistor, and a base electrically connected to the ground via a second capacitor; The first diode is electrically connected between the base of the second transistor and the control signal.

18. The method according to claim 17, characterized in that, Also includes: A bias is generated based on the control signal to bias the first power amplifier circuit.

19. The method according to claim 17, characterized in that, Also includes: Obtain the amplified signal of the first input signal.

20. The method according to claim 17, characterized in that, Also includes: The control signal is generated based on the first input signal.

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