A sine wave amplitude detection circuit
By designing input and output stage transconductance amplifiers and clamping transistor loops, the problem of insufficient amplitude detection accuracy under low impedance conditions was solved, achieving high-speed and high-precision amplitude detection and improving the circuit's response speed and linearity.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHINA MICRO SEMICON (SHENZHEN) CO LTD
- Filing Date
- 2023-06-07
- Publication Date
- 2026-06-02
AI Technical Summary
In the prior art, the amplitude detection circuit has insufficient detection accuracy at low impedance and is not suitable for ordinary CMOS process, which limits the detection speed and accuracy.
The design employs an input and output stage transconductance amplifier and a clamping transistor loop. The first clamping circuit prevents the output stage circuit from turning off, the second clamping circuit improves the response speed, and the filter is combined to achieve high-precision amplitude detection.
It achieves high-precision amplitude detection under low impedance conditions, improves the response speed and measurement accuracy of the detection circuit, and enhances the linearity of the circuit by using a resistor series connection method.
Smart Images
Figure CN116718827B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of integrated circuit technology, and specifically relates to a sine wave amplitude detection circuit. Background Technology
[0002] Amplitude detection is a common analog module used to determine the magnitude of a detected signal. Amplitude detection can be achieved using traditional peak detection. Peak detection circuits utilize the unidirectional conduction characteristic of a diode (or equivalent transistor) to store the peak voltage in a capacitor while preventing reverse charge discharge. The recovery time required for a diode (or transistor) to turn on from off often limits the amplitude detection speed and the minimum detection voltage. Using a high-speed Schottky diode can achieve extremely fast recovery times, but Schottky diodes require BCD technology and are not suitable for ordinary CMOS processes.
[0003] This invention proposes a high-precision amplitude detection scheme that can be implemented using ordinary CMOS technology. This invention can meet the application requirements of high precision, such as for body impedance measurement in body fat scales. Body fat scales measure body fat by detecting the impedance of the human body; at low impedance, the corresponding detection amplitude decreases, requiring higher detection accuracy. The invented technology can significantly improve the detection accuracy at low impedance. Summary of the Invention
[0004] In order to overcome the shortcomings and deficiencies of the existing technology, the present invention provides a sine wave amplitude detection circuit.
[0005] The technical solution adopted in this invention is a sine wave amplitude detection circuit, which includes: an input stage transconductance amplifier Gm, an output stage transconductance amplifier g and its bias current Ib, transconductance amplifier G and its bias current k*Ib, a compensation capacitor C1, a first clamping transistor M1, a second clamping transistor M2 and its clamping bias voltage generator, the output peak voltage Vb of the output stage transconductance amplifier is fed back to the non-inverting input of the input stage, and the output peak voltage Vb is filtered to generate an output voltage Vout;
[0006] The input stage transconductance amplifier Gm, the output stage transconductance amplifier g, and the first clamping transistor M1 loop form the main loop. The output stage transconductance amplifier g and transconductance amplifier G only have the ability to output current and have no ability to receive current. The transconductance amplifier G and the first clamping transistor M1 loop constitute the first clamping circuit. The main loop and the first clamping circuit cooperate with each other to detect the peak value of the input peak voltage Vin and output the peak voltage Vb. The overall response speed of the circuit is improved through the first clamping circuit and the second clamping circuit.
[0007] Furthermore, the first clamping circuit is used to prevent the output stage transconductance amplifier g from being turned off when the input peak voltage Vin is less than the output peak voltage Vb, and at the same time to avoid the response time of the output stage transconductance amplifier g transitioning from the cutoff region to the saturation region.
[0008] Furthermore, the loop of the transconductance amplifier G and the first clamping transistor M1 is used to implement the clamping mechanism. When the input peak voltage Vin is less than the output peak voltage Vb, the input stage transconductance amplifier Gm outputs current, causing Va to tend to rise, which in turn reduces the output current of the output stage transconductance amplifier G and the first clamping transistor M1, and reduces the output peak voltage Vb. The rise in Va also reduces the current of the transconductance amplifier G, thereby reducing Vg, causing the first clamping transistor M1 to transition from the cutoff region to the saturation region, that is, to be turned on. After the first clamping transistor M1 is turned on, it absorbs the output current of the input stage transconductance amplifier Gm, thereby automatically stabilizing Va at a suitable voltage. When Va is clamped, the voltage of Vg is automatically stabilized at a suitable voltage, and at this time, the output current flowing through the transconductance amplifier G is equal to its bias current k*Ib.
[0009] Furthermore, through appropriate design, the transconductance of the output stage transconductance amplifier g with a bias current of Ib is made to satisfy the following expression as well as the transconductance of the transconductance amplifier G with a bias current of k*Ib. At this point, when Va reaches the clamping voltage required by power requirement 3, that is, when the output current flowing through the transconductance amplifier G is equal to its bias current k*Ib, the output current of the output stage transconductance amplifier g is also equal to its bias current Ib. Thus, the output current of the transconductance amplifier g will not continue to decrease as Vin decreases. Therefore, the output peak voltage Vb will not decrease as the input peak voltage Vin decreases, thus achieving the clamping function.
[0010] The transconductance of the transconductance amplifier must satisfy the following expression:
[0011]
[0012] Wherein, g and G represent the transconductance of transconductance amplifiers g and G, respectively; and k represents the proportionality coefficient, which is consistent with the coefficient described in claim 3.
[0013] Furthermore, the second clamping circuit is used to prevent the Vg voltage from being too high when the input peak voltage Vin is greater than the output peak voltage Vb; when the input peak voltage Vin returns to a level lower than the output peak voltage Vb, Vg is rapidly reduced and the first clamping transistor M1 is turned on, thereby improving the response speed of the first clamping circuit.
[0014] Furthermore, the clamping bias voltage generator and the second clamping transistor M2 are used to implement the second clamping circuit. When the input peak voltage Vin increases, Va decreases, causing Vg to rise and turning off the first clamping transistor M1, which then enters the cutoff region. When the input peak voltage Vin continues to increase, Va continues to decrease, and the output current of the transconductance amplifier G also continues to increase, causing Vg to tend to increase to VDD. When Vg continues to increase to the point where the second clamping transistor M2 is automatically turned on, the second clamping transistor M2 begins to receive the output current of the transconductance amplifier G, preventing Vg from increasing further rapidly. When the input peak voltage Vin is less than the output peak voltage Vb, an excessively long Vg recovery time is avoided, allowing the first clamping circuit to quickly generate the clamping function and preventing the output peak voltage Vb from continuing to decrease following the input peak voltage Vin.
[0015] Furthermore, the filter circuit is used to further process the peak output voltage Vb and output it to the next stage circuit. The filter is a capacitor used to store the peak output voltage Vb.
[0016] Furthermore, there are two clamping mechanisms: the first is used to prevent the output stage circuit from entering the shutdown state, and the second is used to clamp the first clamping circuit to ensure the response speed of the first clamping circuit.
[0017] Compared with the prior art, the present invention has the following beneficial effects:
[0018] This invention proposes a sinusoidal wave amplitude detection circuit. The high-precision amplitude detection scheme utilizes a first clamping circuit to prevent the output stage circuit from entering a shutdown state, and a second voltage clamping circuit to ensure the response speed of the first clamping circuit, achieving high-speed and high-precision amplitude detection. In a preferred embodiment, the linearity of the circuit is further improved by connecting a resistor in series between the peak voltage and the output voltage. Using this high-precision amplitude detection scheme, the measurement accuracy of amplitude detection can be significantly improved. Attached Figure Description
[0019] Figure 1 This is a circuit diagram of the high-precision amplitude detection scheme of the present invention;
[0020] Figure 2 This is a circuit diagram of a preferred high-precision amplitude detection scheme of the present invention. Detailed Implementation
[0021] It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other. The following describes the application in further detail with reference to the accompanying drawings and specific embodiments.
[0022] like Figure 1As shown, a sine wave amplitude detection circuit includes an input stage transconductance amplifier Gm, an output stage transconductance amplifier g and its bias current Ib, a transconductance amplifier G and its bias current k*Ib, a compensation capacitor C1, a first clamping transistor M1, a second clamping transistor M2 and its clamping bias voltage generator. The output Vb of the output stage transconductance amplifier is fed back to the non-inverting input of the input stage. After passing through a filter, Vb generates the output voltage Vout.
[0023] The Gm and g loops are the main loops of the invention; g and G only have the ability to output current, not receive current; the G and M1 loops constitute the first clamping circuit. These two loops work together to achieve peak detection of Vin and output the peak voltage Vb. This invention improves the overall response speed of the circuit through the first clamping circuit and the second clamping circuit.
[0024] The purpose of the first clamping circuit is to prevent g from being turned off when the input Vin is less than Vb, thus avoiding the response time of g transitioning from the cutoff region to the saturation region. The designed G and M1 loop implements this clamping mechanism. When the input Vin is less than Vb, Gm outputs current, causing Va to tend to rise, which in turn reduces the output current of g and Vb. The rise in Va also reduces the current of G, thereby reducing Vg, causing M1 to transition from the cutoff region to the saturation region, i.e., to be turned on. After M1 is turned on, it absorbs the output current of Gm, thus automatically stabilizing Va at a suitable voltage. It is easy to see that when Va is clamped, the voltage of Vg is also automatically stabilized at a suitable voltage, at which point the output current flowing through G is equal to its bias current k*Ib. Through appropriate design, g with bias current Ib satisfies the following expression 1, which ensures that at this voltage Va, the output current of g is also exactly equal to its bias current Ib, thus ensuring that Vb does not decrease with the decrease of Vin.
[0025] The transconductance of the transconductance amplifier must satisfy the following expression:
[0026]
[0027] Where gm1 and gm2 represent the transconductance of transconductance amplifiers g and G, respectively, and k represents the proportionality coefficient.
[0028] The purpose of the second clamping circuit is to prevent excessively high Vg voltage when the input Vin is greater than Vb. This allows Vg to decrease rapidly and turn on M1 when Vin returns to a value less than Vb, thus improving the response speed of the first clamping circuit. The designed clamping bias voltage generator and the second clamping transistor M2 implement the second clamping circuit. When the input Vin increases, Va decreases, causing Vg to rise and turning off M1, which then enters the cutoff region. As Vin continues to increase, Va continues to decrease, and the output current of G continues to increase, causing Vg to tend to increase to VDD. When Vg continues to increase to the point where clamping transistor M2 is automatically turned on, M2 will begin to receive the output current of G, thereby preventing Vg from increasing further rapidly. This avoids an excessively long Vg recovery time when Vin is less than Vb, allowing the first clamping circuit to quickly generate clamping function and prevent Vb from continuing to decrease along with Vin.
[0029] Filter circuits are used to further process the peak value Vb and output it to the next stage of the circuit. The simplest filter is a capacitor used to store Vb.
[0030] The two clamping mechanisms described above serve two purposes: first, they prevent the output stage circuit from entering a shutdown state; second, they clamp the first clamping circuit, thus ensuring its response speed. By employing these two methods, the invented detection circuit achieves high-speed and high-precision performance.
[0031] Preferred Solution: A technical solution that further optimizes the overall solution, explaining the reasons for the preference or the better results achieved.
[0032] Preferred solutions, such as Figure 2 As shown, transconductance amplifiers g and G are two PMOS transistors with a width-to-length ratio of 1:k. The filter consists of resistors R1, R2, and capacitor C1, and Vcm is equal to the DC component of the input signal. The clamping bias voltage generator consists of a bias current source, PMOS transistors M3 and M4.
[0033] Removing R1 and R2 results in the detected peak signal as the output signal. Adding R1 enhances the stability of the circuit when driving a large capacitor because it isolates the output node from capacitor C1, reducing the loop phase shift. R1 also improves the circuit's linearity: since the closed-loop output resistance of the main loop depends on its open-loop resistance and loop gain, this value varies with signal amplitude, temperature, and power supply voltage. Adding a stable R1 reduces the contribution of these variations, improving the linearity of the detection circuit. The larger R2 provides a slow discharge path, allowing occasional noise spikes to be released. However, in this case, the voltage Vout will be slightly lower than the peak voltage; the ratio between the two depends on the ratio of R1 and R2, which can be easily compensated for by system calibration.
[0034] The clamping bias voltage generator clamps Vg to approximately VDD-Vsg4 instead of VDD. Here, Vsg4 is the source-gate voltage of M4.
[0035] This invention proposes a sinusoidal wave amplitude detection circuit. The high-precision amplitude detection scheme utilizes a first clamping circuit to prevent the output stage circuit from entering a shutdown state, and a second voltage clamping circuit to ensure the response speed of the first clamping circuit, achieving high-speed and high-precision amplitude detection. In a preferred embodiment, the linearity of the circuit is further improved by connecting a resistor in series between the peak voltage and the output voltage. Using this high-precision amplitude detection scheme, the measurement accuracy of amplitude detection can be significantly improved.
[0036] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," "link," and "fix" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art will understand the specific meaning of the above terms in this invention based on the specific circumstances.
[0037] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various equivalent changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.
Claims
1. A sine wave amplitude detection circuit, characterized in that... The circuit includes: an input stage transconductance amplifier Gm, an output stage transconductance amplifier g and its bias current Ib, a transconductance amplifier G and its bias current k*Ib, a compensation capacitor C1, a first clamping transistor M1, a second clamping transistor M2 and its clamping bias voltage generator, the output peak voltage Vb of the output stage transconductance amplifier is fed back to the non-inverting input of the input stage, and the output peak voltage Vb is filtered to generate the output voltage Vout; The input stage transconductance amplifier Gm, the output stage transconductance amplifier g, and the first clamping transistor M1 constitute the main loop; the output stage transconductance amplifier g and transconductance amplifier G only have the ability to output current and have no ability to receive current; the transconductance amplifier G and the first clamping transistor M1 constitute the first clamping circuit; the main loop and the first clamping circuit cooperate to detect the peak value of the input peak voltage Vin and output the peak voltage Vb; the second clamping transistor M2 and the clamping bias voltage generator constitute the second clamping circuit, which clamps the gate of the first clamping transistor M1; the first clamping circuit and the second clamping circuit are used to improve the overall response speed of the circuit; The output terminal of the input stage transconductance amplifier Gm is connected to the input terminal of the output stage transconductance amplifier g, with the connection node being Va. The output terminal of the output stage transconductance amplifier g outputs a peak voltage Vb, which is fed back directly to the non-inverting input of the input stage transconductance amplifier Gm, and connected to the input terminal of the filter. The filter filters Vb and outputs a voltage Vout. The input terminal of the transconductance amplifier G is connected to node Va, and its output terminal is connected to the control terminal Vg of the first clamping transistor M1. The transconductance amplifier G and the first clamping transistor M1 form a closed-loop first clamping circuit. The source terminal of the second clamping transistor M2 is connected to the control terminal Vg of the first clamping transistor M1, and its gate terminal is connected to the output terminal of the clamping bias voltage generator. The two together constitute the second clamping circuit.
2. The sine wave amplitude detection circuit as described in claim 1, characterized in that, Through appropriate design, the transconductance of the output stage transconductance amplifier g when the bias current is Ib and the transconductance of the transconductance amplifier G when the bias current is k*Ib satisfy the following expression; at this time, when Va reaches the clamping voltage, that is, when the output current flowing through the transconductance amplifier G is equal to its bias current k*Ib, the output current of the output stage transconductance amplifier g is also equal to its bias current Ib. In this way, the output current of the transconductance amplifier g will not continue to decrease as Vin decreases; therefore, the output peak voltage Vb will not decrease as the input peak voltage Vin decreases, that is, the clamping function is achieved. The transconductance of the transconductance amplifier must satisfy the following expression: ; g m1 g represents the transconductance of the output stage transconductance amplifier. m2 denoted by , where represents the transconductance of the transconductance amplifier G, and k represents the proportionality coefficient.
3. The sine wave amplitude detection circuit as described in claim 1, characterized in that, The filter circuit is used to further process the peak output voltage Vb and output it to the next stage circuit. The filter is set as a capacitor to store the peak output voltage Vb.