A catenary bird nest recognition method and device

By combining diagonal cosine feature extraction and support vector machine algorithms, the problem of insufficient memory and computing power for high-resolution bird nest detection in low-cost MCUs is solved, achieving low-power and high-efficiency bird nest recognition.

CN116721241BActive Publication Date: 2026-01-16FUZHOU UNIV
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Patent Information

Application Number
CN202310439576.7
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2023-04-23
Publication Date
2026-01-16
Estimated Expiration
2043-04-23

AI Technical Summary

Technical Problem

Existing technologies struggle to achieve high-resolution image recognition, particularly bird nest detection, in low-cost edge microcontrollers, primarily due to insufficient memory and computing power, resulting in high costs and power consumption.

Method used

By combining diagonal cosine feature extraction and support vector machine algorithms, a fast image judgment can be achieved by extracting a limited number of features during the image decoding process, thereby reducing memory consumption and improving processing speed.

Benefits of technology

Achieving a Bird's Nest detection frequency of 2-3 frames per second in a low-cost MCU with a 160MHz main frequency and 8Mb memory reduces cost and power consumption, making it suitable for ESP32-CAM equipment.

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Abstract

The application discloses a catenary bird nest recognition method and device, comprising the following steps: S1, acquiring a bird nest image; S2, carrying out feature extraction in the decoding process of the bird nest image to realize image judgment. The technical scheme of the application solves the problems of insufficient memory and insufficient computing power when high-resolution image recognition is performed.
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Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of image recognition, and particularly relates to a catenary bird nest recognition method and device. BACKGROUND

[0002] At present, bird damage has become the third largest failure next to lightning damage and external damage. Therefore, identifying the bird nests of power system transmission equipment and removing them is an important measure to reduce bird damage, but the research on bird nest detection of high-voltage transmission lines is still in its infancy. There are two main types of detection methods for bird nest images on transmission lines, namely traditional detection based on feature extraction and automatic detection combined with deep learning. The existing methods usually require GPU and large memory (>=512Mb) high-performance (main frequency >=1GHz) personal computers or high-spec edge processors supporting linux operating system, which are high in cost and high in power consumption. It cannot be realized in low-cost (less than 30 yuan) edge microcontrollers. SUMMARY

[0003] The present application aims to solve the problems of the prior art, and provides a catenary bird nest recognition method and device to solve the problems of insufficient memory and computing power when high-resolution image recognition is performed.

[0004] To achieve the above-mentioned purpose, the present application provides the following solutions.

[0005] A catenary bird nest recognition method, comprising the following steps:

[0006] Step S1, acquiring a bird nest image;

[0007] Step S2, simultaneously performing feature extraction during decoding of the bird nest image to realize image judgment.

[0008] Preferably, the bird nest image is a jpeg image.

[0009] Preferably, step S2 comprises:

[0010] Simultaneously performing diagonal cosine feature extraction during decoding of the jpeg image to obtain a limited number of features;

[0011] According to the limited number of features, a support vector machine algorithm is used to realize fast image judgment.

[0012] Preferably, the diagonal cosine feature includes an alternating component on a diagonal line, and the alternating component on the diagonal line includes a high-frequency component on the diagonal line and a low-frequency component.

[0013] The present application also provides a catenary bird nest recognition device, comprising:

[0014] An acquisition module for acquiring a bird nest image;

[0015] The recognition module is used for feature extraction during decoding of the bird nest image, so as to realize image judgment.

[0016] As a preferred, the bird nest image is a jpeg image.

[0017] As a preferred, the recognition module comprises:

[0018] The extraction unit is used for diagonal cosine feature extraction during decoding of the jpeg image, so as to obtain a limited number of features.

[0019] The judgment unit is used for realizing fast image judgment by using a support vector machine algorithm according to the limited number of features.

[0020] As a preferred, the diagonal cosine feature comprises alternating current components on a diagonal line, and the alternating current components on the diagonal line comprise high-frequency components and low-frequency components.

[0021] Compared with the prior art, the present application has the following advantages:

[0022] The present application can realize a detection frequency of 2-3 frames per second at a minimum in a low-price MCU with a main frequency of 160Mhz and a memory of 8Mb for a jpeg image of 1600X1200 (UXGA). In addition, the present application can realize image recognition without inverse cosine transformation, so as to improve the image recognition speed of related algorithms, and realize high-speed bird nest image processing based on an ESP32-CAM device. BRIEF DESCRIPTION OF DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the present application, the following briefly introduces the drawings needed in the embodiments. Obviously, the drawings described in the following embodiments are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained without creative labor.

[0024] Figure 1 The flowchart of the catenary bird nest recognition method;

[0025] Figure 2 The structural schematic diagram of the catenary bird nest recognition device. DETAILED DESCRIPTION

[0026] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the protection scope of the present application.

[0027] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the present application will be further described in detail below with reference to the drawings and specific embodiments.

[0028] Embodiment 1:

[0029] The existing image recognition technology usually obtains continuous image stream data from the camera. In order to save the transmission bandwidth, reduce the burden of the camera microcontroller, and ensure the real-time of image and video transmission, a lossy compression mode such as JPEG is usually used for high-resolution image data such as UXGA. When the existing machine learning algorithm or deep learning algorithm implements image recognition, it is usually divided into the following steps: jpeg image decoding, decoding the compressed image data into a corresponding resolution image data matrix, taking the image data matrix as the input of the deep learning and machine learning algorithm, and classifying the image according to the trained model through the algorithm. Image decoding requires a large amount of calculation, for example, the most commonly used jpeg file is based on discrete cosine transform. Decoding requires inverse cosine transform of the original file, which itself requires a large amount of computing resources, especially for most MCUs, which do not have corresponding image decoders or GPU hardware image processing units. In addition, the input and processing process of two-dimensional image data is another process. For deep learning, the determination process usually requires a large amount of video card memory, which is determined by the size of the deep learning model. For machine learning algorithms, such as SVM support vector machine or naive Bayes, which are effective in image recognition. Although the model size is small, it at least requires the memory of the image size. For high-resolution images, the memory consumption is at least greater than the memory occupied by the image data itself. For a 1600X1200, 24bit high-resolution image data, the memory consumption is 5.76M. If the program itself memory consumption is considered, the required operation memory number is at least greater than 10Mb. This is difficult to achieve in some conventional MCUs. And for low-cost MCUs, the processing efficiency is limited when processing 10Mb level data. Even if external memory is used to increase the cost, due to the performance limitation of the processor itself (the working frequency is usually less than 250MHz).

[0030] As shown in Figure 1 The embodiment of the present application provides a catenary bird nest recognition method, which comprises the following steps:

[0031] Step S1, acquiring a bird nest image;

[0032] Step S2, feature extraction is performed simultaneously in the decoding process of the bird nest image to realize image judgment.

[0033] As an implementation of the embodiment of the present application, the bird nest image is a jpeg image.

[0034] As an implementation of the embodiment of the present application, step S2 comprises:

[0035] The diagonal cosine feature is extracted simultaneously in the decoding process of the jpeg image, and a limited number of features is obtained.

[0036] According to the limited number of features, a support vector machine algorithm is used to realize fast image judgment.

[0037] As an implementation of the embodiment of the present application, the diagonal cosine feature comprises alternating current components on a diagonal line, and the alternating current components on the diagonal line comprise high-frequency components and low-frequency components.

[0038] The embodiment of the present application integrates the decoding, feature extraction and judgment processes in the bird nest image recognition process. That is, the feature extraction is performed in the decoding process of the jpeg image, and the number of extracted features is limited, thereby reducing the memory consumption. Finally, based on the limited number of features, a support vector machine algorithm is used to realize fast judgment.

[0039] Since the jpeg image is compressed according to the discrete cosine transform, the features extracted by the embodiment of the present application are the discrete Fourier transform coefficients contained in the jpeg image, and the embodiment only extracts the cosine transform coefficients of the diagonal line. After extraction, no inverse cosine transform is needed, and a large amount of computing resources is not consumed.

[0040] Due to the characteristics of the jpeg algorithm itself, the compression ratio is high, and most of the energy falls into a few components after the cosine transform. And the large block region or the block region without high contrast and clear boundary or texture is ignored in the feature extraction.

[0041] The jpeg image itself compresses the high-frequency information according to the sensitivity of the human eye. For an original image of about 5Mb of image data, only a few hundred k of data is compressed, and the compression ratio is usually higher than 10 times. The embodiment of the present application focuses on detecting high-frequency information and medium-frequency information. Therefore, the proportion of memory occupied by the actual feature extraction is smaller. Thus, an 8M memory MCU can realize image processing.

[0042] For the limited number of features and the extremely fast feature extraction speed, a support vector machine algorithm is used, which can realize extremely fast processing speed and can also realize processing in the MCU.

[0043] The technical scheme of the embodiment of the present application, that is, the decoding-feature extraction-judgment scheme, can enable the 8M memory 160MHz frequency MCU to realize fast image judgment of the high-resolution image UXGA (1600X1200) under the premise of ensuring the accuracy (correctness > 85%), and the processing speed of each frame of image is usually 1-2 seconds, not more than 3 seconds. Using other image algorithms, for the MCU of this specification, it will be limited by memory and frequency, and cannot be processed, or program crashes will occur in the processing process due to insufficient memory.

[0044] For an edge processor or a small computing device with a frequency greater than 1GHz and a memory greater than 512MB, such as a Raspberry Pi based on an arm processor or a full Z1 single-core Iron C906 of a risc-V processor, the algorithm speed is much faster than other machines or deep learning algorithms. For a support vector machine algorithm, its speed is at least 1 / 10 (reduced by one order of magnitude) of the algorithm.

[0045] The embodiment of the present application is realized based on the C language to ensure the speed and real-time requirements of the algorithm, and the decoding and feature extraction process is integrated, as follows:

[0046] 1. For a 1 jpeg image, an 8*8 intensity image Y unit is obtained.

[0047] 2. According to the run-length coding specification, decoding and only restoring the AC components of the diagonal line through the quantization table are performed.

[0048] 3. According to a set threshold, AC components greater than the set threshold are extracted. Most image units do not have AC components that meet the full 4 threshold condition and are directly discarded, thereby saving the amount of calculation. The maximum number of AC components extracted can be set to further limit the number of features.

[0049] 5. Support vector machines are used to judge the extracted feature set. Since the number of features is much smaller than the number of pixels of the image itself, only the model information corresponding to the feature coordinates in the training model needs to be extracted and operated with the image features in the SVM judgment. Since the number of features is small, the amount of calculation is also small, so that image recognition of large resolution can be realized in a low-power MCU.

[0050] 6. The training of the SVM model is also based on the diagonal line cosine features extracted from the above-mentioned jpeg image, and is realized by using the open-source libsvm software package.

[0051] Embodiment 2:

[0052] As Figure 2 described, the embodiment of the present application provides a catenary bird nest recognition device, comprising:

[0053] An acquisition module is configured to acquire a bird nest image.

[0054] The recognition module is configured to perform feature extraction simultaneously in the decoding process of the bird nest image, so as to realize image judgment.

[0055] In an embodiment of the present application, the bird nest image is a jpeg image.

[0056] In an embodiment of the present application, the recognition module comprises:

[0057] The extraction unit is configured to perform diagonal cosine feature extraction simultaneously in the decoding process of the jpeg image, so as to obtain a limited number of features.

[0058] The judgment unit is configured to realize fast image judgment by using a support vector machine algorithm according to the limited number of features.

[0059] In an embodiment of the present application, the diagonal cosine feature comprises alternating current components on a diagonal line, and the alternating current components on the diagonal line comprise high-frequency components and low-frequency components.

[0060] The above embodiments are only used to describe the preferred modes of the present application, and are not used to limit the scope of the present application. Any modification and improvement of the technical solutions of the present application made by those skilled in the art without departing from the design spirit of the present application shall fall within the protection scope of the present application.

Claims

1. A catenary bird nest recognition method, characterized in that, The method comprises the following steps: Step S1, acquiring a bird nest image; Step S2, simultaneously performing feature extraction in the decoding process of the bird nest image to realize image judgment; The bird nest image is a jpeg image; Step S2 comprises: Simultaneously performing diagonal cosine feature extraction in the decoding process of the jpeg image to obtain a limited number of features; According to the limited number of features, a support vector machine algorithm is used to realize fast image judgment; After extraction, no inverse cosine transformation is required; The diagonal cosine feature comprises AC components on a diagonal line, and the AC components on the diagonal line comprise high-frequency components and medium-low-frequency components on the diagonal line; According to a set threshold, AC components greater than the set threshold are extracted.

2. A catenary bird nest recognition device for implementing the catenary bird nest recognition method of claim 1, characterized in that, The method comprises: An acquisition module is configured to acquire a bird nest image; An identification module is configured to simultaneously perform feature extraction in the decoding process of the bird nest image to realize image judgment.

Citation Information

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