An adaptive equalization method and device suitable for phase modulation format

Abstract

The present invention relates to the field of digital signal processing technology, and provides an adaptive equalization method and device suitable for phase modulation format. The method includes selectively performing positive conjugation or negative conjugation on a first input signal according to the positive and negative properties of the real part of a first output signal and the positive and negative properties of the error of the first output signal to obtain a first reference value; wherein the first output signal is an output signal in a first output direction, and the first input signal is an input signal in a first input direction; the first reference value is reduced by a corresponding multiple to obtain a first compensation value, and the first compensation value is used to optimize the first filter parameter. The present invention reduces the number of multiplication operations, thereby reducing the processing delay, achieving rapid and stable iterative optimization of filter parameters and rapid convergence of signals, and is therefore suitable for real-time systems.

Description

Technical Field

[0001] The present invention relates to the technical field of digital signal processing, and in particular to an adaptive equalization method and device suitable for phase modulation format. Background Art

[0002] When the signal is transmitted in the link, the instability of the link will inevitably cause power jitter, and the bandwidth limitation of the device will also cause the signal quality to deteriorate. When the signal link medium is optical fiber, it will also be damaged by dispersion, polarization mode dispersion, polarization rotation, etc. Since the signal damage is random and constantly changing, it is impossible to use a fixed digital filter to compensate for the damage. In the existing technology, an adaptive equalizer (AdaptiveEqualizer, AEQ) is usually required to achieve dynamic channel equalization. For polarization multiplexed signals, the adaptive equalizer based on Multiple Input Multiple Output (MIMO) can not only achieve dynamic channel equalization, but also polarization demultiplexing.

[0003] For signals in phase modulation format, the existing adaptive equalization technology utilizes the circular symmetry of the signal, minimizes the cost function, and continuously and dynamically corrects the parameters of the FIR filter according to the value of the cost function during the equalization iteration process to restore the signals in the two polarization directions. However, the existing technology has the following disadvantages: ① A large number of multipliers are used in filtering and parameter updating, which occupies a large amount of computing resources; ② A large number of complex operations based on multiplication lead to an increase in the pipeline delay of the real-time system, so that the filter parameters cannot be updated in time, affecting the signal recovery quality. ③ Convergence failure occurs when processing BPSK (Binary Phase Shift Keying) signals; in addition, the current equalization method for processing BPSK signals requires controlled rotation of the signal at the transmitter, which increases the complexity of the system; or a more complex equalization algorithm is used at the receiver, but the algorithm will fail when the pipeline delay is too large, so it cannot be used in real-time systems. The above disadvantages will cause the current adaptive equalization module to occupy more than 50% of the total multiplier resources, with the disadvantages of high cost and high power consumption, and cannot be directly used for signals in BPSK format (one of the phase modulation formats).

[0004] In view of this, overcoming the defects of the prior art is an urgent problem to be solved in the field of this technology. Summary of the invention

[0005] The technical problem to be solved by the present invention is that a large number of multiplication operations are used in the adaptive equalization method in the prior art, which occupies a large amount of computing resources, increases the processing delay of the system, and cannot be applied to real-time systems.

[0006] The present invention adopts the following technical solution:

[0007] An adaptive equalization method applicable to a phase modulation format, iteratively optimizing each filter parameter according to multiple input signals and multiple output signals obtained by corresponding filtering; wherein iteratively optimizing a first filter parameter corresponding to a combination of a first input direction and a first output direction comprises:

[0008] According to the positive and negative properties of the real part of the first output signal and the positive and negative properties of the error of the first output signal, the first input signal is selectively positively conjugated or negatively conjugated to obtain a first reference value; wherein the first output signal is an output signal in a first output direction, and the first input signal is an input signal in a first input direction;

[0009] The first reference value is reduced by a corresponding multiple to obtain a first compensation value, and the first filtering parameter is optimized using the first compensation value.

[0010] Preferably, the step of selectively performing positive conjugation or negative conjugation on the first input signal according to the positive or negative property of the real part of the first output signal and the positive or negative property of the error of the first output signal to obtain the first reference value specifically includes:

[0011] Performing an XOR operation on the sign bit of the real part of the first output signal and the sign bit of the error of the first output signal to obtain an XOR result;

[0012] If the XOR result is 0, performing positive conjugation on the first output signal to obtain the first reference value;

[0013] If the XOR result is 1, negative conjugate is performed on the first output signal to obtain the first reference value.

[0014] Preferably, in the case of a single filtering channel, reducing the first reference value by a corresponding multiple to obtain the first compensation value specifically includes:

[0015] The first reference value is shifted rightward by a corresponding number of bits to obtain the first compensation value.

[0016] Preferably, in the case of multiple filtering channels, reducing the first reference value by a corresponding multiple to obtain the first compensation value specifically includes:

[0017] The first reference values ​​of the filter channels are added together to obtain a total reference value, and the total reference value is shifted rightward by a corresponding number of bits to obtain the first compensation value.

[0018] Preferably, before performing a right shift operation on the first reference value by a corresponding number of bits, the method further comprises:

[0019] According to the range of the step length, multiple preset step lengths are determined, and the logarithm corresponding to each preset step length as a true number with base 2 is calculated. Each logarithm is rounded to obtain a corresponding preset number of bits, so as to facilitate selecting a corresponding target preset number of bits from the multiple preset number of bits, and the first reference value is shifted right by the target preset number of bits to obtain a first compensation value.

[0020] Preferably, the positive or negative attribute of the error of the first output signal is obtained by comparing the modulus value of the first output signal with a preset modulus value, specifically including:

[0021] When the modulus of the first output signal is greater than the preset modulus, the error of the first output signal is a negative number;

[0022] When the modulus of the first output signal is less than the preset modulus, the error of the first output signal is a positive number.

[0023] Preferably, filtering the multiple input signals to obtain the multiple output signals specifically includes:

[0024] Transpose the input signals in each input direction respectively to obtain corresponding transposed signals;

[0025] Multiplying the transposed signal of the corresponding input direction by the filtering parameter corresponding to the combination of the input direction and the corresponding output direction to obtain the filtering component of the input signal of the input direction in the output direction;

[0026] The filtered components of the input signals in each input direction in the corresponding output direction are added together to obtain the output signal in the output direction.

[0027] Preferably, the multi-channel input signals are obtained by recombining source signals, specifically including:

[0028] Splice the current source signal with the historical source signal to obtain a complete signal;

[0029] Taking the corresponding position of the complete signal as the starting position, N consecutive positions are selected from the starting position as the corresponding input signals; and taking the position with a preset length interval after the starting position as the next starting position, the next round of input signal selection is performed until the number of selected input signals reaches a preset number; wherein N is the number of taps.

[0030] Preferably, the method is applicable to at least one of a QPSK signal, a BPSK signal and an 8PSK signal.

[0031] In a third aspect, the present invention further provides an adaptive equalization device applicable to a phase modulation format, which is used to implement the adaptive equalization method applicable to a phase modulation format described in the first aspect, and the device includes:

[0032] At least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the processor to execute the adaptive equalization method applicable to the phase modulation format described in the first aspect.

[0033] In a fourth aspect, the present invention further provides a non-volatile computer storage medium, wherein the computer storage medium stores computer executable instructions, which are executed by one or more processors to implement the adaptive equalization method applicable to the phase modulation format described in the first aspect.

[0034] The present invention reduces the number of multiplication operations, thereby reducing processing delays, achieving rapid and stable iterative optimization of filtering parameters and rapid convergence of signals, and is therefore suitable for real-time systems. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0036] Figure 1 It is a flow chart of an adaptive equalization method applicable to a phase modulation format provided by an embodiment of the present invention;

[0037] Figure 2 It is a flow chart of an adaptive equalization method applicable to a phase modulation format provided by an embodiment of the present invention;

[0038] Figure 3 is a schematic diagram of an adaptive equalization method applicable to a phase modulation format provided by an embodiment of the present invention;

[0039] Figure 4 It is a schematic diagram comparing the principles of an adaptive equalization method applicable to a phase modulation format provided by an embodiment of the present invention with the prior art;

[0040] Figure 5 It is a schematic diagram of a first adaptive equalization method applicable to a phase modulation format provided by an embodiment of the present invention in a multi-filter channel scenario;

[0041] Figure 6 It is a schematic diagram of a second adaptive equalization method applicable to a phase modulation format provided by an embodiment of the present invention in a multi-filter channel scenario;

[0042] Figure 7 It is a schematic diagram of a third adaptive equalization method applicable to a phase modulation format provided by an embodiment of the present invention in a multi-filter channel scenario;

[0043] Figure 8 It is a flowchart of an adaptive equalization method in the prior art provided by an embodiment of the present invention;

[0044] Fig. 9 It is a flow chart of an adaptive equalization method applicable to a phase modulation format provided by an embodiment of the present invention;

[0045] Fig.10 It is a flow chart of an adaptive equalization method applicable to a phase modulation format provided by an embodiment of the present invention;

[0046] Fig.11 It is a schematic diagram of generating an input signal in an adaptive equalization method applicable to a phase modulation format provided by an embodiment of the present invention;

[0047] Fig.12 It is a schematic diagram of a first adaptive equalization method applicable to a phase modulation format provided by an embodiment of the present invention in a single filtering channel scenario;

[0048] Fig.13 It is a schematic diagram of a second adaptive equalization method applicable to a phase modulation format provided by an embodiment of the present invention in a single filtering channel scenario;

[0049] Fig.14 It is a schematic diagram comparing the convergence rate of an adaptive equalization method applicable to a phase modulation format provided by an embodiment of the present invention and the prior art;

[0050] Fig.15 It is a schematic diagram of sensitivity comparison between an adaptive equalization method applicable to a phase modulation format provided by an embodiment of the present invention and the prior art;

[0051] Fig.16 An adaptive equalization method applicable to a phase modulation format provided by an embodiment of the present invention and a constellation diagram of a corresponding signal processed by the prior art;

[0052] Fig.17 It is a schematic diagram of the architecture of an adaptive equalization device applicable to a phase modulation format provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0053] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0054] The terms "first", "second", etc. in the present invention are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first", "second", etc. may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0055] In the present invention, the combination of corresponding input directions and output directions is represented by corresponding subscripts, wherein the first subscript represents the input direction, and the second subscript represents the output direction. Taking Wxy as an example, the first subscript x represents that the input direction is the X polarization direction, and the second subscript y represents that the output direction is the Y polarization direction. Wxy represents the filtering parameters corresponding to the combination of the input direction being the X polarization direction and the output direction being the Y polarization direction. It should be noted that the corresponding input direction and output direction in the present invention are all exemplified by the two polarization directions of X and Y, which does not limit the present invention to being applicable only to the input and output of the two polarization directions of X and Y. In actual use, the input and output of the four directions of XI, XQ, YI and YQ are also applicable in the present invention.

[0056] In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0057] In order to make the purpose and technical solution of the present invention more clear, the present invention also describes the adaptive equalization method in the prior art. For example, the optimization principle of filtering parameters in the prior art is as follows:

[0058]

[0059] in, is the filter parameter after the nth round of iteration optimization, is the step length, which is adjusted by technicians in this field based on experiments. is the error of the output signal in the nth iteration, is the input signal in the nth iteration, is the conjugate of the input signal in the nth iteration, is the output signal in the nth iteration, is the filter parameter optimized after the n+1th round of iteration. The overall implementation idea is: use the filter parameters obtained after the previous round of iteration , for the input signal Filter and get , detection Error , using the above formula, we can calculate , It is then used for the next round of iteration, so that after multiple iterations, the error of the output signal continues to decrease to restore the signal quality.

[0060] From the above formula, we can know that in calculating The process involves at least 3 multiplication operations, among which It needs to rely on operations such as square, subtraction, and multiplication to obtain it. and It is usually a complex matrix, which greatly increases the complexity of multiplication. Therefore, when using this formula to optimize the filtering parameters, a large amount of computing resources is required, resulting in increased processing delay.

[0061] Embodiment 1:

[0062] The adaptive equalization method in the prior art uses a large number of multiplication operations, which occupies a large amount of computing resources, resulting in an increase in the processing delay of the system, and cannot be applied to real-time systems. In order to solve this problem, embodiment 1 of the present invention provides an adaptive equalization method applicable to a phase modulation format, and the method is applicable to at least one of a QPSK (Quadrature Phase ShiftKeying) signal, a BPSK signal, and an 8PSK (8 Phase Shift Keying) signal. The method comprises: filtering a multi-channel input signal to obtain a multi-channel output signal, and iteratively optimizing each filtering parameter according to the multi-channel input signal and the multi-channel output signal obtained by corresponding filtering; wherein the first filtering parameter corresponding to the combination of the first input direction and the first output direction is iteratively optimized, such as Figure 1 As shown, including:

[0063] In step 201, based on the positive and negative attributes of the real part of the first output signal and the positive and negative attributes of the error of the first output signal, the first input signal is selectively positively conjugated or negatively conjugated to obtain a first reference value; wherein the first output signal is an output signal in a first output direction, and the first input signal is an input signal in a first input direction; the positive and negative attributes refer to whether the corresponding number is positive or negative, the positive conjugation refers to the conjugate complex number of the first input signal as the first reference value, and the negative conjugation refers to the opposite of the conjugate complex number of the first input signal as the first reference value. Wherein, as a special case, when the real part of the first output signal or the error of the first output signal is 0, the corresponding positive and negative attributes are neither positive nor negative, and at this time, the first reference value is 0. Fig.12 For the single-channel filtering scenario shown in FIG. 1 , the multiple input signals are Xin and Yin, and the multiple output signals are Xout and Yout. Figure 5Taking the multi-channel filtering scenario shown as an example, the multiple input signals are Xin_1~Xin_P and Yin_1~Yin_P, and the multiple output signals are Xout_1~Xout_P and Yout_1~Yout_P.

[0064] In step 202, the first reference value is reduced by a corresponding multiple to obtain a first compensation value, and the first compensation value is used to optimize the first filter parameter. Specifically, the first filter parameter is added to the first compensation value to obtain the optimized first filter parameter. The reduction multiple is obtained by those skilled in the art based on empirical analysis, and this reduction multiple is also referred to as step size in subsequent embodiments.

[0065] In an optional embodiment, the first input direction is an X polarization direction or a Y polarization direction, and the first output direction is an X polarization direction or a Y polarization direction. Taking the first input direction as the X polarization direction and the first output direction as the X polarization direction as an example: the first filter parameter corresponding to the combination of the first input direction and the first output direction refers to Wxx; taking the first input direction as the X polarization direction and the first output direction as the Y polarization direction as an example: the first filter parameter corresponding to the combination of the first input direction and the first output direction refers to Wxy; taking the first input direction as the Y polarization direction and the first output direction as the X polarization direction as an example: the first filter parameter corresponding to the combination of the first input direction and the first output direction refers to Wyx; taking the first input direction as the Y polarization direction and the first output direction as the Y polarization direction as an example: the first filter parameter corresponding to the combination of the first input direction and the first output direction refers to Wyy.

[0066] It should be noted that step 201-step 202 is for a single round of iteration. In actual use, multiple rounds of iterative optimization are usually required. Specifically, the first filter parameter after the previous round of iteration is used as the starting filter parameter of the next round of iteration, and the first input signal is filtered using the starting filter parameter to obtain a first output signal. The above step 201 is performed to obtain a first reference value, and the first reference value is reduced by a corresponding multiple to obtain a first compensation value. The first compensation value is added to the starting filter parameter to obtain the first filter parameter after the next round of iterative optimization. In the first iteration, the first filter parameter used is obtained by a person skilled in the art based on empirical analysis. For example, when the number of taps is 11 and the input direction is the X polarization direction and the Y polarization direction, the filter coefficients Wxx and Wyy of the first iteration are set to [0 0 0 0 0 1 0 00 0 0], and the filter coefficients Wxy and Wyx of the first iteration are set to [0 0 0 0 0 0 0 0 0 0 0]. The number of taps refers to the number of tap coefficients. For example, each value in the filter coefficient Wxx is a corresponding tap coefficient. The filter coefficient Wxx contains 11 values, that is, the corresponding number of taps is 11.

[0067] It should be noted here that the "previous round of iteration" and "previous round of iteration" described in this embodiment are relative to two adjacent iteration processes. For example, three rounds of iterations have been performed up to a certain time. For the convenience of description, these three rounds of iterations are referred to as the first round of iteration, the second round of iteration and the third round of iteration in chronological order. The first round of iteration is the "previous round of iteration" of the second round of iteration, the second round of iteration is the "next round of iteration" of the first round of iteration, the second round of iteration is the "previous round of iteration" of the third round of iteration, and the third round of iteration is the "next round of iteration" of the second round of iteration.

[0068] The first output direction and the first input direction do not refer to specific directions, but are used to separate the corresponding limited objects from the same category. Figure 5 For example, in the application scenario Figure 5 In the example, the first input direction can be the X polarization direction or the Y polarization direction, and the corresponding output direction can be the X polarization direction or the Y polarization direction, that is, the first output direction can also be the X polarization direction or the Y polarization direction. In actual use, it is necessary to optimize the filtering parameters. Figure 5 Including , , and Among these four filtering parameters, the filtering parameters corresponding to the combination of input direction X (i.e., input direction is X polarization direction) and output direction X (i.e., output direction is X polarization direction) are: , the filter parameters corresponding to the combination of input direction X (i.e., input direction is X polarization direction) and output direction Y (i.e., output direction is Y polarization direction) are: , the filter parameters corresponding to the combination of input direction Y (i.e., input direction is Y polarization direction) and output direction Y (i.e., output direction is Y polarization direction) are: , the filter parameters corresponding to the combination of input direction Y (i.e., input direction is Y polarization direction) and output direction X (i.e., output direction is X polarization direction) are: .by As the first filtering parameter, it is iteratively optimized. For example, the first input direction is the X direction, the first output direction is the Y direction, and , or The iterative optimization of the first filtering parameter is also implemented based on this concept, which will not be elaborated here.

[0069] The first compensation value calculated according to the reference value may be obtained by multiplying the reference value by a preset step size. Taking the first input direction as the X polarization direction and the first output direction as the Y polarization direction as an example, the basic implementation principle of the above implementation can be expressed as the following formula:

[0070]

[0071] in, is the first filter parameter after the nth round of iterative optimization, is the step length, which is adjusted by technicians in this field based on experiments. is the error of the first output signal in the nth iteration, Representatives Take the symbol and get The positive and negative properties of is the first source signal in the nth iteration, is the conjugate of the first source signal in the nth iteration, is the first output signal in the nth iteration, represent The real part of Representatives Taking the sign of the real part of The positive and negative properties of the real part of is the first filter parameter after the n+1th round of iterative optimization. In this formula, Understood as The positive and negative attributes of get the corresponding 1 or -1 value; similarly, Understood as The positive and negative attributes of and When the positive and negative attributes are consistent, and Multiplying them together gives 1, which corresponds to ;when and When the positive and negative attributes are inconsistent, and Multiplying them together gives -1, which corresponds to .

[0072] It should be noted that the above formula is only a principle description of this embodiment and does not represent that it is necessary to and In actual computer program implementation, there are two optional implementations for performing multiplication operations:

[0073] Implementation Method 1: Selecting the Sign Bit of the Error of the First Output Signal and the sign bit of the real part of the first output signal ,judge and Are they equal? ​​If they are equal, use Calculate the first compensation value, otherwise, use A first compensation value is obtained by calculation.

[0074] The second implementation mode is: according to the positive and negative properties of the real part of the first output signal and the positive and negative properties of the error of the first output signal, the first input signal is selectively positively conjugated or negatively conjugated to obtain a first reference value, such as Figure 2 and Figure 3 As shown, specifically including:

[0075] In step 301, an XOR operation is performed on the sign bit of the real part of the first output signal and the sign bit of the error of the first output signal to obtain an XOR result.

[0076] In step 302, if the XOR result is 0, the first output signal is positively conjugated to obtain the first reference value.

[0077] In step 303, if the XOR result is 1, negative conjugate is performed on the first output signal to obtain the first reference value.

[0078] That is, select the sign bit of the error of the first output signal and the sign bit of the real part of the first output signal ,right and Perform an XOR operation. If the XOR result is 0, use Calculate the first compensation value, otherwise, use The first compensation value is calculated and can be expressed as the following formula:

[0079]

[0080] in, Represents the exclusive OR operation. A sign bit of 0 represents a positive value, and a sign bit of 1 represents a negative value. When the result of the exclusive OR operation on the sign bits of two values ​​is 0, it means that the positive and negative attributes of the two values ​​are the same. When the exclusive OR result is 1, it means that the positive and negative attributes of the two values ​​are different.

[0081] By comparing the above-mentioned implementation mode 1 or implementation mode 2 with the principle of the prior art, it can be obtained that: this embodiment reduces the at least three multiplication operations required for each iterative optimization of a filter parameter in the prior art to only one multiplication operation, and the judgment process or bit operation (including sign bit acquisition and XOR operation) added compared to the prior art consumes much less computing resources for the computer than the multiplication operation, so it can greatly reduce the computing resources consumed by the optimization of the filter parameters, improve computing efficiency, and reduce processing delays.

[0082] The rationality of the implementation of this embodiment will be explained below by comparing the implementation principle of this embodiment with the implementation principle in the prior art. Figure 4 As shown, the principle changes made by this embodiment relative to the prior art are: Replace with ,Will Replace with , these two changes can be understood as is approximately 1 or -1, Approximately 1 or -1, this approximation will cause a certain degree of decrease in calculation accuracy, but in actual use, the calculation accuracy is also affected by the processing delay. The greater the processing delay, the more clock beats are occupied, and the corresponding optimization accuracy of the filter parameters is lower. In the implementation method of this embodiment, due to the reduction in the number of multiplication operations, the processing delay can be reduced, and the accuracy of the filter parameter optimization can be improved, thereby compensating for the decrease in accuracy caused by the approximation, and as the number of iterative optimization increases, the decrease in calculation accuracy caused by the approximate processing is further optimized, thereby ultimately achieving fast and stable iterative optimization of the filter parameters and rapid convergence of the signal.

[0083] In order to further reduce the computing resource usage and improve computing efficiency, this embodiment also provides a preferred implementation method, that is, in the case of a single filtering channel, the first reference value is reduced by a corresponding multiple to obtain a first compensation value, specifically including: performing a right shift operation on the first reference value by a corresponding number of bits to obtain the first compensation value. The number of bits shifted to the right is obtained by those skilled in the art based on experimental analysis, and combined with the above-mentioned implementation method 2, the following formula is obtained:

[0084]

[0085] Where k is the number of bits shifted to the right. Represents shifting the corresponding value to the right by k bits. The shift operation is mathematically equivalent to multiplying the corresponding value by , where m is less than 1 when shifting to the right and greater than 1 when shifting to the left. is equivalent to Based on this principle, the technical personnel in this field determine the k value, thereby performing a shift operation, and using the shift operation to replace the multiplication operation in the prior art. Since the computing resources occupied by the shift operation in the computer are far less than the multiplication operation, this preferred implementation can further reduce the computing resources, reduce the processing delay, and improve the processing efficiency.

[0086] In actual use, there are also multiple filter channels, and multiple filter channels use the same set of filter parameters. Figure 5 Taking the application scenario shown in the figure as an example, each filter channel filters the input signals in different input directions to obtain output signals in different output directions. Figure 5 For example, the input direction is the two polarization directions of X and Y. The first source signal (length is 2P) in the X polarization direction and the second source signal (length is 2P) in the Y polarization direction are recombined to obtain P first input signals Xin_1~Xin_P and P second input signals Yin_1~Yin_P respectively. Each first input signal and the corresponding second input signal are input into the corresponding filter channel. After filtering by the filter channel, the corresponding first output signal Xout and the corresponding second output signal Yout are output. The i-th first input signal Xin_i and the i-th second input signal Yin_i are input into the i-th filter channel, and the i-th first output signal Xout_i and the i-th second output signal Yout_i are output, where i is greater than 0 and not greater than P. Correspondingly, there are P filter channels including FIR_1, FIR_2, ..., FIR_P. Each input signal in the X polarization direction and the input signal in the Y direction are input into the corresponding filter channel. Each filter channel uses , , and The four filtering parameters form a set of filtering parameters, and the corresponding output signals in the X polarization direction (Xout_1~Xout_P) and the Y polarization direction (Yout_1~Yout_P) are obtained through filtering.

[0087] In the case of multiple filtering channels, each filtering channel corresponds to a first reference value calculated, and the first reference value is reduced by a corresponding multiple to obtain a first compensation value, specifically including: adding the first reference values ​​of each filtering channel to obtain a total reference value, and performing a right shift operation on the total reference value by a corresponding number of bits to obtain the first compensation value. In combination with the above embodiments, the related steps in this embodiment will be further integrated to provide a relatively complete logical display of the adaptive equalization method under multiple filtering channels, such as Fig. 9 As shown, specifically including:

[0088] In step 401, based on the positive and negative properties of the real part of the first output signal in the corresponding filter channel and the positive and negative properties of the error of the first output signal, the first input signal of the filter channel is selectively positively conjugated or negatively conjugated to obtain the first reference value of the filter channel; wherein the first output signal is the output signal of the first output direction of the filter channel, and the first input signal is the input signal of the first input direction of the filter channel.

[0089] In step 402, the first reference values ​​of the filter channels are added to obtain a total reference value, the total reference value is shifted rightward by a corresponding number of bits to obtain the first compensation value, and the first filter parameter is optimized using the first compensation value.

[0090] In actual use, there is another implementation method of step 402: adding the first reference values ​​of each filtering channel to obtain a total reference value, multiplying the total reference value by a preset step size to obtain a first compensation value, and using the first compensation value to optimize the first filtering parameter.

[0091] Among them, the specific number of bits shifted to the right is obtained by a technician in this field according to the step length required for adaptive equalization. However, in actual use, in order to improve the accuracy of the adaptive equalization method, the technicians in this field usually select an initial step length to perform the adaptive equalization method, and adjust the step length according to the convergence of the signal quality under the initial step length. In this embodiment, in order to facilitate the technicians in this field to flexibly adjust the step length, this embodiment also provides the following preferred implementation, that is, before the first reference value is shifted to the right by the corresponding number of bits, the method also includes: according to the range of the step length, determining multiple preset step lengths, calculating the logarithm corresponding to each preset step length when it is a true number with 2 as the base, rounding each logarithm to obtain the corresponding preset number of bits, so as to select the corresponding target preset number of bits from the multiple preset number of bits, and performing the right shift operation of the target preset number of bits on the first reference value to obtain the first compensation value. The rounding can be rounding up, rounding down, or rounding according to the corresponding rules preset by the technicians in this field.

[0092] Taking the preset step size of 0.004 as an example, the corresponding calculation is , rounding up -7.96578 to -8, the corresponding preset number of bits is 8. When a value is shifted right by 8 bits, it can be regarded as multiplying the value by , it can be seen that the multiplier in the multiplication operation corresponding to the shift calculation is close to the preset step size of 0.004. Although the present preferred implementation converts the multiplication operation into the shift operation, it loses some calculation accuracy, but improves the processing efficiency and reduces the processing delay, so that the lost part of the accuracy is within the range that can be compensated by the delay accuracy and the iterative process, so it can reduce the computing resources and improve the computing efficiency. At the same time, in order to realize the flexible and adjustable step size, the present embodiment also presets a plurality of preset bit numbers, so that those skilled in the art can flexibly adjust and use them.

[0093] In actual implementation, the pre-set multiple preset bit numbers can be stored in a step selection register. The storage bit width occupied in the step selection register is determined by the number of preset bit numbers. For example, if m preset bit numbers are preset, the storage bit width is ceil(log2(m)), that is, the value obtained by rounding up log2(m). If there are 3 preset bit numbers, the storage bit width is 4. Use 3 values ​​of 00, 01, 10 and 11 to represent the corresponding preset bit numbers, respectively, so as to facilitate the subsequent selection of the corresponding preset bit numbers for use. If the step range is 0.005~0.0001, the specific value of the step can be determined as follows: (It is not necessary to satisfy all gears of a, a-1, a-2..., b. It is only necessary to select a few required gears according to the range for optimization design, as shown below):

[0094] 2^-8 = 0.00390625 (i.e. a-5=8)

[0095] 2^-10 = 0.0097656 (i.e. a-3=10)

[0096] 2^-11 = 0.00048828 (i.e. a-2=11)

[0097] 2^-13 = 0.00012207 (i.e. a=13)

[0098] That is, the preset number of bits is 8, 10, 11 and 13. The bit width of the step selection register is determined according to the number of preset bits n, and the bit width is ceil(log2(n)). The value of the step selection register is matched with the preset number of bits one by one, as shown below:

[0099] 2^-8 = 0.00390625 (i.e. a-5=8) corresponding to mode=00

[0100] 2^-10 = 0.0097656 (i.e. a-3=10) corresponding to mode=01

[0101] 2^-11 = 0.00048828 (i.e. a-2=11) corresponding to mode=10

[0102] 2^-13 = 0.00012207 (i.e. a=13) corresponding to mode=11

[0103] That is, 00 represents the preset number of digits 8, 01 represents the preset number of digits 10, 10 represents the preset number of digits 11, and 11 represents the preset number of digits 13. It should be noted that 2^K represents 2 raised to the power of K.

[0104] In the prior art, the error of the first output signal is calculated by the following formula:

[0105]

[0106] Here, R is a preset modulus value, which is obtained by a person skilled in the art according to analysis of signal quality recovery requirements.

[0107] In this embodiment, only The positive and negative attributes of Therefore, this embodiment also provides the following preferred implementation modes in combination with the above implementation modes, that is, the positive and negative attributes of the error of the first output signal are obtained by comparing the modulus value of the first output signal with the preset modulus value, specifically including:

[0108] When the modulus of the first output signal is greater than the preset modulus, the error of the first output signal is negative, that is, the corresponding sign bit is obtained. is 1.

[0109] When the modulus of the first output signal is less than the preset modulus, the error of the first output signal is a positive number, that is, the corresponding sign bit is obtained. is 0.

[0110] When the modulus value of the first output signal is equal to the preset modulus value, There is no positive or negative attribute, and the first reference value is 0.

[0111] In this preferred embodiment, there is no need to calculate the error of the first output signal. Instead, the positive or negative property of the error is determined by comparing it with a preset modulus value, thereby further simplifying the calculation and improving processing efficiency.

[0112] In actual application scenarios, the multiple input signals are filtered to obtain multiple output signals, such as Fig.10 As shown, specifically including:

[0113] In step 501, the input signals in each input direction are transposed respectively to obtain corresponding transposed signals.

[0114] In step 502, the transposed signal of the corresponding input direction is multiplied by the filtering parameter corresponding to the combination of the input direction and the corresponding output direction to obtain the filtering component of the input signal of the input direction in the output direction.

[0115] In step 503, the filtered components of the input signals in each input direction in the corresponding output direction are added together to obtain the output signal in the output direction.

[0116] Taking the output direction as the Y polarization direction as an example, the above steps 501 to 503 can be expressed as the following formula:

[0117]

[0118] in, is the output signal with the output direction of Y polarization in the corresponding filtering channel, is the input signal with the input direction being the X direction, For Transpose, is the filter parameter corresponding to the combination of the input direction being the X direction and the output direction being the Y direction; is the input signal with the input direction in the Y direction, For Transpose, It is the filtering parameter corresponding to the combination of the input direction being the Y direction and the output direction being the Y direction.

[0119] The multiple input signals may be directly input from the outside, or may be input from external source signals, and the input signals are obtained by recombining the source signals, that is, the multiple input signals are obtained by recombining the source signals, specifically including:

[0120] The current source signal is spliced ​​with the historical source signal to obtain a complete signal; the corresponding position of the complete signal is used as the starting position, and N consecutive positions from the starting position are selected as the corresponding input signals; and the position with a preset length interval after the starting position is used as the next starting position, and the next round of input signal selection is performed until the number of selected input signals reaches the preset number; wherein N is the number of taps. The number of taps, the corresponding position, the preset number and the preset length are obtained by technicians in this field according to the analysis of the needs of adaptive equalization. If there is no historical source signal before the current source signal, the corresponding initial signal can be set by the technicians in this field, and the initial signal and the current source signal are spliced ​​to form a complete signal, such as setting the initial signal to a signal sequence of length 2P, all of which are 0.

[0121] The historical source signal is obtained by caching the source signal received in the clock cycle of the past moment, and the specific cached signal length is obtained by a technician in this field according to the analysis of the adaptive equalization requirements. Figure 5 For example, when a source signal of 2P length in the X direction and a signal of 2P length in the Y direction are input in each clock cycle, and the number of taps N is 11, the preset number is P, such as Fig.11 As shown in (b), the 2P source signal input in the previous cycle is cached. When the 2P signal of the next cycle is received, it is spliced ​​together with the signal of the previous cycle to form a complete signal of 4P length. The first position of the complete signal is used as the starting position, and 11 consecutive positions are selected to form group_1 (i.e., position 1 to position 11), which is the first input signal. The position (i.e., position 3) that is 2 positions (i.e., the preset length is 2) after the first position is used as the next starting position, and the second input signal group_2 (i.e., position 3 to position 13) is selected. By analogy, group_3 (position 5 to position 15) is selected, until group_P (position 2P-1 to position 2P+9) is obtained. It can also be as follows Fig.11 As shown in (a), the 3rd position, the 5th position, etc. are selected as the starting positions in turn to select the corresponding input signal.

[0122] In actual implementation, depending on the number of taps, only caching the source signal of the previous clock cycle for splicing the resulting complete signal may not be sufficient to select P input signals with a length equal to the number of taps. In this case, the cache space can be increased to cache source signals of multiple clock cycles. For example, if there are three clock cycles t2, t3 and t4 before the t1 clock cycle, the source signals of the t2 and t3 clock cycles can be cached and spliced ​​with the source signal of the t1 clock cycle to form a complete signal of 6P length. Alternatively, the source signals of the t2, t3 and t4 clock cycles can be cached and spliced ​​with the source signal of the t1 clock cycle to form a complete signal of 8P length.

[0123] In combination with the preferred implementations in this embodiment, the complete logic in a single filter channel scenario is shown as follows: Fig.12 and Fig.13 As shown, Fig.12 It is a basic implementation framework in a single filter channel scenario. In this scenario, the method described in this embodiment is applied to an adaptive equalization device, which includes: a data cache and reorganization module, a digital filter module, an error detection module, a filter parameter update module, and a step size selection module. Among them, the error detection module includes an X-direction error detection module and a Y-direction error detection module, and the filter parameter update module includes a Wxx filter parameter update module, a Wyx filter parameter update module, a Wxy filter parameter update module, and a Wyy filter parameter update module. Fig.13It is the specific implementation of the error detection module, filter parameter update module and step size selection module.

[0124] The data caching and reorganization module is used to cache the parallel input data, and then reorganize the data according to different source signals required for calculating the output signal to obtain the input signal.

[0125] The digital filtering module is used to multiply and add the input signal with the continuously iteratively updated filter tap coefficients. The obtained output signal is the output of the digital filtering module, which is both the output signal of the entire adaptive equalization device and the input source of the error detection module.

[0126] The error detection module is used to compare the signal power of the output signal with a preset modulus value to obtain the sign of the error of the output signal.

[0127] The filter parameter update module is used to calculate the corresponding reference value according to the input signal, the output signal and the sign of the error of the output signal, and sum up all the parallel output reference values ​​as the compensation values ​​of the four sets of digital filter parameters (Wxx, Wyx, Wxy and Wyy). Fig.12 and Fig.13 In the example, the data flow direction of the input signal and the output signal to the filter parameter update module is not marked, but it does not mean that the data flow direction does not exist. Fig.13 The internal specific implementation of each module can indirectly show the corresponding unidentified data flow direction. For example, in the filter parameter update module, if the input signal Xin is used, there must be a data flow direction for the input signal to be input to the module.

[0128] The step size selection module is used to match the corresponding step size according to the value of the step size selection register, and then perform corresponding shift processing on the filter parameter update value, and output the corresponding compensation value for the digital filter module to iteratively update (add) the filter tap coefficient (i.e., each filter parameter).

[0129] The complete logic display in the multi-filter channel scenario is as follows Figure 5-Figure 7 As shown, Figure 5 It is the basic implementation framework in the multi-filter channel scenario. Its architecture in the actual adaptive equalization device is based on the same concept as the single-filter channel scenario and will not be elaborated here. Figure 6 and Figure 7 These are two optional specific implementations of the error detection module, the filter parameter update module and the step size selection module.

[0130] by Figure 7 As an example, combined with the specific implementation shown Figure 8From the implementation diagram of the error detection module and the filter parameter update module in the prior art shown in the figure, it can be seen that the adaptive equalization method of this embodiment greatly reduces the use of multipliers compared with the prior art. It is obtained through experiments by those skilled in the art that in a multi-filter channel scenario with a tap number of 11, the adaptive equalization method described in this embodiment can be used to filter each symbol and update the filter parameters. The number of real number multiplications used can be reduced from 356 times / per symbol in the prior art to 176 times / per symbol, even if the resource occupation of the multiplier is reduced by more than 50%, thereby greatly saving hardware resources and hardware power consumption.

[0131] like Fig.14 : is a curve diagram comparing the convergence rate of the adaptive equalization method described in this embodiment and the prior art in the same scenario, wherein the solid line is the prior art and the dotted line is the adaptive equalization method of this embodiment. It can be seen that the total number of iterations required for the signal convergence of this embodiment is about 1×10 less than that of the prior art. 4 Since the delay of each round of iteration in this embodiment is much less than that in the prior art, the signal convergence speed in this embodiment is much faster than that in the prior art.

[0132] And through Fig.15 From the signal processing sensitivity performance comparison curve diagram of the adaptive equalization method of the present embodiment and the prior art applied in the same scenario, it can be seen that the final effect of processing the signal by the adaptive equalization method of the present embodiment and the prior art is almost the same.

[0133] At the same time, this embodiment also uses the adaptive equalization method described in this embodiment to process the QPSK signal and the BPSK signal, and uses the existing technology to process the QPSK signal and the BPSK signal, and obtains the following Fig.16 The constellation diagram shown, where Fig.16 (a) is the constellation diagram after the existing technology (i.e., constant modulus algorithm) acts on the QPSK signal. Fig.16 (b) is the constellation diagram after the existing technology (i.e., constant modulus algorithm) is applied to the BPSK signal. Fig.16 (c) is a constellation diagram after the adaptive equalization method of this embodiment acts on the QPSK signal. Fig.16 (d) is the constellation diagram after the adaptive equalization method of this embodiment is applied to the BPSK signal. It can be seen that the adaptive equalization method of this embodiment and the prior art both have good processing effects on the QPSK signal. However, when processing the BPSK signal, the prior art will lead to convergence failure and the appearance of 4 constellation groups. Under the processing of the adaptive equalization method of this embodiment, the BPSK constellation diagram can still be restored well, so that it can be applied to all phase modulation formats.

[0134] Embodiment 2:

[0135] In order to make the purpose, technical solutions and advantages of the present invention more clear, this embodiment is also based on the method described in Example 1, combined with the specific application scenarios under multiple filtering channels, and uses the technical descriptions under related scenarios to explain the implementation process of the present invention under the characteristic scenarios.

[0136] The application scenarios of this embodiment are as follows Figure 5-Figure 7 As shown, it contains multiple filter channels (such as Figure 5 Each filter channel filters the input signal in different input directions to obtain output signals in different output directions. Figure 5 Taking the input direction as an example of two polarization directions of X and Y, the first source signal (length is 2P) in the X polarization direction and the second source signal (length is 2P) in the Y polarization direction are recombined to obtain P first input signals Xin_1~Xin_P and P second input signals Yin_1~Yin_P respectively. Each first input signal and the corresponding second input signal are input into the corresponding filtering channel, and the corresponding first output signal Xout and the corresponding second output signal Yout are output after filtering by the filtering channel. Among them, the i-th first input signal Xin_i and the i-th second input signal Yin_i are input into the i-th filtering channel, and the i-th first output signal Xout_i and the i-th second output signal Yout_i are output, where i is greater than 0 and not greater than P.

[0137] Among them, each filter channel contains multiple filter parameters, and each combination of input direction and output direction corresponds to a filter parameter, such as Figure 5 As shown, including two polarization directions, X and Y, there are four input and output combinations, XX, XY, YY and YX, corresponding to four filter parameters W xx , W xy , W yy and W yx , each filter channel uses these 4 filter parameters. Each time a signal is input, the corresponding output signal is filtered, and the error of the output signal is detected. The filter parameters are optimized according to the error, and the optimized filter parameters are used to filter the next round of input signals, thus forming an iterative optimization. Through continuous signal input and optimization of filter parameters, the filter parameters gradually approach the ideal value, thereby reducing the error of the output signal.

[0138] In this application scenario, the corresponding requirements are determined in advance by those skilled in the art, such as the source signal of the adaptive equalization module is sampled twice, the input parallelism is 16 (i.e. Figure 5The source signal length 2P in the example is 16); the output signal is sampled 1 times, and the output parallelism is 8 (ie, P=8). The quantization bit width is 6, the number of taps of the filter (ie, N in Example 1) is 11, the preset modulus R of the output signal of the adaptive equalization module is 20, and the preset power =400. According to the range of the step length, the number of steps is set to 4, namely 1 / 2^18, 1 / 2^17, 1 / 2^16 and 1 / 2^15. Therefore, according to the step length selection module manufacturing method proposed in the present invention, the bit width of the step length selection register mode is determined to be 2, that is, mode (00) corresponds to a step length of 1 / 2^18, and the corresponding preset number of bits is 18, mode (01) corresponds to a step length of 1 / 2^17, and the corresponding preset number of bits is 17, mode (10) corresponds to a step length of 1 / 2^16, and the corresponding preset number of bits is 16, and mode (11) corresponds to a step length of 1 / 2^15, and the corresponding preset number of bits is 15. Initialize the filter parameters, set Wxx and Wyy at the first iteration to [0 0 0 0 0 1 0 0 0 0 0], and set Wxy and Wyx at the first iteration to [0 0 0 0 0 0 0 0 0 0 0].

[0139] At the rising edge or falling edge (choose one) of each clock cycle, the 2P-channel parallel source signal is cached and spliced ​​with the signal cached in the previous time period to obtain a complete signal that meets the time continuity. Then, according to the number of taps, the required signal with equal length, continuous time and consistent starting point interval is selected for reorganization. Fig.11 As shown, in this embodiment, the data cache module caches two cycles of signals, that is, the cache sequence length is 32 (ie, 4P), which can be expressed as X(1:32) and Y(1:32). Under 2x sampling, the even-numbered signal is selected as the best output signal position for 1x sampling (ie, the position of the output signal that is finally filtered and output), that is, Fig.11 In order to make the signal center of the final input signal the best output signal position, that is, when the best output signal position is n, in this embodiment, when the number of taps is 11, the input signal can be expressed as Xin(n-5:n+5). In order to ensure that the serial number is a positive integer, n takes 8 consecutive even numbers starting from 6, that is, Xout(6:2:20) and Yout(6:2:20) are selected as the output signal (that is, positions 6, 10, 12, ..., 20 are selected as the output signal). With n being 6, 10, 12, ..., 20, the corresponding Xin(n-5:n+5) is selected, and the input signal corresponding to the output signal Xout(6) is Xin(1:11) and Yin(1:11), and the input signal corresponding to the output signal Xout(8) is Xin(3:13) and Yin(3:13), and so on.

[0140] For dual-polarization 16 (i.e. 2P=16) parallel input signals, a total of 8 (i.e. P=8) filter channels need to be designed, such as using 8 2×2 CV-MIMO (complex valued-multiple input and multiple output) FIR (Finite impulse response) filters. At the rising or falling edge of each clock cycle, the input signal is multiplied and added with the corresponding filter parameters to obtain the corresponding output signal, i.e.

[0141]

[0142]

[0143] Among them, each filtering channel outputs 1 output signal Xout and 1 output signal Yout. In the present embodiment, there are 8 filtering channels in total, and 8 output signals Xout and 8 output signals Yout are obtained. The signal length of each Xout and each Yout is consistent with the input signal length of the corresponding filtering channel, which is 11. The 8 Xouts are respectively called Xout_1, Xout_2, ..., Xout_8, and the 8 Youts are respectively called Yout_1, Yout_2, ..., Yout_8.

[0144] Compare the modulus of each output signal with the preset modulus R. If the preset modulus is greater than the modulus of the corresponding output signal, the sign of the error of the corresponding output signal is 0; if the preset modulus is less than the modulus of the corresponding output signal, the sign of the error of the corresponding output signal is 1; if the preset modulus is equal to the modulus of the corresponding output signal, it is considered that the output signal has no error, and no subsequent calculation is required. The first reference value corresponding to the corresponding input and output combination under the filter channel is directly obtained as 0. The sign of the error of the output signal is subsequently referred to as a.

[0145] Take out the sign b of the real part of the output signal, perform an XOR operation on the sign a of the output signal error and the sign b of the real part of the output signal, and then adjust the signs of the real and imaginary parts of the corresponding input X polarization signal vector Xin and the input Y polarization signal vector Yin according to the XOR result to achieve positive conjugation or negative conjugation of the input vector. For example, if the sign b of the real part of Yout_2 output by the second filter channel and the sign a of the error of Yout_2 are XORed to 1, then in the second filter channel, the reference value under the combination of input in the X polarization direction and output in the Y polarization direction is , input is Y polarization direction, Y polarization direction output combination of the reference value ; For example, if the result of the XOR of the real part of Yout_2 output by the second filter channel, b, and the error of Yout_2, a, is 0, then in the second filter channel, the reference value under the combination of input in the X polarization direction and output in the Y polarization direction is , input is Y polarization direction, Y polarization direction output combination of the reference value ; When the preset modulus value is equal to the modulus value of Yout_2, the reference values ​​of both combinations are 0.

[0146] At the rising or falling edge (or one of them) of each clock cycle, the P-way parallel filter parameter update values ​​are accumulated as the total output of the filter parameter update module. In this embodiment, the corresponding reference values ​​in different filter channels are added to obtain the total reference value, that is, when the corresponding input-output combination is YY, the ΔW of different filter channels is added to obtain the total reference value ΔW4 when YY, when the corresponding input-output combination is XY, the ΔW of different filter channels is added to obtain the total reference value ΔW3 when the corresponding input-output combination is XY, when the corresponding input-output combination is YX, the ΔW of different filter channels is added to obtain the total reference value ΔW2 when the corresponding input-output combination is YX, and when the corresponding input-output combination is XX, the ΔW of different filter channels is added to obtain the total reference value ΔW1 when the corresponding input-output combination is XX.

[0147] Read the value of the step selection register mode, and perform corresponding shift operations on ΔW1, ΔW2, ΔW3, and ΔW4. For example, assuming ΔW1=24'h0ff000, where the highest bit is the sign bit, the lower 12 bits represent the decimal bits, and the remaining bits represent the integer bits, then 24'h0ff000 represents the decimal number 255 in the actual operation (that is, the binary number 11111111). When the value of mode is 00, ΔW1 is shifted right by 18 bits, that is, 24'h000003, which means the decimal number in the actual operation is about 0.0007; when the value of mode is 01, ΔW1 is shifted right by 17 bits, that is, 24'h000007, which means the decimal number in the actual operation is about 0.0017; when the value of mode is 10, ΔW1 is shifted right by 16 bits, that is, 24'h00000f, which means the decimal number in the actual operation is about 0.0037; when the value of mode is 11, ΔW1 is shifted right by 15 bits, and 24'h00001f is obtained, which is Wxx, which means the decimal number in the actual operation is about 0.0076. According to this method, four compensation values ​​(ΔWxy, ΔWyx and ΔWyy) are obtained.

[0148] At the rising or falling edge (or one of them) of each clock cycle, the compensation value is added to the corresponding filter parameter of the previous clock cycle to obtain a new filter parameter. In this embodiment, the processing time of the corresponding processing actions is unified, that is, each processing action is executed at the rising edge of the clock cycle, or at the falling edge of the clock cycle. In the next clock cycle, the new filter parameters are used for filtering, and the filter parameters are optimized, so that the iterative optimization of the filter parameters is achieved through multiple clock cycles, and finally the convergence of the output signal is achieved.

[0149] Embodiment 3:

[0150] like Fig.17 , is a schematic diagram of the architecture of an adaptive equalizer for phase modulation format according to an embodiment of the present invention. The adaptive equalizer for phase modulation format according to this embodiment includes one or more processors 21 and a memory 22. Fig.17 A processor 21 is taken as an example.

[0151] The processor 21 and the memory 22 may be connected via a bus or other means. Fig.17 The example of connecting through bus is taken in the following.

[0152] The memory 22, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs and non-volatile computer executable programs, such as the adaptive equalization method applicable to the phase modulation format in Embodiment 1. The processor 21 executes the adaptive equalization method applicable to the phase modulation format by running the non-volatile software programs and instructions stored in the memory 22.

[0153] The memory 22 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other non-volatile solid-state storage devices. In some embodiments, the memory 22 may optionally include a memory remotely arranged relative to the processor 21, and these remote memories may be connected to the processor 21 via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0154] The program instructions / modules are stored in the memory 22, and when executed by the one or more processors 21, the adaptive equalization method applicable to the phase modulation format in the above-mentioned embodiment 1 is executed.

[0155] It is worth noting that the information interaction, execution process, etc. between the modules and units within the above-mentioned devices and systems are based on the same concept as the processing method embodiment of the present invention. The specific contents can be found in the description of the method embodiment of the present invention and will not be repeated here.

[0156] A person skilled in the art may understand that all or part of the steps in the various methods of the embodiments may be completed by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, and the storage medium may include: a read-only memory (ROM), a random access memory (RAM), a disk or an optical disk, etc.

[0157] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. An adaptive equalization method suitable for phase modulation format, characterized in that: Iteratively optimizing each filter parameter according to the multiple input signals and the multiple output signals obtained by corresponding filtering; wherein iteratively optimizing the first filter parameter corresponding to the combination of the first input direction and the first output direction comprises: According to the positive and negative properties of the real part of the first output signal and the positive and negative properties of the error of the first output signal, the first input signal is selectively positively conjugated or negatively conjugated to obtain a first reference value; wherein the first output signal is an output signal in a first output direction, and the first input signal is an input signal in a first input direction; Reduce the first reference value by a corresponding multiple to obtain a first compensation value, and use the first compensation value to optimize the first filtering parameter; The method of selectively performing positive conjugation or negative conjugation on the first input signal according to the positive and negative properties of the real part of the first output signal and the positive and negative properties of the error of the first output signal to obtain a first reference value specifically includes: performing XOR operation on the sign bit of the real part of the first output signal and the sign bit of the error of the first output signal to obtain an XOR result; if the XOR result is 0, performing positive conjugation on the first input signal to obtain the first reference value; if the XOR result is 1, performing negative conjugation on the first input signal to obtain the first reference value.

2. The adaptive equalization method applicable to phase modulation format according to claim 1, characterized in that: In the case of a single filtering channel, reducing the first reference value by a corresponding multiple to obtain a first compensation value specifically includes: The first reference value is shifted rightward by a corresponding number of bits to obtain the first compensation value.

3. The adaptive equalization method applicable to phase modulation format according to claim 1, characterized in that: In the case of multiple filtering channels, reducing the first reference value by a corresponding multiple to obtain a first compensation value specifically includes: The first reference values ​​of the filter channels are added together to obtain a total reference value, and the total reference value is shifted rightward by a corresponding number of bits to obtain the first compensation value.

4. The adaptive equalization method applicable to phase modulation format according to claim 3, characterized in that: Before performing a right shift operation on the first reference value by a corresponding number of bits, the method further includes: According to the range of the step length, multiple preset step lengths are determined, and the logarithm corresponding to each preset step length as a true number with base 2 is calculated. Each logarithm is rounded to obtain a corresponding preset number of bits, so as to facilitate selecting a corresponding target preset number of bits from the multiple preset number of bits, and the first reference value is shifted right by the target preset number of bits to obtain a first compensation value.

5. The adaptive equalization method applicable to phase modulation format according to claim 1, characterized in that: The positive or negative attribute of the error of the first output signal is obtained by comparing the modulus value of the first output signal with a preset modulus value, specifically including: When the modulus of the first output signal is greater than the preset modulus, the error of the first output signal is a negative number; When the modulus of the first output signal is less than the preset modulus, the error of the first output signal is a positive number.

6. The adaptive equalization method applicable to the phase modulation format according to any one of claims 1 to 5, characterized in that: The filtering of the multiple input signals to obtain the multiple output signals specifically includes: Transpose the input signals in each input direction respectively to obtain corresponding transposed signals; Multiplying the transposed signal of the corresponding input direction by the filtering parameter corresponding to the combination of the input direction and the corresponding output direction to obtain the filtering component of the input signal of the input direction in the output direction; The filtered components of the input signals in each input direction in the corresponding output direction are added together to obtain the output signal in the output direction.

7. The adaptive equalization method applicable to the phase modulation format according to any one of claims 1 to 5, characterized in that: The multi-channel input signals are obtained by recombining source signals, specifically including: Splice the current source signal with the historical source signal to obtain a complete signal; Taking the corresponding position of the complete signal as the starting position, N consecutive positions are selected from the starting position as the corresponding input signals; and taking the position with a preset length interval after the starting position as the next starting position, the next round of input signal selection is performed until the number of selected input signals reaches a preset number; wherein N is the number of taps.

8. The adaptive equalization method applicable to the phase modulation format according to any one of claims 1 to 5, characterized in that: The method is applicable to at least one of a QPSK signal, a BPSK signal and an 8PSK signal.

9. An adaptive equalization device suitable for phase modulation format, characterized in that: The device comprises: At least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the processor to execute the adaptive equalization method applicable to the phase modulation format as described in any one of claims 1-8.

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