A low-complexity time-domain parallel clock recovery method based on 4 / 3 times sampling rate

Abstract

This invention proposes a low-complexity time-domain parallel clock recovery method based on a 4 / 3 sampling rate. First, a new error extraction model is proposed. Interpolation processing based on a sinusoidal interpolation algorithm is introduced to achieve clock offset compensation. Next, loop filtering and NCO parallel processing are designed specifically for 4 / 3 symbol rate sampling. After interpolation, redundant sampling points are removed through decision making and elastic buffering. Finally, a sinusoidal interpolation algorithm with fixed interpolation coefficients is used to recover the optimal sampling points under 4 / 3 symbol rate sampling, achieving reliable and accurate recovery of transmitted information. This method can achieve high-precision and high-stability parallel time-domain clock recovery in a 4 / 3 symbol rate sampling receiving system, making it particularly suitable for resource-constrained and limited satellite communication systems.

Description

Technical Field

[0001] The present invention belongs to the technical field of satellite-borne communication reception, and in particular relates to a time-domain parallel clock recovery method applicable to a 4 / 3 times symbol rate sampling reception system. Background Art

[0002] In high-speed satellite communication systems, the different clock sources at the transmitter and receiver lead to certain timing errors in the transceiver, necessitating clock recovery at the receiver to ensure that receive sampling occurs at the optimal time. Furthermore, the clock recovery algorithm in the receiver baseband processing is a crucial factor in determining the minimum design frequency for the receive AD sampling clock. Traditional clock recovery methods, based on their error extraction models, typically use a receive AD sampling clock frequency that is 2, 3, or 4 times the symbol rate of the transmitted signal. As communication rates continue to increase, the power consumption of high-rate AD sampling and parallel receive processing will also increase significantly. Designing clock recovery methods for low AD sampling rates is crucial because it can intuitively and effectively optimize the power consumption of the baseband processing system and, when the maximum sampling rate of the AD device is limited, effectively improve the system's maximum transmission rate capability, thus significantly improving the efficiency of the system.

[0003] Domestic and foreign scholars have conducted extensive research on clock recovery algorithms for sampling rates less than 2 times the sampling rate. According to their implementation methods, they can be divided into two categories. The first category is based on the improved clock algorithm of Mueller-Müller, which is suitable for AD sampling clock recovery at 1 times the symbol rate. However, it requires real-time feedback adjustment of the AD sampling clock, which is difficult to implement and has poor performance under low signal-to-noise ratios. The second category estimates and compensates for the clock offset by introducing a special low-pass filter and a series of related operations in the frequency domain, and finally obtains the optimal symbol sampling point through time domain interpolation. The complex low-pass filtering and timely frequency domain conversion processing make its implementation complex and computationally intensive, making it unsuitable for some resource-constrained application scenarios. Summary of the Invention

[0004] The technical problem solved by the present invention is: to overcome the shortcomings of the existing technology and provide a low-complexity time-domain parallel clock recovery method based on a 4 / 3 times sampling rate, which can realize high-precision recovery of the clock offset error of the received signal in a high-speed satellite communication system with tight resources.

[0005] The technical solution of the present invention is:

[0006] A low-complexity time-domain parallel clock recovery method based on a 4 / 3 times sampling rate, comprising:

[0007] 1) Sampling the input signal at a sampling rate higher than 4 / 3 of the input signal symbol rate, and outputting N parallel sampling data to the clock recovery processing module, where N is an integer multiple of 4;

[0008] 2) Use the clock recovery processing module to process the received N parallel sampling data X k Perform sine decimal interpolation processing of the interpolation sampling point number M, and use the parallel interpolation coefficient μ output by the numerical control oscillator NCO to calculate the interpolation coefficient μ. k,n , obtain the parallel interpolation output data Y at time k k,int , and output it to the elastic cache processing unit;

[0009] 3) Using the elastic buffer processing unit to parallel interpolate the output data Y output by the clock recovery processing module k,int Perform elastic cache processing according to the parallel interpolation coefficient μ output by the numerically controlled oscillator NCO k,n , to achieve accurate positioning and elimination of redundant sampling points, and to perform interpolation output Z with a fixed parallel number N k ={z k,1 ,z k,2 ,...z k,N} to the error extraction module;

[0010] 4) Use the error extraction module to receive the N parallel outputs of the elastic cache processing unit, extract the error information, and obtain the clock offset error extraction information err corresponding to time k k , and output to the loop filter;

[0011] 5) Use loop filter to extract information err of clock offset error through loop filtering k Perform low-pass filtering to obtain the frequency control word w k Output to the numerically controlled oscillator NCO;

[0012] 6) According to the frequency control word w k , the numerically controlled oscillator NCO is used to realize the N-way parallel interpolation coefficient estimation update at time k, and the parallel interpolation coefficient μ is obtained k,n , and output to the clock recovery processing module and the elastic cache processing unit;

[0013] 7) Using the optimal sampling recovery unit, the N parallel signals Z output by the elastic buffer k Perform optimal sampling point recovery to obtain the optimal sampling point information S_out of 3N / 4 parallel symbols at time k k , completing parallel clock recovery based on 4 / 3 times the sampling rate.

[0014] Preferably, the sampling rate is 0.1‰-3‰ higher than 4 / 3 times the input signal symbol rate.

[0015] Preferably, the N channels of parallel sampling data X received by the clock recovery processing module at time k k for:

[0016] X k ={xk,1 ,x k,2 ,...x k,N}={x (k-1)*N+1 ,x (k-1)*N+2 ,....x k*N}.

[0017] Get the parallel interpolation output data Y at time k k,int The method is as follows:

[0018] Set the number of interpolation sampling points M, then the interpolation parallel input data X at time k k,int The length is N+M-1, expressed as:

[0019] X k,int ={x k_int,1 ,x k_int,2 ,...,x k_int,N+M-1}={x k-1,N-M+1 ,...x k-1,N ,x k,1 ,x k,2 ,...x k,N}.

[0020] The parallel interpolation output data corresponding to time k is Y k,int ={y k,1 ,y k,2 ,...y k,N}, which means the following:

[0021]

[0022] Among them, μ k-1,n is the parallel interpolation coefficient output by the numerically controlled oscillator NCO at time k-1, sinc(x)=sin(x) / x.

[0023] Preferably, the elastic cache processing unit includes: a redundant sampling point detection module and an elastic cache queue;

[0024] The elastic cache processing is used to accurately locate and eliminate redundant sampling points. Specifically:

[0025] Utilize the elastic cache queue of the elastic cache processing unit to parallel interpolate the output data Y k,int Perform cache processing;

[0026] The redundant sampling point detection module in the elastic buffer processing unit receives the parallel interpolation coefficients output by the numerically controlled oscillator NCO, and the redundant sampling point detection module obtains the differential result dP through the parallel interpolation coefficients. k , and according to the difference result dP k Perform differential judgment to eliminate redundant sampling points y in the elastic cache queue RS .

[0027] Preferably, according to the difference result dP k The method for performing differential judgment is as follows:

[0028] Differential result dP k It can be expressed as:

[0029] dP k ={dμ1′,dμ2′,...,dμ N ′}

[0030] dμ n ′=μ n ′-μ′ n+1

[0031] P k ={μ1′,μ2′,...,μ′ N+1}={μ k-2,N ,μ k-1,1 ,μ k-1,2 ,...,μ k-1,N}

[0032] When dμ n ′<δ1, it is determined that there are no redundant sampling points in the elastic cache queue of the elastic cache processing unit; otherwise, when dμ n When ′>δ1, the parallel interpolation output data Y is determined k,int There are redundant sampling points in the , and the parallel interpolation output data Y k,int Zhong and dμ n The element corresponding to the subscript n is positioned as the redundant sampling point y RS =y k,n ; Remove redundant sampling points from the elastic cache queue;

[0033] When the number of elements in the cache queue is greater than N, the first N elements in the queue are interpolated and output Z with a fixed parallel path number N. k ={z k,1 ,z k,2 ,...z k,N} to the optimal sampling recovery unit and error extraction module;

[0034] Wherein, n=1, 2, ..., N; δ1 is a decision threshold constant, δ1>0; and the length of the cache queue is greater than or equal to 2N.

[0035] Preferably, the value range of δ1 is 0 to 0.5.

[0036] Preferably, the clock offset error extraction information err corresponding to time k is obtained k , which is expressed as follows:

[0037]

[0038] Preferably, the frequency control word w is obtained k The method is as follows:

[0039] w k =w1-err_LF k

[0040]

[0041] err_LF k =k1err k +(err_sum k-1 +k2err k )

[0042] err_sum k =err_sum k-1 +k2err k

[0043] Among them, k1 and k2 are the design parameters of the proportional integral filter. When k is 1, err_sum k-1 Equal to 0.

[0044] Preferably, the parallel interpolation coefficients μ are obtained k,n The method is as follows:

[0045] μ k,n =NCO k,n / 0.75

[0046] NCO k,n =[NCO k-1,N -n·w k ]mod0.75

[0047] Among them, NCO k,n Equal to [NCO k-1,N -n·w k ] divided by 0.75; when k = 1, NCO k-1,N The initial value range is 0 to 0.75.

[0048] Preferably, the method for obtaining the optimal sampling point information of 3N4-way parallel symbols at time k is specifically as follows:

[0049] S_out k ={s_out k,1 ,s_out k,2 ,...,s_out k,3N4}

[0050]

[0051] The value range of ν is [-1 / 3, 1 / 3].

[0052] The advantages of the present invention compared with the prior art are:

[0053] (1) The present invention can achieve high-precision and high-stability parallel time-domain clock recovery in a 4 / 3 symbol rate sampling receiving system, and is more suitable for resource-constrained and limited satellite communication systems;

[0054] (2) The present invention introduces an interpolation process based on a sinusoidal interpolation algorithm to achieve clock offset compensation, thereby avoiding the introduction of inter-symbol crosstalk during the interpolation process and ensuring the accuracy of clock offset compensation;

[0055] (3) The present invention proposes a new error extraction model, which can accurately realize error information extraction under 4 / 3 times symbol rate sampling reception;

[0056] (4) The present invention specifically designs loop filtering and NCO parallel processing for 4 / 3 times symbol rate sampling, achieving high-precision and high-accuracy parallel interpolation coefficient output;

[0057] (5) The present invention removes redundant sampling points through judgment and elastic buffering after interpolation, thereby avoiding symbol errors caused by the existence of redundant sampling points.

[0058] (6) The present invention realizes the optimal sampling point recovery under 4 / 3 times symbol rate sampling through a fixed interpolation coefficient sine interpolation algorithm, and ultimately realizes reliable and accurate recovery of transmitted information. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] Figure 1 1 is a block diagram of the implementation principle of the method of the present invention;

[0060] Figure 2 The NCO frequency control word convergence process when using the method of the present invention;

[0061] Figure 3 The interpolation coefficient updating process when using the method of the present invention;

[0062] Figure 4 Schematic diagram of ideal sampling points and symbol optimal sampling points using the method of the present invention;

[0063] Figure 5 After using the method of the present invention, the optimal symbol sampling point is output. DETAILED DESCRIPTION

[0064] In response to the limited onboard resources, the present invention proposes a low-complexity time-domain parallel clock recovery method based on a 4 / 3 sampling rate. First, a new error extraction model is proposed, which can accurately extract error information under 4 / 3 symbol rate sampling reception. Next, an interpolation process based on a sinusoidal interpolation algorithm is introduced to achieve clock offset compensation, avoiding the introduction of inter-symbol interference during the interpolation process and ensuring the accuracy of clock offset compensation. Then, loop filtering and NCO parallel processing are specifically designed for 4 / 3 symbol rate sampling to achieve high-precision and high-accuracy parallel interpolation coefficient output. After interpolation, redundant sampling points are removed through judgment and elastic caching, avoiding symbol errors caused by the presence of redundant sampling points. Finally, a sinusoidal interpolation algorithm with fixed interpolation coefficients is used to achieve optimal sampling point recovery under 4 / 3 symbol rate sampling, achieving reliable and accurate recovery of transmitted information.

[0065] In order to better describe the present invention, the present invention is described in detail below with reference to schematic diagrams.

[0066] like Figure 1 As shown, the present invention provides a low-complexity time-domain parallel clock recovery method based on a 4 / 3 times sampling rate, comprising the following steps:

[0067] 1) The receiving end samples the input signal at a sampling rate higher than 4 / 3 times the symbol rate of the input signal. In practice, the sampling rate is generally set to be 0.1‰-3‰ higher than 4 / 3 times the symbol rate of the input signal. The receiving end outputs N parallel sampling data (N must be an integer multiple of 4) to the clock recovery processing module. At any time k, the number of transmission symbols corresponding to the N sampling data is 3N / 4. The N parallel sampling data X received by the clock recovery processing module at time k is k for:

[0068] X k ={x k,1 ,x k,2 ,...x k,N}={x (k-1)*N+1 ,x (k-1)*N+2 ,...x k*N}

[0069] 2) Use the clock recovery processing module to process the received N parallel sampling data X k Perform sine decimal interpolation processing on the interpolation sampling points M to obtain the parallel interpolation output data Y at time k k,int , and outputs it to the elastic cache processing unit; at the same time, the numerically controlled oscillator NCO in the clock recovery processing module outputs the parallel interpolation coefficients to the elastic cache processing unit;

[0070] Perform sine decimal interpolation processing, that is, introduce interpolation processing based on sine interpolation algorithm. Different interpolation sampling points M can be set according to application requirements. Then the interpolation parallel input data X at time k is k,int The length is N+M-1, which can be expressed as:

[0071] X k,int ={x k_int,1 ,x k_int,2 ,...,x k_int,N+M-1}={x k-1,N-M+1 ,...x k-1,N ,x k,1 ,x k,2 ,...x k,N}

[0072] The parallel interpolation output data corresponding to time k is Y k,int ={y k,1 ,y k,2 ,...y k,N}, the interpolation processing based on the sine interpolation algorithm can be expressed as follows:

[0073]

[0074] Among them, μ k-1,n is the parallel interpolation coefficient output by the numerically controlled oscillator NCO in the clock recovery processing module at time k-1, sinc(x)=sin(x) / x.

[0075] 3) The elastic buffer processing unit outputs the parallel interpolation output data Y of the clock recovery processing module k,int Perform elastic cache processing to achieve accurate positioning and elimination of redundant sampling points, and perform interpolation output Z with a fixed parallel path number N k ={z k,1 ,z k,2 ,...z k,N} to the error extraction module.

[0076] The elastic cache processing unit includes: a redundant sampling point detection module and an elastic cache queue. The processing process is as follows:

[0077] Utilize the elastic cache queue of the elastic cache processing unit to parallel interpolate the output data Y k,int Perform cache processing.

[0078] The redundant sampling point detection module in the elastic buffer processing unit receives the parallel interpolation coefficients output by the numerically controlled oscillator NCO in the clock recovery processing module, and the redundant sampling point detection module obtains the differential result dP through the parallel interpolation coefficients. k , and according to the difference result dP k Perform differential judgment to eliminate redundant sampling points y in the elastic cache queueRS Specifically:

[0079] Differential result dP k It can be expressed as:

[0080] dP k ={dμ1′,dμ2′,...,dμ N ′}

[0081] dμ n ′=μ n ′-μ′ n+1

[0082] P k ={μ1′,μ2′,...,μ′ N+1}={μ k-2,N ,μ k-1,1 ,μ k-1,2 ,...,μ k-1,N}

[0083] Where n = 1, 2, ..., N.

[0084] The redundant sampling point detection module detects the differential result dP k Each element dμ in n ' to make a decision, thus buffering the data in the elastic buffer queue and interpolating the output data Y in parallel k,int The redundant sampling points y RS Positioning, filtering out redundant sampling points y RS And removed from the elastic cache queue, where the length of the cache queue is greater than or equal to 2N. Specifically:

[0085] When dμ n ′<δ1, it is determined that there are no redundant sampling points in the elastic cache queue of the elastic cache processing unit; otherwise, when dμ n When ′>δ1, the parallel interpolation output data Y is determined k,int There are redundant sampling points in the , and the parallel interpolation output data Y k,int Zhong and dμ n The element corresponding to the subscript n is positioned as the redundant sampling point y RS =y k,n Where n = 1, 2, ..., N. δ1 is the decision threshold constant, which can be set according to application requirements. Typically, δ1 > 0, and preferably 0 to 0.5. When there are excess sampling points, the excess sampling points are removed from the elastic buffer queue.

[0086] When the number of elements in the cache queue is greater than N, the first N elements in the queue are output to the outside, so as to ensure that the elastic cache queue in the elastic cache processing unit can perform interpolation output Z with a fixed parallel number N. k={z k,1 ,z k,2 ,...z k,N} to the optimal sampling recovery unit and error extraction module.

[0087] 4) The error extraction module designs an error extraction function based on 4 / 3 times symbol rate sampling reception for the N parallel outputs of the elastic buffer queue, and obtains the clock offset error extraction information err corresponding to time k k , and output to the loop filter;

[0088] Among them, the clock offset error extraction information err corresponding to time k k The calculation can be expressed as follows:

[0089]

[0090] 5) The loop filter extracts information err from the clock offset error through loop filtering. k Perform low-pass filtering to obtain the frequency control word w k The output is sent to the numerically controlled oscillator NCO to achieve stable control of the numerically controlled oscillator NCO.

[0091] The loop filter design determines the stability of the entire clock recovery loop and the clock synchronization lock speed. It can be implemented using a traditional proportional-integral structure low-pass filter. The error information after loop filtering can be expressed as follows:

[0092] err_LF k =k1err k +(err_sum k-1 +k2err k )

[0093] err_sum k =err_sum k-1 +k2err k

[0094] Among them, k1 and k2 are the design parameters of the proportional integral filter. When k is 1, err_sum k-1 Equal to 0.

[0095] Then the frequency control word w input to NCO at time k is k Updates as follows:

[0096] w k =w1-err_LF k

[0097]

[0098] 6) According to the frequency control word w k, the numerically controlled oscillator NCO is used to realize the N-way parallel interpolation coefficient estimation update at time k, and the parallel interpolation coefficient μ is obtained k,n , and output it to the clock recovery processing module and the redundant sampling point detection module in the elastic buffer processing unit;

[0099] The update process of NCO and μ is as follows: Figure 2 、 Figure 3 As shown. Get the parallel interpolation coefficient μ k,n The estimation process is expressed as follows:

[0100] μ k,n =NCO k,n / 0.75

[0101] NCO k,n =[NCO k-1,N -n·w k ]mod0.75

[0102] Among them, NCO k,n Equal to NCO k-1,N -n·w k Remainder when divided by 0.75; when k=1, NCO k-1,N The initial value range is 0 to 0.75.

[0103] 7) The present invention adopts a loop locking design to achieve real-time estimation and compensation of parallel clock offset, and elastic buffer outputs N parallel signals Z k ={z k,1 ,z k,2 ,...z k,N} is the ideal sampling point at the ideal 4 / 3 times rate. In order to correctly recover the transmitted information, the optimal sampling recovery unit needs to complete the optimal sampling point recovery of 3N4 symbols corresponding to the N parallel signals. Figure 4 As shown, the present invention realizes the optimal sampling point recovery through the interpolation processing of the sinusoidal interpolation algorithm. Finally, the optimal sampling point information of 3N4 parallel symbols at time k is obtained:

[0104] S_out k ={s_out k,1 ,s_out k,2 ,...,s_out k,3N4}

[0105]

[0106] The value range of ν is [-1 / 3, 1 / 3].

[0107] At this point, the parallel clock recovery based on 4 / 3 times the sampling rate is completed. The recovery result is as follows Figure 5 shown.

[0108] The present invention can realize high-precision and high-stability parallel time-domain clock recovery in a 4 / 3 times symbol rate sampling receiving system, and is more suitable for resource-constrained and limited satellite communication systems.

[0109] Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention are within the scope of protection of the technical solutions of the present invention. In the absence of conflict, the embodiments of the present application and the technical features in the embodiments can be combined with each other.

[0110] The contents not described in detail in the specification of the present invention belong to the common knowledge of those skilled in the art.

Claims

1. A low-complexity time-domain parallel clock recovery method based on 4 / 3 times the sampling rate, characterized in that: include: Sampling the input signal at a sampling rate higher than 4 / 3 of the input signal symbol rate, and outputting N parallel sampling data to the clock recovery processing module, where N is an integer multiple of 4; The clock recovery processing module is used to process the received N parallel sampling data X k Perform sine decimal interpolation processing of the interpolation sampling point number M, and use the parallel interpolation coefficient μ output by the numerical control oscillator NCO to calculate the interpolation coefficient μ. k,n , obtain the parallel interpolation output data Y at time k k,int , and output it to the elastic cache processing unit; The parallel interpolation output data Y output by the clock recovery processing module is processed by the elastic buffer processing unit. k,int Perform elastic cache processing according to the parallel interpolation coefficient μ output by the numerically controlled oscillator NCO k,n , to achieve accurate positioning and elimination of redundant sampling points, and to perform interpolation output Z with a fixed parallel number N k ={z k,1 ,z k,2 ,...z k,N } to the error extraction module; The error extraction module receives the N parallel outputs of the elastic cache processing unit, extracts the error information, and obtains the clock offset error extraction information err corresponding to time k. k , and output to the loop filter; The loop filter is used to extract the clock offset error information err through loop filtering. k Perform low-pass filtering to obtain the frequency control word w k Output to the numerically controlled oscillator NCO; According to the frequency control word w k , the numerically controlled oscillator NCO is used to realize the N-way parallel interpolation coefficient estimation update at time k, and the parallel interpolation coefficient μ is obtained k,n , and output to the clock recovery processing module and the elastic cache processing unit; Using the optimal sampling recovery unit, the N parallel signals Z output by the elastic buffer are k Perform optimal sampling point recovery to obtain the optimal sampling point information S_out of 3N / 4 parallel symbols at time k k , completing parallel clock recovery based on 4 / 3 times the sampling rate.

2. The low-complexity time-domain parallel clock recovery method based on 4 / 3 times sampling rate according to claim 1, characterized in that: The sampling rate is 0.1‰-3‰ higher than 4 / 3 times the input signal symbol rate.

3. The low-complexity time-domain parallel clock recovery method based on 4 / 3 times sampling rate according to claim 2, characterized in that: Get the parallel interpolation output data Y at time k k,int The method is as follows: Set the number of interpolation sampling points M, then the interpolation parallel input data X at time k k,int The length is N+M-1, expressed as: X k,int ={x k_int,1 ,x k_int,2 ,…,x k_int,N+M-1 }; The parallel interpolation output data corresponding to time k is Y k,int ={y k,1 ,y k,2 ,...y k,N }, which means the following: Where n = 1, 2, ..., N, μ k-1,n is the parallel interpolation coefficient output by the numerically controlled oscillator NCO at time k-1, sinc(x)=sin(x) / x.

4. The low-complexity time-domain parallel clock recovery method based on 4 / 3 times sampling rate according to claim 3, characterized in that: The elastic cache processing unit includes: a redundant sampling point detection module and an elastic cache queue; The elastic cache processing is used to accurately locate and eliminate redundant sampling points. Specifically: Utilize the elastic cache queue of the elastic cache processing unit to parallel interpolate the output data Y k,int Perform cache processing; The redundant sampling point detection module in the elastic buffer processing unit receives the parallel interpolation coefficients output by the numerically controlled oscillator NCO, and the redundant sampling point detection module obtains the differential result dP through the parallel interpolation coefficients. k , and according to the difference result dP k Perform differential judgment to eliminate redundant sampling points y in the elastic cache queue RS .

5. The low-complexity time-domain parallel clock recovery method based on 4 / 3 times sampling rate according to claim 4, characterized in that: According to the difference result dP k The method for performing differential judgment is as follows: Differential result dP k It can be expressed as: dP k ={dμ′1,dμ′2,…,dμ′ N } dμ′ n =μ′ n -μ′ n+1 ; P k ={μ′1,μ′2,…,μ′ N+1 }={μ k-2,N ,m k-1,1 ,m k-1,2 ,…,m k-1,N } When dμ′ n <δ1, it is determined that there are no redundant sampling points in the elastic cache queue of the elastic cache processing unit; otherwise, when dμ′ n >δ1, then the parallel interpolation output data Y is determined k,int There are redundant sampling points in the , and the parallel interpolation output data Y k,int and dμ′ n The element corresponding to the subscript n is located as the redundant sampling point y RS =y k,n ; Remove redundant sampling points from the elastic cache queue; When the number of elements in the cache queue is greater than N, the first N elements in the queue are interpolated and output Z with a fixed parallel path number N. k ={z k,1 ,z k,2 ,...z k,N } to the optimal sampling recovery unit and error extraction module; Wherein, n=1, 2, ..., N; δ1 is a decision threshold constant, δ1>0; and the length of the cache queue is greater than or equal to 2N.

6. The low-complexity time-domain parallel clock recovery method based on 4 / 3 times sampling rate according to claim 5, characterized in that: The value range of δ1 is 0 to 0.

5.

7. A low-complexity time-domain parallel clock recovery method based on 4 / 3 times sampling rate according to any one of claims 1 to 6, characterized in that: Get the clock offset error extraction information err corresponding to time k k , specifically:

8. The low-complexity time-domain parallel clock recovery method based on 4 / 3 times sampling rate according to claim 7, characterized in that: Get the frequency control word w k The method is as follows: w k =0.75-err_LF k err_LF k =k1err k +(err_sum k-1 +k2err k ) err_sum k =err_sum k-1 +k2err k Among them, k1 and k2 are the design parameters of the proportional integral filter. When k is 1, err_sum k-1 Equal to 0.

9. The low-complexity time-domain parallel clock recovery method based on 4 / 3 times sampling rate according to claim 8, characterized in that: Get the parallel interpolation coefficient μ k,n The method is as follows: μ k,n =NCO k,n / 0.75 NCO k,n =[NCO k-1,N -n·w k ]mod 0.75 Among them, NCO k,n Equal to [NCO k-1,N -n·w k ] divided by 0.75; when k = 1, NCO k-1,N The initial value range is 0 to 0.

75.

10. The low-complexity time-domain parallel clock recovery method based on 4 / 3 times sampling rate according to claim 9, characterized in that: The method for obtaining the optimal sampling point information of 3N / 4 parallel symbols at time k is as follows: S_out k ={s_out k,1 ,s_out k,2 ,...,s_out k,3N / 4 } The value range of ν is [-1 / 3, 1 / 3].

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