A digital integrated circuit radiation effect in-situ test system and test method

Abstract

The application provides a kind of digital integrated circuit radiation effect in situ test system and test method, to solve the technical problems that the performance and function of existing radiation effect in situ test system cannot be comprehensively tested to digital integrated circuit.The test system includes driving unit, acquisition unit and analysis unit;Acquisition unit includes SMU test module and at least one digital vector test module, SMU test module is used to power supply for the digital integrated circuit to be measured and collects the power consumption current of the digital integrated circuit to be measured;Digital vector test module is used to input electrical signal excitation for the digital integrated circuit to be measured, and collects the level signal output by the digital integrated circuit to be measured;Analysis unit is used to receive the information collected by SMU test module and each digital vector test module, and process it.

Description

Technical Field

[0001] The present invention relates to a radiation effect testing system, and in particular to an in-situ radiation effect testing system and a testing method for a digital integrated circuit. Background Art

[0002] With the development of space technology, aerospace missions are increasing rapidly. As spacecraft operate in outer space, they are exposed to radiation from electrons, protons, and heavy ions of various energies, which can cause space radiation effects in electronic components. Currently, radiation damage to electronic components caused by space radiation effects has become a major cause of spacecraft failures, accounting for approximately 45% of on-orbit failures.

[0003] While electrons and heavy ions can only cause one or two space radiation effects, protons can cause three major space radiation effects: total ionizing radiation dose effects, single-event effects, and displacement damage effects. Consequently, in recent years, numerous research institutions have built numerous proton accelerators, utilizing ground-based accelerator radiation simulations to study the mechanisms of proton-induced radiation damage to electronic components.

[0004] Digital integrated circuits are a crucial component of spacecraft electronic systems. These include large-scale integrated circuits (LSICs) such as memory, FPGAs, and DSPs, as well as small- and medium-scale integrated circuits in the 54 and 74 series. Radiation effects can directly cause digital IC electrical parameter deviations or even functional failure, leading to malfunction of the entire spacecraft system. Therefore, prior to spaceflight use, digital ICs must undergo radiation resistance evaluation testing, typically performed through either in-situ or off-site testing.

[0005] Displacement testing involves irradiating the digital integrated circuit under test and then placing it on a digital integrated circuit test system for performance and functionality testing. While displacement testing can obtain comprehensive device parameters, it suffers from time-varying effects, requiring the shortest possible intervals during displacement testing. Furthermore, device activation occurs after neutron or proton displacement damage exposure, requiring immediate removal from the radiation source for testing, which can pose a health risk. During total ionizing dose irradiation, few radiation source organizations possess digital integrated circuit test systems, and transporting these bulky, weight-intensive systems to the test site is impractical. Therefore, irradiation testing often involves transporting digital integrated circuit devices to a digital integrated circuit test system after irradiation. However, this transportation process consumes considerable time, causing device annealing, and resulting in significant deviations between test values ​​and actual values ​​after irradiation. On the other hand, single-event radiation effect assessment tests for digital integrated circuits typically utilize in-situ testing. In-situ testing involves testing the device under test while it is being irradiated. The test system typically utilizes hardware based on test boards for large-scale digital integrated circuits, such as FPGAs and DSPs, and software based on the functional and performance characteristics of the device under test. During irradiation, sensitive device parameters are monitored in real time. This method facilitates real-time monitoring of devices undergoing radiation testing and allows for timely determination of device failure thresholds. However, due to the limited secondary development and functional expansion capabilities of technologies such as FPGAs and DSPs, current in-situ radiation effect testing systems cannot fully test all performance and functional parameters of digital integrated circuit systems. Summary of the Invention

[0006] The purpose of the present invention is to solve the technical problem that the existing radiation effect in-situ testing system cannot fully test the performance and function of digital integrated circuits, and to provide a digital integrated circuit radiation effect in-situ testing system and testing method.

[0007] In order to achieve the above objectives, the technical solutions provided by the present invention are as follows:

[0008] A digital integrated circuit radiation effect in-situ test system, which is special in that it includes a driving unit, an acquisition unit and an analysis unit; the acquisition unit includes an SMU test module and at least one digital vector test module;

[0009] The input end of the SMU test module and the input end of each digital vector test module are respectively connected to the driving unit; the SMU test module and each digital vector test module are respectively used to be connected to the digital integrated circuit to be tested, and the digital integrated circuit to be tested is located in the radiation field; the SMU test module is used to power the digital integrated circuit to be tested and collect the power consumption current of the digital integrated circuit to be tested; the digital vector test module is used to input a test vector for the digital integrated circuit to be tested and collect the level signal output by the digital integrated circuit to be tested;

[0010] The analysis unit is connected to the output end of the SMU test module and the output end of each digital vector test module respectively, and is used to receive information collected by the SMU test module and each digital vector test module and process the information.

[0011] Furthermore, it also includes a display unit, which is connected to the analysis unit and is used to display the processing results output by the analysis unit.

[0012] Furthermore, the driving unit and the collecting unit are both located outside the radiation field.

[0013] Furthermore, the driving unit and the collecting unit are both located in the radiation field and are shielded by an anti-radiation shielding box.

[0014] Furthermore, the SMU test module includes at least one dual-channel SMU test board, or at least two single-channel SMU test boards.

[0015] Furthermore, the driving unit, SMU test module, digital vector test module and analysis unit are all programmed using LabVIEW and Python programming languages.

[0016] In addition, the present invention also provides an in-situ testing method for radiation effects of digital integrated circuits, comprising the following steps:

[0017] Step 1: Build the system

[0018] Build the above-mentioned digital integrated circuit radiation effect in-situ test system and set the reference level V OL and V OH and place the digital integrated circuit to be tested in the radiation field;

[0019] Step 2] Drive the acquisition unit

[0020] The SMU test module and each digital vector test module are driven respectively by the driving unit to power the digital integrated circuit to be tested and input a fixed test vector;

[0021] Step 3: Collect functional data

[0022] Using a digital vector test module to specify an input sampling time for each output pin on the digital integrated circuit under test, and receiving a level signal output by the digital integrated circuit under test within the input sampling time, wherein the level signal is the functional data of the digital integrated circuit under test;

[0023] Step 4: Collect performance data

[0024] Collecting performance data of the digital integrated circuit to be tested through a digital vector test module, wherein the performance data includes AC parameters and DC parameters;

[0025] Step 5] Data analysis and processing

[0026] Processing the data collected in step 3] and step 4] to obtain the radiation sensitivity parameters of the digital integrated circuit to be tested, and selecting the top three radiation sensitivity parameters;

[0027] Step 6] Obtain the boundary value of radiation damage

[0028] The shmoo test method is used to test the top three radiation-sensitive parameters to obtain the radiation damage boundary value of the digital integrated circuit to be tested; the radiation damage boundary value refers to the failure value of the sensitive parameter at a certain dose point, as well as the failure value of the electrical parameters related to the sensitive parameter test, thereby completing the in-situ test of the radiation effect of the digital integrated circuit.

[0029] Furthermore, step 5 is specifically as follows:

[0030] 5.1] Use RobustScaler to transform the functional data collected in step 3] and the performance data collected in step 4], and remove outliers;

[0031] 5.2] Use the sklearn.decomposition.PCA class to reduce the dimensionality of the data after removing outliers, and use the n_components parameter in the sklearn.decomposition.PCA class to specify the number of feature dimensions of the data after dimensionality reduction;

[0032] 5.3] The data after dimensionality reduction is normalized and the variance is set to 1 to obtain the true radiation sensitivity parameters.

[0033] Furthermore, in step 3], the output signal level is compared with the reference level V set in step 1] OL or V OH If the output signal level is less than the set reference level V OL It means that the output logic function of the output pin of the digital integrated circuit to be tested is low level. If the output signal level is greater than the set reference level V OHIt means that the output logic function of the output pin of the digital integrated circuit under test is high level.

[0034] Furthermore, step 6 is specifically as follows:

[0035] Two-dimensional or three-dimensional shmoo test views are established for the top three sensitive parameters among the radiation sensitive parameters and the electrical parameters related to their tests, and then the mutual influence curves between the top three sensitive parameters are obtained, and finally the radiation damage boundary values ​​of the radiation sensitive parameters of the digital integrated circuit to be tested during irradiation are obtained.

[0036] Compared with the prior art, the present invention has the following beneficial effects:

[0037] 1. The test system of the present invention includes a drive unit, an acquisition unit, and an analysis unit. The acquisition unit includes an SMU test module and at least one digital vector test module. The SMU test module is used to power the digital integrated circuit under test and collect the power consumption current of the digital integrated circuit under test. The digital vector test module is used to input electrical signal excitation to the digital integrated circuit under test and collect the level signal output by the digital integrated circuit under test. The analysis unit is used to receive and process the information collected by the SMU test module and each digital vector test module. The present invention uses a combination of hardware and software to complete a comprehensive test of the functions and performance parameters of the digital integrated circuit during the irradiation process. The overall structure is highly integrated and has a wide range of applications.

[0038] 2. The testing method of the present invention can quantitatively determine the effect of each radiation-sensitive parameter on the radiation damage of the digital integrated circuit to be tested. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 This is a schematic structural diagram of an embodiment of an in-situ testing system for radiation effects of digital integrated circuits according to the present invention;

[0040] Figure 2 This is a flow chart of an embodiment of an in-situ testing method for radiation effects of a digital integrated circuit according to the present invention;

[0041] Figure 3 This is a flow chart of the data analysis and processing process in an embodiment of an in-situ testing method for radiation effects of digital integrated circuits of the present invention.

[0042] The reference numerals are as follows:

[0043] 1-driving unit, 2-acquisition unit, 3-analysis unit, 4-SMU test module, 5-digital vector test module, 6-digital integrated circuit to be tested, 7-display unit. DETAILED DESCRIPTION

[0044] To make the objectives, technical solutions and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0045] Reference Figure 1 The present invention provides an in-situ testing system for radiation effects of digital integrated circuits, comprising a drive unit 1, a collection unit 2, an analysis unit 3, and a display unit 7. The digital integrated circuit 6 to be tested is located within a radiation field. The drive unit 1 and the collection unit 2 can be located either outside or within the radiation field. If both are located within the radiation field, the drive unit 1 and the collection unit 2 must be shielded by an anti-radiation shielding box.

[0046] The acquisition unit 2 includes an SMU test module 4 and at least one digital vector test module 5. The input end of the SMU test module 4 and the input end of each digital vector test module 5 are respectively connected to the drive unit 1. The SMU test module 4 and each digital vector test module 5 are respectively used to connect to the digital integrated circuit 6 to be tested. The SMU test module 4 includes at least one dual-channel SMU test board, or at least two single-channel SMU test boards, which are used to power the digital integrated circuit 6 to be tested and collect the power consumption current of the digital integrated circuit 6 to be tested. The digital vector test module 5 is used to input a test vector for the digital integrated circuit 6 to be tested and collect the level signal output by the digital integrated circuit 6 to be tested.

[0047] In this embodiment, the acquisition unit 2 uses a PXI board-based test chassis, which is equipped with an SMU test board and two digital vector test boards. The digital vector test module 5 is mounted on the digital vector test board. The digital vector test board provides electrical signal excitation to the input pins of the digital integrated circuit under test and receives output electrical signals from the output pins of the digital integrated circuit under test. Each digital vector test board has 32 digital channels, which means that the acquisition unit 2 can be used to collect data from the digital integrated circuit 6 under test with no more than 64 input and output pins. If the digital integrated circuit 6 under test has a large number of pins, it is possible to consider inserting more digital vector test boards.

[0048] Drive unit 1 uses a PXI-based controller board, installed in a test chassis, and connected to the display terminal screen via the controller's display cable. Alternatively, a laptop or desktop computer can be used as the test system controller, with Bluetooth or MXI cables used to control the test chassis from an external computer.

[0049] Analysis unit 3 is connected to the output of SMU test module 4 and the output of each digital vector test module 5, respectively, and is configured to receive information collected by SMU test module 4 and each digital vector test module 5 and process the received information. Display unit 7 is connected to analysis unit 3 and is configured to display the processing results output by analysis unit 3.

[0050] The driving unit 1, SMU test module 4, digital vector test module 5 and analysis unit 3 are all programmed using LabVIEW and Python programming languages, and the entire test system is controlled by software.

[0051] Reference Figure 2 The present invention also provides a method for in-situ testing of radiation effects of digital integrated circuits, comprising the following steps:

[0052] Step 1: Build the system

[0053] Build an in-situ test system for digital integrated circuit radiation effects and set the reference level V OL and V OH and placing the digital integrated circuit 6 to be tested in the radiation field.

[0054] Specifically, the digital integrated circuit (IC) under test (6) is clamped onto the base of a universal irradiation test PCB. This PCB features a universal design that allows testing and irradiation of digital ICs with up to 64 pins, in various packages, with varying power supply and ground pin sequences. The other side of the PCB features female connectors for VCC, GND, and VHDCI. These are connected to the SMU test module (4) and digital vector test module (5) outside the radiation field via shielded VHDCI cables and shielded BNC triaxial cables.

[0055] Step 2] Drive the acquisition unit

[0056] The drive unit 1 drives the SMU test module 4 and each digital vector test module 5, supplies power to the digital integrated circuit 6 under test, and inputs a fixed test vector. The corresponding level and timing are input to the input pins according to specific requirements.

[0057] Step 3: Collect functional data

[0058] After the driving instruction is input to the digital integrated circuit 6 to be tested, the digital vector test module 5 is used to specify an input sampling time for each output pin on the digital integrated circuit 6 to be tested, and the level signal output by the digital integrated circuit 6 to be tested within the input sampling time is received. The level signal is the functional data of the digital integrated circuit 6 to be tested.

[0059] In this step, the output signal level must be compared with the reference level V set in step 1. OLor V OH For comparison, since the test vector contains the expected logic state of each pin, if the expected state is logic 0, when sampling is performed, the signal level output by the digital integrated circuit 6 under test is less than the set reference level V OL , it means that the output logic function of the output pin of the digital integrated circuit to be tested is low level; if the expected value is logic 1, the output signal level is greater than the set reference level V OH , it means that the output logic function of the output pin of the digital integrated circuit under test is high level.

[0060] Step 4: Collect performance data

[0061] The digital vector test module 5 collects the DC current and voltage signals and AC time signals of the digital integrated circuit 6 to be tested, and obtains performance data of the digital integrated circuit 6 to be tested, the performance data including AC parameters and DC parameters.

[0062] AC parameter testing is based on functional testing. When measuring one or more functional or performance parameters as specified in the device manual, the input voltage levels and timings are used as a benchmark. If the test data setup time is used, it is set to the values ​​specified in the datasheet, the remaining parameters are relaxed, and the corresponding functional vector is run. If the functional test fails, the failure is due to the setup time. If the result passes, the next step is to relax the setup time parameter and test another AC parameter.

[0063] The DC parameter test mainly uses the PMU (Precision Measurement Unit) in the digital vector test board to accurately measure the DC parameters. The PMU can drive current into the digital integrated circuit 6 under test and measure the voltage, or measure the current generated after adding voltage to the digital integrated circuit 6 under test.

[0064] Step 5] Data analysis and processing

[0065] Reference Figure 3 Since in-situ online irradiation will generate a large amount of irradiation data during the irradiation period, it will be a huge problem to process and analyze the massive amount of data of more than Gb, find the radiation sensitive parameters from it, and reveal the correlation between the sensitive parameters. The data analysis and processing process of the present invention mainly adopts the principal component analysis algorithm. The principal component analysis transforms the electrical parameter data obtained from the experiment into a set of linearly independent matrices of each dimension through linear transformation, extracts the main characteristic components in the radiation effect test data, reduces the radiation effect data with multi-dimensional electrical parameters to two-dimensional or three-dimensional electrical parameter data, and expresses the variance ratio of the first principal component to the second principal component, thereby obtaining the top three radiation sensitive parameters most affected during the irradiation process. The processing process is divided into three parts, as follows:

[0066] 5.1 Data Preprocessing

[0067] In order to improve the accuracy of the principal component analysis of the experimental radiation effect data, the data needs to be preprocessed. In this embodiment, RobustScaler is used to convert the functional data collected in step 3] and the performance data collected in step 4] to medians and quartiles, respectively. The direct result of the conversion is to remove the outliers generated during the irradiation process, ensuring that the data is within a certain error range to establish a mathematical model.

[0068] 5.2 Data Dimensionality Reduction

[0069] During the irradiation test, it is necessary to monitor multiple electrical parameters of the digital integrated circuit 6 to be tested, and the number of electrical parameters may even reach more than 10. However, each parameter is not equally important to the radiation damage mechanism of the digital integrated circuit 6 to be tested. Therefore, it is necessary to select the parameter characteristics that have a decisive influence on the mechanism analysis.

[0070] Use the sklearn.decomposition.PCA class to reduce the dimensionality of the data after removing outliers, and use the n_components parameter in the sklearn.decomposition.PCA class to specify the number of feature dimensions of the data after dimensionality reduction, so as to facilitate the rapid extraction of key parameter features.

[0071] 5.3 Feature Extraction

[0072] Using principal component analysis to extract key parameter features is to use the data whitening function. Since the various performance parameters of radiation effects will have a certain correlation, the whitening function is to normalize each feature of the data after dimensionality reduction, set the variance to 1, reduce the correlation of performance parameters, and obtain the true radiation sensitive parameters, providing data guarantee for the subsequent radiation effect damage mechanism analysis.

[0073] The present invention uses data processing software to store each parameter collected online into a named Excel file. By setting a threshold for each parameter, if a parameter exceeds this threshold during irradiation, the parameter is determined to be radiation-sensitive. Using principal component analysis (PCA), a machine learning method, the ranking of each radiation-sensitive parameter in terms of radiation damage impact is mathematically analyzed, and the top three radiation-sensitive parameters with the greatest impact are selected.

[0074] Step 6] Obtain the boundary value of radiation damage

[0075] The Shmoo test method is used to test the top three radiation-sensitive parameters. During the test, the test board is again driven to obtain test results for the three radiation-sensitive parameters and the electrical parameters related to the three radiation-sensitive parameter tests. A two-dimensional or three-dimensional Shmoo test view is then established, and the interaction curve between the top three radiation-sensitive parameters is obtained. Ultimately, the radiation damage boundary value of the radiation-sensitive parameters of the digital integrated circuit 6 under test during the irradiation period is obtained, thereby completing the in-situ radiation effect test of the digital integrated circuit 6. In this embodiment, the radiation damage boundary value refers to the failure value of the sensitive parameter at a certain dose point and the failure value of the electrical parameter related to the sensitive parameter test. This boundary value can be used in the next step of analyzing the radiation damage mechanism of the digital device.

[0076] This method combines hardware and software to test the performance parameters of digital integrated circuits during irradiation. It uses a machine learning library function to determine radiation-sensitive parameters and proposes a ranking of their impact on radiation damage. This data processing method can be incorporated into standard radiation effects methods to ensure the scientific and conservative nature of radiation effects testing. Furthermore, the method can quantitatively determine the impact of each radiation-sensitive parameter on radiation damage in digital integrated circuits, enabling comprehensive testing of their performance and functionality.

[0077] The technical solution of the present invention enables comprehensive monitoring of various performance parameters of digital integrated circuits, facilitating the localization of single-event effects (SEEs) in digital integrated circuits and their corresponding radiation hardening. It also plays a positive role in the development of SEE testing methods and standards for digital integrated circuits. Furthermore, the testing method based on the present invention enables more comprehensive performance parameter testing during online testing of digital integrated circuit total ionizing dose and displacement effects, providing a better foundation for the updating and development of testing methods for these two effects.

Claims

1. An in-situ testing system for radiation effects of digital integrated circuits, characterized by: It comprises a driving unit (1), an acquisition unit (2) and an analysis unit (3); the acquisition unit (2) comprises an SMU test module (4) and at least one digital vector test module (5); The input end of the SMU test module (4) and the input end of each digital vector test module (5) are respectively connected to the drive unit (1); The SMU test module (4) and each digital vector test module (5) are respectively used to connect to a digital integrated circuit (6) to be tested, and the digital integrated circuit (6) to be tested is located in the radiation field; The SMU test module (4) is used to supply power to the digital integrated circuit (6) to be tested and to collect the power consumption current of the digital integrated circuit (6) to be tested; the digital vector test module (5) is used to input a test vector to the digital integrated circuit (6) to be tested and to collect the level signal output by the digital integrated circuit (6) to be tested; The analysis unit (3) is respectively connected to the output end of the SMU test module (4) and the output end of each digital vector test module (5), and is used to receive information collected by the SMU test module (4) and each digital vector test module (5), and process the information.

2. The digital integrated circuit radiation effect in-situ testing system according to claim 1, characterized in that: It also includes a display unit (7), which is connected to the analysis unit (3) and is used to display the processing results output by the analysis unit (3).

3. The digital integrated circuit radiation effect in-situ testing system according to claim 2, characterized in that: The driving unit (1) and the collecting unit (2) are both located outside the radiation field.

4. The digital integrated circuit radiation effect in-situ testing system according to claim 2, characterized in that: The driving unit (1) and the collecting unit (2) are both located in the radiation field and are shielded by an anti-radiation shielding box.

5. The digital integrated circuit radiation effect in-situ testing system according to claim 3 or 4, characterized in that: The SMU test module (4) includes at least one dual-channel SMU test board, or at least two single-channel SMU test boards.

6. The digital integrated circuit radiation effect in-situ testing system according to claim 5, characterized in that: The driving unit (1), SMU test module (4), digital vector test module (5) and analysis unit (3) are all programmed using LabVIEW and Python programming languages.

7. A method for in-situ testing of radiation effects of digital integrated circuits, characterized in that: The following steps are involved: Step 1: Build the system Build the digital integrated circuit radiation effect in-situ test system according to any one of claims 1-6, set the reference level V OL and V OH and placing the digital integrated circuit (6) to be tested in the radiation field; Step 2] Drive the acquisition unit The SMU test module (4) and each digital vector test module (5) are driven respectively by the driving unit (1), power is supplied to the digital integrated circuit (6) to be tested, and a fixed test vector is input; Step 3: Collect functional data Using a digital vector test module (5) to specify an input sampling time for each output pin on the digital integrated circuit (6) to be tested, and receiving a level signal output by the digital integrated circuit (6) to be tested within the input sampling time, wherein the level signal is functional data of the digital integrated circuit (6) to be tested; Step 4: Collect performance data collecting performance data of a digital integrated circuit (6) to be tested through a digital vector test module (5), wherein the performance data includes AC parameters and DC parameters; Step 5] Data analysis and processing Processing the data collected in step 3] and step 4] to obtain radiation sensitivity parameters of the digital integrated circuit (6) to be tested, and selecting the top three radiation sensitivity parameters; Step 6] Obtain the boundary value of radiation damage The top three radiation sensitive parameters are tested using the shmoo test method to obtain the radiation damage boundary value of the digital integrated circuit (6) to be tested, thereby completing the in-situ test of the radiation effect of the digital integrated circuit (6); the radiation damage boundary value refers to the failure value of the sensitive parameter at a certain dose point, as well as the failure value of the electrical parameter related to the sensitive parameter test.

8. The in-situ testing method for radiation effects of digital integrated circuits according to claim 7, characterized in that: Step 5 is as follows: 5.1] Use RobustScaler to transform the functional data collected in step 3] and the performance data collected in step 4], and remove outliers; 5.2] Use the sklearn.decomposition.PCA class to reduce the dimensionality of the data after removing outliers, and use the n_components parameter in the sklearn.decomposition.PCA class to specify the number of feature dimensions of the data after dimensionality reduction; 5.3] The data after dimensionality reduction is normalized and the variance is set to 1 to obtain the true radiation sensitivity parameters.

9. The in-situ testing method for radiation effects of digital integrated circuits according to claim 8, characterized in that: In step 3, compare the output signal level with the reference level V set in step 1. OL or V OH If the output signal level is less than the set reference level V OL It means that the output logic function of the output pin of the digital integrated circuit to be tested is low level. If the output signal level is greater than the set reference level V OH It means that the output logic function of the output pin of the digital integrated circuit under test is high level.

10. The in-situ testing method for radiation effects of digital integrated circuits according to claim 9, characterized in that: Step 6] Specifically: Two-dimensional or three-dimensional shmoo test views are established for the top three sensitive parameters among the radiation sensitive parameters and the electrical parameters related to their tests, and then the mutual influence curves between the top three sensitive parameters are obtained, and finally the radiation damage boundary values ​​of the radiation sensitive parameters of the digital integrated circuit (6) to be tested during the irradiation period are obtained.

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