Display panel and display device

Abstract

The present invention discloses a display panel and a display device, wherein the display panel comprises: an array substrate and a color film substrate and a sealing glue which are arranged opposite to each other, wherein the color film substrate comprises a common electrode layer, the array substrate comprises a first base substrate and a common electrode pin, and the common electrode pin is located on a side of the first base substrate close to the color film substrate; an insulating layer, which is located on a side of the common electrode pin close to the color film substrate, the insulating layer has a first via hole which exposes the common electrode pin, and the first via hole is located in the orthographic projection of the first base substrate by the sealing glue; a first liner, which is located in the first via hole; a first conductive layer, which at least partially covers the insulating layer and the first liner, and the first conductive layer is connected to the exposed common electrode pin in the first via hole; a first protective layer, which at least partially covers the first conductive layer and is disconnected at the first liner, and the common electrode layer is electrically connected to the first conductive layer exposed on the surface of the first liner through the sealing glue.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] In a high temperature and high humidity environment during reliability testing of existing liquid crystal display panels, water vapor easily enters the box of the liquid crystal display panel through the edge of the frame sealant, thereby causing corrosion of the via holes near the frame sealant.

[0003] In order to prevent via corrosion, polyimide (PI) is usually required to cover the via near the frame sealant to strengthen the via protection. However, due to the close relative position of the via and the frame sealant, coupled with the problem of PI coating accuracy, PI is easy to diffuse to the frame sealant position, thereby covering the common electrode line of the array substrate at the frame sealant position. In addition, due to the large resistance of PI, the conductivity of the gold ball located in the frame sealant connecting the common electrode line of the array substrate and the common electrode on the color filter substrate side will be affected, resulting in poor uniformity of the common electrode signal, and prone to problems such as abnormal screen flickering. Summary of the invention

[0004] The embodiments of the present invention provide a display panel and a display device to solve the above technical problems in the prior art.

[0005] In a first aspect, in order to solve the above technical problems, an embodiment of the present invention provides a display panel, comprising an array substrate and a color filter substrate arranged opposite to each other, and a frame sealant arranged between the array substrate and the color filter substrate, wherein the color filter substrate comprises a common electrode layer arranged near one side of the array substrate, and the array substrate comprises:

[0006] A first base substrate and a common electrode pin, wherein the common electrode pin is located on a side of the first base substrate close to the color filter substrate;

[0007] an insulating layer, located on a side of the common electrode pin close to the color filter substrate, the insulating layer having a first via hole exposing the common electrode pin, and the first via hole is located within the orthographic projection of the frame sealant on the first base substrate;

[0008] A first liner, located in the first via hole;

[0009] a first conductive layer, at least partially covering the insulating layer and the first liner, the first conductive layer being connected to the exposed common electrode pin in the first via hole;

[0010] The first protection layer at least partially covers the first conductive layer and is disconnected at the first liner. The common electrode layer is electrically connected to the first conductive layer exposed on the surface of the first liner through the frame sealing glue.

[0011] In a possible implementation manner, the color filter substrate further includes:

[0012] a second substrate base plate;

[0013] A black matrix is ​​located on a side of the second base substrate close to the array substrate; and the common electrode layer is located on a side of the black matrix close to the array substrate.

[0014] A second spacer is located between the second base substrate and the common electrode layer, and overlaps with an orthographic projection of the first spacer on the second base substrate;

[0015] The second protective layer covers the common electrode layer and is disconnected at the second liner, so that the frame sealant is electrically connected to the common electrode layer exposed on the surface of the second liner.

[0016] In a possible implementation manner, the thickness of the second liner is greater than the sum of the thicknesses of the common electrode layer and the second protective layer.

[0017] In a possible implementation manner, the color filter substrate further includes a color resist layer located between the second base substrate and the common electrode layer;

[0018] The second spacer is arranged on the same layer as the color resist layer.

[0019] In a possible implementation manner, the material of the second spacer is the same as the material of the color resist corresponding to any color in the color resist layer.

[0020] In a possible implementation manner, the longitudinal section of the second cushion material includes a rectangle or a trapezoid.

[0021] In a possible implementation manner, the first protective layer and the second protective layer are alignment layers.

[0022] In a possible implementation manner, the first liner and the insulating layer are provided in the same layer and with the same material.

[0023] In a possible implementation manner, the longitudinal section of the first cushion material includes a rectangle or a trapezoid.

[0024] The height of the first spacer is greater than or equal to the height of the insulating layer.

[0025] In a possible implementation manner, the first protection layer partially overlaps with the first via hole and does not overlap with a top surface of the first spacer.

[0026] In a possible implementation, the display panel includes a display area and a peripheral non-display area, the frame sealing glue is arranged in the peripheral non-display area, the peripheral non-display area also includes a circuit area, the circuit area includes a transfer hole structure, the first conductive layer and the first protective layer sequentially cover the transfer hole structure, and the gate signal line is switched to the source and drain layer through the first conductive layer and the transfer hole structure.

[0027] In a second aspect, an embodiment of the present invention provides a display device, comprising the display panel as described in the first aspect.

[0028] The beneficial effects of the present invention are as follows:

[0029] In the embodiment provided by the present invention, the display panel includes an array substrate and a color filter substrate arranged opposite to each other, and a frame sealant arranged between the array substrate and the color filter substrate, the color filter substrate includes a common electrode layer arranged near one side of the array substrate, and the array substrate includes: a first base substrate and a common electrode pin, the common electrode pin is located on the side of the first base substrate near the color filter substrate; an insulating layer, located on the side of the common electrode pin near the color filter substrate, the insulating layer has a first via hole exposing the common electrode pin, and the first via hole is located in the orthographic projection of the first base substrate by the frame sealant; a first gasket, located in the first via hole; a first conductive layer, at least partially covering the insulating layer and the first gasket, the first conductive layer is connected to the exposed common electrode pin in the first via hole; a first protective layer, at least partially covering the first conductive layer and disconnected at the first gasket, the common electrode layer is electrically connected to the first conductive layer exposed on the surface of the first gasket through the frame sealant. In the above scheme, since a first spacer with a height greater than or equal to the height of the insulating layer is arranged in the first via hole, when the first protective layer is coated on the first conductive layer except for the area corresponding to the first via hole, the first protective layer can be disconnected at the first spacer, so that the first conductive layer located on the surface of the first spacer can be exposed to the frame sealing glue. Therefore, the first protective layer can protect the area outside the area corresponding to the frame sealing glue in the array substrate from the intrusion of water vapor, and the common electrode pin can be well conductive with the common electrode layer through the frame sealing glue, thereby preventing the problem of abnormal screen flickering and improving the display effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 It is a structural schematic diagram of a display panel in the related art;

[0031] Figure 2 is a schematic diagram of the structure of another display panel;

[0032] Figure 3 A schematic diagram of the structure of a display panel provided by an embodiment of the present invention;

[0033] Figure 4A schematic diagram of the structure of a display panel provided by an embodiment of the present invention;

[0034] Figure 5 A schematic diagram of the structure of a display panel provided by an embodiment of the present invention;

[0035] Figure 6 A top view of a display panel provided by an embodiment of the present invention;

[0036] Figure 7 A schematic structural diagram of another display panel provided by an embodiment of the present invention.

[0037] Reference numerals:

[0038] Related technologies:

[0039] Array substrate 1', color filter substrate 2', frame sealant 3, first base substrate 11', gate layer 12', common electrode pin 121', first signal pin 122', gate insulation layer 13', source and drain electrode layer 14', second signal pin 141', planar layer 15', first electrode layer 16', first alignment layer 17', transfer hole structure H';

[0040] A second base substrate 21', a black matrix 22', a second conductive layer 23', and a second alignment layer 24';

[0041] Sealing glue 3, matrix layer 31, conductive balls 32;

[0042] The present invention:

[0043] An array substrate 1, a first base substrate 11, a common electrode pin 12, an insulating layer 13, a first via hole H, a first liner 14, a first conductive layer 15, a first protective layer 16, a gate insulating layer 131, and a planar layer 132;

[0044] The second base substrate 20 , the common electrode layer 21 , the black matrix 22 , the second liner 23 , and the second protection layer 24 . DETAILED DESCRIPTION

[0045] The embodiments of the present invention provide a display panel and a display device to solve the above technical problems in the prior art.

[0046] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and understandable, the present invention will be further described below with reference to the accompanying drawings and examples. However, the exemplary embodiments can be implemented in various forms and should not be understood as being limited to the embodiments described herein; on the contrary, these embodiments are provided to make the present invention more comprehensive and complete, and to fully convey the concepts of the exemplary embodiments to those skilled in the art. The same figure marks in the figures represent the same or similar structures, and thus their repeated descriptions will be omitted. The words expressing position and direction described in the present invention are all explained using the accompanying drawings as examples, but changes can be made as needed, and the changes made are all included in the scope of protection of the present invention. The drawings of the present invention are only used to illustrate the relative position relationship and do not represent the true proportions.

[0047] It should be noted that specific details are described in the following description to facilitate a full understanding of the present invention. However, the present invention can be implemented in a variety of other ways different from those described herein, and those skilled in the art can make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below. The subsequent description of the specification is a preferred embodiment of the present application, but the description is for the purpose of illustrating the general principles of the present application and is not intended to limit the scope of the present application. The scope of protection of the present application shall be determined by the definition of the attached claims.

[0048] It should be understood that in the description of the embodiments of the present invention, the words "first", "second", etc. are only used for the purpose of distinguishing the description, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying an order. In the description of the embodiments of the present invention, "plurality" refers to two or more.

[0049] The term "and / or" in the embodiments of the present invention is only a description of the association relationship of the associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0050] See also Figure 1 The figure is a schematic diagram of the structure of a display panel in the related art.

[0051] The display panel comprises an array substrate 1 ′ and a color filter substrate 2 which are arranged opposite to each other, and a frame sealant 3 which is arranged between the array substrate 1 ′ and the color filter substrate 2 .

[0052] The array substrate 1' comprises: a first base substrate 11', a gate layer 12' located on one side of the first base substrate 11', the gate layer 12' comprising a common electrode pin 121' and a first signal pin 122' located in a non-display area, a gate insulating layer 13' located on a side of the gate layer 12' away from the first base substrate 11', a source-drain electrode layer 14' located on a side of the gate insulating layer 13' away from the first base substrate 11', the source-drain electrode layer 14' comprising a second signal pin 141' located in the non-display area, a planar layer 15' located on a side of the source-drain electrode layer 14' away from the first base substrate 11', a first electrode layer 16' located on a side of the planar layer 15' away from the first base substrate 11', and a first alignment layer 17' located on a side of the first electrode layer 16' away from the first base substrate 11'. The first signal pin 122' and the second signal pin 141' are located in the area between the frame sealant 3 and the display area, the first alignment layer 17' extends from the display area to the edge of the non-display area, and the transfer hole structure H' corresponding to the first signal pin 122' and the second signal pin 141' has no overlap.

[0053] The color filter substrate 2' includes: a second base substrate 21', a black matrix 22' located on the side of the second base substrate 21' facing the array substrate 1', a second conductive layer 23 located on the side of the black matrix 22' facing the array substrate 1', and a second alignment layer 24' located on the side of the second conductive layer 23 facing the array substrate 1'. The second alignment layer 24' extends from the display area to the edge of the non-display area and has no overlap with the transfer hole structure H' corresponding to the first signal pin 122' and the second signal pin 141'.

[0054] like Figure 1 As shown, in the area where the sealant 3 is projected onto the array substrate 1', there is a common electrode pin 121'. The sealant 3 includes a matrix layer 31 and a conductive structure 32 located in the matrix layer 31. The common electrode pin 121' is electrically connected to the second electrode layer in the color filter substrate 2 through the portion at the corresponding position of the first conductive layer and the conductive structure 32.

[0055] When the reliability test of the display panel is carried out in a high temperature and high humidity environment, water vapor easily enters the interior of the display panel through the edge of the frame sealant 3, thereby causing corrosion of the via holes near the frame sealant 3. Although in the prior art, the alignment layer in the display area is extended to the non-display area on the electrode layer surfaces corresponding to the array substrate 1' and the color film substrate 2' to protect part of the area, the transfer hole structure H' near the frame sealant 3 is not coated with the alignment layer because it is close to the frame sealant 3, which makes it easy for water vapor to corrode this part of the transfer hole structure H', resulting in poor display effect of the display panel.

[0056] If the alignment layer is coated on the transfer hole structure H' close to the sealant 3, the sealant 3 will easily diffuse into the via hole corresponding to the common electrode pin 121' due to its fluidity during coating, covering the first electrode layer 16' therein (such as Figure 2 As shown in the figure, which is a structural schematic diagram of another display panel), this will affect the conductivity of the gold ball located in the frame sealant 3 connecting the common electrode line of the array substrate 1' and the common electrode on the color filter substrate 2 side, resulting in poor uniformity of the common electrode signal and prone to problems such as abnormal screen flickering.

[0057] In order to solve the above problems, embodiments of the present invention provide a display panel and a display device, which are described in detail below with reference to the accompanying drawings.

[0058] See also Figure 3 A schematic diagram of the structure of a display panel provided by an embodiment of the present invention. The display panel includes an array substrate 1 and a color filter substrate arranged opposite to each other, a sealant 3 arranged between the array substrate 1 and the color filter substrate (the sealant 3 is arranged in the peripheral non-display area of ​​the display panel, which can be a closed circle), and the color filter substrate includes a common electrode layer 21 arranged near one side of the array substrate 1 ( Figure 3 Only the common electrode layer 21 is shown, and the structure of the color filter substrate is similar to Figure 1 The structure of the color film substrate is the same as that of the color film substrate, which will not be repeated here. The array substrate 1 includes:

[0059] A first base substrate 11 and a common electrode pin 12, wherein the common electrode pin 12 is located on a side of the first base substrate 11 close to the color filter substrate; optionally, the common electrode pin 12 is used to achieve electrical connection with a capacitor plate for transmitting a common signal for transmitting a common electrical signal.

[0060] The insulating layer 13 is located on a side of the common electrode pin 12 close to the color filter substrate. The insulating layer 13 has a first via H exposing the common electrode pin, and the first via H is located in the orthographic projection of the sealant 3 on the first base substrate 11. The insulating layer 13 includes a gate insulating layer 131 and a planar layer 132.

[0061] Optionally, the height of the first liner 14 may be equal to the height of the gate insulating layer 131, and the first liner 14 may be made of the same material as the gate insulating layer 131; Figure 3 FIG. 1 is a schematic diagram showing the structure of another display panel provided by an embodiment of the present invention;

[0062] Optionally, the height of the first liner 14 may be equal to the height of the flat layer 132, and the first liner 14 may be made of the same material as the flat layer 132; Figure 4 FIG. 1 is a schematic diagram showing the structure of another display panel provided by an embodiment of the present invention;

[0063] Optionally, the first liner 14 is located in the first via hole H, and the height of the first liner 14 is greater than or equal to the height of the insulating layer 13, that is, greater than or equal to the height of the gate insulating layer 131 plus the planar layer 132 (eg, Figure 3 As shown), the first liner and the insulating layer 13 are made of the same material;

[0064] Of course, you can also Figure 4 , Figure 5 As shown, the height of the first spacer 14 is greater than the height of the gate insulating layer 131 , the planar layer 132 , or the sum of the two. The gate insulating layer 131 and / or the planar layer 132 with different heights are prepared by using a half-tone mask.

[0065] A first conductive layer 15 at least partially covers the insulating layer 13 and the first liner 14, and the first conductive layer 15 is connected to the exposed common electrode pin 12 in the first via hole H;

[0066] The first protection layer 16 at least partially covers the first conductive layer 15 and is disconnected at the first liner 14 . The common electrode layer 21 is electrically connected to the first conductive layer 15 exposed on the surface of the first liner 14 through the sealant 3 .

[0067] Optionally, the first protection layer 16 partially overlaps with the first via hole H, and does not overlap with the top surface of the first liner 14. Figure 3 The first protection layer 16 does not overlap with the first liner 14 in the first via hole H.

[0068] The sealant 3 includes a matrix layer 31 and a conductive structure 32 in the matrix layer 31. The conductive structure 32 can electrically connect the common electrode layer 21 to the first conductive layer 15 exposed on the surface of the first liner 14. Optionally, the conductive structure 32 can be a conductive gold ball structure.

[0069] In the embodiment provided by the present invention, a first liner 14 having a height greater than or equal to that of the insulating layer 13 is provided in the first via hole H, so that when the first protective layer 16 is coated on the first conductive layer 15 except for the area corresponding to the first via hole H, the first protective layer 16 can be disconnected at the first liner 14, so that the first conductive layer 15 located on the surface of the first liner 14 can be exposed to the sealing glue 3, so that the first protective layer 16 can protect the area outside the area corresponding to the sealing glue 3 in the array substrate 1 from water vapor intrusion, and the common electrode pin 12 can be well conductively connected to the common electrode layer 21 through the sealing glue 3, thereby preventing the problem of abnormal screen flickering and improving the display effect.

[0070] In some embodiments, the first liner 14 is provided in the same layer and the same material as the insulating layer 13. In this way, the first liner 14 can be formed without adding additional processes or materials, thereby effectively improving production efficiency and facilitating material management.

[0071] In other embodiments, the longitudinal section of the first cushion 14 includes a rectangle or a trapezoid, so that the first cushion 14 is formed during manufacturing.

[0072] See also Figure 6 A top view of a display panel provided by an embodiment of the present invention. The display panel includes a display area AA and a peripheral non-display area BB, a frame sealant 3 is disposed in the peripheral non-display area BB, the peripheral non-display area BB also includes a circuit area CC, the circuit area CC includes a transfer hole structure H', a first conductive layer 15 and a first protective layer 16 sequentially cover the transfer hole structure H', and the gate signal line is switched to the source and drain layer through the first conductive layer 15 and the transfer hole structure 16.

[0073] Please continue to see Figure 3 The array substrate 1 also includes a first signal pin 122' and a second signal pin 141', and a transfer hole structure H' corresponding to the first signal pin 122' and the second signal pin 141' respectively. The first protective layer 16 covers the transfer hole H', thereby preventing water vapor from corroding the transfer hole structure H' and improving the display effect of the display panel.

[0074] Optionally, the transfer hole structure H' can be a via hole arranged in the circuit area CC in the peripheral non-display area BB, for example, it can be a via hole in the gate drive circuit, and this via hole is used to switch the gate signal line layer to the source and drain layer, and the gate signal line layer and the source and drain layer are electrically connected through the via hole and the first conductive layer 15. At this time, the first protective layer 16 covers at least a portion of the first electrode layer in the frame sealant 3 extending from the transfer hole structure H', but does not overlap with the top of the first liner 14, which can not only protect the transfer hole structure H' in the peripheral non-display area BB from water vapor erosion, etc., but also ensure that the conductive structure 32 in the frame sealant 3 can be electrically connected to the common electrode pin 12 on one side of the array substrate 1.

[0075] In some embodiments, the first signal pin 122' can be arranged in the same layer as the common electrode pin 12, such as both arranged in the gate layer 12', and the common electrode pin 12 can also be arranged in the same layer as the second signal pin 141', such as both arranged in the source and drain layer 14'. The first signal pin 122' and the second signal pin 141' can carry clock signals.

[0076] See also Figure 7 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention. The color filter substrate of the display panel also includes:

[0077] A second substrate 20;

[0078] The black matrix 22 is located on a side of the second base substrate 20 close to the array substrate 1; the common electrode layer 21 is located on a side of the second liner 23 close to the array substrate 1;

[0079] The second spacer 23 is located between the second base substrate 20 and the common electrode layer 21 and overlaps with the orthographic projection of the first spacer 14 on the second base substrate 20;

[0080] The second protection layer 24 covers the common electrode layer 21 and is disconnected at the second liner 23 , so that the sealant 3 is electrically connected to the common electrode layer 21 exposed on the surface of the second liner 23 .

[0081] In the embodiment provided by the present invention, a second protective layer 24 is provided on the surface of the common electrode layer 21, and the second protective layer 24 is disconnected at the second pad 23, so that the second protective layer 24 can be used to protect the area of ​​the common electrode layer 21 except the second pad 23, thereby preventing water vapor from invading and corroding the common electrode layer 21, thereby improving the display effect of the display surface.

[0082] In some embodiments, the material used for the first protective layer 16 and the second protective layer 24 is polyamide.

[0083] In other embodiments, the material used for the first conductive layer 15 and the common electrode layer 21 may be indium tin oxide (ITO). Optionally, the display area of ​​the display panel includes gate lines and data lines, and the gate lines and data lines intersect to define pixel units. The pixel units include switching transistors and pixel electrodes. The display area AA also includes a common electrode. The first conductive layer 15 may be in the same layer and material as the pixel electrode or the common electrode of the display area AA.

[0084] Please continue to see Figure 7 , the thickness h3 of the second liner 23 is greater than the sum of the thicknesses of the common electrode layer 21 and the second protective layer 24 (h4+h5).

[0085] In the embodiment provided by the present invention, by setting the thickness h3 of the second spacer 23 to be greater than the sum of the thicknesses of the common electrode layer 21 and the second protective layer 24 (h4+h5), the second protective layer 24 can be effectively disconnected at the second spacer.

[0086] In some embodiments, the color filter substrate further includes a color resist layer located between the second base substrate 20 and the common electrode layer 21;

[0087] The second spacer 23 is disposed on the same layer as the color resist layer.

[0088] The color resist layer includes red color resist, green color resist and blue color resist, and the material used by the second spacer 23 can be the same as the color resist of any color.

[0089] In the embodiment provided by the present invention, by arranging the second spacer 23 and the color resist layer in the same layer, the second spacer 23 can be formed without adding any process, thereby effectively improving production efficiency. The material used for the second spacer 23 is set to be the same as the material of the color resist corresponding to any color in the color resist layer, so that no additional material is added, which is convenient for production management.

[0090] In some embodiments, the longitudinal section of the second liner 23 may be rectangular or trapezoidal, which facilitates the manufacture of the second liner 23 .

[0091] In some embodiments, the display panel further includes a liquid crystal layer, and the liquid crystal layer is located between the array substrate and the color film substrate.

[0092] In some embodiments, the specific type of the display panel is not limited, for example, it can be a TN (Twisted Nematic) mode display panel, a VA (Vertical Alignment) mode display panel, an IPS (In-Plane-Switching) or ADS (ADvanced Super Dimension Switch) mode display panel, and the like.

[0093] Based on the same inventive concept, an embodiment of the present invention provides a display device, which includes the display panel as described above.

[0094] The display device may be a display device such as a liquid crystal display, a liquid crystal display screen, a liquid crystal television, or may be a mobile device such as a mobile phone, a tablet computer, a notebook, or the like.

[0095] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0096] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A display panel, comprising an array substrate and a color filter substrate arranged opposite to each other, and a frame sealant arranged between the array substrate and the color filter substrate, wherein the color filter substrate comprises a common electrode layer arranged near one side of the array substrate, characterized in that: The array substrate comprises: A first base substrate and a common electrode pin, wherein the common electrode pin is located on a side of the first base substrate close to the color filter substrate; an insulating layer, located on a side of the common electrode pin close to the color filter substrate, the insulating layer having a first via hole exposing the common electrode pin, and the first via hole is located within the orthographic projection of the frame sealant on the first base substrate; A first liner, located in the first via hole; a first conductive layer, at least partially covering the insulating layer and the first liner, the first conductive layer being connected to the exposed common electrode pin in the first via hole; a first protective layer, at least partially covering the first conductive layer and being disconnected at the first liner, wherein the common electrode layer is electrically connected to the first conductive layer exposed on the surface of the first liner through the frame sealing glue; The color film substrate further includes: a second substrate base plate; A black matrix is ​​located on a side of the second base substrate close to the array substrate; and the common electrode layer is located on a side of the black matrix close to the array substrate. A second spacer is located between the second base substrate and the common electrode layer, and overlaps with an orthographic projection of the first spacer on the second base substrate; The second protective layer covers the common electrode layer and is disconnected at the second liner, so that the frame sealant is electrically connected to the common electrode layer exposed on the surface of the second liner; wherein the first protective layer and the second protective layer are alignment layers.

2. The display panel according to claim 1, wherein: The thickness of the second liner is greater than the sum of the thicknesses of the common electrode layer and the second protection layer.

3. The display panel according to claim 2, wherein: The color filter substrate further includes a color resist layer located between the second base substrate and the common electrode layer; The second spacer is arranged on the same layer as the color resist layer.

4. The display panel according to claim 3, wherein: The material of the second spacer is the same as the material of the color resist corresponding to any color in the color resist layer.

5. The display panel according to claim 1, wherein: The longitudinal section of the second cushion material may have a rectangular or trapezoidal shape.

6. The display panel according to any one of claims 1 to 5, characterized in that: The first liner and the insulating layer are provided in the same layer and with the same material.

7. The display panel according to any one of claims 1 to 5, characterized in that: The longitudinal section of the first cushion material may have a rectangular or trapezoidal shape.

8. The display panel according to any one of claims 1 to 5, characterized in that: The height of the first spacer is greater than or equal to the height of the insulating layer.

9. The display panel according to any one of claims 1 to 5, characterized in that: The first protection layer partially overlaps with the first via hole and does not overlap with a top surface of the first spacer.

10. The display panel according to any one of claims 1 to 5, characterized in that: The display panel includes a display area and a peripheral non-display area, the frame sealing glue is arranged in the peripheral non-display area, the peripheral non-display area also includes a circuit area, the circuit area includes a transfer hole structure, the first conductive layer and the first protective layer sequentially cover the transfer hole structure, and the gate signal line is switched to the source and drain layer through the first conductive layer and the transfer hole structure.

11. A display device, characterized in that: Comprising the display panel as described in any one of claims 1-10.

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