A fast-locking wide-range high-precision digital time converter

Abstract

The application discloses a high-precision digital time converter with wide adjustable range and fast locking, which comprises a coarse delay unit, a fine delay unit, a time-to-digital converter, a lookup table module and a delay control circuit; the coarse delay unit is used for generating a coarse delay signal according to a reference clock, and the signal is connected to the fine delay unit for further fine delay; the fine delay unit is used for further delaying the coarse delay signal and outputting a fine delay signal, which is respectively connected to a signal input port of the time-to-digital converter and a system output IO. The application can be used for generating a high-precision phase adjustable excitation signal in an ATE device, and can also be used for other suitable high-precision digital time conversion applications.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of digital integrated circuit design, and particularly relates to a wide adjustable range high-precision digital time converter with fast locking. BACKGROUND

[0002] A digital time converter (DTC) is a device for converting digital signals into time signals, which can generate a frequency offset or phase offset signal from a fixed reference frequency signal and is applied to the technical fields of automatic test equipment (ATE), phase-locked loop, and synchronous application system.

[0003] Commonly used digital time converters often have difficulty in simultaneously achieving the characteristics of fast locking, wide adjustable range, and high precision. For example, a digital time converter using a multi-phase reference clock can achieve fast locking and a very wide delay adjustment range, but since the reference clock frequency is difficult to be raised to a very high level, and its precision is limited by the time difference between the reference clock phases, the quantized time interval often reaches several hundred picoseconds or even higher, which cannot achieve the characteristic of high precision. A digital time converter using a multi-cycle clock phase difference based on the principle of vernier method can achieve good delay precision, but the drawback is that the reaction time is sacrificed, that is, it often needs many clock cycles to output a delay signal, and the width of the delay signal is difficult to adjust.

[0004] In the field of automatic test equipment (ATE) applications, a high-precision adjustable phase excitation signal is often required, and this function can be achieved by constructing a digital time converter. The converter generally requires short and stable locking time, an adjustment range of at least one system clock, and a quantized time interval of at least 50 ps. SUMMARY

[0005] Therefore, the purpose of the present application is to provide a wide adjustable range high-precision digital time converter with fast locking, which can be used for ATE devices to generate high-precision phase adjustable excitation signals, and can also be used for other suitable high-precision digital time conversion applications.

[0006] A wide adjustable range high-precision digital time converter with fast locking comprises a coarse delay timer, a fine delay timer, a time-to-digital converter, a lookup table module, and a delay control circuit.

[0007] The coarse delay timer is used to generate a coarse delay signal according to a reference clock, which is input into the fine delay timer for further fine delay.

[0008] The fine delay timer is used to further delay the coarse delay signal and output a fine delay signal, which is respectively input into the input port of the time-to-digital converter and the system output IO.

[0009] The time-to-digital converter is used for measuring the time difference between the fine delay signal and the start delay enable signal.

[0010] The look-up table module is used for calculating the corresponding delay value of each tap output of the measured fine delay and storing it in the storage according to the size. When the delay is performed, the delay control circuit queries the tap corresponding to the fine delay value from the look-up table module.

[0011] The delay control circuit is used for calculating the control word sent by the upper computer or other modules except the digital time converter as a coarse and fine control word and inputting it to the coarse delay and look-up table module. The delay control circuit also accepts the fine delay tap corresponding to the fine control word returned from the look-up table and inputs it to the fine delay.

[0012] The coarse delay is counted according to the system clock period, and the coarse delay signal is released when the value corresponding to the coarse delay control signal is reached.

[0013] The fine delay uses a tap delay chain structure, and the delay path is composed of a delay chain formed by cascading delay units and a selector array for selecting the output tap. The tap delay chain uses a delay unit cascade chain or a delay unit cascade chain using double-chain interpolation. Any selected tap output in the tap delay chain has a corresponding unique delay time, and different delay times are arranged to quantize the system clock into a time interval of at least 50ps.

[0014] In the calibration state, each tap is traversed as an output and its corresponding delay time is measured. In the delay state, the tap value input by the delay control circuit is accepted, and the tap corresponding to the tap value is selected as the fine delay signal output.

[0015] The time-to-digital converter has a measurement accuracy greater than the delay accuracy of the high-precision digital time converter.

[0016] The look-up table module saves the measurement results of the time-to-digital converter in the calibration state and calculates the average delay difference of each tap output. Based on this, the tap value corresponding to the input fine control word is output in the delay state.

[0017] The high-precision digital time conversion includes the following steps:

[0018] Step 1, build the circuit of the high-precision digital time converter;

[0019] Step 2, the system is powered on or the calibration button is triggered to enter the calibration state.

[0020] Step 3, the same tap is selected to repeat the output of the fine delay signal with the same delay difference, and the number of repetitions is any suitable value that can measure a more accurate delay difference corresponding to the tap, and the measured delay difference is saved to the RAM each time;

[0021] Step 4, change the output tap, repeat step 2 until all taps are traversed;

[0022] Step 5, calculate the delay difference corresponding to each tap and establish a lookup table of delay time corresponding taps;

[0023] Step 6, enter the delay state, calculate and output the coarse delay value and the fine delay value according to the control word input by the upper computer or other modules except the digital time converter, input the fine delay value into the lookup table module to obtain the returned tap value, and set the output tap of the fine delay device to the value.

[0024] The application has the beneficial effect that the application proposes a fast locking wide adjustable range high precision digital time converter applied to automatic test equipment in the application field of automatic test equipment (ATE) which needs to output high precision adjustable phase excitation signal function, which can also be applied to other suitable scenarios.

[0025] Commonly used digital time converters often have difficulty in simultaneously considering the characteristics of fast locking, wide adjustable range and high precision. For example, the digital time converter using multiple phase reference clocks often has limited precision, and the digital time converter using multiple cycle clock phase difference often sacrifices reaction time to achieve better delay precision.

[0026] The converter uses a tap delay chain and a selector array to realize quantization delay within at least 50ps, and uses a high precision time digital converter for calibration, which can significantly reduce the nonlinearity of the tap delay chain and the selector array structure. After calibration, only the coarse and fine counters need to be set according to the set delay value to complete the delay setting, which realizes the characteristic of fast locking. The two-step quantization method of the coarse and fine delay devices realizes a wide adjustable range, and the adjustable delay range covered can reach the maximum number of count periods corresponding to the delay time provided by the coarse delay device. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1 The digital time converter structure proposed by the application is shown in the figure.

[0028] Figure 2 The system workflow diagram of the digital time converter proposed by the application is shown in the figure.

[0029] Figure 3 The general structure diagram of the fine delay device described in the application is shown in the figure.

[0030] Figure 4A schematic diagram of a fine delay line structure of a digital time converter of improved structure.

[0031] Figure 5 Actual test results of an embodiment. DETAILED DESCRIPTION

[0032] The application is further described below in conjunction with the accompanying drawings and embodiments.

[0033] A fast locking wide adjustable range high precision digital time converter, the system comprises a coarse delay line, a fine delay line, a time-to-digital converter, a lookup table module, a delay control circuit. It uses the coarse delay line to achieve an adjustable delay range covering multiple system cycles, and uses the fine delay line to achieve a fine delay covering a time interval of more than one system cycle. The coarse and fine delays can be set successfully within one clock cycle to achieve the purpose of fast locking.

[0034] The coarse delay line is used to generate a coarse delay signal, which is input into the fine delay line for further fine delay. It counts according to the system clock cycle, and releases the coarse delay signal when the coarse delay control signal reaches the corresponding value. The coarse delay line writes the coarse delay control word into the delay cycle setting register within one cycle after receiving the delay setting enable, and the delay setting takes effect.

[0035] The fine delay line is used to further delay the coarse delay signal, and its output is a fine delay signal, which is respectively input into the time-to-digital converter and the system output IO.

[0036] The fine delay line includes a tapped delay line structure, and the delay path is composed of a delay chain of cascaded delay units and a selector array for selecting the output taps. The tapped delay line can use a general cascaded chain of delay units, or a modified double-chain interpolation cascaded chain of delay units. Any selected tap output in the tapped delay line has a corresponding unique delay time, and different delay times are arranged to quantize the system clock into a time interval of at least 50ps or less.

[0037] The fine delay line traverses each tap as an output and measures its corresponding delay time in the calibration state, and accepts the tap value input by the delay control circuit in the delay state. After receiving the delay setting enable, the tap corresponding to the tap value is selected as the fine delay signal output within one cycle.

[0038] The time-to-digital converter is used to measure the difference between the fine delay signal and the start delay enable signal under the reference clock. It can choose any suitable implementation method, and its measurement accuracy must be greater than the delay accuracy of the digital time converter.

[0039] The look-up table module is used to measure the delay of each tap and convert the fine delay time into the corresponding output tap when the delay is controlled. The look-up table module first calculates the delay value corresponding to each tap output of the measured fine delay. When calculating, the same tap output is repeatedly set a suitable number of times, the measured delay difference of each tap output is averaged as the delay difference corresponding to the tap, and the delay difference is arranged and stored in the RAM according to the size of the calculated delay difference. When the delay is controlled, the delay control circuit queries the tap corresponding to the fine delay value from the look-up table module, and the look-up table outputs the tap value corresponding to the input fine delay time to the delay control circuit.

[0040] The delay control circuit is used to calculate the control signal sent by the upper computer or other modules except the digital time converter and input the control signal to the coarse delay and the look-up table module respectively. According to the delay control word input by the upper computer or other modules except the digital time converter, the corresponding coarse control word and fine control word are calculated, wherein the coarse control word is the number of periods that need to be delayed, and the fine control word is the specific fine delay time interval. The coarse control word is input to the coarse delay, the fine control word is input to the look-up table module to find the corresponding tap value, and the returned tap value is input to the fine delay. The coarse and fine delays will receive the delay setting enable signal sent by the delay control module at the same time, and the setting is completed within a period.

[0041] The system workflow of the fast-locked wide-adjustable-range high-precision digital time converter includes the following steps:

[0042] Step 1, build the circuit of any of the digital time converters;

[0043] Step 2, the system is powered on or the calibration button is triggered to enter the calibration state;

[0044] Step 3, select the same tap to repeatedly output the same fine delay signal with the same delay difference, and the number of repetitions can be any suitable value that can measure the more accurate delay difference corresponding to the tap. The measured delay difference is saved to the RAM;

[0045] Step 4, change the output tap, and repeat step 2 until all taps are traversed;

[0046] Step 5, calculate the delay difference corresponding to each tap and establish the look-up table of the delay time corresponding to the tap;

[0047] Step 6, enter the delay state, calculate and output the coarse delay value and the fine delay value according to the control word input by the upper computer or other modules except the digital time converter, input the fine delay value into the look-up table module to obtain the returned tap value, and set the output tap of the fine delay to the value. Embodiment

[0048] The application discloses a high-precision digital time converter with wide adjustable range and fast locking, which comprises a coarse delay, a fine delay, a time-to-digital converter, a lookup table module and a delay control circuit. Figure 1

[0049] The reference clock signal Clk_ref is connected to the coarse delay first, and the coarse delay signal Coar_dly is output after the coarse delay, and the fine delay is connected. The output tap of the fine delay has been locked according to the tap value Tap_sel given by the calculation circuit. The coarse delay signal Coar_dly is output as the fine delay signal Fine_dly through the tap delay chain and the selector array in the fine delay. The fine delay signal is connected to the system output IO and the input end of the internal time-to-digital converter at the same time. The time-to-digital converter accepts the fine delay signal and compares the delay difference Meas_res between the reference clock under the trigger coarse delay and the rising edge of the delay enable, and the delay time corresponding to each tap is traversed through multiple measurements and saved in the RAM. The lookup table module also accepts the fine delay control word Fine_time input by the delay control circuit, that is, the fine delay time, and finds the output tap with the closest output delay in the RAM, and returns the lookup result Ref_tap to the delay control circuit. The delay control circuit accepts the control word Dly_time from the upper computer or other modules outside the time-to-digital converter, and calculates the coarse delay control word Coar_time and the fine delay control word Fine_time, wherein the coarse control word is the number of periods required for delay, and the fine control word is the specific fine delay time interval. The coarse control word is input into the coarse delay, the fine control word is input into the lookup table module to find the corresponding tap value, and the returned tap value Ref_tap is input into the fine delay. The coarse delay and the fine delay will receive the delay setting enable signal Set_en sent by the delay control module at the same time, and the setting is completed in a period, and the coarse delay starts to delay when the delay start enable Gen_en is received.

[0050] The digital time converter needs to calibrate the delay time corresponding to each tap before working, and the working process of the calibration is as shown in Figure 2

[0051] Step 1, the delay period of the coarse delay is set to 0, and the output tap of the fine delay is set to the 0th tap.

[0052] Step 2, a single calibration start enable is sent to the coarse counter and the lookup table module, the coarse delay signal is immediately released by the coarse delay, the coarse delay signal is input into the fine delay and delayed to the fine delay signal input into the lookup table module.

[0053] ​​Step 3, the lookup table module takes the moment of arrival of the reference measurement fine delay signal as the reference to calculate the delay difference between the two;

[0054] Step 4, repeat the operation of steps 2-3 for each tap for a suitable number of times, and store all the results in the RAM;

[0055] Step 5, after measuring all the taps, average the delay difference measured for the same tap, and set the result as the delay time corresponding to each tap;

[0056] After calibration, the system will enter the delay state. In this state, the system receives control signals from the host computer or other modules other than the digital time converter. The delay control module calculates and sends the fine control word to the lookup table module to query the corresponding output tap after receiving the control word. After receiving the fine delay output tap value returned by the lookup table module, the delay control module enables the delay setting enable signal Set_en in the same cycle, and the coarse and fine delay timers will be set successfully in one cycle.

[0057] The coarse delay timer sets the counter value to the new coarse delay control word immediately after receiving the coarse delay control word and the write enable signal from the delay control module. When the coarse delay timer receives the delay enable signal Gen_en from the delay control module, it starts counting immediately. When the count reaches the set value minus one, the coarse delay signal is released. At this time, the coarse delay signal has been delayed for the number of cycles set by the delay setting. The coarse delay signal is connected to the fine delay timer.

[0058] The fine delay timer is used to further delay the coarse delay signal, and its output is the fine delay signal. In the delay state, it accepts the tap value input by the delay control circuit and selects the tap corresponding to the tap value as the fine delay signal output.

[0059] The fine delay timer includes a tap delay chain structure. The delay path is composed of a delay chain formed by cascading delay units and a selector array that selects the output tap. Selecting any tap output has a corresponding unique delay time. Different delay times can be arranged in size to quantize the system clock into a certain time interval.

[0060] Figure 3 The fine delay timer with a tap delay chain structure generally has the structure shown. It mainly consists of a delay unit cascade chain and a selector array.

[0061] The delay unit can be any combination logic device, such as a buffer, an inverter, etc. When implemented in an FPGA, it is particularly suitable to use the internal carry chain structure to implement the delay unit cascade chain.

[0062] Since the output taps are generally more, a selector array is needed to be composed of multiple selectors to select the outputs of the taps of the delay chain as a final output. Generally, the outputs of each tap are required to pass through the same number of selectors to reduce the output delay nonlinearity caused by the selector array.

[0063] An improved tap delay chain structure is shown in Figure 4 Since the delay units used have their inherent delay time, when a quantized delay interval exceeding the inherent delay time is required to be implemented, the fine delay unit shown in Figure 3 is no longer applicable.

[0064] Figure 4 The tap delay chain in the fine delay unit is composed of two cascaded chains of delay units, and the tap output delay difference of the two cascaded chains is interpolated with each other in the time axis, so that a quantized delay interval exceeding the inherent delay time can be implemented. This structure is particularly suitable for the digital time converter based on FPGA, and a vernier type or ring type delay chain can be used to build the digital time converter in ASIC.

[0065] The outputs of the fine delay unit are connected to the system output port of the digital time converter and the input of the time digital converter, respectively.

[0066] The time digital converter is used to measure the difference between the fine delay signal and the start delay enable signal. Any suitable implementation method can be selected, and the measurement accuracy must be greater than the delay accuracy of the digital time converter of claim 1.

[0067] The look-up table module is used to measure the delay corresponding to the tap and convert the fine delay time into the corresponding output tap during delay control. The look-up table module first calculates the delay value corresponding to each tap output of the measured fine delay unit, wherein the same tap output is repeatedly set a suitable number of times during calculation, the measured delay difference of each delay output of the same tap is averaged as the delay difference corresponding to the tap, and the delay difference is arranged and stored in the RAM according to the size. During the delay, the delay control circuit queries the tap corresponding to the fine delay value from the look-up table module, the module finds the tap value stored in the address corresponding to the fine delay value in the RAM, and outputs the value to the delay control circuit.

[0068] This scheme can be implemented based on the ZYNQ-7 ZC706 development board of Xilinx Company. Since there are differences in performance and underlying devices of different FPGAs, the performance of the time digital converter implemented by the ZYNQ-7 ZC706 development board will also be different.

[0069] The performance of the digital time converter implemented on the ZYNQ-7 ZC706 development board is shown in Figure 5As shown, the embodiment uses a modified fine delay line. Since the double chain interpolation method makes the two chains staggered on the time axis, the taps at the beginning and end of the fine delay line correspond to a large delay, and the middle is small. The system clock of the embodiment is 400MHz, so the fine delay line needs to cover a time interval of 2500ps, and the 50th to 450th taps are taken as effective taps. The performance analysis of this section is shown in the figure, and the resolution, i.e. the average quantization time interval, is about 7.05ps, the integral nonlinearity INL is (-16.20, 8.27) LSB, and the differential nonlinearity DNL is (-1.00, 5.38) LSB.

[0070] The embodiments in the above description can be further combined or replaced, and the embodiments are only used to describe the preferred embodiments of the present application, and do not limit the concept and scope of the present application. Without departing from the design idea of the present application, various changes and improvements made by those skilled in the art to the technical solutions of the present application all belong to the protection scope of the present application. The protection scope of the present application is given by the appended claims and any equivalents thereof.

Claims

1. A fast-locking wide-tunable-range high-precision digital time-to-digital converter, characterized in that: The high-precision digital time converter comprises a coarse time delay device, a fine time delay device, a time-to-digital converter, a look-up table module and a delay control circuit. The coarse time delay device is used for generating a coarse time delay signal according to a reference clock, and the signal is input into the fine time delay device for further fine time delay. The fine time delay device is used for further time delaying the coarse time delay signal, and outputting a fine time delay signal, which is input into a time-to-digital converter and a system output IO. The time-to-digital converter is used for measuring a time difference between the fine time delay signal and a start time delay enable signal. The look-up table module is used for calculating and storing, in a storage, a corresponding time delay value of each tap output of the fine time delay device according to the measured time delay value, and arranging the time delay value according to the size. The delay control circuit is used for calculating a control word sent by a host computer or other modules except the time-to-digital converter into coarse and fine control words, and inputting the control words into the coarse time delay device and the look-up table module.

2. The high precision digital time converter of claim 1, wherein: The coarse time delay device is used for counting according to a system clock period, and releasing a coarse time delay signal when a corresponding value of a coarse time delay control signal is reached.

3. The high precision digital time converter of claim 1, wherein: The fine time delay device adopts a tap delay chain structure, and a delay path is composed of a delay chain formed by cascading delay units and a selector array for selecting a tap output. In a calibration state, each tap is selected as an output, and a corresponding delay time is measured.

4. The high precision digital time converter of claim 1, wherein: The time-to-digital converter has a measurement precision greater than that of the high-precision digital time converter.

5. The high precision digital time-to-digital converter of claim 4, wherein: In a calibration state, the look-up table module saves a measurement result of the time-to-digital converter, and calculates an average delay difference of each tap output. In a delay state, a corresponding tap value is output according to an input fine control word.

6. The high precision digital time converter of claim 1, wherein: The high-precision digital time converter comprises the following steps: Step 1: building a circuit of the high-precision digital time converter; Step 2: entering a calibration state when a system is powered on or a calibration button is triggered; Step 3: selecting the same tap to repeatedly output a fine delay signal with the same delay difference, and the number of repetitions is any suitable value capable of measuring a relatively accurate delay difference corresponding to the tap, and the measured delay difference is saved into a RAM each time; Step 4: changing the output tap, and repeating step 2 until all taps are traversed; Step 5: calculating a delay difference corresponding to each tap, and establishing a look-up table of delay time corresponding to the tap. Step 6, entering delay state, calculating and outputting coarse delay value and fine delay value according to control word input by other module except host computer or digital time converter, inputting fine delay value into look-up table module to get returned tap value, setting output tap of fine delay device as the value.

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