An LDO startup circuit

Abstract

This application addresses the problems of currently used overshoot voltage suppression methods by providing an LDO startup circuit, comprising: a first current source connected to a first terminal of a first capacitor via a first switch; a second terminal of the first capacitor grounded, and the first terminal of the first capacitor grounded via a second switch; a control module connected to the control terminals of the first and second switches; and the output terminal of the EA in the LDO connected to the positive terminal of the power supply via a first switching transistor, the control terminal of the first switching transistor being connected to the first terminal of the first capacitor. This application avoids overshoot when the LDO is powered on by pulling up the output voltage of the EA, reducing the risk of damage to subsequent circuits, without altering the startup characteristics of the EA or affecting its performance. Furthermore, the circuit structure provided in this application means that the first capacitor is not in the feedback loop of the LDO, and a pF level capacitor is sufficient, thus not affecting the stability of the LDO.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to an LDO startup circuit. Background Technology

[0002] In modern power management chips, low dropout regulators (LDOs) are an indispensable component. They can maintain a stable output voltage over a wide range of load current and input voltage, while maintaining a small input-output voltage difference. Furthermore, LDOs are characterized by high efficiency, low noise, and low cost, thus gaining widespread application.

[0003] Traditional LDOs such as Figure 1 As shown, it consists of an error amplifier (EA), an output driver transistor M3, a feedback loop (R1 and R2 circuit section), and an output capacitor C2. Due to its inherent structural problem, the LDO's output voltage Vout will have a momentary overshoot during the power-on process. A high overshoot voltage will cause irreversible damage to the subsequent circuits.

[0004] Currently, the main methods to prevent voltage and current overshoot during startup are as follows:

[0005] 1. Add a clamping circuit to the output of the LDO to suppress overshoot voltage. When the output voltage is too high, the clamping circuit opens to discharge current to the output terminal, restoring the output voltage to a normal level. This method discharges the output current only after the overshoot has occurred. Due to the lag in the response process, there is still a risk of damaging subsequent circuits.

[0006] 2. Add a startup circuit to the EA to change its startup characteristics. This method, by altering the EA's circuit structure, will have a certain impact on the EA's performance.

[0007] 3. Add a capacitor to the output terminal. This method of directly adding a capacitor to the output terminal requires a relatively large capacitance value, reaching the nF to uF level, and will also affect the stability of the LDO.

[0008] Therefore, those skilled in the art urgently need an LDO startup circuit that avoids the problems of the aforementioned commonly used overshoot voltage suppression methods. Summary of the Invention

[0009] The purpose of this application is to provide an LDO startup circuit that avoids the problems of the aforementioned commonly used overshoot voltage suppression methods.

[0010] To solve the above-mentioned technical problems, this application provides an LDO startup circuit, including: a first switch, a second switch, a first capacitor, a control module, a first switching transistor, and a first current source;

[0011] The first current source is connected to the first terminal of the first capacitor via the first switch, and is used to charge the first capacitor when the first switch is closed; the second terminal of the first capacitor is grounded, and the first terminal of the first capacitor is grounded via the second switch; the control module is connected to the control terminals of the first switch and the second switch, and is used to output control signals to control the opening and closing states of the first switch and the second switch, wherein the opening and closing states of the first switch and the second switch are always opposite; the output terminal of EA in the LDO is connected to the positive terminal of the power supply via the first switching transistor, and the control terminal of the first switching transistor is connected to the first terminal of the first capacitor.

[0012] Preferably, the control signal is the LDO enable signal.

[0013] Preferably, the control module is a current comparison module; the current comparison module is used to compare the bias current of EA with a preset reference current; when the bias current of EA is greater than or equal to the reference current, the control signal is output to close the first switch and open the second switch; when the bias current of EA is less than the reference current, the control signal is output to open the first switch and close the second switch.

[0014] Preferably, it further includes: a voltage comparison module and a third switch; the control terminal of the first switch is connected to the positive terminal of the power supply through the third switch; the input terminal of the voltage comparison module is connected to the output terminal of the LDO, and the output terminal of the voltage comparison module is connected to the control terminal of the third switch, for comparing the output voltage of the LDO with a preset reference voltage, and controlling the opening and closing state of the third switch according to the result.

[0015] Preferably, the current comparison module includes: a second current source, an inverter, and a second switching transistor;

[0016] The first terminal of the second current source is connected to the positive terminal of the power supply. The second terminal of the second current source and the input terminal of the inverter are grounded through the second switching transistor. The second current source is used to provide a reference current. The control terminal of the second switching transistor is connected to the current mirror of the bias current of EA. The output terminal of the inverter is connected to the control terminals of the first and second switches.

[0017] Preferably, the voltage comparison module is a voltage comparator;

[0018] The non-inverting input of the voltage comparator is connected to the output of the LDO as the input of the voltage comparison module; the inverting input of the voltage comparator is connected to the reference voltage source, which provides the reference voltage; the output of the voltage comparator is connected to the control terminal of the third switch as the output of the voltage comparison module.

[0019] Preferably, the first switch, the second switch, and the third switch are MOSFETs.

[0020] Preferably, the first and second switching transistors are MOSFETs.

[0021] Preferably, the output current value of the second current source is the bias current value when EA is operating normally.

[0022] Preferably, it further includes an indicator device, which is connected to the control terminals of the first switch, the second switch, and the third switch, and is used to issue corresponding prompt information when the first switch, the second switch, and the third switch are in different open or closed states.

[0023] The LDO startup circuit provided in this application achieves the following: When the first switch is not closed, the voltage across the first capacitor is 0, so the voltage input to the control terminal of the first switching transistor is also 0. At this time, the first switching transistor is turned on, and the output terminal of EA is essentially directly connected to the positive terminal of the power supply, causing the output voltage of EA to be pulled up. The output driver transistor is cut off, and the LDO output voltage is 0, thus avoiding overshoot when the LDO is powered on. When the first switch is closed, the first current source charges the first capacitor, causing the voltage at the first terminal of the first capacitor to rise slowly. The first switching transistor gradually turns on, and the pull-up force on the output terminal of EA gradually decreases until the control terminal of the output driver transistor is once again controlled by the output voltage of EA, and the LDO operates normally. The LDO startup circuit provided in this application pulls up the output voltage of the EA to avoid overshoot. This method avoids overshoot from the moment the LDO is powered on. Compared with the current method of discharging the current from the moment overshoot occurs, it avoids the risk of damage to subsequent circuits and does not change the circuit structure of the EA, so it will not affect the performance of the EA. In addition, in the circuit structure provided in this application, the first capacitor only provides a slowly increasing voltage through charging and discharging. Therefore, a pF-level capacitor is sufficient for the selection of the first capacitor. At the same time, the first capacitor is not in the feedback loop of the LDO and will not affect the stability of the LDO. Attached Figure Description

[0024] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 A schematic diagram of a conventional LDO circuit structure is provided for this invention;

[0026] Figure 2A schematic diagram of the circuit structure of an LDO startup circuit provided by the present invention;

[0027] Figure 3 A schematic diagram of another LDO startup circuit provided by the present invention. Detailed Implementation

[0028] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0029] The core of this application is to provide an LDO startup circuit.

[0030] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0031] Existing LDO structures such as Figure 1 As shown, it includes: an error amplifier EA, an output driver transistor M3, a first resistor R1, a second resistor R2, and an output capacitor C2. For specific connections, please refer to [link to documentation]. Figure 1 The specific details of this embodiment will not be elaborated upon here.

[0032] Figure 1 The traditional LDO shown has inherent structural problems, and its output voltage Vout will experience momentary overshoot during power-up. The high overshoot voltage can cause irreversible damage to the subsequent circuits of the LDO. Therefore, the common methods to suppress overshoot voltage are to add a clamping circuit at the output of the LDO, add a startup circuit in EA, and add a capacitor at the output of the LDO.

[0033] However, the above methods all have some problems that cannot be ignored: adding a clamping circuit only discharges current to the LDO output after overshoot occurs. Due to the lag in the response process, there is still a risk of damage to the subsequent circuits; adding a startup circuit to the EA will change the circuit structure of the EA, so it will also affect the performance of the EA; the capacitor added to the LDO output needs to have a large capacitance value, reaching the nF to uF level, which will affect the stability of the LDO.

[0034] Therefore, to solve the above problems, this application provides an LDO startup circuit, such as... Figure 2 As shown, it includes: a first switch K1, a second switch K2, a first capacitor C1, a control module 1, a first switching transistor M1, and a first current source I1;

[0035] The first current source I1 is connected to the first terminal of the first capacitor C1 through the first switch K1, and is used to charge the first capacitor C1 when the first switch K1 is closed; the second terminal of the first capacitor C1 is grounded, and the first terminal of the first capacitor C1 is grounded through the second switch K2; the control module 1 is connected to the control terminals of the first switch K1 and the second switch K2, and is used to output the control signal Vctl to control the opening and closing states of the first switch K1 and the second switch K2, wherein the opening and closing states of the first switch K1 and the second switch K2 are always opposite; the output terminal of EA in the LDO is connected to the positive terminal VCC of the power supply through the first switch M1, and the control terminal of the first switch M1 is connected to the first terminal of the first capacitor C1.

[0036] Among them, the first switch M1 mainly plays the role of controlling the output pull-up voltage. Therefore, in practical applications, it can be preferably implemented as a field-effect transistor (MOSFET). Correspondingly, the first switch K1 and the second switch K2 can also be electronic switches, or even MOSFETs.

[0037] MOSFETs are commonly used in switching circuits due to their advantages such as small size, light weight, long life, strong anti-interference ability, and low power consumption. Since MOSFETs are controlled by voltage, they are suitable for the purpose of controlling the pull-up voltage through the voltage across the first capacitor C1 in this application. Therefore, the first switch K1, the second switch K2, and the first switching transistor M1 are preferably MOSFETs.

[0038] When the first switch K1, the second switch K2, and the first switching transistor M1 are MOSFETs, the corresponding control terminals of the first switch K1, the second switch K2, and the first switching transistor M1 are the gates of the MOSFETs. The connections mentioned above, such as those through the first switch K1, the second switch K2, and the first switching transistor M1, are all connected to the source or drain of the MOSFET, and then connected to other hardware structures through the other terminal of the source or drain of the MOSFET.

[0039] like Figure 2In the circuit structure shown, when the LDO is powered on (i.e., when the positive power supply VCC is powered on), the first switch K1 is open and the second switch K2 is closed. At this time, both ends of the first capacitor C1 are grounded and there is no voltage. Therefore, the gate of the first switching transistor M1 also has no voltage input. Since the source of the first switching transistor M1 is connected to the positive power supply, the first switching transistor M1 is turned on. The positive power supply VCC is equivalent to being directly connected to the output terminal of EA, pulling up the output voltage Vgate of EA. As a result, the gate voltage of the output driving transistor M3 is equal to the source voltage, the output driving transistor M3 is turned off, and the LDO output terminal does not output voltage, thus achieving the effect of suppressing overshoot voltage. Meanwhile, when the first switch K1 is closed and the second switch K2 is open, the first current source I1 is directly connected to the first terminal of the first capacitor C1 to charge it, causing the voltage at the first terminal of the first capacitor C1 to rise slowly. Therefore, the voltage Vramp at the gate of the first switching transistor M1 rises slowly and the voltage at the drain falls slowly, which means that the output pull-up voltage falls slowly. Thus, the control effect of the output driving transistor M3 is gradually handed over to the output voltage Vgate of EA until the LDO fully recovers to normal operation.

[0040] Regarding how control module 1 controls the first switch K1 and the second switch K2, initially, it controls the first switch K1 to be open and the second switch K2 to be closed, grounding the first capacitor C1 and discharging the voltage from the previous charging process, thus keeping the voltage across the first capacitor C1 at 0. When the LDO starts, control module 1 can output a corresponding control signal Vctl to close the first switch K1 and open the second switch K2. The control signal Vctl can be two signals generated by control module 1 that control the first switch K1 and the second switch K2 respectively. Since the opening and closing states of the first switch K1 and the second switch K2 are always opposite, one possible implementation is that the first switch K1 is a normally open contact and the second switch K2 is a normally closed contact. Therefore, the control signal Vctl can also be the same signal that controls both the first switch K1 and the second switch K2 simultaneously.

[0041] The LDO startup circuit provided in this application controls the conduction and cutoff of the first switching transistor M1 by controlling the charging and discharging of the first capacitor C1, and outputs a slowly decreasing pull-up voltage when M1 is on. This first pulls up the output voltage Vgate of EA and then slowly releases it, causing the output voltage Vout of the LDO to rise slowly, thereby avoiding overshoot. Compared with adding a clamping circuit to the LDO output, this method avoids the risk of damage to subsequent circuits caused by overshoot due to the corresponding lag. Furthermore, since the LDO startup circuit provided in this application suppresses overshoot voltage by pulling up the output voltage Vgate of EA, it does not change the circuit structure of EA and therefore does not affect its performance. Additionally, the capacitor in the LDO startup circuit provided in this application controls the voltage at the control terminal of the first switching transistor M1 by charging and discharging, so only a pF-level capacitor is required. The first capacitor C1 is not in the LDO's feedback loop and will not affect the stability of the LDO.

[0042] Since the LDO startup circuit provided in this application needs to return the control of the gate of the output drive transistor M3 to the output voltage Vgate of EA after avoiding overshoot during power-on, the LDO startup circuit provided in this application should start after the LDO is powered on in order to avoid affecting the normal operation of the LDO. Therefore, this embodiment provides a preferred implementation: the control signal Vctl is the enable signal of the LDO.

[0043] Since LDOs are typically used in power management chips, the corresponding LDO enable signal should also be issued by the structure or device that plays a control role in the power management chip. In this embodiment, the structure or device that issues the LDO enable signal in the power management chip is the control module 1 mentioned in this embodiment.

[0044] In this embodiment, the enable signal of the LDO is used as the control signal Vctl to control the opening and closing states of the first switch K1 and the second switch K2. This allows the control module 1 to be reused as a structure and device that plays a control role in the power management chip while suppressing overshoot voltage. This reduces costs and saves space, further meeting users' needs for miniaturization and economy in power management chips.

[0045] In addition to the above, this embodiment also provides another preferred implementation scheme for the specific implementation of the control signal Vctl and control module 1:

[0046] Control module 1 is a current comparison module 2; current comparison module 2 is used to compare the bias current of EA with the preset reference current; when the bias current of EA is greater than or equal to the reference current, the output control signal Vctl closes the first switch K1 and opens the second switch K2; when the bias current of EA is less than the reference current, the output control signal Vctl opens the first switch K1 and closes the second switch K2.

[0047] One preferred method for setting the preset reference current is to take the value of the bias current of EA during normal operation. When the mirror image Ibais of the EA bias current is greater than or equal to the reference current, it indicates that the EA current is normal and the power-on process has ended, thus achieving the purpose of determining whether the EA is currently operating normally.

[0048] At this time, the control signal Vctl should be output to close the first switch K1 and open the second switch K2, and the pull-up voltage should be slowly reduced so that the voltage Vgate at the output terminal of EA is gradually released. The output drive transistor M3 is then controlled by the voltage Vgate at the output terminal of EA again, and the LDO resumes normal operation.

[0049] Furthermore, to further illustrate the LDO circuit provided in this application, this embodiment also provides a preferred solution when the control module 1 is a current comparison module 2, such as... Figure 3 As shown, the current comparison module 2 includes:

[0050] Second current source I2, inverter Inv, and second switch M2;

[0051] The first terminal of the second current source I2 is connected to the positive terminal VCC of the power supply. The second terminal of the second current source I2 and the input terminal of the inverter Inv are grounded through the second switch M2. The second current source I2 is used to provide a reference current. The control terminal of the second switch M2 is connected to the current mirror of the bias current of EA. The output terminal of the inverter Inv is connected to the control terminals of the first switch K1 and the second switch K2.

[0052] In addition, the second switch M2 mentioned in this embodiment has a similar function to the first switch M1, both acting as a switch. Therefore, like the first switch M1, the second switch M2 can also be preferably a MOSFET to obtain the advantages of MOSFETs such as small size, light weight, long life, strong anti-interference ability, and low power consumption.

[0053] The preferred solution provided in this embodiment compares the bias current of EA with the preset reference current through the current comparison module 2, which can determine whether the current working state of EA is normal. When EA is working normally, the output control signal Vctl closes the first switch K1 and opens the second switch K2, which can further ensure that there is no overshoot when LDO is powered on, so as to reduce the risk of irreversible damage to the downstream circuit of LDO.

[0054] Furthermore, since the LDO startup circuit provided in this application requires continuous charging of the first capacitor C1 for a period of time before the output voltage Vgate of EA can be fully released, in some scenarios requiring rapid response, the subsequent circuitry of the LDO must start working quickly after the LDO startup is complete. Therefore, if the output voltage Vgate of EA has not been fully released after the LDO startup is complete, it will affect the driving capability of the LDO, and thus affect the normal operation of the subsequent circuitry. Therefore, if... Figure 3 As shown, based on the above embodiments, this embodiment also provides a preferred implementation scheme. The LDO startup circuit provided in this application further includes: a voltage comparison module 3 and a third switch K3;

[0055] The control terminal of the first switching transistor M1 is connected to the positive power supply VCC through the third switch K3; the input terminal of the voltage comparison module 3 is connected to the output terminal of the LDO, and the output terminal of the voltage comparison module 3 is connected to the control terminal of the third switch K3. It is used to compare the output voltage Vout of the LDO with the preset reference voltage Vref_2, and control the opening and closing state of the third switch K3 according to the result.

[0056] The gate of the first switching transistor M1 is connected to the positive power supply VCC via the third switch K3. Since the source of the first switching transistor M1 is also connected to the positive power supply VCC, when the third switch K3 is closed, the first switching transistor M1 is turned off and no longer outputs a pull-up voltage to the output terminal of EA. This returns control of the output drive transistor M3 to the output voltage Vgate of EA, and the LDO resumes normal operation. Simultaneously, the opening and closing state of the third switch K3 is controlled by the voltage comparator module 3. The input terminal of the voltage comparator module 3 is connected to the output terminal of the LDO to obtain the LDO's output voltage Vout. The LDO's output voltage Vout is compared with a preset reference voltage Vref_2 to determine whether the LDO has completed startup. If startup is complete, the voltage comparator module 3 controls the third switch K3 to close, thereby turning off the first switching transistor M1 and no longer affecting the LDO's driving capability, allowing the subsequent circuits to respond quickly and operate.

[0057] Among them, the voltage comparison module 3 can be a microcontroller or other device with voltage comparison function. At the same time, for the sake of cost and ease of implementation, the voltage comparison module 3 can preferably be a voltage comparator.

[0058] Correspondingly, such as Figure 3As shown, the input terminal of voltage comparison module 3 is the non-inverting input terminal of voltage comparator Comp, which is connected to the output terminal of LDO to obtain the output voltage Vout of LDO; the output terminal of voltage comparison module 3 is the output terminal of voltage comparator Comp, which is connected to the control terminal of third switch K3 to output an electrical signal to control the closing or closing of third switch K3; the inverting input terminal of voltage comparator Comp is connected to reference voltage source to obtain the reference voltage Vref_2 provided by reference voltage source; the third switch K3 can preferably be a MOSFET to achieve the same advantages as the first switch K1 and the second switch K2 in the above embodiment, which are preferably MOSFETs.

[0059] In a preferred embodiment, the voltage comparison module 3 and the third switch K3 further control the first switching transistor M1. When the voltage comparison module 3 detects that the LDO has finished starting, it is no longer necessary to pull up the output voltage Vgate of EA. At this time, the voltage comparison module 3 controls the third switch K3 to close, pull up the voltage Vramp at the control terminal of the first switching transistor M1, turn off the first switching transistor M1, and restore the normal operation of the LDO. This will no longer affect the driving capability of the LDO, thus meeting the need for fast response in some application scenarios.

[0060] As can be seen from the above embodiments, the LDO startup circuit provided in this application controls the pull-up voltage output to the output terminal of EA by controlling the closed states of the first switch K1, the second switch K2, and the third switch K3. Therefore, in some application scenarios, users may need to know the open and closed states of the first switch K1, the second switch K2, and the third switch K3. Therefore, based on the above embodiments, this embodiment also provides a preferred implementation scheme, in which the LDO startup circuit further includes: an indicator device connected to the control terminals of the first switch K1, the second switch K2, and the third switch K3, used to issue corresponding prompt information when the first switch K1, the second switch K2, and the third switch K3 are in different open and closed states.

[0061] The indicating device is connected to the control terminals of the first switch K1, the second switch K2, and the third switch K3. When the control module 1, the current comparison module 2, and the voltage comparison module 3 control the first switch K1, the second switch K2, and the third switch K3 to close or close by outputting electrical signals, the indicating device can also obtain the corresponding electrical signals, thereby knowing the open or closed state that each switch should be in at this time, and issuing corresponding prompts to remind the operator.

[0062] The prompting device can be a microcontroller, central processing unit (CPU), or other control device connected to the display screen, which outputs image signals to the display screen to prompt the operator; the prompting device can also be a light-emitting diode, which indicates the on / off state of the corresponding switch by the on / off state of the light-emitting diode; or it can be a speaker, buzzer, or other sound-emitting device, which emits prompt information in the form of sound signals. This embodiment does not limit this.

[0063] This embodiment uses a prompting device connected to the control terminal of each switch to obtain the electrical signal input to the control terminal of each switch, to know the open / closed state that each switch should be in, and to issue corresponding prompt information, so that the operator can know the open / closed state of each switch and make a more detailed and accurate judgment on the working state of the LDO circuit.

[0064] To further illustrate the LDO startup circuit provided in this application, a detailed description of its practical application follows:

[0065] like Figure 3 As shown, the LDO startup circuit provided in this application includes: a soft-start module 4, a current comparison module 2, and a voltage comparison module 3;

[0066] The soft-start module 4 includes: a first switch K1, a second switch K2, a third switch K3, a first capacitor C1, a first current source I1, and a first switching transistor M1.

[0067] The first terminal of the first current source I1 is connected to the positive power supply VCC, and the second terminal of the first current source I1 is connected to the first terminal of the first switch K1. The second terminal of the first switch K1 is connected to the first terminal of the second switch K2, the first terminal of the first capacitor C1, and the gate of the first switching transistor M1. The second terminal of the second switching transistor M2 is grounded. The control terminals of the first switching transistor M1 and the second switching transistor M2 are connected to the output terminal of the inverter Inv. The second terminal of the first capacitor C1 is grounded. The source of the first switching transistor M1 is connected to the positive power supply VCC, and the drain is connected to the output terminal of EA. The first terminal of the third switch K3 is connected to the positive power supply VCC, the second terminal is connected to the gate of the first switching transistor M1, and the control terminal is connected to the output terminal of the voltage comparator Comp.

[0068] The current comparison module 2 includes: a second current source I2, a second switching transistor M2, and an inverter Inv;

[0069] The first terminal of the second current source I2 is connected to the positive power supply VCC, and the second terminal is connected to the input terminal of the inverter Inv and the drain of the second switch M2; the gate of the second switch M2 is connected to the current mirror source of the bias current of EA, and the source is grounded; the output terminal of the inverter Inv is connected to the control terminal of the first switch K1 and the second switch K2.

[0070] Voltage comparison module 3 includes: voltage comparator Comp;

[0071] The inverting input of voltage comparator Comp is connected to the reference voltage source, the non-inverting input is connected to the output of LDO, and the output is connected to the control terminal of the third switch K3.

[0072] When the LDO is powered on, the EA starts working. The first switch K1 is open, the second switch K2 is closed, and the third switch K3 is open. At this time, there is no voltage across the first capacitor C1, so there is no voltage input to the gate of the first switching transistor M1. The first switching transistor M1 is turned on, which is equivalent to outputting a pull-up voltage equal to the positive voltage of the power supply to the output terminal of the EA, so that the output drive transistor M3 is turned off, thus avoiding overshoot.

[0073] When EA is working normally, the current value of the current source mirrored by the bias current of EA input to the gate of the second switch M2 is equal to the current value of the current source I2 input to the drain of the second switch M2. The electrical signal output by the inverter Inv controls the first switch K1 to close and the second switch K2 to open. The first capacitor C1 starts to charge, the gate voltage of the first switch M1 gradually increases, the output pull-up voltage gradually decreases, and the output voltage Vgate of EA is slowly released.

[0074] When the LDO starts, the LDO's output voltage Vout reaches the set value, which is also the reference voltage value. After being acquired and compared by the voltage comparator Comp, the output electrical signal controls the third switch K3 to close, pulling up the gate voltage of the first switch M1, causing the first switch M1 to turn off, shutting down the soft start module 4, and no longer outputting the pull-up voltage. The LDO then works normally.

[0075] The above provides a detailed description of an LDO startup circuit provided in this application. The various embodiments in the specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

[0076] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

Claims

1. An LDO startup circuit, characterized in that, include: The system comprises a first switch, a second switch, a first capacitor, a control module, a first switching transistor, a first current source, a voltage comparison module, and a third switch. The first current source is connected to the first terminal of the first capacitor through the first switch, and is used to charge the first capacitor when the first switch is closed; the second terminal of the first capacitor is grounded, and the first terminal of the first capacitor is grounded through the second switch; The control module is connected to the control terminals of the first switch and the second switch, and is used to output control signals to control the opening and closing states of the first switch and the second switch, wherein the opening and closing states of the first switch and the second switch are always opposite; the output terminal of EA in LDO is connected to the positive terminal of the power supply through the first switching transistor, and the control terminal of the first switching transistor is connected to the first terminal of the first capacitor; The control terminal of the first switching transistor is connected to the positive terminal of the power supply through the third switch; the input terminal of the voltage comparison module is connected to the output terminal of the LDO, and the output terminal of the voltage comparison module is connected to the control terminal of the third switch, which is used to compare the output voltage of the LDO with a preset reference voltage, and control the opening and closing state of the third switch according to the result; The control module is a current comparison module; the current comparison module is used to compare the bias current of the EA with a preset reference current; when the bias current of the EA is greater than or equal to the reference current, the control signal is output to close the first switch and open the second switch; when the bias current of the EA is less than the reference current, the control signal is output to open the first switch and close the second switch; wherein, the preset reference current is: the bias current value of the EA when it is working normally; The current comparison module includes: a second current source, an inverter, and a second switching transistor; The first terminal of the second current source is connected to the positive terminal of the power supply, and the second terminal of the second current source and the input terminal of the inverter are grounded through the second switch. The second current source is used to provide the reference current. The control terminal of the second switch is connected to the current mirror of the bias current of EA. The output terminal of the inverter is connected to the control terminals of the first switch and the second switch. The voltage comparison module is a voltage comparator; The non-inverting input of the voltage comparator is connected to the output of the LDO as the input of the voltage comparison module; the inverting input of the voltage comparator is connected to a reference voltage source, which provides the reference voltage; the output of the voltage comparator is connected to the control terminal of the third switch as the output of the voltage comparison module.

2. The LDO startup circuit according to claim 1, characterized in that, The control signal is the LDO enable signal.

3. The LDO startup circuit according to claim 1 or 2, characterized in that, The first switch, the second switch, and the third switch are MOSFETs.

4. The LDO startup circuit according to claim 1, characterized in that, The first switch and the second switch are MOSFETs.

5. The LDO startup circuit according to claim 1, characterized in that, The output current value of the second current source is the bias current value when the EA is working normally.

6. The LDO startup circuit according to claim 1 or 2, characterized in that, It also includes an indicator device, which is connected to the control terminals of the first switch, the second switch, and the third switch, and is used to issue corresponding prompt information when the first switch, the second switch, and the third switch are in different open or closed states.

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